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([178.233.24.52]) by smtp.gmail.com with ESMTPSA id o1-20020adfeac1000000b0032dab20e773sm11077833wrn.69.2023.11.15.09.08.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Nov 2023 09:08:32 -0800 (PST) From: Alper Nebi Yasak To: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Conor Dooley , devicetree@vger.kernel.org, Krzysztof Kozlowski , Stephen Boyd , Michael Turquette , Rob Herring , linux-mediatek@lists.infradead.org, =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Matthias Brugger , Chen-Yu Tsai , linux-clk@vger.kernel.org, AngeloGioacchino Del Regno , Alper Nebi Yasak Subject: [PATCH v2 1/2] clk: mediatek: mt8173-infracfg: Handle unallocated infracfg when module Date: Wed, 15 Nov 2023 20:06:24 +0300 Message-ID: <20231115170825.908640-1-alpernebiyasak@gmail.com> X-Mailer: git-send-email 2.42.0 MIME-Version: 1.0 X-Spam-Status: No, score=-0.6 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Wed, 15 Nov 2023 09:09:00 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782650653464885622 X-GMAIL-MSGID: 1782650653464885622 The MT8173 infracfg clock driver does initialization in two steps, via a CLK_OF_DECLARE_DRIVER declaration. However its early init function doesn't get to run when it's built as a module, presumably since it's not loaded by the time it would have been called by of_clk_init(). This causes its second-step probe() to return -ENOMEM when trying to register clocks, as the necessary clock_data struct isn't initialized by the first step. MT2701 and MT6797 clock drivers also use this mechanism, but they try to allocate the necessary clock_data structure if missing in the second step. Mimic that for the MT8173 infracfg clock as well to make it work as a module. Signed-off-by: Alper Nebi Yasak --- Changes in v2: - Rewrite patch subject for consistency v1: https://lore.kernel.org/lkml/20231108213734.140707-1-alpernebiyasak@gmail.com/ drivers/clk/mediatek/clk-mt8173-infracfg.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) base-commit: bc962b35b139dd52319e6fc0f4bab00593bf38c9 diff --git a/drivers/clk/mediatek/clk-mt8173-infracfg.c b/drivers/clk/mediatek/clk-mt8173-infracfg.c index 2f2f074e231a..ecc8b0063ea5 100644 --- a/drivers/clk/mediatek/clk-mt8173-infracfg.c +++ b/drivers/clk/mediatek/clk-mt8173-infracfg.c @@ -98,7 +98,17 @@ CLK_OF_DECLARE_DRIVER(mtk_infrasys, "mediatek,mt8173-infracfg", static int clk_mt8173_infracfg_probe(struct platform_device *pdev) { struct device_node *node = pdev->dev.of_node; - int r; + int r, i; + + if (!infra_clk_data) { + infra_clk_data = mtk_alloc_clk_data(CLK_INFRA_NR_CLK); + if (!infra_clk_data) + return -ENOMEM; + } else { + for (i = 0; i < CLK_INFRA_NR_CLK; i++) + if (infra_clk_data->hws[i] == ERR_PTR(-EPROBE_DEFER)) + infra_clk_data->hws[i] = ERR_PTR(-ENOENT); + } r = mtk_clk_register_gates(&pdev->dev, node, infra_gates, ARRAY_SIZE(infra_gates), infra_clk_data); From patchwork Wed Nov 15 17:06:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alper Nebi Yasak X-Patchwork-Id: 165511 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b909:0:b0:403:3b70:6f57 with SMTP id t9csp2681111vqg; Wed, 15 Nov 2023 09:09:11 -0800 (PST) X-Google-Smtp-Source: AGHT+IHv3xIpdkM4EB5H20mL9ECb/+uz5RyS6+OWcMuw3Olz0hb647PdMnI0dppoWkwBECuqOkA9 X-Received: by 2002:a05:6a20:1444:b0:17b:689e:c757 with SMTP id a4-20020a056a20144400b0017b689ec757mr11507148pzi.11.1700068151133; Wed, 15 Nov 2023 09:09:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700068151; cv=none; d=google.com; s=arc-20160816; b=Q/Msz7z8RFZ2oLUqIPdC1516RdRqQ9xhGG/iOBFUJMwoqe1JUXlEZXGqo2eLb/Ny8m xWZS3yzR2tJRFI81wh+Ed0SiwnRqZGnJIzrAhW0sr85eBNygsTpLHOq1mcLJ3ZPs3s/l R15XPEpMrxiTI1C7wO3ZBsRoMQvfeLvV1j1VDo6B8RqNdAOBA/rmD96TmSf6w3eN7zzq IFZyZrwTrLbuJkeldkQS5kQiMcl4LYGa2I2A9WtkKxIMsxQjNFIOP3Sn/l/rvQh9s7HL 182XUNRxn3ER1/lYSB+aFTTyspS+/2rPmmQoSZVSeC6KdQ7ngYgeMqNim8QNgY/fpk1Q 5EZg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=qrrnyZWXKRYwxEi6KzPQsaUn7ssz3ZkVcCNWua0g1gk=; fh=KQf4xIu43KDoh6S4ByKWJArpPvHRTIbBuBFWqcc3xek=; b=HuYi3DyPxxjsXOauQJNWBkPmxhGoCxulc+ofUp1KXtG+1F5nP2TB7Onv5ZucQwxHbn NlYzqB+PAETZrS4zpF63h7VP7M5fRU+5J72BAaGCozYRlObNRloaaWjqCNguSX+oGVbv 1yUOiJhhqujhKSQTE/j6dmUC8LUH7IbSMrZjF9xoKf+0VrmNIEhKCvIrdzO8eGXbfsW9 7BN+yebedPhT+vUIQmRWw4SmxUHhsRV0yWE/Abq5SygduoXcY6pDkPeu0SwXaujkyAGE I4SrP5HpCJ0l6ZYTYlXpbrnut3b/7hDNejahjLLie9DlFWYPoy3QIN1WkX56bqErAlLg RWkQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b=ICccXjMG; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from groat.vger.email (groat.vger.email. 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([178.233.24.52]) by smtp.gmail.com with ESMTPSA id o1-20020adfeac1000000b0032dab20e773sm11077833wrn.69.2023.11.15.09.08.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Nov 2023 09:08:35 -0800 (PST) From: Alper Nebi Yasak To: linux-kernel@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org, Conor Dooley , devicetree@vger.kernel.org, Krzysztof Kozlowski , Stephen Boyd , Michael Turquette , Rob Herring , linux-mediatek@lists.infradead.org, =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Matthias Brugger , Chen-Yu Tsai , linux-clk@vger.kernel.org, AngeloGioacchino Del Regno , Alper Nebi Yasak Subject: [PATCH v2 2/2] arm64: dts: mediatek: mt8173: Fix timer 13 MHz clock description Date: Wed, 15 Nov 2023 20:06:25 +0300 Message-ID: <20231115170825.908640-2-alpernebiyasak@gmail.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231115170825.908640-1-alpernebiyasak@gmail.com> References: <20231115170825.908640-1-alpernebiyasak@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.6 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Wed, 15 Nov 2023 09:09:08 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782650661754838205 X-GMAIL-MSGID: 1782650661754838205 A previous patch fixes an issue with the mt8173-infracfg clock driver when working as a module, but has the side effect of skipping set up of CLK_INFRA_CLK_13M in that case. This clock is used by the timer device. Similar to the MT8183, MT8192, MT8195 and MT8186 cases [1], change the input clock of the timer block a fixed factor divide-by-2 clock that takes the 26 MHz oscillator as its input. Also remove the RTC clock from the timer node while we're here. According to commit 59311b19d7f63 ("clocksource/drivers/timer-mediatek: Add system timer bindings") it is no longer used. [1] https://lore.kernel.org/all/20221201084229.3464449-1-wenst@chromium.org/ Signed-off-by: Alper Nebi Yasak --- Tested on a MT8173 Chromebook. But I'm not sure I understand all of this, so review with a pinch of salt. Do we need to remove CLK_INFRA_CLK_13M from mt8173-infracfg after this? Changes in v2: - Add this patch arch/arm64/boot/dts/mediatek/mt8173.dtsi | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index c47d7d900f28..9062ca124d69 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -244,6 +244,15 @@ psci { cpu_on = <0x84000003>; }; + clk13m: fixed-factor-clock-13m { + compatible = "fixed-factor-clock"; + #clock-cells = <0>; + clocks = <&clk26m>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "clk13m"; + }; + clk26m: oscillator0 { compatible = "fixed-clock"; #clock-cells = <0>; @@ -530,8 +539,7 @@ timer: timer@10008000 { "mediatek,mt6577-timer"; reg = <0 0x10008000 0 0x1000>; interrupts = ; - clocks = <&infracfg CLK_INFRA_CLK_13M>, - <&topckgen CLK_TOP_RTC_SEL>; + clocks = <&clk13m>; }; pwrap: pwrap@1000d000 {