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Allow it in bindings. Signed-off-by: Konrad Dybcio --- Documentation/devicetree/bindings/iommu/arm,smmu.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 9066e6df1ba1..1897d0d4d820 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -159,7 +159,7 @@ properties: through the TCU's programming interface. power-domains: - maxItems: 1 + maxItems: 3 nvidia,memory-controller: description: | From patchwork Wed Nov 9 11:12:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 17481 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp273718wru; Wed, 9 Nov 2022 03:14:28 -0800 (PST) X-Google-Smtp-Source: AMsMyM4UiyZ9wz8TIoXVnQyoBzmr4Xfqssn3HpQ+LFHz2S1o0F3TLzGOtEz7j4quRXr1t2wEWMWu X-Received: by 2002:a05:6402:22d4:b0:461:ca0f:affc with SMTP id dm20-20020a05640222d400b00461ca0faffcmr1079235edb.169.1667992468685; Wed, 09 Nov 2022 03:14:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1667992468; cv=none; d=google.com; s=arc-20160816; b=TfWGgfdBUmZjFfKBbOjGUamsF0HGgyUSIotJjeLAUrl6clpzE7FZKWUXXAnVIVZZzd 0+uJcaS+6aLI/ckosrW+KHP7dcxid1tx8ZeslX58W7UfkgcSS4jrvbrft2SMhscucRsq cmm2nZfHaR5xdlhSZjq6v794XAC4d2HBTvapyOrUPjpIU/L/7n/5KhAgMuRiM4+wOf0+ RsmpHx9qcWkfvzkpG7hpXYPQBdpDqwszhRqGE6nuE4UkOdD7wl43oSUrklzNj/dyahlV NboR9IEy3CVEsA3bne0HlAT2AfzNxoKUw0DVeZJ6EpITGLHrGsNT7IUzwcNz8lYtVkZ5 xgLw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=f/pc7jhWkIohCmzvLPeFxuZOhmufYr1Nl7f4rSC4zF4=; b=GAlxSHqyoIdABuUHLleueorJ0VoqfQgn+k5C0XEeOTZ/iLjUL8yQjJEgF90EiJYTTM Qm6iGvMBa690sZFdltJUYhu3cJdGPdZX77z2W878+hbE9doK07Rh+SaXU5gvzBzYdpSE nSWBmEUZSpN6ogbOmtZwUxcjI5ho3CrOfIHL4HY12tCqav2yevAF6JxiTU/3NzZZT4eu dn9a0aLNHzZqv/+5If7QBMV900HRqwWKQqB9yJUdBMf24GZm3PD4n8YqK/PtKOqzLhY7 u6B6gjw8D+lz6R7Rhefyfr6cbti2uQW8SVM+NbL/Ggq2s4bj+b5Q/LLr8wMLfxz6/9yt wchw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CuYAPoJX; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/dma/qcom,gpi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml index 232895fa1d8d..e7ba1c47a88e 100644 --- a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml +++ b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml @@ -26,6 +26,7 @@ properties: - enum: - qcom,sc7280-gpi-dma - qcom,sm6115-gpi-dma + - qcom,sm6375-gpi-dma - qcom,sm8350-gpi-dma - qcom,sm8450-gpi-dma - const: qcom,sm6350-gpi-dma From patchwork Wed Nov 9 11:12:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 17491 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp274547wru; Wed, 9 Nov 2022 03:16:32 -0800 (PST) X-Google-Smtp-Source: AMsMyM5qpBbjGxKsvg5zHGRlgBBqOXzJu5cZAzdv+J+X9uzuOFgMqnmbdLwHjQ3xI/qZEeqmUlBr X-Received: by 2002:a17:906:d1c3:b0:7ae:2d6f:5a50 with SMTP id bs3-20020a170906d1c300b007ae2d6f5a50mr26232720ejb.198.1667992591932; Wed, 09 Nov 2022 03:16:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1667992591; cv=none; d=google.com; s=arc-20160816; b=zJPv1+LKUUYp+Carx2IKrOjpNuSU59wTWZEJF7UBziv0CNuRyl8KcUMMLL8KwnKiEL DEHpkoOFnAK0VpAcrIg6Uqjzuh42g0jFelCGxImxof6sDpF9bSZHMIM1l/E//GvHuBtM xZp7o/u+bcSzB4RyO3dP5pODRt0W9Tjrb6ABQZcJ6Bf2YF+j5H1li13DSaTLGWmWVciq YwN67pjqd0hYPgC0y2oNigDZcX7qLDYD6ZOiKtxYRYD3yW2jU1Pbs8+ZxzxNEE++66ei uJyfT27S/Awi/5DZ72SWbXZIfr5prX66+LOKRedmruu2+2x4AAcrYskhcgCoc8No/hZD dtsA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=dw8yiTzUnE0/1jed/kvyGb1dCoZQTp6ZbqhV1sxsfZ0=; b=08VWpcnlsNwv8k9f5AUDTh6M7IGqAoCW5kr8tP/FDcf+DV60L7CtNzcgisdwvDZBo9 xQA9ORHeltU4slKHbN2SXvX7QUrWoGVDJrKqN6JR/iW/ZxqQmbLwYtXqa7Gn0SOhNYce UjAuvtUW57DGTjS5VKkYsSaEWCjuMcQxdLRM5fL5qNnT24q4tCy2FwTWNCPFEc8ZBl+f Jw27J5vPfiR20gTbd7fNqXPwcOKv/BUoHuJPNdAhBUVNeYT0jFTn8MvavWerf9Qnn/WF R47toS+puyP+4VguebDSDo2QpmRXuMRcZJx5BXXplBn94sn7LMubq+foVmzBVD1IvWcc y4zA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LgW7dKax; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Add a DT with the SID changed to allow it to work. Unfortunately, the entire DT needs to be copied even if the diff is very little, as the node names are not unique. Including pm6125 and pmk8350 together for example, would make pmk8350 overwrite the pm6125 node, as both are defined as 'pmic@0'. Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/pmk8350_sid6.dtsi | 73 ++++++++++++++++++++++ 1 file changed, 73 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/pmk8350_sid6.dtsi diff --git a/arch/arm64/boot/dts/qcom/pmk8350_sid6.dtsi b/arch/arm64/boot/dts/qcom/pmk8350_sid6.dtsi new file mode 100644 index 000000000000..00390f8b9c97 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/pmk8350_sid6.dtsi @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) 2022, Linaro Limited + */ + +#include +#include +#include +#include + +&spmi_bus { + pmk8350: pmic@6 { + compatible = "qcom,pmk8350", "qcom,spmi-pmic"; + reg = <0x6 SPMI_USID>; + #address-cells = <1>; + #size-cells = <0>; + + pmk8350_pon: pon@1300 { + compatible = "qcom,pm8998-pon"; + reg = <0x1300>; + + pon_pwrkey: pwrkey { + compatible = "qcom,pmk8350-pwrkey"; + interrupts = <0x6 0x13 0x7 IRQ_TYPE_EDGE_BOTH>; + linux,code = ; + status = "disabled"; + }; + + pon_resin: resin { + compatible = "qcom,pmk8350-resin"; + interrupts = <0x6 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; + status = "disabled"; + }; + }; + + pmk8350_vadc: adc@3100 { + compatible = "qcom,spmi-adc7"; + reg = <0x3100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <0x6 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + #io-channel-cells = <1>; + }; + + pmk8350_adc_tm: adc-tm@3400 { + compatible = "qcom,adc-tm7"; + reg = <0x3400>; + interrupts = <0x6 0x34 0x0 IRQ_TYPE_EDGE_RISING>; + #address-cells = <1>; + #size-cells = <0>; + #thermal-sensor-cells = <1>; + status = "disabled"; + }; + + pmk8350_rtc: rtc@6100 { + compatible = "qcom,pmk8350-rtc"; + reg = <0x6100>, <0x6200>; + reg-names = "rtc", "alarm"; + interrupts = <0x6 0x62 0x1 IRQ_TYPE_EDGE_RISING>; + status = "disabled"; + }; + + pmk8350_gpios: gpio@b000 { + compatible = "qcom,pmk8350-gpio", "qcom,spmi-gpio"; + reg = <0xb000>; + gpio-controller; + gpio-ranges = <&pmk8350_gpios 0 0 4>; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; From patchwork Wed Nov 9 11:12:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 17489 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp274420wru; Wed, 9 Nov 2022 03:16:12 -0800 (PST) X-Google-Smtp-Source: AMsMyM6//vi/lfuvtLI3l+kw2raP1V/F1HFKFeC4eOjvjg7bEahudZT047mRHoP5TRHGNGG90Xz2 X-Received: by 2002:a17:906:4803:b0:7ae:958:49d4 with SMTP id w3-20020a170906480300b007ae095849d4mr33120576ejq.697.1667992572235; Wed, 09 Nov 2022 03:16:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1667992572; cv=none; d=google.com; s=arc-20160816; b=VdMRQb7C4PmW/E9NCRIQ4Qdku/xTVKZapKSgdi6oukWHCV6/qfZb+EI5hjv5t2PplK qFGlD1k+ci40n55PNwH82N0vBB32h348dMc8iUbJOVxOoi4GAqg9yfhorcKM5PexwCWU /FVch3CI6VkijB4VBxl836HvwFfW4Q3hIG27kwpTma5ZYkKbDHNEygHSS4vELVh+K0zN uCr9oHEbJ8OgE5cxs6451zA/sYC3AXMlKrtVGaQGFr7sokB8kdgQRV+JsmMAHzMA0gft uHu0tY/2njI7z/RSwXG2ou/k4wgqvb847tghRUjzNtWHCEe7mChzEKnBpZx2ORr7PTMk 8yqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Pye56l5tV+PFr5V02s5kVYgOc0gcJFpQaxO9onF9KkY=; b=EOjODlVUgYdjVoYwt4fO3TLoXZJT1f+X5iNwobzHTpP/PsM9Z17kwSRiyngZZdfk26 9RHEhUspp1EjM/0ryIIvW93NfUSyBwsuLbcurFNgeaT+lKxb2k9aiSmnsAtLW1J6gqkt 2/clmyLCusGwQbZEvJB/on+ekRt9z1tUPbIHE7UC0cvXeE3SqMNnx6cQC79Z5wiI/HgM 2u6Nej61q1JwzACkkh71ZTRbC798IW1qp6Toa3gmTPy6bJBqClqfJ++rss49rbSpdcRf Gluud3voMbQ2ZSx3gzG2+b/ziIaSsOyz1XlQWv02LvgsAYpkb4LE5137Jwp6IdMSC9Zz VBTA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BxELVLup; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 40 ++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 9b1a497e5ca7..62a64dd731a0 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -567,6 +567,46 @@ rpm_msg_ram: sram@45f0000 { reg = <0 0x045f0000 0 0x7000>; }; + gpi_dma0: dma-controller@4a00000 { + compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0 0x04a00000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + ; + dma-channels = <10>; + dma-channel-mask = <0x1f>; + iommus = <&apps_smmu 0x16 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + + gpi_dma1: dma-controller@4c00000 { + compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0 0x04c00000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + ; + dma-channels = <10>; + dma-channel-mask = <0x1f>; + iommus = <&apps_smmu 0xd6 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + usb_1: usb@4ef8800 { compatible = "qcom,sm6375-dwc3", "qcom,dwc3"; reg = <0 0x04ef8800 0 0x400>; From patchwork Wed Nov 9 11:12:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 17485 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp274020wru; Wed, 9 Nov 2022 03:15:11 -0800 (PST) X-Google-Smtp-Source: AMsMyM7bfgtTeBEwk0tsOctG7h2WXyHDDF/9gueF3S+vVO30EkXiFdUO82ej184f2dxqQN4dZ7BL X-Received: by 2002:a05:6402:1619:b0:462:b059:9655 with SMTP id f25-20020a056402161900b00462b0599655mr58418197edv.316.1667992511669; Wed, 09 Nov 2022 03:15:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1667992511; cv=none; d=google.com; s=arc-20160816; b=kYaejq10HQyrXX0VSMpphStF98YMIpDMLhAQEtdkKMiWOv0mkGALw386CqVkJLwfzG qTtKTKXOPbJjhjpIIkskLcw44uA829zuMQ/gcxFdLxyD2jgsgVvqQyb8nPebiJPswX/H 7q+fINFzmO+3btcD7fAWcF3eJCqq1pA5/hzHuhQZkdYwdQTbc8Ngt0VP2kg2EY39Mkoe WcObY0J+WXm8QTR1xqHQOstsDVGMSeIkjNetIvJfDPxrisXsEB1Cr6ien600xXY37yEa 15/sTB/SO4h8/ioO3bBM7/sDL94p2+7ILT8M9lTj4MgJ4eI46T7kkpa6mNwkNEG4IY+B cvbw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Kkk0BVciICMQdiXq3b4b24zIaTChjtWtKsRDR0Xn5SM=; b=JMXCwf6JMdmSQQMuhEodxN+xT1dRUkHDM56bMSwXfEb5n/TtPua0xKla046fz/jqMA DnwXVYDPwkdz2X/CBTrj17pg5lDULcA9LG2V6RonBA9+U9tMeNT92g7eQeOrtHAsnsSh RGMrv2RxV+u3DZp1f7ITj20fE/dIQnBiNjQnxtaRDxtGaV8kF8mPcd55PR/7Lf2CCPQq IongANttHWW6YKdQ4j4Mp0WMTrX0V3WUk5jqoBA76QwnmjxnOtHq06muS0QhvUnEWmb6 6voZvj1uR5BqG0QaE6sQnS8W0Gimi5AdcfbV6ZNgSxZ09XwkFHv8mFzoygJWt3EjODnZ mLuA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=norvNgsU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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I can guesstimate the correct settings for other buses, but: - I have no hardware to test it on - Some QUPs are straight up missing pin funcs in TLMM - Vendors probably didn't really care and used whatever was there in the reference design and BSP - should any other be used, they can be configured at a later time Signed-off-by: Konrad Dybcio Acked-by: Krzysztof Kozlowski --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 43 ++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 62a64dd731a0..952156891476 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -519,6 +519,49 @@ tlmm: pinctrl@500000 { gpio-controller; #interrupt-cells = <2>; #gpio-cells = <2>; + + qup_i2c0_default: qup-i2c0-default-state { + pins = "gpio0", "gpio1"; + function = "qup00"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c1_default: qup-i2c1-default-state { + pins = "gpio61", "gpio62"; + function = "qup01"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c2_default: qup-i2c2-default-state { + pins = "gpio45", "gpio46"; + function = "qup02"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c8_default: qup-i2c8-default-state { + pins = "gpio19", "gpio20"; + /* TLMM, GCC and vendor DT all have different indices.. */ + function = "qup12"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c10_default: qup-i2c10-default-state { + pins = "gpio4", "gpio5"; + function = "qup10"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi0_default: qup-spi0-default-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "qup00"; + drive-strength = <6>; + bias-disable; + }; }; gcc: clock-controller@1400000 { From patchwork Wed Nov 9 11:12:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 17487 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp274176wru; Wed, 9 Nov 2022 03:15:39 -0800 (PST) X-Google-Smtp-Source: AMsMyM4iU2nYtt/nhZEOdoa5xBcAXOidAM9UgDUeFiJVlsGalb5tXXRgAISoAg0DELAq/lqLTVOB X-Received: by 2002:a17:907:9603:b0:742:9ed3:3af2 with SMTP id gb3-20020a170907960300b007429ed33af2mr55924959ejc.510.1667992539587; Wed, 09 Nov 2022 03:15:39 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1667992539; cv=none; d=google.com; s=arc-20160816; b=F+UDGlvM2MpMybhcEf2f+ECZoHE68mEer8kqnjH8tld4g/I9T3bqgfg3QfsHIycTcO WHN9p/W3VLuYx9zaWgrkuo5lxVPBl+WxxlSmXU2glceqV1BpRVDfudGs2v1VWNHJ+8pF mp/VrEbN+McP8JvrwNY98/BQvagQ/15EyZ8kVH3MKN5tC+ACTH3dGZnRAnjXb1ZxAWNT FyI78FB/7ev+e9/pldyTmnnL1f4WOfS+s2QDUVGu5/5qoCo/ecXvXQt7lAIET6Az0rcr mUT9JU7rGMJvoE6JUl69LmsV/olFxRTfQjtsdGsa9JM/ind2tXEJIQfGg9pdmg9rWM0O tDDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=iAgMkFLh+A9qlmK7u0Nv6XHzT4Yq7Xys6b3k49GmNps=; b=QdrTLxlW1qik4iMa2M98hJHWoZCKTmLLo/opaldOWjh5p+ml9CIh8qA/pf3D2OURTm JvNR1D94N7FvOkMCyiqbuk9mr7KjeFi0hJEqyh2taBJpuJ1Xrq1ha0+1B+BFTonvn0Hb w7cP7grFUc1Z5oM2FzA/3upVPEyyXPS+anWBgjfMjpGVakMDn5wOjjvg1+M1o24Z5L16 1TPPAIp9z2h0QvDosiTPMvfzwo9H1+1UZ50X6FgSYffAbvfXCEdUZWPV8J4PcMFROwf9 qsK2i19JWafrupR/WSK37Wciuly13k+6/MRzH45UtlFgqm75UsQauTFyrXnkGBqdnFRI bnPQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="TE5f/I0y"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Note that: - QUP3/4/5 and 11 are straight up missing - There may be more QUPs physically on the SoC that work perfectly fine, but Qualcomm decided not to expose them on the downstream kernel - Many are missing pinctrls, as there are both missing pin funcs in the TLMM driver and missing configuration settings (though they are possible to guesstimate quite easily) Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 306 +++++++++++++++++++++++++++ 1 file changed, 306 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 952156891476..6adffd927a8e 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -317,6 +318,25 @@ CLUSTER_PD: cpu-cluster0 { }; }; + qup_opp_table: opp-table-qup { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-128000000 { + opp-hz = /bits/ 64 <128000000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -630,6 +650,125 @@ gpi_dma0: dma-controller@4a00000 { status = "disabled"; }; + qupv3_id_0: geniqup@4ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x04ac0000 0x0 0x2000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + iommus = <&apps_smmu 0x3 0x0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + i2c0: i2c@4a80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a80000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c0_default>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@4a80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a80000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi0_default>; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@4a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a84000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c1_default>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@4a84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a84000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@4a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a88000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c2_default>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@4a88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a88000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + /* + * As per GCC, QUP3/4/5/11 also exist, but are not even defined downstream. + * There is a comment in the included DTSI of another SoC saying that they + * are not "bolled out" (probably meaning not routed to solder balls) + * TLMM driver however, suggests there are as many as 15 QUPs in total! + * Most of which don't even have pin configurations for.. Sad stuff! + */ + }; + gpi_dma1: dma-controller@4c00000 { compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma"; reg = <0 0x04c00000 0 0x60000>; @@ -650,6 +789,173 @@ gpi_dma1: dma-controller@4c00000 { status = "disabled"; }; + qupv3_id_1: geniqup@4cc0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x04cc0000 0x0 0x2000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0xc3 0x0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + i2c6: i2c@4c80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04c80000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interrupts = ; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi6: spi@4c80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04c80000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@4c84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04c84000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interrupts = ; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi7: spi@4c84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04c84000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c@4c88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04c88000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c8_default>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi8: spi@4c88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04c88000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c9: i2c@4c8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04c8c000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interrupts = ; + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi9: spi@4c8c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04c8c000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c10: i2c@4c90000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04c90000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c10_default>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi10: spi@4c90000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04c90000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + usb_1: usb@4ef8800 { compatible = "qcom,sm6375-dwc3", "qcom,dwc3"; reg = <0 0x04ef8800 0 0x400>; From patchwork Wed Nov 9 11:12:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 17488 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp274301wru; Wed, 9 Nov 2022 03:15:54 -0800 (PST) X-Google-Smtp-Source: AMsMyM4aJPue4bVcCqisVY67Gb9uS3rxrYaCTHk7Dm6rJ3SkUdhv0K6Ii3XHhZvbcNLoZ9Pzw/Aj X-Received: by 2002:a17:907:7f11:b0:7ae:32b7:eb53 with SMTP id qf17-20020a1709077f1100b007ae32b7eb53mr25736940ejc.5.1667992554218; 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Signed-off-by: Konrad Dybcio --- .../qcom/sm6375-sony-xperia-murray-pdx225.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts index 450d4a557df1..6a0f4c0bf7ad 100644 --- a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts +++ b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts @@ -65,6 +65,22 @@ vph_pwr: vph-pwr-regulator { }; }; +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <13 4>; }; From patchwork Wed Nov 9 11:12:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 17493 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp275212wru; Wed, 9 Nov 2022 03:18:06 -0800 (PST) X-Google-Smtp-Source: AMsMyM7Q7KuBFVSZnptWjHONY/DVwndiQN715mQINn8/r2q1TVTc8KCfm6Bexa8dh0DxmnpnTRCv X-Received: by 2002:a05:6402:430a:b0:462:2e05:30b5 with SMTP id m10-20020a056402430a00b004622e0530b5mr58621893edc.246.1667992686337; Wed, 09 Nov 2022 03:18:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1667992686; cv=none; d=google.com; s=arc-20160816; b=zgzIB5t2IFLEGvUhIBfQEBCQk2FZpeZAlxQ+f1wYNoFowxpk+ZwBeTIizO8bGQI0e5 HnmIoffaSjZjhiuuaomisXYEHjdueYie5VwXBwcKrP0ZOr/fGYve/aeekgKZdzqTdzFf OyE4MeZYT1xx3FKDiYCrtad3IgjNdYKdKN+MMOXxsgkY4AR6DslrtZnjKjnM2RTC4FUa Oe2U1wPoGZ6UUOk+zusHbL3TqCwmalc8/S5TwpLt4O521h7ikMA1Omwrzp0i9wFyCNcj Dpp4e14+Dhp+ShvSKdLK28h4kOEr7ja0X1zknrMDQz4pr1LZYh0DGoFEZ2quL4Ej+6u8 k2xw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=6f2LrcsgR15wJRkGdfTFJiQo01CUBHznKnMZobnWz+8=; b=scOULF16EKU2japTbACmQy3c+4RHjrHmvymT54MHNf11Kpp1tfA+2b3Fpq23W4Bctt CESdTWK9jSdZJIKqNr05PD8Oj997KShZwTBDXzHv8YIpwaqIQm1aT24rxbbgSe58Rc93 cxOc2CM6H81sdEQ6zhAGIfvnJ4oOA7fYYYEu4FQOXz0dl+Q2+g84+l+p62nlahem7GDB Ltv+8bSgsihMqmcjsVwXzFjT97fWC8ntkDzbAKepCZrdQH7I9mTPyy5WsHfZdWyFanH3 1968HsrdxcPVlUjVrn2e7XFlPTCsxC13PzG3yeNOHn3VxrZ326EbQOLpyLWlDwWbvs0K DzQQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jbeyJb5o; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Konrad Dybcio --- .../qcom/sm6375-sony-xperia-murray-pdx225.dts | 22 +++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts index 6a0f4c0bf7ad..d34b4b96e1b9 100644 --- a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts +++ b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts @@ -7,8 +7,13 @@ #include #include "sm6375.dtsi" +#include "pm6125.dtsi" +#include "pmk8350_sid6.dtsi" #include "pmr735a.dtsi" +/* PM6125 PON is used and we can't have duplicate labels */ +/delete-node/ &pmk8350_pon; + / { model = "Sony Xperia 10 IV"; compatible = "sony,pdx225", "qcom,sm6375"; @@ -73,6 +78,23 @@ &gpi_dma1 { status = "okay"; }; +&pmk8350_adc_tm { + status = "okay"; +}; + +&pmk8350_rtc { + status = "okay"; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; From patchwork Wed Nov 9 11:12:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 17490 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp274495wru; Wed, 9 Nov 2022 03:16:23 -0800 (PST) X-Google-Smtp-Source: AA0mqf7VFLI5Wh1Xlu02sfjrocvPco9XLNgc8kiIG50Q/0gYl2FOQnNEMeUmmZaCVBiCDcRpjreZ X-Received: by 2002:a17:906:a157:b0:7ae:5d04:c96 with SMTP id bu23-20020a170906a15700b007ae5d040c96mr16708854ejb.564.1667992583161; Wed, 09 Nov 2022 03:16:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1667992583; cv=none; d=google.com; s=arc-20160816; b=dG56FSyf3+C+JeRDsFJbmlzjCpfFU2KrvWxcTQs8+Ok4lNR3XQeMgwMRBEAygeCWD5 LNp56QyIbJ6+qmtt2SCEmN1R6md4jufPvFweNp/oGXzPlLdIcIQq9x7YMZsINwm/tPan nm4vMU+/px3Fgq0026z+gsZGgqLZszAgI4QzKcZL+QRiL+GQ7bwLhn3eC0iDhXi1hB7k I5F7uYcA1vT+rg5jThT550x0b1O71mtY0mbxHuu1ji+9DYCEn3tlA0x8bDXriRaPxbcC EuTOVhaGWHATklH7qEnB6T+1qUp/LRvfOBaE6PRK3/oP/dMo3crWL2ce1fCz6EtSGSwt WWAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=qBu0DAqnkYkL46/OegDUIMhoEPze3QFWuGsvoEBwl2o=; b=p8StJA575xihq4YlE3CzS5YIsohvo/D6GypF3ZEfCYgQflQtFxuE6tPtY+xVt3QqOv K0sVsMznkpbfBxl6hBQuTEX19SDkaGOqaNXbbmccGvdEo8LYVh8dDBhTbfglHko4sVLZ hB1BUl/fR2sToF/+6nX0WzvpskEttrcT7EoNFzj2qaTxO4dCnwQ2brWXFQ3H2rnztTne Tb/v/Dqd2Fm+z6NwshrhdcSSVyZXzl5gt216vVTl5w/PCvv2x+OmI+YIlZgAwRIvyTDL DofNeSGRg01aH0pd/Eu64eym9RfKNHyxKxCwhvDjYrDFris4XakFy8E/6IfdImXgBtA9 G6IA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gVtzcJ1b; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Konrad Dybcio --- .../qcom/sm6375-sony-xperia-murray-pdx225.dts | 182 ++++++++++++++++++ 1 file changed, 182 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts index d34b4b96e1b9..17094e588a3a 100644 --- a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts +++ b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts @@ -95,6 +95,188 @@ &pon_resin { status = "okay"; }; +&rpm_requests { + regulators-0 { + compatible = "qcom,rpm-pm6125-regulators"; + + pm6125_s5: s5 { + regulator-min-microvolt = <382000>; + regulator-max-microvolt = <1120000>; + }; + + pm6125_s6: s6 { + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <1374000>; + }; + + pm6125_s7: s7 { + regulator-min-microvolt = <1574000>; + regulator-max-microvolt = <2040000>; + }; + + /* + * S8 is VDD_GFX + * L1 is VDD_LPI_CX + */ + + pm6125_l2: l2 { + regulator-min-microvolt = <1170000>; + regulator-max-microvolt = <1304000>; + }; + + pm6125_l3: l3 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + }; + + pm6125_l4: l4 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + }; + + pm6125_l5: l5 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3050000>; + }; + + pm6125_l6: l6 { + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + }; + + pm6125_l7: l7 { + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1050000>; + }; + + pm6125_l8: l8 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1304000>; + }; + + pm6125_l9: l9 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + }; + + pm6125_l10: l10 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + pm6125_l11: l11 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + pm6125_l12: l12 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + }; + + pm6125_l13: l13 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1980000>; + }; + + pm6125_l14: l14 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + }; + + pm6125_l15: l15 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3544000>; + }; + + pm6125_l16: l16 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + /* L17 is VDD_LPI_MX */ + + pm6125_l18: l18 { + regulator-min-microvolt = <830000>; + regulator-max-microvolt = <920000>; + }; + + pm6125_l19: l19 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <3304000>; + }; + + pm6125_l20: l20 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <3304000>; + }; + + pm6125_l21: l21 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + }; + + pm6125_l22: l22 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <3544000>; + }; + + pm6125_l23: l23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + }; + + pm6125_l24: l24 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <3544000>; + }; + }; + + regulators-1 { + compatible = "qcom,rpm-pmr735a-regulators"; + + /* + * S1 is VDD_MX + * S2 is VDD_CX + */ + + pmr735a_l1: l1 { + regulator-min-microvolt = <570000>; + regulator-max-microvolt = <650000>; + }; + + pmr735a_l2: l2 { + regulator-min-microvolt = <352000>; + regulator-max-microvolt = <796000>; + }; + + pmr735a_l3: l3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + + pmr735a_l4: l4 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + }; + + pmr735a_l5: l5 { + regulator-min-microvolt = <751000>; + regulator-max-microvolt = <824000>; + }; + + pmr735a_l6: l6 { + regulator-min-microvolt = <504000>; + regulator-max-microvolt = <868000>; + }; + + pmr735a_l7: l7 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; + }; +}; + &qupv3_id_0 { status = "okay"; }; From patchwork Wed Nov 9 11:12:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 17492 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp274622wru; Wed, 9 Nov 2022 03:16:39 -0800 (PST) X-Google-Smtp-Source: AMsMyM7LdJseQrJCXzUw1+eqeBEnu/4xc3jGfvJiYAvMd7zRU5Kbzm5vPhfQpOSavyVkRkDSj80q X-Received: by 2002:a17:907:a02:b0:7ac:9a51:3403 with SMTP id bb2-20020a1709070a0200b007ac9a513403mr57624901ejc.220.1667992598934; Wed, 09 Nov 2022 03:16:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1667992598; cv=none; d=google.com; s=arc-20160816; b=KabihZbxS0CcYIXEf5jM/Jz5ZKZ8hdy0tWMGkWbgosJAZtIheCgg7dqAdAEiAbAO8V DN4qQuZa5zlUrbGgfNJnEFeBsdDDSm1o/K1B4C35SYkSrNvVBrAqaqvnSmaGv4ZzXrpu du66IB4TN+oQ8p2uO+rr3LNfq7Rm/FzV83J1Av5ETvFz1J7iWR9mTeKEJ4xEoL+EilNc VY4snscTj+w2TgYKGpnsxhXldQ5DQOdMvBHCEfq3MH60Fkfo5pdXQNzCuQosSEU6z2R2 wERB45qiaG5M8fmFOHPqedvmNM2Cft8tgUNUAoXNHSlpiRj9/y8W4UaBDP7MWyqZ58Rj yZoA== ARC-Message-Signature: i=1; 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The OEM that built the Xperia 10 IV for SONY decided to use some kind of a GPIO regulator that needs to be enabled at all times for both the touch panel and the display panel to function. Signed-off-by: Konrad Dybcio --- .../qcom/sm6375-sony-xperia-murray-pdx225.dts | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts index 17094e588a3a..33083f18755b 100644 --- a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts +++ b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts @@ -78,6 +78,23 @@ &gpi_dma1 { status = "okay"; }; +&i2c8 { + clock-frequency = <400000>; + status = "okay"; + + touchscreen@48 { + compatible = "samsung,s6sy761"; + reg = <0x48>; + interrupt-parent = <&tlmm>; + interrupts = <22 0x2008>; + + vdd-supply = <&pm6125_l13>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_default &ts_avdd_default>; + }; +}; + &pmk8350_adc_tm { status = "okay"; }; @@ -287,6 +304,20 @@ &qupv3_id_1 { &tlmm { gpio-reserved-ranges = <13 4>; + + ts_int_default: ts-int-default-state { + pins = "gpio22"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + ts_avdd_default: ts-avdd-default-state { + pins = "gpio59"; + function = "gpio"; + drive-strength = <8>; + output-high; + }; }; &usb_1 {