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Wed, 15 Nov 2023 14:09:11 +0000 Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AFE8hnf006439 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 15 Nov 2023 14:08:43 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Wed, 15 Nov 2023 06:08:40 -0800 From: Luo Jie To: , , , , , , , , , , CC: , , , Subject: [PATCH v3 1/6] net: phylink: move phylink_pcs_neg_mode() to phylink.c Date: Wed, 15 Nov 2023 22:06:25 +0800 Message-ID: <20231115140630.10858-2-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231115140630.10858-1-quic_luoj@quicinc.com> References: <20231115140630.10858-1-quic_luoj@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: rcuT2Rurk_3x0Oxw1a63LkR82UtloGJl X-Proofpoint-GUID: rcuT2Rurk_3x0Oxw1a63LkR82UtloGJl X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-15_13,2023-11-15_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 impostorscore=0 malwarescore=0 mlxscore=0 clxscore=1015 bulkscore=0 suspectscore=0 lowpriorityscore=0 adultscore=0 phishscore=0 spamscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311150110 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Wed, 15 Nov 2023 06:10:27 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782639488792315522 X-GMAIL-MSGID: 1782639488792315522 From: Vladimir Oltean Russell points out that there is no user of phylink_pcs_neg_mode() outside of phylink.c, nor is there planned to be any, so we can just move it there. Suggested-by: Russell King (Oracle) Signed-off-by: Vladimir Oltean Signed-off-by: Luo Jie --- drivers/net/phy/phylink.c | 65 ++++++++++++++++++++++++++++++++++++++ include/linux/phylink.h | 66 --------------------------------------- 2 files changed, 65 insertions(+), 66 deletions(-) diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c index 25c19496a336..162f51b0986a 100644 --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c @@ -162,6 +162,71 @@ static const char *phylink_an_mode_str(unsigned int mode) return mode < ARRAY_SIZE(modestr) ? modestr[mode] : "unknown"; } +/** + * phylink_pcs_neg_mode() - helper to determine PCS inband mode + * @mode: one of %MLO_AN_FIXED, %MLO_AN_PHY, %MLO_AN_INBAND. + * @interface: interface mode to be used + * @advertising: adertisement ethtool link mode mask + * + * Determines the negotiation mode to be used by the PCS, and returns + * one of: + * + * - %PHYLINK_PCS_NEG_NONE: interface mode does not support inband + * - %PHYLINK_PCS_NEG_OUTBAND: an out of band mode (e.g. reading the PHY) + * will be used. + * - %PHYLINK_PCS_NEG_INBAND_DISABLED: inband mode selected but autoneg + * disabled + * - %PHYLINK_PCS_NEG_INBAND_ENABLED: inband mode selected and autoneg enabled + * + * Note: this is for cases where the PCS itself is involved in negotiation + * (e.g. Clause 37, SGMII and similar) not Clause 73. + */ +static unsigned int phylink_pcs_neg_mode(unsigned int mode, phy_interface_t interface, + const unsigned long *advertising) +{ + unsigned int neg_mode; + + switch (interface) { + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_QSGMII: + case PHY_INTERFACE_MODE_QUSGMII: + case PHY_INTERFACE_MODE_USXGMII: + /* These protocols are designed for use with a PHY which + * communicates its negotiation result back to the MAC via + * inband communication. Note: there exist PHYs that run + * with SGMII but do not send the inband data. + */ + if (!phylink_autoneg_inband(mode)) + neg_mode = PHYLINK_PCS_NEG_OUTBAND; + else + neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED; + break; + + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_2500BASEX: + /* 1000base-X is designed for use media-side for Fibre + * connections, and thus the Autoneg bit needs to be + * taken into account. We also do this for 2500base-X + * as well, but drivers may not support this, so may + * need to override this. + */ + if (!phylink_autoneg_inband(mode)) + neg_mode = PHYLINK_PCS_NEG_OUTBAND; + else if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, + advertising)) + neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED; + else + neg_mode = PHYLINK_PCS_NEG_INBAND_DISABLED; + break; + + default: + neg_mode = PHYLINK_PCS_NEG_NONE; + break; + } + + return neg_mode; +} + static unsigned int phylink_interface_signal_rate(phy_interface_t interface) { switch (interface) { diff --git a/include/linux/phylink.h b/include/linux/phylink.h index 875439ab45de..d589f89c612c 100644 --- a/include/linux/phylink.h +++ b/include/linux/phylink.h @@ -98,72 +98,6 @@ static inline bool phylink_autoneg_inband(unsigned int mode) return mode == MLO_AN_INBAND; } -/** - * phylink_pcs_neg_mode() - helper to determine PCS inband mode - * @mode: one of %MLO_AN_FIXED, %MLO_AN_PHY, %MLO_AN_INBAND. - * @interface: interface mode to be used - * @advertising: adertisement ethtool link mode mask - * - * Determines the negotiation mode to be used by the PCS, and returns - * one of: - * - * - %PHYLINK_PCS_NEG_NONE: interface mode does not support inband - * - %PHYLINK_PCS_NEG_OUTBAND: an out of band mode (e.g. reading the PHY) - * will be used. - * - %PHYLINK_PCS_NEG_INBAND_DISABLED: inband mode selected but autoneg - * disabled - * - %PHYLINK_PCS_NEG_INBAND_ENABLED: inband mode selected and autoneg enabled - * - * Note: this is for cases where the PCS itself is involved in negotiation - * (e.g. Clause 37, SGMII and similar) not Clause 73. - */ -static inline unsigned int phylink_pcs_neg_mode(unsigned int mode, - phy_interface_t interface, - const unsigned long *advertising) -{ - unsigned int neg_mode; - - switch (interface) { - case PHY_INTERFACE_MODE_SGMII: - case PHY_INTERFACE_MODE_QSGMII: - case PHY_INTERFACE_MODE_QUSGMII: - case PHY_INTERFACE_MODE_USXGMII: - /* These protocols are designed for use with a PHY which - * communicates its negotiation result back to the MAC via - * inband communication. Note: there exist PHYs that run - * with SGMII but do not send the inband data. - */ - if (!phylink_autoneg_inband(mode)) - neg_mode = PHYLINK_PCS_NEG_OUTBAND; - else - neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED; - break; - - case PHY_INTERFACE_MODE_1000BASEX: - case PHY_INTERFACE_MODE_2500BASEX: - /* 1000base-X is designed for use media-side for Fibre - * connections, and thus the Autoneg bit needs to be - * taken into account. We also do this for 2500base-X - * as well, but drivers may not support this, so may - * need to override this. - */ - if (!phylink_autoneg_inband(mode)) - neg_mode = PHYLINK_PCS_NEG_OUTBAND; - else if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, - advertising)) - neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED; - else - neg_mode = PHYLINK_PCS_NEG_INBAND_DISABLED; - break; - - default: - neg_mode = PHYLINK_PCS_NEG_NONE; - break; - } - - return neg_mode; -} - /** * struct phylink_link_state - link state structure * @advertising: ethtool bitmask containing advertised link modes From patchwork Wed Nov 15 14:06:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 165387 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b909:0:b0:403:3b70:6f57 with SMTP id t9csp2560666vqg; Wed, 15 Nov 2023 06:09:18 -0800 (PST) X-Google-Smtp-Source: AGHT+IHjeOse9OL3BesFs414Cm7D/buS/Y3rh7bZxqzeg0ulsdtCWyR52kPK/SbAIseer3kxeQyl X-Received: by 2002:a17:90b:1d07:b0:280:299d:4b7e with SMTP id on7-20020a17090b1d0700b00280299d4b7emr8379095pjb.19.1700057357982; Wed, 15 Nov 2023 06:09:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700057357; cv=none; d=google.com; s=arc-20160816; b=XNI3vCLEzPQYs/7uoeOVSBQwU3SxeiHDtJnZVaT0MAjHvW+D08S8AIj0iN1VVvQ6Zw yhEidesbety5s5LHx8wsFwdfOiJEfb1ZzxCcp37e7yiQ4srNUtV7gP5QocqXjlcIWX5u o+YPviqjMk9m6vi0lCz0uMnRjPArBpM8ZJ8pM8zS2BURrL6H8E5TFiSDpeVqUBPnqXkQ gom2tpqUFNgdEHDmjgo7+/yljjrDrDBKS4QZmBJ5HyZnkLqX2eWHv9oN2jaxKHz0ZE6e X/lHWsQOFB/3cHaDX1BSu0nJq/izGJ+rCx33xJrBlI3pscBXOqyVkZ+Ja6nRCOxRNYez j5lg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ACeIv0gd2tHOeUGVi71LfYiWOVkoF4WrCPcf1rDwtuk=; fh=CzJZH1Mq0+1gFor3WuKjwLRRL9rPD0zvQs0go/fRLgA=; b=j4cABHbtJf4ns6iViMt161ApxYB6d4+n8qC2H9fVJBdNf0uoR5XE7ZoXmLjlVWbbKU gigro5dN6vA6Kj6E9yfPzpF/2JXsWcA4xtFW4q9rG01KHAo18LrXsm+oiiWTtTnwNCAi Xclgc0buYBcC2e2xZZExTHrM5/x67Qcs/s/dEPPE+cX5RkfbpoFSWZmAf980WJPMP4j4 QlfKaSDXB4EVUva2cvl9i7G6dxYOifUTGQf+OQRPErOF1YwvcX/tVENsMwJyF9Bqh4zZ EIo24Qlg5w7fZWLDsGh6BYN8VEd5TBNhVMRa+Z5wwJMXg9lh360m/sP+ERixcJGoOkZL be+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=ZTSOYblD; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from snail.vger.email (snail.vger.email. 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Wed, 15 Nov 2023 14:08:47 +0000 Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AFE8ke7015987 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 15 Nov 2023 14:08:46 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Wed, 15 Nov 2023 06:08:43 -0800 From: Luo Jie To: , , , , , , , , , , CC: , , , Subject: [PATCH v3 2/6] net: phy: introduce core support for phy-mode = "10g-qxgmii" Date: Wed, 15 Nov 2023 22:06:26 +0800 Message-ID: <20231115140630.10858-3-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231115140630.10858-1-quic_luoj@quicinc.com> References: <20231115140630.10858-1-quic_luoj@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: aAi4rUSm8-zhoJVbyLcwMYkvYJOM742r X-Proofpoint-ORIG-GUID: aAi4rUSm8-zhoJVbyLcwMYkvYJOM742r X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-15_13,2023-11-15_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxlogscore=999 clxscore=1015 suspectscore=0 mlxscore=0 malwarescore=0 bulkscore=0 impostorscore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311150109 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 15 Nov 2023 06:09:16 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782639344346713062 X-GMAIL-MSGID: 1782639344346713062 From: Vladimir Oltean 10G-QXGMII is a MAC-to-PHY interface defined by the USXGMII multiport specification. It uses the same signaling as USXGMII, but it multiplexes 4 ports over the link, resulting in a maximum speed of 2.5G per port. Some in-tree SoCs like the NXP LS1028A use "usxgmii" when they mean either the single-port USXGMII or the quad-port 10G-QXGMII variant, and they could get away just fine with that thus far. But there is a need to distinguish between the 2 as far as SerDes drivers are concerned. Signed-off-by: Vladimir Oltean Signed-off-by: Luo Jie --- .../devicetree/bindings/net/ethernet-controller.yaml | 1 + Documentation/networking/phy.rst | 6 ++++++ drivers/net/phy/phy-core.c | 1 + drivers/net/phy/phylink.c | 12 ++++++++++-- include/linux/phy.h | 4 ++++ include/linux/phylink.h | 1 + 6 files changed, 23 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml b/Documentation/devicetree/bindings/net/ethernet-controller.yaml index 9f6a5ccbcefe..044880d804db 100644 --- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml @@ -104,6 +104,7 @@ properties: - usxgmii - 10gbase-r - 25gbase-r + - 10g-qxgmii phy-mode: $ref: "#/properties/phy-connection-type" diff --git a/Documentation/networking/phy.rst b/Documentation/networking/phy.rst index 1283240d7620..f64641417c54 100644 --- a/Documentation/networking/phy.rst +++ b/Documentation/networking/phy.rst @@ -327,6 +327,12 @@ Some of the interface modes are described below: This is the Penta SGMII mode, it is similar to QSGMII but it combines 5 SGMII lines into a single link compared to 4 on QSGMII. +``PHY_INTERFACE_MODE_10G_QXGMII`` + Represents the 10G-QXGMII PHY-MAC interface as defined by the Cisco USXGMII + Multiport Copper Interface document. It supports 4 ports over a 10.3125 GHz + SerDes lane, each port having speeds of 2.5G / 1G / 100M / 10M achieved + through symbol replication. The PCS expects the standard USXGMII code word. + Pause frames / flow control =========================== diff --git a/drivers/net/phy/phy-core.c b/drivers/net/phy/phy-core.c index 966c93cbe616..1cd58723d6d0 100644 --- a/drivers/net/phy/phy-core.c +++ b/drivers/net/phy/phy-core.c @@ -141,6 +141,7 @@ int phy_interface_num_ports(phy_interface_t interface) return 1; case PHY_INTERFACE_MODE_QSGMII: case PHY_INTERFACE_MODE_QUSGMII: + case PHY_INTERFACE_MODE_10G_QXGMII: return 4; case PHY_INTERFACE_MODE_PSGMII: return 5; diff --git a/drivers/net/phy/phylink.c b/drivers/net/phy/phylink.c index 162f51b0986a..e9ab20bd6984 100644 --- a/drivers/net/phy/phylink.c +++ b/drivers/net/phy/phylink.c @@ -191,6 +191,7 @@ static unsigned int phylink_pcs_neg_mode(unsigned int mode, phy_interface_t inte case PHY_INTERFACE_MODE_QSGMII: case PHY_INTERFACE_MODE_QUSGMII: case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10G_QXGMII: /* These protocols are designed for use with a PHY which * communicates its negotiation result back to the MAC via * inband communication. Note: there exist PHYs that run @@ -283,6 +284,7 @@ static int phylink_interface_max_speed(phy_interface_t interface) return SPEED_1000; case PHY_INTERFACE_MODE_2500BASEX: + case PHY_INTERFACE_MODE_10G_QXGMII: return SPEED_2500; case PHY_INTERFACE_MODE_5GBASER: @@ -552,7 +554,11 @@ static unsigned long phylink_get_capabilities(phy_interface_t interface, switch (interface) { case PHY_INTERFACE_MODE_USXGMII: - caps |= MAC_10000FD | MAC_5000FD | MAC_2500FD; + caps |= MAC_10000FD | MAC_5000FD; + fallthrough; + + case PHY_INTERFACE_MODE_10G_QXGMII: + caps |= MAC_2500FD; fallthrough; case PHY_INTERFACE_MODE_RGMII_TXID: @@ -972,6 +978,7 @@ static int phylink_parse_mode(struct phylink *pl, phylink_set(pl->supported, 25000baseSR_Full); fallthrough; case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10G_QXGMII: case PHY_INTERFACE_MODE_10GKR: case PHY_INTERFACE_MODE_10GBASER: phylink_set(pl->supported, 10baseT_Half); @@ -1844,7 +1851,8 @@ static int phylink_bringup_phy(struct phylink *pl, struct phy_device *phy, if (phy->is_c45 && config.rate_matching == RATE_MATCH_NONE && interface != PHY_INTERFACE_MODE_RXAUI && interface != PHY_INTERFACE_MODE_XAUI && - interface != PHY_INTERFACE_MODE_USXGMII) + interface != PHY_INTERFACE_MODE_USXGMII && + interface != PHY_INTERFACE_MODE_10G_QXGMII) config.interface = PHY_INTERFACE_MODE_NA; else config.interface = interface; diff --git a/include/linux/phy.h b/include/linux/phy.h index 3cc52826f18e..e0af0378e2a1 100644 --- a/include/linux/phy.h +++ b/include/linux/phy.h @@ -125,6 +125,7 @@ extern const int phy_10gbit_features_array[1]; * @PHY_INTERFACE_MODE_10GKR: 10GBASE-KR - with Clause 73 AN * @PHY_INTERFACE_MODE_QUSGMII: Quad Universal SGMII * @PHY_INTERFACE_MODE_1000BASEKX: 1000Base-KX - with Clause 73 AN + * @PHY_INTERFACE_MODE_10G_QXGMII: 10G-QXGMII - 4 ports over 10G USXGMII * @PHY_INTERFACE_MODE_MAX: Book keeping * * Describes the interface between the MAC and PHY. @@ -165,6 +166,7 @@ typedef enum { PHY_INTERFACE_MODE_10GKR, PHY_INTERFACE_MODE_QUSGMII, PHY_INTERFACE_MODE_1000BASEKX, + PHY_INTERFACE_MODE_10G_QXGMII, PHY_INTERFACE_MODE_MAX, } phy_interface_t; @@ -286,6 +288,8 @@ static inline const char *phy_modes(phy_interface_t interface) return "100base-x"; case PHY_INTERFACE_MODE_QUSGMII: return "qusgmii"; + case PHY_INTERFACE_MODE_10G_QXGMII: + return "10g-qxgmii"; default: return "unknown"; } diff --git a/include/linux/phylink.h b/include/linux/phylink.h index d589f89c612c..d7e32c9f3ae1 100644 --- a/include/linux/phylink.h +++ b/include/linux/phylink.h @@ -614,6 +614,7 @@ static inline int phylink_get_link_timer_ns(phy_interface_t interface) case PHY_INTERFACE_MODE_SGMII: case PHY_INTERFACE_MODE_QSGMII: case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10G_QXGMII: return 1600000; case PHY_INTERFACE_MODE_1000BASEX: From patchwork Wed Nov 15 14:06:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 165391 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b909:0:b0:403:3b70:6f57 with SMTP id t9csp2561239vqg; Wed, 15 Nov 2023 06:10:00 -0800 (PST) X-Google-Smtp-Source: AGHT+IG2JGcwDDGPEurlxIqhABGXe1OVLcVaVKPcHqtZ/KSHXiwoXMHYa4cNmqnqE3/udg3rG+vN X-Received: by 2002:a05:6830:1e99:b0:6bf:1925:13a0 with SMTP id n25-20020a0568301e9900b006bf192513a0mr5403502otr.33.1700057400521; Wed, 15 Nov 2023 06:10:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700057400; cv=none; d=google.com; s=arc-20160816; b=fbyfucDyl1F8a2S7bbJlco1BqhiN0GgU3CzUC5yS33Xs2bs2g6M5rDajRVw63RAvt5 ejW2pc/w+QuAIUX7wQjUEDXvW4utYN8BIVARUK2XqKH3MOxKl1F6TxhHCGq0RbkMd8JA IRdgZ8xXbKXn2/Kz8MyMgXGF3KzGV/Pg9CPUZ1/CBPQGeO58+2ChJijVxQ/JKD7dZ21f g1v9VhpLMt/emwof4VTq9ocwhxFFWVFXJIV2gb6go9ULdqvLagZgDvFChOvyUgAh1QyF Q3Z7ozNBbTXfS9MIVDz5uQuk3Iv18u1+K6EHfyoFf5BYAey+sjPRZx+T6bGZzCfSUmMG 4Qzg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=lbd+Zrs6s/evKvo0xLI+MWTKrpEWpt+Gp3cYTw1rZk8=; fh=CzJZH1Mq0+1gFor3WuKjwLRRL9rPD0zvQs0go/fRLgA=; b=CcXctnAo3tWsK03AQkRTV5dYWE9NpmrHlJE6cm0T3zUlw7uRAI7GbgpxwGf8WGhSUp qJN0kWjEYQ4nn85wL0ScISCrdpqkZYihzDhGEa/f4PH4cWj6c1J96hMml+itdANR2nrN c439XSrLVJYrE5mnMQJDCVwH7Wsu+PgeMRIF/WBJoaLUjThrYZM/XIcf16o4OK4vxFSN t5zgE2R+0cyq1I/Axzj0N43AvCgOKSmMZDfzMomWoujKuzkcMhDlWwtz8WCwgHl4Q2Ke jLv+v1PnsIxzWi2/U0YXRieRk9qM02+CToMf81H/l4big2S23iD4vYhQoQoEYGRN/8B6 18BQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=k1AInPWw; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from lipwig.vger.email (lipwig.vger.email. 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Wed, 15 Nov 2023 06:09:56 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782639388995227466 X-GMAIL-MSGID: 1782639388995227466 Add qca8084 PHY support, which is four-port PHY with maximum link capability 2.5G, the features of each port is almost same as QCA8081 and slave seed config is not needed. Three kind of interface modes supported by qca8084. PHY_INTERFACE_MODE_10G_QXGMII, PHY_INTERFACE_MODE_2500BASEX and PHY_INTERFACE_MODE_SGMII. The PCS(serdes) and clock are also needed to be configured to bringup qca8084 PHY, which will be added in the pcs driver. The additional CDT configurations used for qca8084. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 48 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index 37fb033e1c29..471d5c13d76d 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -176,6 +176,7 @@ #define AT8030_PHY_ID_MASK 0xffffffef #define QCA8081_PHY_ID 0x004dd101 +#define QCA8084_PHY_ID 0x004dd180 #define QCA8327_A_PHY_ID 0x004dd033 #define QCA8327_B_PHY_ID 0x004dd034 @@ -1760,6 +1761,9 @@ static bool qca808x_is_prefer_master(struct phy_device *phydev) static bool qca808x_has_fast_retrain_or_slave_seed(struct phy_device *phydev) { + if (phydev_id_compare(phydev, QCA8084_PHY_ID)) + return false; + return linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported); } @@ -1824,6 +1828,21 @@ static int qca808x_read_status(struct phy_device *phydev) return ret; if (phydev->link) { + /* There are two PCSs available for QCA8084, which support the following + * interface modes. + * + * 1. PHY_INTERFACE_MODE_10G_QXGMII utilizes PCS1 for all available 4 ports, + * which is for all link speeds. + * + * 2. PHY_INTERFACE_MODE_2500BASEX utilizes PCS0 for the fourth port, + * which is only for the link speed 2500M same as QCA8081. + * + * 3. PHY_INTERFACE_MODE_SGMII utilizes PCS0 for the fourth port, + * which is for the link speed 10M, 100M and 1000M same as QCA8081. + */ + if (phydev->interface == PHY_INTERFACE_MODE_10G_QXGMII) + return 0; + if (phydev->speed == SPEED_2500) phydev->interface = PHY_INTERFACE_MODE_2500BASEX; else @@ -1958,6 +1977,14 @@ static int qca808x_cable_test_start(struct phy_device *phydev) phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060); phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060); + if (phydev_id_compare(phydev, QCA8084_PHY_ID)) { + /* Adjust the positive and negative pulse thereshold of CDT */ + phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8075, 0xa060); + + /* Disable the near echo bypass */ + phy_modify_mmd(phydev, MDIO_MMD_PCS, 0x807f, BIT(15), 0); + } + return 0; } @@ -2227,6 +2254,26 @@ static struct phy_driver at803x_driver[] = { .cable_test_start = qca808x_cable_test_start, .cable_test_get_status = qca808x_cable_test_get_status, .link_change_notify = qca808x_link_change_notify, +}, { + /* Qualcomm QCA8084 */ + PHY_ID_MATCH_MODEL(QCA8084_PHY_ID), + .name = "Qualcomm QCA8084", + .flags = PHY_POLL_CABLE_TEST, + .probe = at803x_probe, + .config_intr = at803x_config_intr, + .handle_interrupt = at803x_handle_interrupt, + .get_tunable = at803x_get_tunable, + .set_tunable = at803x_set_tunable, + .set_wol = at803x_set_wol, + .get_wol = at803x_get_wol, + .get_features = qca808x_get_features, + .config_aneg = at803x_config_aneg, + .suspend = genphy_suspend, + .resume = genphy_resume, + .read_status = qca808x_read_status, + .soft_reset = qca808x_soft_reset, + .cable_test_start = qca808x_cable_test_start, + .cable_test_get_status = qca808x_cable_test_get_status, }, }; module_phy_driver(at803x_driver); @@ -2242,6 +2289,7 @@ static struct mdio_device_id __maybe_unused atheros_tbl[] = { { PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) }, { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) }, { PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) }, + { PHY_ID_MATCH_MODEL(QCA8084_PHY_ID) }, { } }; From patchwork Wed Nov 15 14:06:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 165388 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b909:0:b0:403:3b70:6f57 with SMTP id t9csp2560766vqg; Wed, 15 Nov 2023 06:09:26 -0800 (PST) X-Google-Smtp-Source: AGHT+IF6YtiZ+0njZDjpAJbIHSuVxIsgIgwSqeH9bOtv7lMhmvfv/d5xxdCMLU3OyyH9pNBic026 X-Received: by 2002:a17:902:d389:b0:1cc:3ae2:493f with SMTP id e9-20020a170902d38900b001cc3ae2493fmr5355620pld.65.1700057366430; Wed, 15 Nov 2023 06:09:26 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700057366; cv=none; d=google.com; s=arc-20160816; b=jjpcY9D3OqRr68T1/iITH4IPn1dRGwzcNAQ6XqzJwpUmxDux3aLGiz2s18HrQG2XU6 6uB919xeFrN5PPFQ+U3kpD9w/C6aEkEV2whTny29es7scu61PulN7B5dtA1q7M1uYWe3 b3pVZkEf0Y016NIiNPSsyvuuj9t3en00Qhy5neyCKWqkvmMg31RXGEpUEBQs1SRama5v a/AMFpZOC+drHSyWKzFL8v8HPHn54vwQ2p6MBsTfvvaZ9yGJOU2zEMroUhbofm+QZJ6n aaCGMTu3gpO6Cv15Zk52uA6czPBjHIeHjfYNWIJo0rQ1RxPiLP13EJzfFxkCU3IZc+vV NgJQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=CLpJvxEOJWPI/XnaXTlnX9ueptBWpRe+/Nh9WcXUebo=; fh=CzJZH1Mq0+1gFor3WuKjwLRRL9rPD0zvQs0go/fRLgA=; b=i8fh+Hirm5eDXauu89OEagPPFRSI+tA/OTDfQd1SH/QnmlFpAnoCD77Z5VJY+2OG0B WY+KmYluf6zx+pu9VFFUAgh44U+Bxykv510TX6Oh/KC7mUTUjdSm8w0yMRnLYSIMFFNx H8aRYE3w6AtCA9d/v4KKz0UkBJqvzOSb/G4OtbIEEaueOYiEF0VYpeDtwDiyi4UWiT9a Lxak3IwHFgw0+iWverW3lk7DxYIIY5t0Yc2rUx9MkDMuxQL0maW8E2owYPuAlZ0UX0FW HLkd09cphUYcLQYYI9aI1Yh0u/PfX2NBeuAKdYs+M0hz8uuRB/FIrcj72UWb9pmbF4XM 35yA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=pzgMqZRH; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from snail.vger.email (snail.vger.email. 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Wed, 15 Nov 2023 06:09:21 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782639353033826346 X-GMAIL-MSGID: 1782639353033826346 The function phydev_id_is_qca808x is applicable to the PHY qca8081 and qca8084. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index 471d5c13d76d..f56202f5944d 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -1165,6 +1165,12 @@ static void at803x_link_change_notify(struct phy_device *phydev) } } +static inline bool phydev_id_is_qca808x(struct phy_device *phydev) +{ + return phydev_id_compare(phydev, QCA8081_PHY_ID) || + phydev_id_compare(phydev, QCA8084_PHY_ID); +} + static int at803x_read_specific_status(struct phy_device *phydev) { int ss; @@ -1184,8 +1190,8 @@ static int at803x_read_specific_status(struct phy_device *phydev) if (sfc < 0) return sfc; - /* qca8081 takes the different bits for speed value from at803x */ - if (phydev->drv->phy_id == QCA8081_PHY_ID) + /* qca808x takes the different bits for speed value from at803x */ + if (phydev_id_is_qca808x(phydev)) speed = FIELD_GET(QCA808X_SS_SPEED_MASK, ss); else speed = FIELD_GET(AT803X_SS_SPEED_MASK, ss); @@ -1316,7 +1322,7 @@ static int at803x_config_aneg(struct phy_device *phydev) */ ret = 0; - if (phydev->drv->phy_id == QCA8081_PHY_ID) { + if (phydev_id_is_qca808x(phydev)) { int phy_ctrl = 0; /* The reg MII_BMCR also needs to be configured for force mode, the @@ -1470,8 +1476,8 @@ static int at803x_cdt_start(struct phy_device *phydev, int pair) { u16 cdt; - /* qca8081 takes the different bit 15 to enable CDT test */ - if (phydev->drv->phy_id == QCA8081_PHY_ID) + /* qca808x takes the different bit 15 to enable CDT test */ + if (phydev_id_is_qca808x(phydev)) cdt = QCA808X_CDT_ENABLE_TEST | QCA808X_CDT_LENGTH_UNIT | QCA808X_CDT_INTER_CHECK_DIS; @@ -1487,7 +1493,7 @@ static int at803x_cdt_wait_for_completion(struct phy_device *phydev) int val, ret; u16 cdt_en; - if (phydev->drv->phy_id == QCA8081_PHY_ID) + if (phydev_id_is_qca808x(phydev)) cdt_en = QCA808X_CDT_ENABLE_TEST; else cdt_en = AT803X_CDT_ENABLE_TEST; From patchwork Wed Nov 15 14:06:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 165390 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b909:0:b0:403:3b70:6f57 with SMTP id t9csp2561141vqg; Wed, 15 Nov 2023 06:09:52 -0800 (PST) X-Google-Smtp-Source: AGHT+IHQcD42yGGJ5fAVzEwq50PgsRx8JvUEX6Mrxj3+DK4Dk/3KzS0/tc7edrMSDOlkIZJWPWSz X-Received: by 2002:a05:6808:6546:b0:3a9:c647:c9ca with SMTP id fn6-20020a056808654600b003a9c647c9camr18208980oib.5.1700057392410; Wed, 15 Nov 2023 06:09:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700057392; cv=none; d=google.com; s=arc-20160816; b=m2HAXFlu6VkvbMi/UhALdymToDqr6z9JRomHyCV7a9vSuxQ1xK1BbpRZb1UqbClwc1 xV8jTuQHG8PHMVHR3J4kkYGr+5wyG9Aks3AHF9ALrG8A2HyZEXmHty48gDjkHP6dhiw1 mL93X/gNVhOmszb9WLziaZboorF6cac8Oh8L1sBr20bEb1sd+3IPet4KhNjYzcWiFiUs K54eI1+zgWcYVARF6VzM2F2Bv6969lvftkFW3lKcsLUHRoBTx+dLjRMWt8JFQV+N1YG+ zL231ZW6cmmQpslRToQIAjAGMmyrjo+ABB20b3Wsm60EmD50kjcLJwT0mNYZrmd2BJ5f Pshg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=xoUh7MWwDswQU0Qbcu6kSaukCEbi0jZ75coOg98MRMg=; fh=CzJZH1Mq0+1gFor3WuKjwLRRL9rPD0zvQs0go/fRLgA=; b=XeUdbkCJmBxGwdjKeU98PMYznQnmsKe9uDkEyOOepo94CKaUMbvtv4RrJUkQsbruiX bqCbqCY0L+9H85eujeE4LmU9t9U6z05bIeU9y2oNtHUNAjlD3HNNrG+wpiobigVogJw3 fGzFcxJa10c9RgADY/LgpZg0x48mj2qiFPVEbzSbWrhK/H5OqRrXTVVuaDdch3fu86+a ERFna3ZVr22exXZFmydVHwBblby5sdctmIjrBAUtWMyRneuVIzEpBzFygtE1xhJSuoHy ZHqa0+cFrGIquGGsi9kUoRG5P5DHEdjja8veaDiWush11mYiokYkrL8/QAKdAlhQefqB DTTw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b="K5PK/9VB"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from snail.vger.email (snail.vger.email. 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Wed, 15 Nov 2023 06:09:51 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782639380398086721 X-GMAIL-MSGID: 1782639380398086721 Configure MSE detect threshold and ADC clock edge invert. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 27 +++++++++++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index f56202f5944d..06a068ca5539 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -280,6 +280,15 @@ #define QCA8081_PHY_SERDES_MMD1_FIFO_CTRL 0x9072 #define QCA8081_PHY_FIFO_RSTN BIT(11) +/* QCA8084 ADC clock edge */ +#define QCA8084_ADC_CLK_SEL 0x8b80 +#define QCA8084_ADC_CLK_SEL_ACLK GENMASK(7, 4) +#define QCA8084_ADC_CLK_SEL_ACLK_FALL 0xf +#define QCA8084_ADC_CLK_SEL_ACLK_RISE 0x0 + +#define QCA8084_MSE_THRESHOLD 0x800a +#define QCA8084_MSE_THRESHOLD_2P5G_VAL 0x51c6 + MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); MODULE_AUTHOR("Matus Ujhelyi"); MODULE_LICENSE("GPL"); @@ -2083,6 +2092,23 @@ static void qca808x_link_change_notify(struct phy_device *phydev) QCA8081_PHY_FIFO_RSTN, phydev->link ? QCA8081_PHY_FIFO_RSTN : 0); } +static int qca8084_config_init(struct phy_device *phydev) +{ + int ret; + + /* Invert ADC clock edge */ + ret = at803x_debug_reg_mask(phydev, QCA8084_ADC_CLK_SEL, + QCA8084_ADC_CLK_SEL_ACLK, + FIELD_PREP(QCA8084_ADC_CLK_SEL_ACLK, + QCA8084_ADC_CLK_SEL_ACLK_FALL)); + if (ret < 0) + return ret; + + /* Adjust MSE threshold value to avoid link issue with some link partner */ + return phy_write_mmd(phydev, MDIO_MMD_PMAPMD, + QCA8084_MSE_THRESHOLD, QCA8084_MSE_THRESHOLD_2P5G_VAL); +} + static struct phy_driver at803x_driver[] = { { /* Qualcomm Atheros AR8035 */ @@ -2280,6 +2306,7 @@ static struct phy_driver at803x_driver[] = { .soft_reset = qca808x_soft_reset, .cable_test_start = qca808x_cable_test_start, .cable_test_get_status = qca808x_cable_test_get_status, + .config_init = qca8084_config_init, }, }; module_phy_driver(at803x_driver); From patchwork Wed Nov 15 14:06:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 165389 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b909:0:b0:403:3b70:6f57 with SMTP id t9csp2561008vqg; Wed, 15 Nov 2023 06:09:42 -0800 (PST) X-Google-Smtp-Source: AGHT+IH50mNWxz1H/ZiOs+W70+NX4ZE+67yv70Sc3BX+HF9WG5S5evgySGg6Wn/J3rsXUagg5Pjy X-Received: by 2002:a05:6808:998:b0:3a8:432a:ea13 with SMTP id a24-20020a056808099800b003a8432aea13mr15629896oic.46.1700057382664; Wed, 15 Nov 2023 06:09:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700057382; cv=none; d=google.com; s=arc-20160816; b=OG5bo9WOG7Yj+tqgDhBp87N3ilvMt5EDiMHn9/75D7mheGicz1t6Un1lziYasMPQpD 2tjrpV6QLKQfaucv2kXrqCLbtLiVaq56J6yrPYF811EhqrmpCy7n9Yz7H21PV9mLotpj SX2qTIIVuBnk26248ki6LFe7pGbJA11yilg0sOGZLy4jgrr6GohmZFKqbwLl/cTpNnst L2qGl6k1nG1dfcvrnDaNDp2IkMSiYxSRvpDEVBJrbsdo4tZEnDcu0Q3zK4tGh6kiygFI iQccg4CIT64Rcgzk3jQA1/m/LPcXB2X2HV63TAW6Juh60VQQS1CkJO7EBNNLGUcvjWwE qvhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=uxMZ5i08IIj1P3XHjsuTSAB7PjcYnIlgE+t3bDDRN3U=; fh=CzJZH1Mq0+1gFor3WuKjwLRRL9rPD0zvQs0go/fRLgA=; b=kE1UNhfrL1R6QJFvBJroeHwTrCwC/tl1K4o0uH4EnJwy7wBVdKzSfDavbcNUTamcV1 seiiuXBlUoQWIcfhT2v47aBNgqJ6yxsR83FcMeGEb+fxZywMmdL+8R2nr0q1yOkZH2vE pDQ+KOYVakNXET7uxEs2w2GAE+yUzAL1BRIDEd6/hP10DVrYJr2VCDb0NUjabAzrzElA 8JW/COMS+R/N+1pY60jd0uebcsd2Bipx0VHYHAASb+oGuhAU9F9pZvj6HMYyQk6ViCn4 wsPXv29UfxeJduBtTA0OE8ZEtePpnxAOGzM0Sdk0bEkp84DAgXGEi7glMg/o52iHAJ6F d2Ag== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=VauVzqMg; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from lipwig.vger.email (lipwig.vger.email. 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Wed, 15 Nov 2023 14:09:00 +0000 Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AFE8xA3025907 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 15 Nov 2023 14:08:59 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Wed, 15 Nov 2023 06:08:56 -0800 From: Luo Jie To: , , , , , , , , , , CC: , , , Subject: [PATCH v3 6/6] net: phy: qca8084: add qca8084_link_change_notify Date: Wed, 15 Nov 2023 22:06:30 +0800 Message-ID: <20231115140630.10858-7-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231115140630.10858-1-quic_luoj@quicinc.com> References: <20231115140630.10858-1-quic_luoj@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: N0jsMtbKAqLZ6WNTZscxJ4XS3MsUe4uF X-Proofpoint-ORIG-GUID: N0jsMtbKAqLZ6WNTZscxJ4XS3MsUe4uF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-15_13,2023-11-15_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 mlxlogscore=999 clxscore=1015 suspectscore=0 mlxscore=0 malwarescore=0 bulkscore=0 impostorscore=0 adultscore=0 lowpriorityscore=0 priorityscore=1501 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311150109 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Wed, 15 Nov 2023 06:09:37 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782639370047484000 X-GMAIL-MSGID: 1782639370047484000 When the link is changed, qca8084 needs to do the fifo reset and adjust the IPG level for the qusgmii link speed 1000M. Signed-off-by: Luo Jie --- drivers/net/phy/at803x.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/net/phy/at803x.c b/drivers/net/phy/at803x.c index 06a068ca5539..7267ce858937 100644 --- a/drivers/net/phy/at803x.c +++ b/drivers/net/phy/at803x.c @@ -289,6 +289,13 @@ #define QCA8084_MSE_THRESHOLD 0x800a #define QCA8084_MSE_THRESHOLD_2P5G_VAL 0x51c6 +#define QCA8084_FIFO_CONTROL 0x19 +#define QCA8084_FIFO_MAC_2_PHY BIT(1) +#define QCA8084_FIFO_PHY_2_MAC BIT(0) + +#define QCA8084_MMD7_IPG_OP 0x901d +#define QCA8084_IPG_10_TO_11_EN BIT(0) + MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver"); MODULE_AUTHOR("Matus Ujhelyi"); MODULE_LICENSE("GPL"); @@ -2109,6 +2116,35 @@ static int qca8084_config_init(struct phy_device *phydev) QCA8084_MSE_THRESHOLD, QCA8084_MSE_THRESHOLD_2P5G_VAL); } +static void qca8084_link_change_notify(struct phy_device *phydev) +{ + int ret; + + ret = phy_modify(phydev, QCA8084_FIFO_CONTROL, + QCA8084_FIFO_MAC_2_PHY | QCA8084_FIFO_PHY_2_MAC, + 0); + if (ret) + return; + + /* If the PHY works on PHY_INTERFACE_MODE_10G_QXGMII mode, the fifo needs to + * be kept as reset state in link down status. + */ + if (phydev->interface != PHY_INTERFACE_MODE_10G_QXGMII || phydev->link) { + msleep(50); + ret = phy_modify(phydev, QCA8084_FIFO_CONTROL, + QCA8084_FIFO_MAC_2_PHY | QCA8084_FIFO_PHY_2_MAC, + QCA8084_FIFO_MAC_2_PHY | QCA8084_FIFO_PHY_2_MAC); + if (ret) + return; + } + + /* Enable IPG 10 to 11 tuning on link speed 1000M of QUSGMII mode. */ + if (phydev->interface == PHY_INTERFACE_MODE_10G_QXGMII) + phy_modify_mmd(phydev, MDIO_MMD_AN, QCA8084_MMD7_IPG_OP, + QCA8084_IPG_10_TO_11_EN, + phydev->speed == SPEED_1000 ? QCA8084_IPG_10_TO_11_EN : 0); +} + static struct phy_driver at803x_driver[] = { { /* Qualcomm Atheros AR8035 */ @@ -2307,6 +2343,7 @@ static struct phy_driver at803x_driver[] = { .cable_test_start = qca808x_cable_test_start, .cable_test_get_status = qca808x_cable_test_get_status, .config_init = qca8084_config_init, + .link_change_notify = qca8084_link_change_notify, }, }; module_phy_driver(at803x_driver);