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Wed, 15 Nov 2023 03:25:35 +0000 Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AF3PZvZ016141 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 15 Nov 2023 03:25:35 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Tue, 14 Nov 2023 19:25:30 -0800 From: Luo Jie To: , , , , , , , , , , , , , CC: , , , , Subject: [PATCH 1/9] net: mdio: ipq4019: increase eth_ldo_rdy for ipq5332 platform Date: Wed, 15 Nov 2023 11:25:07 +0800 Message-ID: <20231115032515.4249-2-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231115032515.4249-1-quic_luoj@quicinc.com> References: <20231115032515.4249-1-quic_luoj@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: _wE0V0DvETp7XIFPwrxmAuugPYZkJuh9 X-Proofpoint-GUID: _wE0V0DvETp7XIFPwrxmAuugPYZkJuh9 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-15_01,2023-11-14_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 adultscore=0 clxscore=1015 spamscore=0 bulkscore=0 phishscore=0 mlxscore=0 mlxlogscore=999 priorityscore=1501 suspectscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311150027 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Tue, 14 Nov 2023 19:26:32 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782598929470145483 X-GMAIL-MSGID: 1782598929470145483 There are two PCS(UNIPHY) supported in SOC side on ipq5332, and three PCS(UNIPHY) supported on ipq9574. Signed-off-by: Luo Jie --- drivers/net/mdio/mdio-ipq4019.c | 55 +++++++++++++++++++-------------- 1 file changed, 32 insertions(+), 23 deletions(-) diff --git a/drivers/net/mdio/mdio-ipq4019.c b/drivers/net/mdio/mdio-ipq4019.c index abd8b508ec16..9d444f5f7efb 100644 --- a/drivers/net/mdio/mdio-ipq4019.c +++ b/drivers/net/mdio/mdio-ipq4019.c @@ -18,28 +18,31 @@ #define MDIO_DATA_WRITE_REG 0x48 #define MDIO_DATA_READ_REG 0x4c #define MDIO_CMD_REG 0x50 -#define MDIO_CMD_ACCESS_BUSY BIT(16) -#define MDIO_CMD_ACCESS_START BIT(8) -#define MDIO_CMD_ACCESS_CODE_READ 0 -#define MDIO_CMD_ACCESS_CODE_WRITE 1 -#define MDIO_CMD_ACCESS_CODE_C45_ADDR 0 -#define MDIO_CMD_ACCESS_CODE_C45_WRITE 1 -#define MDIO_CMD_ACCESS_CODE_C45_READ 2 +#define MDIO_CMD_ACCESS_BUSY BIT(16) +#define MDIO_CMD_ACCESS_START BIT(8) +#define MDIO_CMD_ACCESS_CODE_READ 0 +#define MDIO_CMD_ACCESS_CODE_WRITE 1 +#define MDIO_CMD_ACCESS_CODE_C45_ADDR 0 +#define MDIO_CMD_ACCESS_CODE_C45_WRITE 1 +#define MDIO_CMD_ACCESS_CODE_C45_READ 2 /* 0 = Clause 22, 1 = Clause 45 */ #define MDIO_MODE_C45 BIT(8) -#define IPQ4019_MDIO_TIMEOUT 10000 -#define IPQ4019_MDIO_SLEEP 10 +#define IPQ4019_MDIO_TIMEOUT 10000 +#define IPQ4019_MDIO_SLEEP 10 /* MDIO clock source frequency is fixed to 100M */ -#define IPQ_MDIO_CLK_RATE 100000000 +#define IPQ_MDIO_CLK_RATE 100000000 -#define IPQ_PHY_SET_DELAY_US 100000 +#define IPQ_PHY_SET_DELAY_US 100000 + +/* Maximum SOC PCS(uniphy) number on IPQ platform */ +#define ETH_LDO_RDY_CNT 3 struct ipq4019_mdio_data { - void __iomem *membase; - void __iomem *eth_ldo_rdy; + void __iomem *membase; + void __iomem *eth_ldo_rdy[ETH_LDO_RDY_CNT]; struct clk *mdio_clk; }; @@ -210,13 +213,15 @@ static int ipq_mdio_reset(struct mii_bus *bus) int ret; /* To indicate CMN_PLL that ethernet_ldo has been ready if platform resource 1 - * is specified in the device tree. + * or more resource are specified in the device tree. */ - if (priv->eth_ldo_rdy) { - val = readl(priv->eth_ldo_rdy); - val |= BIT(0); - writel(val, priv->eth_ldo_rdy); - fsleep(IPQ_PHY_SET_DELAY_US); + for (ret = 0; ret < ETH_LDO_RDY_CNT; ret++) { + if (priv->eth_ldo_rdy[ret]) { + val = readl(priv->eth_ldo_rdy[ret]); + val |= BIT(0); + writel(val, priv->eth_ldo_rdy[ret]); + fsleep(IPQ_PHY_SET_DELAY_US); + } } /* Configure MDIO clock source frequency if clock is specified in the device tree */ @@ -252,11 +257,14 @@ static int ipq4019_mdio_probe(struct platform_device *pdev) if (IS_ERR(priv->mdio_clk)) return PTR_ERR(priv->mdio_clk); - /* The platform resource is provided on the chipset IPQ5018 */ + /* The platform resource is provided on the chipset IPQ5018/IPQ5332 */ /* This resource is optional */ - res = platform_get_resource(pdev, IORESOURCE_MEM, 1); - if (res) - priv->eth_ldo_rdy = devm_ioremap_resource(&pdev->dev, res); + for (ret = 0; ret < ETH_LDO_RDY_CNT; ret++) { + res = platform_get_resource(pdev, IORESOURCE_MEM, ret + 1); + if (res) + priv->eth_ldo_rdy[ret] = devm_ioremap(&pdev->dev, + res->start, resource_size(res)); + } bus->name = "ipq4019_mdio"; bus->read = ipq4019_mdio_read_c22; @@ -288,6 +296,7 @@ static void ipq4019_mdio_remove(struct platform_device *pdev) static const struct of_device_id ipq4019_mdio_dt_ids[] = { { .compatible = "qcom,ipq4019-mdio" }, { .compatible = "qcom,ipq5018-mdio" }, + { .compatible = "qcom,ipq5332-mdio" }, { } }; MODULE_DEVICE_TABLE(of, ipq4019_mdio_dt_ids); From patchwork Wed Nov 15 03:25:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 165165 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:6358:a59:b0:164:83eb:24d7 with SMTP id 25csp2363081rwb; Tue, 14 Nov 2023 19:27:03 -0800 (PST) X-Google-Smtp-Source: AGHT+IHiXsluBEKJrA3CKXILpLsGGL3JZ85SaidXaCPQXo8+I+H/ExFluqA9RNT28TNWpm2RQfQR X-Received: by 2002:a05:6808:370b:b0:3b2:e649:b5fb with SMTP id cq11-20020a056808370b00b003b2e649b5fbmr13052217oib.15.1700018823197; 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Wed, 15 Nov 2023 03:25:39 +0000 Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AF3PdaH016200 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 15 Nov 2023 03:25:39 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Tue, 14 Nov 2023 19:25:34 -0800 From: Luo Jie To: , , , , , , , , , , , , , CC: , , , , Subject: [PATCH 2/9] net: mdio: ipq4019: Enable the clocks for ipq5332 platform Date: Wed, 15 Nov 2023 11:25:08 +0800 Message-ID: <20231115032515.4249-3-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231115032515.4249-1-quic_luoj@quicinc.com> References: <20231115032515.4249-1-quic_luoj@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: FOHgjdOsE8aPEiwjEgtTyPlMMSho_lpP X-Proofpoint-GUID: FOHgjdOsE8aPEiwjEgtTyPlMMSho_lpP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-15_01,2023-11-14_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 adultscore=0 clxscore=1015 spamscore=0 bulkscore=0 phishscore=0 mlxscore=0 mlxlogscore=999 priorityscore=1501 suspectscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311150027 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 14 Nov 2023 19:26:08 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782598937263636176 X-GMAIL-MSGID: 1782598937263636176 For the platform ipq5332, the related GCC clocks need to be enabled to make the GPIO reset of the MDIO slave devices taking effect. Signed-off-by: Luo Jie --- drivers/net/mdio/mdio-ipq4019.c | 67 +++++++++++++++++++++++++++++---- 1 file changed, 60 insertions(+), 7 deletions(-) diff --git a/drivers/net/mdio/mdio-ipq4019.c b/drivers/net/mdio/mdio-ipq4019.c index 9d444f5f7efb..a77982a1a1e1 100644 --- a/drivers/net/mdio/mdio-ipq4019.c +++ b/drivers/net/mdio/mdio-ipq4019.c @@ -34,16 +34,35 @@ /* MDIO clock source frequency is fixed to 100M */ #define IPQ_MDIO_CLK_RATE 100000000 +#define IPQ_UNIPHY_AHB_CLK_RATE 100000000 +#define IPQ_UNIPHY_SYS_CLK_RATE 24000000 #define IPQ_PHY_SET_DELAY_US 100000 /* Maximum SOC PCS(uniphy) number on IPQ platform */ #define ETH_LDO_RDY_CNT 3 +enum mdio_clk_id { + MDIO_CLK_MDIO_AHB, + MDIO_CLK_UNIPHY0_AHB, + MDIO_CLK_UNIPHY0_SYS, + MDIO_CLK_UNIPHY1_AHB, + MDIO_CLK_UNIPHY1_SYS, + MDIO_CLK_CNT +}; + struct ipq4019_mdio_data { void __iomem *membase; void __iomem *eth_ldo_rdy[ETH_LDO_RDY_CNT]; - struct clk *mdio_clk; + struct clk *clk[MDIO_CLK_CNT]; +}; + +const char *const mdio_clk_name[] = { + "gcc_mdio_ahb_clk", + "gcc_uniphy0_ahb_clk", + "gcc_uniphy0_sys_clk", + "gcc_uniphy1_ahb_clk", + "gcc_uniphy1_sys_clk" }; static int ipq4019_mdio_wait_busy(struct mii_bus *bus) @@ -212,6 +231,38 @@ static int ipq_mdio_reset(struct mii_bus *bus) u32 val; int ret; + /* For the platform ipq5332, there are two uniphy available to connect the + * ethernet devices, the uniphy gcc clock should be enabled for resetting + * the connected device such as qca8386 switch or qca8081 PHY effectively. + */ + if (of_device_is_compatible(bus->parent->of_node, "qcom,ipq5332-mdio")) { + int i; + unsigned long rate = 0; + + for (i = MDIO_CLK_UNIPHY0_AHB; i < MDIO_CLK_CNT; i++) { + switch (i) { + case MDIO_CLK_UNIPHY0_AHB: + case MDIO_CLK_UNIPHY1_AHB: + rate = IPQ_UNIPHY_AHB_CLK_RATE; + break; + case MDIO_CLK_UNIPHY0_SYS: + case MDIO_CLK_UNIPHY1_SYS: + rate = IPQ_UNIPHY_SYS_CLK_RATE; + break; + default: + break; + } + + ret = clk_set_rate(priv->clk[i], rate); + if (ret) + return ret; + + ret = clk_prepare_enable(priv->clk[i]); + if (ret) + return ret; + } + } + /* To indicate CMN_PLL that ethernet_ldo has been ready if platform resource 1 * or more resource are specified in the device tree. */ @@ -225,11 +276,11 @@ static int ipq_mdio_reset(struct mii_bus *bus) } /* Configure MDIO clock source frequency if clock is specified in the device tree */ - ret = clk_set_rate(priv->mdio_clk, IPQ_MDIO_CLK_RATE); + ret = clk_set_rate(priv->clk[MDIO_CLK_MDIO_AHB], IPQ_MDIO_CLK_RATE); if (ret) return ret; - ret = clk_prepare_enable(priv->mdio_clk); + ret = clk_prepare_enable(priv->clk[MDIO_CLK_MDIO_AHB]); if (ret == 0) mdelay(10); @@ -253,10 +304,6 @@ static int ipq4019_mdio_probe(struct platform_device *pdev) if (IS_ERR(priv->membase)) return PTR_ERR(priv->membase); - priv->mdio_clk = devm_clk_get_optional(&pdev->dev, "gcc_mdio_ahb_clk"); - if (IS_ERR(priv->mdio_clk)) - return PTR_ERR(priv->mdio_clk); - /* The platform resource is provided on the chipset IPQ5018/IPQ5332 */ /* This resource is optional */ for (ret = 0; ret < ETH_LDO_RDY_CNT; ret++) { @@ -266,6 +313,12 @@ static int ipq4019_mdio_probe(struct platform_device *pdev) res->start, resource_size(res)); } + for (ret = 0; ret < MDIO_CLK_CNT; ret++) { + priv->clk[ret] = devm_clk_get_optional(&pdev->dev, mdio_clk_name[ret]); + if (IS_ERR(priv->clk[ret])) + return PTR_ERR(priv->clk[ret]); + } + bus->name = "ipq4019_mdio"; bus->read = ipq4019_mdio_read_c22; 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Wed, 15 Nov 2023 03:25:44 +0000 Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AF3PhHa016232 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 15 Nov 2023 03:25:43 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Tue, 14 Nov 2023 19:25:39 -0800 From: Luo Jie To: , , , , , , , , , , , , , CC: , , , , Subject: [PATCH 3/9] net: mdio: ipq4019: Enable GPIO reset for ipq5332 platform Date: Wed, 15 Nov 2023 11:25:09 +0800 Message-ID: <20231115032515.4249-4-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231115032515.4249-1-quic_luoj@quicinc.com> References: <20231115032515.4249-1-quic_luoj@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: dMWqGeS7OtRSWS9hgAccMs904vHfMNvj X-Proofpoint-GUID: dMWqGeS7OtRSWS9hgAccMs904vHfMNvj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-15_01,2023-11-14_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 priorityscore=1501 bulkscore=0 spamscore=0 impostorscore=0 mlxscore=0 phishscore=0 malwarescore=0 lowpriorityscore=0 mlxlogscore=999 adultscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311150027 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 14 Nov 2023 19:26:11 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782598939030964639 X-GMAIL-MSGID: 1782598939030964639 Before doing GPIO reset on the MDIO slave devices, the common clock output to MDIO slave device should be enabled, and the related GCC clocks also need to be configured. Because of these extra configurations, the MDIO bus level GPIO and PHY device level GPIO can't be leveraged. Need to add the device tree property "phy-reset-gpio" of MDIO node to enable this special GPIO reset. Signed-off-by: Luo Jie --- drivers/net/mdio/mdio-ipq4019.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/net/mdio/mdio-ipq4019.c b/drivers/net/mdio/mdio-ipq4019.c index a77982a1a1e1..93ae4684de31 100644 --- a/drivers/net/mdio/mdio-ipq4019.c +++ b/drivers/net/mdio/mdio-ipq4019.c @@ -12,6 +12,7 @@ #include #include #include +#include #define MDIO_MODE_REG 0x40 #define MDIO_ADDR_REG 0x44 @@ -55,6 +56,7 @@ struct ipq4019_mdio_data { void __iomem *membase; void __iomem *eth_ldo_rdy[ETH_LDO_RDY_CNT]; struct clk *clk[MDIO_CLK_CNT]; + struct gpio_descs *reset_gpios; }; const char *const mdio_clk_name[] = { @@ -275,6 +277,24 @@ static int ipq_mdio_reset(struct mii_bus *bus) } } + /* Do the optional reset on the devices connected with MDIO bus */ + if (priv->reset_gpios) { + unsigned long *values = bitmap_zalloc(priv->reset_gpios->ndescs, GFP_KERNEL); + + if (!values) + return -ENOMEM; + + bitmap_fill(values, priv->reset_gpios->ndescs); + gpiod_set_array_value_cansleep(priv->reset_gpios->ndescs, priv->reset_gpios->desc, + priv->reset_gpios->info, values); + + fsleep(IPQ_PHY_SET_DELAY_US); + bitmap_zero(values, priv->reset_gpios->ndescs); + gpiod_set_array_value_cansleep(priv->reset_gpios->ndescs, priv->reset_gpios->desc, + priv->reset_gpios->info, values); + bitmap_free(values); + } + /* Configure MDIO clock source frequency if clock is specified in the device tree */ ret = clk_set_rate(priv->clk[MDIO_CLK_MDIO_AHB], IPQ_MDIO_CLK_RATE); if (ret) @@ -319,6 +339,19 @@ static int ipq4019_mdio_probe(struct platform_device *pdev) return PTR_ERR(priv->clk[ret]); } + /* This GPIO reset is for qca8084 PHY, which is only probeable by MDIO bus + * after the following steps completed. + * + * 1. Enable LDO to provide clock for qca8084 and enable SoC GCC uniphy related clocks. + * 2. Do GPIO reset on the qca8084 PHY. + * 3. Configure the PHY address that is customized according to device treee. + * 4. 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Tue, 14 Nov 2023 19:27:10 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782598947446794112 X-GMAIL-MSGID: 1782598947446794112 The reference clock of CMN PLL block is selectable, the internal 48MHZ is used by default. The output clock of CMN PLL block is for providing the clock source of ethernet device(such as qca8084), there are 1 X 25MHZ and 3 x 50MHZ output clocks available. Signed-off-by: Luo Jie --- drivers/net/mdio/mdio-ipq4019.c | 81 ++++++++++++++++++++++++++++++++- 1 file changed, 80 insertions(+), 1 deletion(-) diff --git a/drivers/net/mdio/mdio-ipq4019.c b/drivers/net/mdio/mdio-ipq4019.c index 93ae4684de31..ca9cda98d1f8 100644 --- a/drivers/net/mdio/mdio-ipq4019.c +++ b/drivers/net/mdio/mdio-ipq4019.c @@ -43,6 +43,13 @@ /* Maximum SOC PCS(uniphy) number on IPQ platform */ #define ETH_LDO_RDY_CNT 3 +#define CMN_PLL_REFERENCE_CLOCK 0x784 +#define CMN_PLL_REFCLK_INDEX GENMASK(3, 0) +#define CMN_PLL_REFCLK_EXTERNAL BIT(9) + +#define CMN_PLL_POWER_ON_AND_RESET 0x780 +#define CMN_ANA_EN_SW_RSTN BIT(6) + enum mdio_clk_id { MDIO_CLK_MDIO_AHB, MDIO_CLK_UNIPHY0_AHB, @@ -54,6 +61,7 @@ enum mdio_clk_id { struct ipq4019_mdio_data { void __iomem *membase; + void __iomem *cmn_membase; void __iomem *eth_ldo_rdy[ETH_LDO_RDY_CNT]; struct clk *clk[MDIO_CLK_CNT]; struct gpio_descs *reset_gpios; @@ -227,12 +235,73 @@ static int ipq4019_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum, return 0; } +/* For the CMN PLL block, the reference clock can be configured according to + * the device tree property "cmn_ref_clk", the internal 48MHZ is used by default + * on the ipq533 platform. + * + * The output clock of CMN PLL block is provided to the MDIO slave devices, + * threre are 4 CMN PLL output clocks (1x25MHZ + 3x50MHZ) enabled by default. + * + * such as the output 50M clock for the qca8084 PHY. + */ +static void ipq_cmn_clock_config(struct mii_bus *bus) +{ + u32 reg_val; + const char *cmn_ref_clk; + struct ipq4019_mdio_data *priv = bus->priv; + + if (priv && priv->cmn_membase) { + reg_val = readl(priv->cmn_membase + CMN_PLL_REFERENCE_CLOCK); + reg_val &= ~(CMN_PLL_REFCLK_EXTERNAL | CMN_PLL_REFCLK_INDEX); + + /* Select reference clock source */ + cmn_ref_clk = of_get_property(bus->parent->of_node, "cmn_ref_clk", NULL); + if (!cmn_ref_clk) { + /* Internal 48MHZ selected by default */ + reg_val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 7); + } else { + if (!strcmp(cmn_ref_clk, "external_25MHz")) + reg_val |= (CMN_PLL_REFCLK_EXTERNAL | + FIELD_PREP(CMN_PLL_REFCLK_INDEX, 3)); + else if (!strcmp(cmn_ref_clk, "external_31250KHz")) + reg_val |= (CMN_PLL_REFCLK_EXTERNAL | + FIELD_PREP(CMN_PLL_REFCLK_INDEX, 4)); + else if (!strcmp(cmn_ref_clk, "external_40MHz")) + reg_val |= (CMN_PLL_REFCLK_EXTERNAL | + FIELD_PREP(CMN_PLL_REFCLK_INDEX, 6)); + else if (!strcmp(cmn_ref_clk, "external_48MHz")) + reg_val |= (CMN_PLL_REFCLK_EXTERNAL | + FIELD_PREP(CMN_PLL_REFCLK_INDEX, 7)); + else if (!strcmp(cmn_ref_clk, "external_50MHz")) + reg_val |= (CMN_PLL_REFCLK_EXTERNAL | + FIELD_PREP(CMN_PLL_REFCLK_INDEX, 8)); + else + reg_val |= FIELD_PREP(CMN_PLL_REFCLK_INDEX, 7); + } + + writel(reg_val, priv->cmn_membase + CMN_PLL_REFERENCE_CLOCK); + + /* assert CMN PLL */ + reg_val = readl(priv->cmn_membase + CMN_PLL_POWER_ON_AND_RESET); + reg_val &= ~CMN_ANA_EN_SW_RSTN; + writel(reg_val, priv->cmn_membase); + fsleep(IPQ_PHY_SET_DELAY_US); + + /* deassert CMN PLL */ + reg_val |= CMN_ANA_EN_SW_RSTN; + writel(reg_val, priv->cmn_membase + CMN_PLL_POWER_ON_AND_RESET); + fsleep(IPQ_PHY_SET_DELAY_US); + } +} + static int ipq_mdio_reset(struct mii_bus *bus) { struct ipq4019_mdio_data *priv = bus->priv; u32 val; int ret; + ipq_cmn_clock_config(bus); + /* For the platform ipq5332, there are two uniphy available to connect the * ethernet devices, the uniphy gcc clock should be enabled for resetting * the connected device such as qca8386 switch or qca8081 PHY effectively. @@ -328,11 +397,21 @@ static int ipq4019_mdio_probe(struct platform_device *pdev) /* This resource is optional */ for (ret = 0; ret < ETH_LDO_RDY_CNT; ret++) { res = platform_get_resource(pdev, IORESOURCE_MEM, ret + 1); - if (res) + if (res && strcmp(res->name, "cmn_blk")) priv->eth_ldo_rdy[ret] = devm_ioremap(&pdev->dev, res->start, resource_size(res)); } + /* The CMN block resource is for providing clock source of ethernet, which can + * be optionally configured on the platform ipq9574 and ipq5332. + */ + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cmn_blk"); + if (res) { + priv->cmn_membase = devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(priv->cmn_membase)) + return PTR_ERR(priv->cmn_membase); + } + for (ret = 0; ret < MDIO_CLK_CNT; ret++) { priv->clk[ret] = devm_clk_get_optional(&pdev->dev, mdio_clk_name[ret]); if (IS_ERR(priv->clk[ret])) From patchwork Wed Nov 15 03:25:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 165167 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:6358:a59:b0:164:83eb:24d7 with SMTP id 25csp2363097rwb; Tue, 14 Nov 2023 19:27:06 -0800 (PST) X-Google-Smtp-Source: AGHT+IHS7/WokCtdZKJ6m+i8NoS4VqMBAyUaD5ApPfH6oLTk98AP3gUEDL75EwYNsYop4LSPbZl9 X-Received: by 2002:a17:902:e80d:b0:1cc:1106:cf5b with SMTP id u13-20020a170902e80d00b001cc1106cf5bmr5589258plg.19.1700018826186; Tue, 14 Nov 2023 19:27:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700018826; cv=none; d=google.com; s=arc-20160816; b=rmmgTrOTd3qV8JbTfUYLSq6TslrWiVjh0nWQtcosz4V5QVIK0P90f7nYNmzlc9FXHz SFWEA096NJvaNwSbF2IQgsNu/5vsYK+/JYJp19u+gY08+EUZxlJsRx2RYAZB+HBCMcob jt264JI7PjBKSgIJvYumrIG56FmMuq3Ggl1EFA/PWVcgBmuBowpmtMDz4KHRBAL96ors buPDl7UohEH6ZWuyUc6vOsomD2v/AiL+sYAW6eCkBiesNUczNngr0nuYr/wY9pm+kTgZ AhvS/rseZtDmfvZYvAvLZfsnn6TZ4INpkPtF5dG1DNDzjZo2tmC1PS37UsRIPXcOyajo PbNQ== ARC-Message-Signature: i=1; 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Wed, 15 Nov 2023 03:25:52 +0000 Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AF3PpDq026882 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 15 Nov 2023 03:25:51 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Tue, 14 Nov 2023 19:25:47 -0800 From: Luo Jie To: , , , , , , , , , , , , , CC: , , , , Subject: [PATCH 5/9] net: mdio: ipq4019: support MDIO clock frequency divider Date: Wed, 15 Nov 2023 11:25:11 +0800 Message-ID: <20231115032515.4249-6-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231115032515.4249-1-quic_luoj@quicinc.com> References: <20231115032515.4249-1-quic_luoj@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Yn8tRo-Bwc-iLrmWU7cRIMRRpz2pQE-h X-Proofpoint-GUID: Yn8tRo-Bwc-iLrmWU7cRIMRRpz2pQE-h X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-15_01,2023-11-14_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 impostorscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 mlxscore=0 bulkscore=0 clxscore=1015 malwarescore=0 mlxlogscore=999 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311150027 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 14 Nov 2023 19:26:21 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782598940505267434 X-GMAIL-MSGID: 1782598940505267434 The MDIO clock frequency can be divided according to the register value. The MDIO system clock is fixed to 100MHZ, the working frequency is 100MHZ/(divider + 1), the divider value is from the bit[7:0] of control register 0x40. Signed-off-by: Luo Jie --- drivers/net/mdio/mdio-ipq4019.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/net/mdio/mdio-ipq4019.c b/drivers/net/mdio/mdio-ipq4019.c index ca9cda98d1f8..44a8a866f8ee 100644 --- a/drivers/net/mdio/mdio-ipq4019.c +++ b/drivers/net/mdio/mdio-ipq4019.c @@ -30,6 +30,9 @@ /* 0 = Clause 22, 1 = Clause 45 */ #define MDIO_MODE_C45 BIT(8) +/* MDC frequency is SYS_CLK/(MDIO_CLK_DIV + 1), SYS_CLK is 100MHz */ +#define MDIO_CLK_DIV_MASK GENMASK(7, 0) + #define IPQ4019_MDIO_TIMEOUT 10000 #define IPQ4019_MDIO_SLEEP 10 @@ -65,6 +68,7 @@ struct ipq4019_mdio_data { void __iomem *eth_ldo_rdy[ETH_LDO_RDY_CNT]; struct clk *clk[MDIO_CLK_CNT]; struct gpio_descs *reset_gpios; + int clk_div; }; const char *const mdio_clk_name[] = { @@ -98,6 +102,7 @@ static int ipq4019_mdio_read_c45(struct mii_bus *bus, int mii_id, int mmd, data = readl(priv->membase + MDIO_MODE_REG); data |= MDIO_MODE_C45; + data |= FIELD_PREP(MDIO_CLK_DIV_MASK, priv->clk_div); writel(data, priv->membase + MDIO_MODE_REG); @@ -139,6 +144,7 @@ static int ipq4019_mdio_read_c22(struct mii_bus *bus, int mii_id, int regnum) data = readl(priv->membase + MDIO_MODE_REG); data &= ~MDIO_MODE_C45; + data |= FIELD_PREP(MDIO_CLK_DIV_MASK, priv->clk_div); writel(data, priv->membase + MDIO_MODE_REG); @@ -171,6 +177,7 @@ static int ipq4019_mdio_write_c45(struct mii_bus *bus, int mii_id, int mmd, data = readl(priv->membase + MDIO_MODE_REG); data |= MDIO_MODE_C45; + data |= FIELD_PREP(MDIO_CLK_DIV_MASK, priv->clk_div); writel(data, priv->membase + MDIO_MODE_REG); @@ -214,6 +221,7 @@ static int ipq4019_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum, data = readl(priv->membase + MDIO_MODE_REG); data &= ~MDIO_MODE_C45; + data |= FIELD_PREP(MDIO_CLK_DIV_MASK, priv->clk_div); writel(data, priv->membase + MDIO_MODE_REG); @@ -431,6 +439,9 @@ static int ipq4019_mdio_probe(struct platform_device *pdev) return dev_err_probe(&pdev->dev, PTR_ERR(priv->reset_gpios), "mii_bus %s couldn't get reset GPIO\n", bus->id); + /* MDIO default frequency is 6.25MHz */ + priv->clk_div = 0xf; + bus->name = "ipq4019_mdio"; bus->read = ipq4019_mdio_read_c22; bus->write = ipq4019_mdio_write_c22; From patchwork Wed Nov 15 03:25:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 165170 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:6358:a59:b0:164:83eb:24d7 with SMTP id 25csp2363174rwb; Tue, 14 Nov 2023 19:27:22 -0800 (PST) X-Google-Smtp-Source: AGHT+IHUy0CUluIbFBACi6/u/YgdkN156nacd72rjkJ+u7hu0+27FXuG1avHCemF86yFaEgzK5dq X-Received: by 2002:a17:902:c94e:b0:1cc:47a6:12b8 with SMTP id i14-20020a170902c94e00b001cc47a612b8mr5357709pla.46.1700018841725; Tue, 14 Nov 2023 19:27:21 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700018841; cv=none; d=google.com; s=arc-20160816; b=Qyh5Qha45ADJY0G4jqv1lx8eFGLptOb2n+Y0YeLPePrixkNhrgNwH2fGQtkA+sCG7S 11Z0F9doOScV4aUNiqOhDB6SnvAmYSm6kBxNpoLQpCuriR1CTw88C00QEeeD7LNJ3YKr 0m0lAdHHJCpEvA2wQRdkFTKtmhAIiX2DDLsrbn6TUBgp7bh7EKKqPudF7OGx2q4Rd9rK 08E5YeqdH4c9banaZ2VpbV0zkl8K6uN4+fW/xtZnGmjUcqfFi1uoaaVd3uTdTC/zpe6t XqICycR5IQ3dMKAy9sAV1FraXWygP/ny7aMhNA4y5xtTEfAAmPT8CGaGuNGwS/7OCmqa iNhQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Ch3fs4DOJF9AEat2vjf10IuYor92WSy7oL8pvdQzo3Y=; fh=+g5tGayWdOm7NVf+9R7F5Bp+AAhjebsKXKT3IUU1ti0=; b=itmudVVGdIyZRMMLaM99ipg5HcO+usQJD6TMbBJcQCw1vZCwJuElcpGAcEgmltL+TQ 0L4s+serdHNonZKtZO0pQ+TX7E1x3BMD871wbxXvkvjtpJ586kR6tKpVrKtKZoVvVfiY BZF6g6j273idssJA+lazWnRpRybLS9n41LMkBjjtYAYkAHKLdz2CvmSg5MXNpkzTrmOC oHEXRQTEhgecDgQi5aj8bctQo1buNEQqkjug4UqO6Rk7xJCPu4L3IZUkbj516GcIDhT/ yQ0ZWkxxPs/uChJGCu5DVNje+tkMNxC51/IAH+d0SVkzH1cjKG9mDyL8ZL4APaRCBgCs Dx4A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=SG1ICeDD; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from groat.vger.email (groat.vger.email. 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Wed, 15 Nov 2023 03:25:56 +0000 Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AF3Ptxh019626 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 15 Nov 2023 03:25:55 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Tue, 14 Nov 2023 19:25:51 -0800 From: Luo Jie To: , , , , , , , , , , , , , CC: , , , , Subject: [PATCH 6/9] net: mdio: ipq4019: Support qca8084 switch register access Date: Wed, 15 Nov 2023 11:25:12 +0800 Message-ID: <20231115032515.4249-7-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231115032515.4249-1-quic_luoj@quicinc.com> References: <20231115032515.4249-1-quic_luoj@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: iRXbT_UTQK-CqxY2pwrtibLUTNavA9FY X-Proofpoint-GUID: iRXbT_UTQK-CqxY2pwrtibLUTNavA9FY X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-15_01,2023-11-14_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 impostorscore=0 lowpriorityscore=0 phishscore=0 adultscore=0 mlxscore=0 bulkscore=0 clxscore=1015 malwarescore=0 mlxlogscore=999 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311150027 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Tue, 14 Nov 2023 19:27:11 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782598957273855695 X-GMAIL-MSGID: 1782598957273855695 For qca8084 chip, there are GCC, TLMM and security control modules besides the PHY, these moudles are accessed with 32 bits value, which has the special MDIO sequences to read or write this 32bit register. There are initial configurations needed to make qca8084 PHY probeable, and the PHY address of qca8084 can also be customized before creating the PHY device on MDIO bus register, all these configurations are located in switch modules that are accessed by the 32bit register. Signed-off-by: Luo Jie --- drivers/net/mdio/mdio-ipq4019.c | 74 +++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/drivers/net/mdio/mdio-ipq4019.c b/drivers/net/mdio/mdio-ipq4019.c index 44a8a866f8ee..8dc611666c34 100644 --- a/drivers/net/mdio/mdio-ipq4019.c +++ b/drivers/net/mdio/mdio-ipq4019.c @@ -53,6 +53,14 @@ #define CMN_PLL_POWER_ON_AND_RESET 0x780 #define CMN_ANA_EN_SW_RSTN BIT(6) +/* QCA8084 includes the PHY chip, GCC/TLMM and the control modules, + * except for the PHY register, other registers are accessed by MDIO bus + * with 32bit value, which has the special MDIO sequences to access the + * switch modules register. + */ +#define IPQ_HIGH_ADDR_PREFIX 0x18 +#define IPQ_LOW_ADDR_PREFIX 0x10 + enum mdio_clk_id { MDIO_CLK_MDIO_AHB, MDIO_CLK_UNIPHY0_AHB, @@ -243,6 +251,72 @@ static int ipq4019_mdio_write_c22(struct mii_bus *bus, int mii_id, int regnum, return 0; } +static inline void split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page, u16 *sw_addr) +{ + *r1 = regaddr & 0x1c; + + regaddr >>= 5; + *r2 = regaddr & 0x7; + + regaddr >>= 3; + *page = regaddr & 0xffff; + + regaddr >>= 16; + *sw_addr = regaddr & 0xff; +} + +static int qca8084_set_page(struct mii_bus *bus, u16 sw_addr, u16 page) +{ + return bus->write(bus, IPQ_HIGH_ADDR_PREFIX | (sw_addr >> 5), sw_addr & 0x1f, page); +} + +static int qca8084_mii_read(struct mii_bus *bus, u16 addr, u16 reg, u32 *val) +{ + int ret, data; + + ret = bus->read(bus, addr, reg); + if (ret >= 0) { + data = ret; + + ret = bus->read(bus, addr, reg | BIT(1)); + if (ret >= 0) + *val = data | ret << 16; + } + + return ret < 0 ? ret : 0; +} + +static int qca8084_mii_write(struct mii_bus *bus, u16 addr, u16 reg, u32 val) +{ + int ret; + + ret = bus->write(bus, addr, reg, lower_16_bits(val)); + if (!ret) + ret = bus->write(bus, addr, reg | BIT(1), upper_16_bits(val)); + + return ret; +} + +static int qca8084_modify(struct mii_bus *bus, u32 regaddr, u32 clear, u32 set) +{ + u16 reg, addr, page, sw_addr; + u32 val; + int ret; + + split_addr(regaddr, ®, &addr, &page, &sw_addr); + ret = qca8084_set_page(bus, sw_addr, page); + if (ret < 0) + return ret; + + ret = qca8084_mii_read(bus, IPQ_LOW_ADDR_PREFIX | addr, reg, &val); + if (ret < 0) + return ret; + + val &= ~clear; + val |= set; + return qca8084_mii_write(bus, IPQ_LOW_ADDR_PREFIX | addr, reg, val); +}; + /* For the CMN PLL block, the reference clock can be configured according to * the device tree property "cmn_ref_clk", the internal 48MHZ is used by default * on the ipq533 platform. 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Wed, 15 Nov 2023 03:26:01 +0000 Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AF3PxvZ029492 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 15 Nov 2023 03:25:59 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Tue, 14 Nov 2023 19:25:55 -0800 From: Luo Jie To: , , , , , , , , , , , , , CC: , , , , Subject: [PATCH 7/9] net: mdio: ipq4019: program phy address when "fixup" defined Date: Wed, 15 Nov 2023 11:25:13 +0800 Message-ID: <20231115032515.4249-8-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231115032515.4249-1-quic_luoj@quicinc.com> References: <20231115032515.4249-1-quic_luoj@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: TJUdN1DJWmnlHOIpUDZXM3jgGvOWxbTF X-Proofpoint-ORIG-GUID: TJUdN1DJWmnlHOIpUDZXM3jgGvOWxbTF X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-15_01,2023-11-14_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 mlxlogscore=999 priorityscore=1501 suspectscore=0 adultscore=0 spamscore=0 lowpriorityscore=0 mlxscore=0 bulkscore=0 phishscore=0 impostorscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311150026 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Tue, 14 Nov 2023 19:27:22 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782598965264272687 X-GMAIL-MSGID: 1782598965264272687 The PHY/PCS MDIO address can be programed when the property "fixup" of phy node is defined. The qca8084 PHY/PCS address configuration register is accessed by MDIO bus with the special MDIO sequence. The PHY address configuration register of IPQ5018 is accessed by local bus. Add the function ipq_mdio_preinit, which should be called before the PHY device scanned and registered. Signed-off-by: Luo Jie --- drivers/net/mdio/mdio-ipq4019.c | 107 +++++++++++++++++++++++++++++++- 1 file changed, 106 insertions(+), 1 deletion(-) diff --git a/drivers/net/mdio/mdio-ipq4019.c b/drivers/net/mdio/mdio-ipq4019.c index 8dc611666c34..1c461c243ae0 100644 --- a/drivers/net/mdio/mdio-ipq4019.c +++ b/drivers/net/mdio/mdio-ipq4019.c @@ -61,6 +61,15 @@ #define IPQ_HIGH_ADDR_PREFIX 0x18 #define IPQ_LOW_ADDR_PREFIX 0x10 +/* QCA8084 PHY & PCS address can be customized, 4 PHYs and 3 PCSs are + * available. + */ +#define QCA8084_PHY_ADDR_LENGTH 5 +#define QCA8084_PHY_ADDR_NUM 4 +#define QCA8084_PCS_ADDR_NUM 3 +#define QCA8084_PHY_ADDR_MASK GENMASK(19, 0) +#define QCA8084_PCS_ADDR_MASK GENMASK(14, 0) + enum mdio_clk_id { MDIO_CLK_MDIO_AHB, MDIO_CLK_UNIPHY0_AHB, @@ -317,6 +326,102 @@ static int qca8084_modify(struct mii_bus *bus, u32 regaddr, u32 clear, u32 set) return qca8084_mii_write(bus, IPQ_LOW_ADDR_PREFIX | addr, reg, val); }; +/* The PHY/PCS MDIO address can be programed when the device tree property + * "fixup" of PHY node is specified. + */ +static int ipq_phy_addr_fixup(struct mii_bus *bus, struct device_node *mdio_node) +{ + const __be32 *phy_cfg; + u32 phy_addr_val, pcs_addr_val; + int ret, phy_index, pcs_index; + struct device_node *child; + + phy_index = 0; + pcs_index = 0; + phy_addr_val = 0; + pcs_addr_val = 0; + for_each_available_child_of_node(mdio_node, child) { + ret = of_mdio_parse_addr(&bus->dev, child); + if (ret < 0) + continue; + + if (!of_property_present(child, "fixup")) + continue; + + if (of_property_present(child, "compatible")) { + pcs_addr_val |= ret << (QCA8084_PHY_ADDR_LENGTH * pcs_index); + pcs_index++; + } else { + phy_addr_val |= ret << (QCA8084_PHY_ADDR_LENGTH * phy_index); + phy_index++; + } + } + + if (!phy_addr_val && !pcs_addr_val) + return 0; + + if (phy_index > QCA8084_PHY_ADDR_NUM || pcs_index > QCA8084_PCS_ADDR_NUM) { + dev_err(&bus->dev, + "Too many MDIO address(phy number %d, pcs number %d) to be programed\n", + phy_index, pcs_index); + return -1; + } + + phy_cfg = of_get_property(mdio_node, "phyaddr-fixup", &ret); + + /* For MDIO access, phyaddr-fixup only provides the register address, + * such as qca8084 PHY. + * + * As for local bus, the register length also needs to be provided, + * such as the internal PHY of IPQ5018, only PHY address can be programed. + */ + if (!phy_cfg || (ret != (2 * sizeof(__be32)) && ret != sizeof(__be32))) + return 0; + + if (ret == sizeof(__be32)) { + const __be32 *pcs_cfg; + + /* MDIO access for customizing PHY address of qca8084 */ + if (phy_addr_val != 0) { + ret = qca8084_modify(bus, be32_to_cpup(phy_cfg), + QCA8084_PHY_ADDR_MASK, phy_addr_val); + if (ret) + return ret; + } + + pcs_cfg = of_get_property(mdio_node, "pcsaddr-fixup", NULL); + /* Programe the PCS address if pcsaddr-fixup specified */ + if (pcs_cfg && pcs_addr_val != 0) { + ret = qca8084_modify(bus, be32_to_cpup(pcs_cfg), + QCA8084_PCS_ADDR_MASK, pcs_addr_val); + if (ret) + return ret; + } + } else { + void __iomem *ephy_cfg_base; + + /* Local bus access for customizing internal PHY address of IPQ5018 */ + ephy_cfg_base = ioremap(be32_to_cpup(phy_cfg), be32_to_cpup(phy_cfg + 1)); + if (!ephy_cfg_base) + return -ENOMEM; + + if (phy_addr_val != 0) + writel(phy_addr_val, ephy_cfg_base); + } + + return 0; +} + +static int ipq_mdio_preinit(struct mii_bus *bus) +{ + struct device_node *mdio_node = dev_of_node(&bus->dev); + + if (!mdio_node) + return 0; + + return ipq_phy_addr_fixup(bus, mdio_node); +} + /* For the CMN PLL block, the reference clock can be configured according to * the device tree property "cmn_ref_clk", the internal 48MHZ is used by default * on the ipq533 platform. @@ -455,7 +560,7 @@ static int ipq_mdio_reset(struct mii_bus *bus) if (ret == 0) mdelay(10); - return ret; + return ipq_mdio_preinit(bus); } static int ipq4019_mdio_probe(struct platform_device *pdev) From patchwork Wed Nov 15 03:25:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 165171 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:6358:a59:b0:164:83eb:24d7 with SMTP id 25csp2363194rwb; Tue, 14 Nov 2023 19:27:27 -0800 (PST) X-Google-Smtp-Source: AGHT+IGuinUg9Ktu7xiUQrQ39fLl6IWgOehuduqKU+vJ1cQ0+ffHCL+3S/DoLoi5n76atht0EGGK X-Received: by 2002:a05:6870:a989:b0:1ef:b5e9:a4ef with SMTP id ep9-20020a056870a98900b001efb5e9a4efmr14304208oab.55.1700018847525; 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Wed, 15 Nov 2023 03:26:04 +0000 Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AF3Q3AN027042 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 15 Nov 2023 03:26:03 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Tue, 14 Nov 2023 19:25:59 -0800 From: Luo Jie To: , , , , , , , , , , , , , CC: , , , , Subject: [PATCH 8/9] net: mdio: ipq4019: add qca8084 configurations Date: Wed, 15 Nov 2023 11:25:14 +0800 Message-ID: <20231115032515.4249-9-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231115032515.4249-1-quic_luoj@quicinc.com> References: <20231115032515.4249-1-quic_luoj@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 4NAnnWRyDbDXXoaCSaZvNVHyMXg0t5_- X-Proofpoint-ORIG-GUID: 4NAnnWRyDbDXXoaCSaZvNVHyMXg0t5_- X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-15_01,2023-11-14_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 phishscore=0 clxscore=1015 bulkscore=0 priorityscore=1501 spamscore=0 mlxscore=0 suspectscore=0 mlxlogscore=976 malwarescore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311150027 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Tue, 14 Nov 2023 19:27:19 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782598963153664215 X-GMAIL-MSGID: 1782598963153664215 The PHY & PCS clocks need to be enabled and the reset sequence needs to be completed to make qca8084 PHY probeable by MDIO bus. Signed-off-by: Luo Jie --- drivers/net/mdio/mdio-ipq4019.c | 133 +++++++++++++++++++++++++++++++- 1 file changed, 132 insertions(+), 1 deletion(-) diff --git a/drivers/net/mdio/mdio-ipq4019.c b/drivers/net/mdio/mdio-ipq4019.c index 1c461c243ae0..9bdd49be2361 100644 --- a/drivers/net/mdio/mdio-ipq4019.c +++ b/drivers/net/mdio/mdio-ipq4019.c @@ -70,6 +70,30 @@ #define QCA8084_PHY_ADDR_MASK GENMASK(19, 0) #define QCA8084_PCS_ADDR_MASK GENMASK(14, 0) +/* QCA8084 GCC & security control registers */ +/* LDO control, BIT20 for PHY0 and PHY1, BIT21 for PHY2 and PHY3 */ +#define EPHY_CFG 0xC90F018 +#define EPHY_CFG_LDO_CTRL GENMASK(21, 20) + +/* GEPHY TX&RX clock control register starts from GEPHY0_TX, + * end with GEPHY3_RX, the gap is 0x20. + */ +#define GEPHY0_TX_CBCR 0xC800058 +#define GEPHY3_RX_CBCR 0xC800138 +#define GEPHY_CBCR_GAP 0x20 + +#define SRDS0_SYS_CBCR 0xC8001A8 +#define SRDS1_SYS_CBCR 0xC8001AC +#define EPHY0_SYS_CBCR 0xC8001B0 +#define EPHY1_SYS_CBCR 0xC8001B4 +#define EPHY2_SYS_CBCR 0xC8001B8 +#define EPHY3_SYS_CBCR 0xC8001BC +#define CLK_EN BIT(0) +#define CLK_RESET BIT(2) + +#define GCC_GEPHY_MISC 0xC800304 +#define GCC_GEPHY_MISC_DSP_RESET GENMASK(4, 0) + enum mdio_clk_id { MDIO_CLK_MDIO_AHB, MDIO_CLK_UNIPHY0_AHB, @@ -412,14 +436,121 @@ static int ipq_phy_addr_fixup(struct mii_bus *bus, struct device_node *mdio_node return 0; } +static inline int qca8084_clock_en_set(struct mii_bus *bus, u32 reg, bool enable) +{ + return qca8084_modify(bus, reg, CLK_EN, enable ? CLK_EN : 0); +} + +static inline int qca8084_clock_reset(struct mii_bus *bus, u32 reg) +{ + int ret; + + ret = qca8084_modify(bus, reg, CLK_RESET, CLK_RESET); + if (ret) + return ret; + + usleep_range(20000, 21000); + return qca8084_modify(bus, reg, CLK_RESET, 0); +} + +static int qca8084_clock_config(struct mii_bus *bus) +{ + u32 reg; + int ret; + + /* Enable PCS */ + ret = qca8084_clock_en_set(bus, SRDS0_SYS_CBCR, true); + if (ret) + return ret; + + ret = qca8084_clock_en_set(bus, SRDS1_SYS_CBCR, true); + if (ret) + return ret; + + /* Reset PCS */ + ret = qca8084_clock_reset(bus, SRDS0_SYS_CBCR); + if (ret) + return ret; + + ret = qca8084_clock_reset(bus, SRDS1_SYS_CBCR); + if (ret) + return ret; + + /* Disable EPHY GMII RX & TX clock */ + reg = GEPHY0_TX_CBCR; + while (reg <= GEPHY3_RX_CBCR) { + ret = qca8084_clock_en_set(bus, reg, false); + if (ret) + return ret; + + reg += GEPHY_CBCR_GAP; + } + + /* Enable EPHY */ + ret = qca8084_clock_en_set(bus, EPHY0_SYS_CBCR, true); + if (ret) + return ret; + + ret = qca8084_clock_en_set(bus, EPHY1_SYS_CBCR, true); + if (ret) + return ret; + + ret = qca8084_clock_en_set(bus, EPHY2_SYS_CBCR, true); + if (ret) + return ret; + + ret = qca8084_clock_en_set(bus, EPHY3_SYS_CBCR, true); + if (ret) + return ret; + + /* Reset EPHY */ + ret = qca8084_clock_reset(bus, EPHY0_SYS_CBCR); + if (ret) + return ret; + + ret = qca8084_clock_reset(bus, EPHY1_SYS_CBCR); + if (ret) + return ret; + + ret = qca8084_clock_reset(bus, EPHY2_SYS_CBCR); + if (ret) + return ret; + + ret = qca8084_clock_reset(bus, EPHY3_SYS_CBCR); + if (ret) + return ret; + + /* Deassert EPHY DSP */ + ret = qca8084_modify(bus, GCC_GEPHY_MISC, GCC_GEPHY_MISC_DSP_RESET, 0); + if (ret) + return ret; + + /* Enable efuse loading into analog circuit */ + ret = qca8084_modify(bus, EPHY_CFG, EPHY_CFG_LDO_CTRL, 0); + if (ret) + return ret; + + /* Sleep 10ms */ + usleep_range(10000, 11000); + return 0; +} + static int ipq_mdio_preinit(struct mii_bus *bus) { + int ret; struct device_node *mdio_node = dev_of_node(&bus->dev); if (!mdio_node) return 0; - return ipq_phy_addr_fixup(bus, mdio_node); + ret = ipq_phy_addr_fixup(bus, mdio_node); + if (ret) + return ret; + + if (of_property_read_bool(mdio_node, "mdio-clk-fixup")) + ret = qca8084_clock_config(bus); + + return ret; } /* For the CMN PLL block, the reference clock can be configured according to From patchwork Wed Nov 15 03:25:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jie Luo X-Patchwork-Id: 165169 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:6358:a59:b0:164:83eb:24d7 with SMTP id 25csp2363134rwb; Tue, 14 Nov 2023 19:27:14 -0800 (PST) X-Google-Smtp-Source: AGHT+IEnOKeGwvgzSkWPLTNaJFbB3+MEWjwMiRITqTvCcTet9bN/OAhVc+HfZW3AJsVzbWqAtilU X-Received: by 2002:a17:90b:1bca:b0:281:416e:1c3f with SMTP id oa10-20020a17090b1bca00b00281416e1c3fmr10655986pjb.28.1700018833767; Tue, 14 Nov 2023 19:27:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700018833; cv=none; d=google.com; s=arc-20160816; b=CxD5NfE0rENghjkULjGWE4UPQ3U1La64r9qQltdNh2fM7Ab1y6UmGgLtUavRL/hMGj pTC2iQNbiIILb3oW+oaPoOy6Bku5lHBH4F+kN7OcmOjj9MlrQ0Clz/lcGGF8atCYNLah uXvN6EmSz/5LB+K7dchRbPktb34b+82Xml6uACcScL8QtGOn7IYb4K98Viio6D41in8d dLKsPSbUDawPlOFYKQ3diSZ+QMoztDfHa1HV+FbZW4/SQJRNoIM5eBNwKmOTKw5vNIvC HN5i9QtWWMHol1ti1gBE5TWVlUhLZ0nm449x7BqpJDcGXpraXu7CnoLMvBdyKwLNFodA SGCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=AQpWJyQavn2ZQqxdC8CNOkUtvM8ck18GRwWMCErMJ1s=; fh=+g5tGayWdOm7NVf+9R7F5Bp+AAhjebsKXKT3IUU1ti0=; b=UNEqdJ74WE/wFg3w18+PIuE5iOzhZR59Ury6pfpwc8+l1PqSC4quU+3xAY9HtM0TTu TOaI0dJn2CwWzb6D2Ys0b+RlOkrryQCpnEOVCMCwUq0caJjZUb443dRlupwAhNN5t+b1 CKIyfu03P+pWAVy97v62ADqjrALWTxSp7/57ElPBGtHE6Gjcl2yB7MehZWN5uJINiYUO TNmZBOCjVqtj8RqHzHDgcRSd8/VTq7nDAQpaShKIV4ND7WFWDrkq2Sm8Rlq191laQrQW PrmXHRDa+2R19/ASrXSCEBWXcgHSr9DfdhL/cS15Grg7w9C0Zfffwh2tfOovt/QkLaIx 2i3Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=YiRYMVtS; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from snail.vger.email (snail.vger.email. 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Wed, 15 Nov 2023 03:26:09 +0000 Received: from nasanex01c.na.qualcomm.com (nasanex01c.na.qualcomm.com [10.45.79.139]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3AF3Q8so027100 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 15 Nov 2023 03:26:08 GMT Received: from akronite-sh-dev02.qualcomm.com (10.80.80.8) by nasanex01c.na.qualcomm.com (10.45.79.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Tue, 14 Nov 2023 19:26:03 -0800 From: Luo Jie To: , , , , , , , , , , , , , CC: , , , , Subject: [PATCH 9/9] dt-bindings: net: ipq4019-mdio: Document ipq5332 platform Date: Wed, 15 Nov 2023 11:25:15 +0800 Message-ID: <20231115032515.4249-10-quic_luoj@quicinc.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20231115032515.4249-1-quic_luoj@quicinc.com> References: <20231115032515.4249-1-quic_luoj@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01c.na.qualcomm.com (10.45.79.139) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: bOk5oRJxc54QUcI3xmGN9Nx9uw3jSauR X-Proofpoint-ORIG-GUID: bOk5oRJxc54QUcI3xmGN9Nx9uw3jSauR X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-11-15_01,2023-11-14_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 phishscore=0 clxscore=1015 bulkscore=0 priorityscore=1501 spamscore=0 mlxscore=0 suspectscore=0 mlxlogscore=999 malwarescore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2311060000 definitions=main-2311150027 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 14 Nov 2023 19:26:57 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782598948372653573 X-GMAIL-MSGID: 1782598948372653573 On platform IPQ5332, the MDIO address of qca8084 can be programed when the device tree property "fixup" defined, the clock sequence needs to be completed before the PHY probeable. Signed-off-by: Luo Jie --- .../bindings/net/qcom,ipq4019-mdio.yaml | 138 +++++++++++++++++- 1 file changed, 130 insertions(+), 8 deletions(-) diff --git a/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml b/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml index 3407e909e8a7..7ff92be14ee1 100644 --- a/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml +++ b/Documentation/devicetree/bindings/net/qcom,ipq4019-mdio.yaml @@ -15,11 +15,13 @@ properties: - enum: - qcom,ipq4019-mdio - qcom,ipq5018-mdio + - qcom,ipq5332-mdio - items: - enum: - qcom,ipq6018-mdio - qcom,ipq8074-mdio + - qcom,ipq9574-mdio - const: qcom,ipq4019-mdio "#address-cells": @@ -30,19 +32,47 @@ properties: reg: minItems: 1 - maxItems: 2 + maxItems: 5 description: - the first Address and length of the register set for the MDIO controller. - the second Address and length of the register for ethernet LDO, this second - address range is only required by the platform IPQ50xx. + the first Address and length of the register set for the MDIO controller, + the optional second, third and fourth address and length of the register + for ethernet LDO, these three address range are required by the platform + IPQ50xx/IPQ5332, the last address and length is for the CMN clock to + select the reference clock. + + reg-names: + minItems: 1 + maxItems: 5 clocks: - items: - - description: MDIO clock source frequency fixed to 100MHZ + minItems: 1 + maxItems: 5 + description: + MDIO system clock frequency fixed to 100MHZ, and the GCC uniphy + clocks enabled for resetting ethernet PHY. clock-names: - items: - - const: gcc_mdio_ahb_clk + minItems: 1 + maxItems: 5 + + phy-reset-gpio: + minItems: 1 + maxItems: 3 + description: + GPIO used to reset the PHY, each GPIO is for resetting the connected + ethernet PHY device. + + phyaddr-fixup: + description: Register address for programing MDIO address of PHY devices + + pcsaddr-fixup: + description: Register address for programing MDIO address of PCS devices + + mdio-clk-fixup: + description: The initialization clocks to be configured + + fixup: + description: The MDIO address of PHY/PCS device to be programed required: - compatible @@ -61,6 +91,8 @@ allOf: - qcom,ipq5018-mdio - qcom,ipq6018-mdio - qcom,ipq8074-mdio + - qcom,ipq5332-mdio + - qcom,ipq9574-mdio then: required: - clocks @@ -70,6 +102,29 @@ allOf: clocks: false clock-names: false + - if: + properties: + compatible: + contains: + enum: + - qcom,ipq5332-mdio + then: + properties: + clocks: + items: + - description: MDIO clock source frequency fixed to 100MHZ + - description: UNIPHY0 AHB clock source frequency fixed to 100MHZ + - description: UNIPHY0 SYS clock source frequency fixed to 24MHZ + - description: UNIPHY1 AHB clock source frequency fixed to 100MHZ + - description: UNIPHY1 SYS clock source frequency fixed to 24MHZ + clock-names: + items: + - const: gcc_mdio_ahb_clk + - const: gcc_uniphy0_ahb_clk + - const: gcc_uniphy0_sys_clk + - const: gcc_uniphy1_ahb_clk + - const: gcc_uniphy1_sys_clk + unevaluatedProperties: false examples: @@ -100,3 +155,70 @@ examples: reg = <4>; }; }; + + - | + #include + #include + + mdio@90000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "qcom,ipq5332-mdio"; + reg = <0x90000 0x64>, <0x7A00610 0x4>, <0x7A10610 0x4>, <0x9B000 0x800>; + reg-names = "mdio", "eth_ldo1", "eth_ldo2", "cmn_blk"; + + clocks = <&gcc GCC_MDIO_AHB_CLK>, + <&gcc GCC_UNIPHY0_AHB_CLK>, + <&gcc GCC_UNIPHY0_SYS_CLK>, + <&gcc GCC_UNIPHY1_AHB_CLK>, + <&gcc GCC_UNIPHY1_SYS_CLK>; + + clock-names = "gcc_mdio_ahb_clk", + "gcc_uniphy0_ahb_clk", + "gcc_uniphy0_sys_clk", + "gcc_uniphy1_ahb_clk", + "gcc_uniphy1_sys_clk"; + + phy-reset-gpio = <&tlmm 51 GPIO_ACTIVE_LOW>; + phyaddr-fixup = <0xC90F018>; + pcsaddr-fixup = <0xC90F014>; + mdio-clk-fixup; + + qca8kphy0: ethernet-phy@1 { + reg = <1>; + fixup; + }; + + qca8kphy1: ethernet-phy@2 { + reg = <2>; + fixup; + }; + + qca8kphy2: ethernet-phy@3 { + reg = <3>; + fixup; + }; + + qca8kphy3: ethernet-phy@4 { + reg = <4>; + fixup; + }; + + qca8kpcs0: pcsphy0@5 { + compatible = "qcom,qca8k_pcs"; + reg = <5>; + fixup; + }; + + qca8kpcs1: pcsphy1@6 { + compatible = "qcom,qca8k_pcs"; + reg = <6>; + fixup; + }; + + qca8kxpcs: xpcsphy@7 { + compatible = "qcom,qca8k_pcs"; + reg = <7>; + fixup; + }; + };