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bh=e9PkxN0L8KE0i7IVWK24vkAYYs7UKTVGv+zzvcbjSrg=; b=VF+l+Z406rQGDOg4e5ucrm0qdFiYhTp59VXha88Z5gqr3LQ1RHksaHiDfl598lPDQP qqg5KcBXJ7waW7wZgTidEX/vJu/B9RG96iT7dFtD8sdnrXfiKI9rCK6XTogTq7cZRl+E EIRcJ+wz2G2eMvTItKuybxBVbx9l9n4nA8t9rN0q2L3mlYq2t4E9sHWSl+hD0WsNPXK9 kuXxzbJUPLFuVzfn3e4re1om9DZuAva/+zbPbtPBlsdcqMGiN/GZD60+pO61E5M0oAZE Tfp2ntkemBMD7IDznVcTSnd4Y8vQat8gDU5/SiwkjF5nhxJgDOh44Vtue0IDV9Zpyczg oLug== X-Gm-Message-State: AOJu0YycKLHkBP/pLgoKrhoUEfHnwq9QUiCuoSwomNFS4vKo43dTZB5b nox9SsmCFY1LnxAy0fChLrbzBLtsNdxlkdq6kvkJ9Q== X-Received: by 2002:a17:902:ecc8:b0:1cc:54b5:b4fa with SMTP id a8-20020a170902ecc800b001cc54b5b4famr4798799plh.18.1700007703221; Tue, 14 Nov 2023 16:21:43 -0800 (PST) Received: from vineet-framework.hq.rivosinc.com ([12.44.203.122]) by smtp.gmail.com with ESMTPSA id f8-20020a170902684800b001cc46240491sm6445110pln.136.2023.11.14.16.21.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 16:21:42 -0800 (PST) From: Vineet Gupta To: gcc-patches@gcc.gnu.org Cc: Jeff Law , Robin Dapp , gnu-toolchain@rivosinc.com, Patrick O'Neill , Vineet Gupta Subject: [PATCH RESEND v4] RISC-V: elide unnecessary sign extend when expanding cmp_and_jump Date: Tue, 14 Nov 2023 16:21:28 -0800 Message-Id: <20231115002128.2143444-1-vineetg@rivosinc.com> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782587305209178854 X-GMAIL-MSGID: 1782587305209178854 RV64 compare and branch instructions only support 64-bit operands. At Expand time, the backend conservatively zero/sign extends its operands even if not needed, such as incoming function args which ABI/ISA guarantee to be sign-extended already (this is true for SI, HI, QI operands) And subsequently REE fails to eliminate them as "missing defintion(s)" or "multiple definition(s) since function args don't have explicit definition. So during expand riscv_extend_comparands (), if an operand is a subreg-promoted SI with inner DI, which is representative of a function arg, just peel away the subreg to expose the DI, eliding the sign extension. As Jeff noted this routine is also used in if-conversion so potentially can also help there. Note there's currently patches floating around to improve REE and also a new pass to eliminate unneccesary extensions, but it is still beneficial to not generate those extra extensions in first place. It is obviously less work for post-reload passes such as REE, but even for earlier passes, such as combine, having to deal with one less thing and ensuing fewer combinations is a win too. Way too many existing tests used to observe this issue. e.g. gcc.c-torture/compile/20190827-1.c -O2 -march=rv64gc It elimiates the SEXT.W v3 of this patch was deemed clean by Pre-commit CI #499. Will wait for this version to be cleared by CI as well. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_sign_extend_if_not_subreg_prom): New. * (riscv_extend_comparands): Call New function on operands. Signed-off-by: Vineet Gupta --- gcc/config/riscv/riscv.cc | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index ecee7eb4727c..389633e44cac 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -3691,6 +3691,24 @@ riscv_zero_if_equal (rtx cmp0, rtx cmp1) cmp0, cmp1, 0, 0, OPTAB_DIRECT); } +/* Helper function for riscv_extend_comparands to Sign-extend the OP. + However if the OP is SI subreg promoted with an inner DI, such as + (subreg/s/v:SI (reg/v:DI) 0) + just peel off the SUBREG to get DI, avoiding extraneous extension. */ + +static void +riscv_sign_extend_if_not_subreg_prom (rtx *op) +{ + if (GET_CODE (*op) == SUBREG + && SUBREG_PROMOTED_VAR_P (*op) + && SUBREG_PROMOTED_SIGNED_P (*op) + && (GET_MODE_SIZE (GET_MODE (XEXP (*op, 0))).to_constant () + == GET_MODE_SIZE (word_mode))) + *op = XEXP (*op, 0); + else + *op = gen_rtx_SIGN_EXTEND (word_mode, *op); +} + /* Sign- or zero-extend OP0 and OP1 for integer comparisons. */ static void @@ -3720,9 +3738,10 @@ riscv_extend_comparands (rtx_code code, rtx *op0, rtx *op1) } else { - *op0 = gen_rtx_SIGN_EXTEND (word_mode, *op0); + riscv_sign_extend_if_not_subreg_prom (op0); + if (*op1 != const0_rtx) - *op1 = gen_rtx_SIGN_EXTEND (word_mode, *op1); + riscv_sign_extend_if_not_subreg_prom (op1); } } }