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[135.19.110.125]) by smtp.gmail.com with ESMTPSA id u2-20020a05621411a200b00674a45499dcsm25274qvv.88.2023.11.14.15.00.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 15:00:27 -0800 (PST) From: Jonathan Marek To: freedreno@lists.freedesktop.org Cc: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Kuogee Hsieh , Jessica Zhang , Vinod Polimera , Kalyan Thota , Konrad Dybcio , Arnaud Vrac , linux-arm-msm@vger.kernel.org (open list:DRM DRIVER FOR MSM ADRENO GPU), dri-devel@lists.freedesktop.org (open list:DRM DRIVER FOR MSM ADRENO GPU), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 1/6] drm/msm/dpu: fix video mode DSC for DSI Date: Tue, 14 Nov 2023 17:58:29 -0500 Message-Id: <20231114225857.19702-2-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20231114225857.19702-1-jonathan@marek.ca> References: <20231114225857.19702-1-jonathan@marek.ca> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Tue, 14 Nov 2023 15:01:03 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782582226306616461 X-GMAIL-MSGID: 1782582226306616461 Add necessary DPU changes for DSC to work with DSI video mode. Note this changes the logic to enable HCTL to match downstream, it will now be enabled for the no-DSC no-widebus case. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 2 +- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 11 +++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 13 ++++++++++++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 1 + 5 files changed, 26 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 1cf7ff6caff4..d745c8678b9d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -2477,7 +2477,7 @@ enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder) return INTF_MODE_NONE; } -unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc) +unsigned int dpu_encoder_helper_get_dsc(const struct dpu_encoder_phys *phys_enc) { struct drm_encoder *encoder = phys_enc->parent; struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h index 6f04c3d56e77..7e27a7da0887 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h @@ -332,7 +332,7 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode( * used for this encoder. * @phys_enc: Pointer to physical encoder structure */ -unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc); +unsigned int dpu_encoder_helper_get_dsc(const struct dpu_encoder_phys *phys_enc); /** * dpu_encoder_helper_split_config - split display configuration helper function diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index a01fda711883..df10800a9615 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -100,6 +100,8 @@ static void drm_mode_to_intf_timing_params( } timing->wide_bus_en = dpu_encoder_is_widebus_enabled(phys_enc->parent); + if (dpu_encoder_helper_get_dsc(phys_enc)) + timing->compression_en = true; /* * for DP, divide the horizonal parameters by 2 when @@ -112,6 +114,15 @@ static void drm_mode_to_intf_timing_params( timing->h_front_porch = timing->h_front_porch >> 1; timing->hsync_pulse_width = timing->hsync_pulse_width >> 1; } + + /* + * for DSI, if compression is enabled, then divide the horizonal active + * timing parameters by compression ratio. + */ + if (phys_enc->hw_intf->cap->type != INTF_DP && timing->compression_en) { + timing->width = timing->width / 3; /* XXX: don't assume 3:1 compression ratio */ + timing->xres = timing->width; + } } static u32 get_horizontal_total(const struct dpu_hw_intf_timing_params *timing) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index e8b8908d3e12..d6fe45a6da2d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -166,10 +166,21 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, * video timing. It is recommended to enable it for all cases, except * if compression is enabled in 1 pixel per clock mode */ + if (!p->compression_en || p->wide_bus_en) + intf_cfg2 |= INTF_CFG2_DATA_HCTL_EN; + if (p->wide_bus_en) - intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN | INTF_CFG2_DATA_HCTL_EN; + intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN; data_width = p->width; + if (p->wide_bus_en && !dp_intf) + data_width = p->width >> 1; + + if (p->compression_en) + intf_cfg2 |= INTF_CFG2_DCE_DATA_COMPRESS; + + if (p->compression_en && dp_intf) + DPU_ERROR("missing adjustments for DSC+DP\n"); hsync_data_start_x = hsync_start_x; hsync_data_end_x = hsync_start_x + data_width - 1; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h index c539025c418b..15a5fdadd0a0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h @@ -33,6 +33,7 @@ struct dpu_hw_intf_timing_params { u32 hsync_skew; bool wide_bus_en; + bool compression_en; }; struct dpu_hw_intf_prog_fetch { From patchwork Tue Nov 14 22:58:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Marek X-Patchwork-Id: 165122 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:6358:a59:b0:164:83eb:24d7 with SMTP id 25csp2254887rwb; Tue, 14 Nov 2023 15:01:19 -0800 (PST) X-Google-Smtp-Source: AGHT+IHdTwR9ZhKIvZ+2pZ+pTkZYWHYfsSjv04zz9DXaF1tLXx3O7z0mmYgWUK8r6TILQC6PGr/t X-Received: by 2002:a05:6870:bd46:b0:1e9:af65:e30b with SMTP id og6-20020a056870bd4600b001e9af65e30bmr15507317oab.38.1700002879672; Tue, 14 Nov 2023 15:01:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700002879; cv=none; d=google.com; s=arc-20160816; b=TT9HmRo0Q3mbXlsD6KSdTTBiJE6ig9Dw/jW8K8z2hvmasmK1bhdbgOJVUteNCdKc3P NTSRqp6fJc1mA3HHal4RFnktJGaUXaWCEfTSgSDDRTij0MnMzFyGXCoGhc4mUN+o66VG 0smtIJltPb2oTwSZ9jeu3+8Q0tTAW1EzLbsxYzVmM2LYioFEZ9E0//mckE7XJVInV6Jt /9I5Kvwj5hESJP4qXcewUGjGRTQAFBE0ulupjd8fhKSuJaGZRLuYv2ILxiFrOaTNk1Q2 BB5btDddW0LSebMBiruiNiv792Jfb4PefXQRkp+rgCjPx7SQpVS8LZK+p0wOLmSj11+w GgWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=w/GFqO4G/MklaH9jw4JV/Pzz1KPVstRySwUanh5xWC0=; fh=LaCKDShnR+ozrrSQ0mRdij6kZAEWj/Wyvmszaw04AvU=; b=NAGlie+qelFhdzko5TF1zURnXofidi4F918iG9572u3eFyfFUc+sEQB0PJo0a5sPIo jXYiuW0s40nbQWhnx1+fcj3d0G/IdJPDv/3wbDDICYxFEUfSenp3FCzQl8WIHm6bwtVt eX08RVaayTZqvM4r+eo+PDsaH+VsV/Gvy/6a0JFfBA9H5GdDpxCiQLT9Yv5zgnA+vjET IILaCH/mNLNAH/b0rA/scAfemHS40FA1JdN8ayeHYKq3yTz66+bfY87EpWa52nGzXiyt Yv8CqaFBBCPtMzMhy8kQOey76gyr/obIroFB250QsQvIP/fvkFtgByv8fsoMkn5SaVbg MQug== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@marek.ca header.s=google header.b=ZtISVJTJ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from lipwig.vger.email (lipwig.vger.email. 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[135.19.110.125]) by smtp.gmail.com with ESMTPSA id u2-20020a05621411a200b00674a45499dcsm25274qvv.88.2023.11.14.15.00.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 15:00:31 -0800 (PST) From: Jonathan Marek To: freedreno@lists.freedesktop.org Cc: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Jessica Zhang , Konrad Dybcio , Jiasheng Jiang , linux-arm-msm@vger.kernel.org (open list:DRM DRIVER FOR MSM ADRENO GPU), dri-devel@lists.freedesktop.org (open list:DRM DRIVER FOR MSM ADRENO GPU), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 2/6] drm/msm/dsi: set video mode widebus enable bit when widebus is enabled Date: Tue, 14 Nov 2023 17:58:30 -0500 Message-Id: <20231114225857.19702-3-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20231114225857.19702-1-jonathan@marek.ca> References: <20231114225857.19702-1-jonathan@marek.ca> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Tue, 14 Nov 2023 15:01:08 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782582219595861078 X-GMAIL-MSGID: 1782582219595861078 The value returned by msm_dsi_wide_bus_enabled() doesn't match what the driver is doing in video mode. Fix that by actually enabling widebus for video mode. Fixes: efcbd6f9cdeb ("drm/msm/dsi: Enable widebus for DSI") Signed-off-by: Jonathan Marek Reviewed-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Reviewed-by: Jessica Zhang --- drivers/gpu/drm/msm/dsi/dsi.xml.h | 1 + drivers/gpu/drm/msm/dsi/dsi_host.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h index 2a7d980e12c3..f0b3cdc020a1 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.xml.h +++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h @@ -231,6 +231,7 @@ static inline uint32_t DSI_VID_CFG0_TRAFFIC_MODE(enum dsi_traffic_mode val) #define DSI_VID_CFG0_HSA_POWER_STOP 0x00010000 #define DSI_VID_CFG0_HBP_POWER_STOP 0x00100000 #define DSI_VID_CFG0_HFP_POWER_STOP 0x01000000 +#define DSI_VID_CFG0_DATABUS_WIDEN 0x02000000 #define DSI_VID_CFG0_PULSE_MODE_HSA_HE 0x10000000 #define REG_DSI_VID_CFG1 0x0000001c diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index deeecdfd6c4e..f2c1cbd08d4d 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -745,6 +745,8 @@ static void dsi_ctrl_enable(struct msm_dsi_host *msm_host, data |= DSI_VID_CFG0_TRAFFIC_MODE(dsi_get_traffic_mode(flags)); data |= DSI_VID_CFG0_DST_FORMAT(dsi_get_vid_fmt(mipi_fmt)); data |= DSI_VID_CFG0_VIRT_CHANNEL(msm_host->channel); + if (msm_dsi_host_is_wide_bus_enabled(&msm_host->base)) + data |= DSI_VID_CFG0_DATABUS_WIDEN; dsi_write(msm_host, REG_DSI_VID_CFG0, data); /* Do not swap RGB colors */ From patchwork Tue Nov 14 22:58:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Marek X-Patchwork-Id: 165124 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:6358:a59:b0:164:83eb:24d7 with SMTP id 25csp2255165rwb; Tue, 14 Nov 2023 15:01:40 -0800 (PST) X-Google-Smtp-Source: AGHT+IF4tCSXbFQ7KZZMvljWZvFs7bQ1pzfEact29ilkIeU3vux2N0/Gqy7C1OMPO9wPV2yigPNn X-Received: by 2002:a9d:5e93:0:b0:6d2:e1fc:f39b with SMTP id f19-20020a9d5e93000000b006d2e1fcf39bmr3751512otl.0.1700002900575; Tue, 14 Nov 2023 15:01:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700002900; cv=none; d=google.com; s=arc-20160816; b=EH5+LyMSRDODawM2eBLfS29FRP7z3j1tL3uKnasTzhQuTL0Q1DOrBcDV14xMaWiUBJ 7kHaosyLuD1QfXvwc0jpR628DRBj+m09XJEHqW7LoejxnvFMvimoozDhExiyrwFdh03w NInTTWpr9d6lv8zNi8yTbCZVKCkUSU7OoFguo9V1m4T29pyAMApDoB6hYaHQGm5oYL+D +S7lbwg0Ew/QJToDEGe6QKl8dfDIQeTFe5pphCkU6L7IX+RhA4/Qppp9POfbl2wkQv0L CVBbkQRrpJZT8HwQ5Dd2tnYt/DptWNev1hToiMlXOP/+ebXybv4CK1lS5bkZ2U/yXP5j fHAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=3bXNM4Q60WzU91mEPZf4VyqZpLI234VBPPnXZJAmol4=; fh=TYfdUrC4lqPSkACFST9l1m125NDrPCO8TsLlqEg/j/Q=; b=sUZbpAkfPJzbw3ilpXUmxBz7EbNY3DSeXu/z8VGpIFt+ojFlSyuivS7x8KUVdds+m1 rbvElx8m9JLRb5O0KKmbB+f+OqbzEFGASiN2TXczkEWk5chwjQeq5QYNJch+M9OWHvTY IChVuDlFX+Qmtoca4tPlsafPlcATRsco+jMJrLKCKgKvNQrF957s7FIlE3prCFEROBNl gOsDbxLxypYmHnwzvyFviFkO67Kyfyh7h1RWzq30oCSV9E5ZvdEG6HfcpYB50Ev/OurN yUMI0imOx/cBc1C7SXBNMy2vy2F2ffu6es+lTNr7XnIo1C7iAMTKKG5RJxYawhy0imcj RPag== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@marek.ca header.s=google header.b=R8MWxDcM; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from lipwig.vger.email (lipwig.vger.email. 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[135.19.110.125]) by smtp.gmail.com with ESMTPSA id u2-20020a05621411a200b00674a45499dcsm25274qvv.88.2023.11.14.15.00.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 15:00:34 -0800 (PST) From: Jonathan Marek To: freedreno@lists.freedesktop.org Cc: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Jessica Zhang , Konrad Dybcio , Jiasheng Jiang , Vinod Koul , linux-arm-msm@vger.kernel.org (open list:DRM DRIVER FOR MSM ADRENO GPU), dri-devel@lists.freedesktop.org (open list:DRM DRIVER FOR MSM ADRENO GPU), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 3/6] drm/msm/dsi: set VIDEO_COMPRESSION_MODE_CTRL_WC (fix video mode DSC) Date: Tue, 14 Nov 2023 17:58:31 -0500 Message-Id: <20231114225857.19702-4-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20231114225857.19702-1-jonathan@marek.ca> References: <20231114225857.19702-1-jonathan@marek.ca> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Tue, 14 Nov 2023 15:01:38 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782582241097393615 X-GMAIL-MSGID: 1782582241097393615 Video mode DSC won't work if this field is not set correctly. Set it to fix video mode DSC (for slice_per_pkt==1 cases at least). Fixes: 08802f515c3 ("drm/msm/dsi: Add support for DSC configuration") Signed-off-by: Jonathan Marek Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/dsi_host.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index f2c1cbd08d4d..66f198e21a7e 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -849,6 +849,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod u32 slice_per_intf, total_bytes_per_intf; u32 pkt_per_line; u32 eol_byte_num; + u32 bytes_per_pkt; /* first calculate dsc parameters and then program * compress mode registers @@ -856,6 +857,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod slice_per_intf = msm_dsc_get_slices_per_intf(dsc, hdisplay); total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf; + bytes_per_pkt = dsc->slice_chunk_size; /* * slice_per_pkt; */ eol_byte_num = total_bytes_per_intf % 3; @@ -893,6 +895,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg_ctrl); dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2); } else { + reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_WC(bytes_per_pkt); dsi_write(msm_host, REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg); } } From patchwork Tue Nov 14 22:58:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Marek X-Patchwork-Id: 165125 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:6358:a59:b0:164:83eb:24d7 with SMTP id 25csp2255426rwb; Tue, 14 Nov 2023 15:02:02 -0800 (PST) X-Google-Smtp-Source: AGHT+IHl4YjJbgNrE7kU0ECQFWP5bBKYQaxB9XKwdtoVX9+dd2pdSnLQa3q7eyQYGlTe+lDyyam0 X-Received: by 2002:a05:6870:f609:b0:1f0:597d:fe25 with SMTP id ek9-20020a056870f60900b001f0597dfe25mr14819201oab.45.1700002921813; Tue, 14 Nov 2023 15:02:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700002921; cv=none; d=google.com; s=arc-20160816; b=RQq0moHA2m8I9b/i84gTaBawy0T85UEA6aIwwOJsbP5Sgvx1oKW6/Em61+iq2Fk9t0 fb/UsNvTRBriEGdINKLfVJczXhd/ebrRpyhe4V6GuumcrND83z+0Sg6uxRJQMCCwyQ7O KkpZ42PIRVNENnKJKlZoTfTByQG1SjfdxG/2jrwtVE2aYVRG/tIWPSJfSUgNVJ98UPOv OP0oLiZPB/JHr580Rk+gmsXk0hgBx/n9mVEh1rrqPaEfB9J/TJ1UZmBZxI+lAWaZuc98 2AFg5VzorG/G6TPppAUCLu41SFhBO8tYV0SqjL7/vbVToiELRQrRAyp8nlbXekDnQGm0 MEhA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=cpJg20SvqJHFde7hdRwbQhfmXK7eKDJA+6y+igvktAk=; fh=LaCKDShnR+ozrrSQ0mRdij6kZAEWj/Wyvmszaw04AvU=; b=ufRcKBZk1iPXbXw5X1K32oc0NdZi2lvwR4EZ+MEUiSOCz0cFKet107YsKFPqD+3LO4 RiqPzH8cl0JWaVqw5qJsU2o0yhf6GloDYagQYgtG+FAJTEnicZlU/tdX5YNNAT2HJRZw 9TKoxHOhdIMuHMRib8ekMyW1XviaGIg8qnxJ/zn1kMmiSYjlxRu4aHf+s1GOpx0OwQe0 07FchIWTmf5G/Y68inVbV0bfQvQTVrlkPQCpEDcxKrJe/DlLW+rO0F61F/x4u/po50RS elM+82vqa4o50PxaYlY+NXCvls3jyKxM4t/iuXZ6q06ATY+YcDR58AG2V7J2N6CHIsHn nOGA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@marek.ca header.s=google header.b=CaIrtYL5; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from agentk.vger.email (agentk.vger.email. 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[135.19.110.125]) by smtp.gmail.com with ESMTPSA id u2-20020a05621411a200b00674a45499dcsm25274qvv.88.2023.11.14.15.00.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 15:00:37 -0800 (PST) From: Jonathan Marek To: freedreno@lists.freedesktop.org Cc: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Jessica Zhang , Konrad Dybcio , Jiasheng Jiang , linux-arm-msm@vger.kernel.org (open list:DRM DRIVER FOR MSM ADRENO GPU), dri-devel@lists.freedesktop.org (open list:DRM DRIVER FOR MSM ADRENO GPU), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 4/6] drm/msm/dsi: add a comment to explain pkt_per_line encoding Date: Tue, 14 Nov 2023 17:58:32 -0500 Message-Id: <20231114225857.19702-5-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20231114225857.19702-1-jonathan@marek.ca> References: <20231114225857.19702-1-jonathan@marek.ca> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Tue, 14 Nov 2023 15:01:49 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782582263793884773 X-GMAIL-MSGID: 1782582263793884773 Make it clear why the pkt_per_line value is being "divided by 2". Signed-off-by: Jonathan Marek Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/dsi_host.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 66f198e21a7e..842765063b1b 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -877,6 +877,8 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod /* DSI_VIDEO_COMPRESSION_MODE & DSI_COMMAND_COMPRESSION_MODE * registers have similar offsets, so for below common code use * DSI_VIDEO_COMPRESSION_MODE_XXXX for setting bits + * + * pkt_per_line is log2 encoded, >>1 works for supported values (1,2,4) */ reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_PKT_PER_LINE(pkt_per_line >> 1); reg |= DSI_VIDEO_COMPRESSION_MODE_CTRL_EOL_BYTE_NUM(eol_byte_num); From patchwork Tue Nov 14 22:58:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Marek X-Patchwork-Id: 165127 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:6358:a59:b0:164:83eb:24d7 with SMTP id 25csp2255474rwb; Tue, 14 Nov 2023 15:02:04 -0800 (PST) X-Google-Smtp-Source: AGHT+IFGXfr6Hk31qPkCAUuSZfg5bFsO2FG8bBggFfMEiRAMJwIfq1K1j4og/PRQhv5bRG76Am2h X-Received: by 2002:a54:4015:0:b0:3ae:5c48:6f41 with SMTP id x21-20020a544015000000b003ae5c486f41mr13025765oie.28.1700002924692; Tue, 14 Nov 2023 15:02:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700002924; cv=none; d=google.com; s=arc-20160816; b=A95xe66zZbUWfwL4RnEWHMQQ80TppYXxye/LQIv/5ubu84Ed2WKuW2sncj4ru19a4e Ke7G86wviAqj6zbeXb7GYH4WNSaej3MNrQYa/wNuuU8TIyQYf8aKY/yoJV/6MaGum7RE CCMEbUQqMQKCJ3jceRk5lV1Um0aZoGQGMe2oR6ct9tE6dflTjpaynVVAz3o04iHqJYrM 6lJrxS+YCmwZvga/FnOLEU9CNJdESJw3cWRBk90nbZ9LFk7a+7vt22KlUb6JYGuRwfFj lsUbWFWprcsQGFoZsY1wyVvABLxY48ZaKdx03s6AO8CE66Tr3F6Ng3vv9l+xKnjiN7wK mYrg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=QnYJwckhVUb/hQ+VqWd+HwwnYfkR02viqwW11QKBHpA=; fh=hNzy279nNrT6vqFZVGbdEj98BPqlmJm87ylu2ANBV4I=; b=W8HxBZV/fxiQZ0XSnNmRC8YiM4xNre/+6yxCuZYjZ5UnDbG5DTATooadBLQTSDTQjU 6TY8BgxCzpKsAvfOnXLqNSqdQhCMzbsKpMy92X5ShKbKmxYv6fDU55d7YF9p3W3Ic/ys kLC2fG2AXRORN/2pxst8GkEt9tshuH4VBwzYyhFtFiOUu7gN7jVSs4zN4Yx49iDThqO0 J9UwUnl3lLjw9wNm0zyRtWnwbytsgemS1uhKoHLghv0ck8fT+w64q8mpOBAp6z281fKg xzcyOvpqVNIE1ev8FJmY7wqGopNAf3NlLunGPrbMUrP1H8vy0ndC5q//O7sspkSf2iiw EbOg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@marek.ca header.s=google header.b=UPLkPeCL; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from agentk.vger.email (agentk.vger.email. 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[135.19.110.125]) by smtp.gmail.com with ESMTPSA id u2-20020a05621411a200b00674a45499dcsm25274qvv.88.2023.11.14.15.00.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 15:00:40 -0800 (PST) From: Jonathan Marek To: freedreno@lists.freedesktop.org Cc: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Jessica Zhang , Konrad Dybcio , Jiasheng Jiang , linux-arm-msm@vger.kernel.org (open list:DRM DRIVER FOR MSM ADRENO GPU), dri-devel@lists.freedesktop.org (open list:DRM DRIVER FOR MSM ADRENO GPU), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 5/6] drm/msm/dsi: support DSC configurations with slice_per_pkt > 1 Date: Tue, 14 Nov 2023 17:58:33 -0500 Message-Id: <20231114225857.19702-6-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20231114225857.19702-1-jonathan@marek.ca> References: <20231114225857.19702-1-jonathan@marek.ca> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Tue, 14 Nov 2023 15:01:54 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782582266607985295 X-GMAIL-MSGID: 1782582266607985295 Add a dsc_slice_per_pkt field to mipi_dsi_device struct and the necessary changes to msm driver to support this field. Note that the removed "pkt_per_line = slice_per_intf * slice_per_pkt" comment is incorrect. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/dsi/dsi_host.c | 25 ++++++++++--------------- include/drm/drm_mipi_dsi.h | 1 + 2 files changed, 11 insertions(+), 15 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 842765063b1b..892a463a7e03 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -161,6 +161,7 @@ struct msm_dsi_host { struct drm_display_mode *mode; struct drm_dsc_config *dsc; + unsigned int dsc_slice_per_pkt; /* connected device info */ unsigned int channel; @@ -857,17 +858,10 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod slice_per_intf = msm_dsc_get_slices_per_intf(dsc, hdisplay); total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf; - bytes_per_pkt = dsc->slice_chunk_size; /* * slice_per_pkt; */ + bytes_per_pkt = dsc->slice_chunk_size * msm_host->dsc_slice_per_pkt; eol_byte_num = total_bytes_per_intf % 3; - - /* - * Typically, pkt_per_line = slice_per_intf * slice_per_pkt. - * - * Since the current driver only supports slice_per_pkt = 1, - * pkt_per_line will be equal to slice per intf for now. - */ - pkt_per_line = slice_per_intf; + pkt_per_line = slice_per_intf / msm_host->dsc_slice_per_pkt; if (is_cmd_mode) /* packet data type */ reg = DSI_COMMAND_COMPRESSION_MODE_CTRL_STREAM0_DATATYPE(MIPI_DSI_DCS_LONG_WRITE); @@ -1004,12 +998,8 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) else /* * When DSC is enabled, WC = slice_chunk_size * slice_per_pkt + 1. - * Currently, the driver only supports default value of slice_per_pkt = 1 - * - * TODO: Expand mipi_dsi_device struct to hold slice_per_pkt info - * and adjust DSC math to account for slice_per_pkt. */ - wc = msm_host->dsc->slice_chunk_size + 1; + wc = msm_host->dsc->slice_chunk_size * msm_host->dsc_slice_per_pkt + 1; dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL, DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) | @@ -1636,8 +1626,13 @@ static int dsi_host_attach(struct mipi_dsi_host *host, msm_host->lanes = dsi->lanes; msm_host->format = dsi->format; msm_host->mode_flags = dsi->mode_flags; - if (dsi->dsc) + if (dsi->dsc) { msm_host->dsc = dsi->dsc; + msm_host->dsc_slice_per_pkt = dsi->dsc_slice_per_pkt; + /* for backwards compatibility, assume 1 if not set */ + if (!msm_host->dsc_slice_per_pkt) + msm_host->dsc_slice_per_pkt = 1; + } /* Some gpios defined in panel DT need to be controlled by host */ ret = dsi_host_init_panel_gpios(msm_host, &dsi->dev); diff --git a/include/drm/drm_mipi_dsi.h b/include/drm/drm_mipi_dsi.h index c9df0407980c..3e32fa52d94b 100644 --- a/include/drm/drm_mipi_dsi.h +++ b/include/drm/drm_mipi_dsi.h @@ -193,6 +193,7 @@ struct mipi_dsi_device { unsigned long hs_rate; unsigned long lp_rate; struct drm_dsc_config *dsc; + unsigned int dsc_slice_per_pkt; }; #define MIPI_DSI_MODULE_PREFIX "mipi-dsi:" From patchwork Tue Nov 14 22:58:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonathan Marek X-Patchwork-Id: 165126 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:6358:a59:b0:164:83eb:24d7 with SMTP id 25csp2255456rwb; Tue, 14 Nov 2023 15:02:04 -0800 (PST) X-Google-Smtp-Source: AGHT+IH0TzZcbuI/ms5dUeCrl4uXYtff47N4+AXutVtDv9NKh5ayQ8MuRzzDNzbx2fK3DafEDTLK X-Received: by 2002:a9d:6c52:0:b0:6b9:6419:1cde with SMTP id g18-20020a9d6c52000000b006b964191cdemr3662502otq.22.1700002923929; Tue, 14 Nov 2023 15:02:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1700002923; cv=none; d=google.com; s=arc-20160816; b=OkG3fyCeKlUMuZUbakv6Btui0QkHV89/V0lpWkYTwvxGJS2sx7G8Fvj66THBIB19a3 s7fypoBeay7gyVeYt81qUvwBW8Bv5TTQxMh77ouFNVINKDCjjLC2Rms5lLnkgLLUZou0 aHhoKUKAL+umvh7QzqPE1P0aDdCo6I0Kgc/aGCO0d74FGUGXnb//7YOXQ47FMLMG3G4H p/xsDR6ny2h4N6lmILnLiPCCGfCY3lWqCpPRhaYnBrC9/m0wSlbRmno6xpOLQOrM77a4 mdt/9ZPNkdxuGeMvG/uf76kzlhJJQq1cnkvhH9OAHtj1HvC893UA9zSDP6/SLpjEEQrR Tf5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=YR/mkTlXJRgIJS/EJMZQRz4ww5S2W5Npa8fLQfW52YM=; fh=Taw2aTPrWCmdBsyCnBge+kB40ZNcXykoKebViUVdeSU=; b=O8ccBeKbu9SgM/3a36gSIyVjd1vlXWgr29CuYh2JX+wuAVrnUBCxv/NYttjyRjeOva yIk3gW8SsIdnR9vti5HLj+ZFDS6t0EqNSFaXCWb2s22KaTybdHF4WPsOcXk50mw3mOb7 IBkvSThujXE1zzzvwc+1avwiZFthvLsr8kVmVXFv4GTaPGFHMHT6pIcWhvORDuUb9vj/ y9whkMML/GUI8VgJgDSECe1zW7bXUh7E+pWUytBx7CfAMw4q3L4YOdoFCS2EvuGjgYcI byENGwSHFoU2IQga2MmFNBScirPtUgo5rLdr5QebrfoTDOamczyPrV2QkoksRYCXXF1+ Ka4A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@marek.ca header.s=google header.b=MS2inVka; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from agentk.vger.email (agentk.vger.email. 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[135.19.110.125]) by smtp.gmail.com with ESMTPSA id u2-20020a05621411a200b00674a45499dcsm25274qvv.88.2023.11.14.15.00.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Nov 2023 15:00:46 -0800 (PST) From: Jonathan Marek To: freedreno@lists.freedesktop.org Cc: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Konrad Dybcio , Jessica Zhang , Jiasheng Jiang , Doug Anderson , linux-arm-msm@vger.kernel.org (open list:DRM DRIVER FOR MSM ADRENO GPU), dri-devel@lists.freedesktop.org (open list:DRM DRIVER FOR MSM ADRENO GPU), linux-kernel@vger.kernel.org (open list) Subject: [PATCH v2 6/6] drm/msm/dsi: fix DSC for the bonded DSI case Date: Tue, 14 Nov 2023 17:58:34 -0500 Message-Id: <20231114225857.19702-7-jonathan@marek.ca> X-Mailer: git-send-email 2.26.1 In-Reply-To: <20231114225857.19702-1-jonathan@marek.ca> References: <20231114225857.19702-1-jonathan@marek.ca> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Tue, 14 Nov 2023 15:01:53 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782582265975408706 X-GMAIL-MSGID: 1782582265975408706 For the bonded DSI case, DSC pic_width and timing calculations should use the width of a single panel instead of the total combined width. Signed-off-by: Jonathan Marek --- drivers/gpu/drm/msm/dsi/dsi.h | 3 ++- drivers/gpu/drm/msm/dsi/dsi_host.c | 20 +++++++++++--------- drivers/gpu/drm/msm/dsi/dsi_manager.c | 2 +- 3 files changed, 14 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index 28379b1af63f..3a641e69447c 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h @@ -93,7 +93,8 @@ int msm_dsi_host_power_off(struct mipi_dsi_host *host); int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host, const struct drm_display_mode *mode); enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host, - const struct drm_display_mode *mode); + const struct drm_display_mode *mode, + bool is_bonded_dsi); unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host); int msm_dsi_host_register(struct mipi_dsi_host *host); void msm_dsi_host_unregister(struct mipi_dsi_host *host); diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 892a463a7e03..cf06736e5a60 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -940,8 +940,7 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) mode->hdisplay, mode->vdisplay); return; } - - dsc->pic_width = mode->hdisplay; + dsc->pic_width = hdisplay; dsc->pic_height = mode->vdisplay; DBG("Mode %dx%d\n", dsc->pic_width, dsc->pic_height); @@ -952,6 +951,11 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) if (ret) return; + if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) + dsi_update_dsc_timing(msm_host, false, hdisplay); + else + dsi_update_dsc_timing(msm_host, true, hdisplay); + /* Divide the display by 3 but keep back/font porch and * pulse width same */ @@ -968,9 +972,6 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) } if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) { - if (msm_host->dsc) - dsi_update_dsc_timing(msm_host, false, mode->hdisplay); - dsi_write(msm_host, REG_DSI_ACTIVE_H, DSI_ACTIVE_H_START(ha_start) | DSI_ACTIVE_H_END(ha_end)); @@ -989,9 +990,6 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) DSI_ACTIVE_VSYNC_VPOS_START(vs_start) | DSI_ACTIVE_VSYNC_VPOS_END(vs_end)); } else { /* command mode */ - if (msm_host->dsc) - dsi_update_dsc_timing(msm_host, true, mode->hdisplay); - /* image data and 1 byte write_memory_start cmd */ if (!msm_host->dsc) wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1; @@ -2479,7 +2477,8 @@ int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host, } enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host, - const struct drm_display_mode *mode) + const struct drm_display_mode *mode, + bool is_bonded_dsi) { struct msm_dsi_host *msm_host = to_msm_dsi_host(host); struct drm_dsc_config *dsc = msm_host->dsc; @@ -2489,6 +2488,9 @@ enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host, if (!msm_host->dsc) return MODE_OK; + if (is_bonded_dsi) + pic_width = mode->hdisplay / 2; + if (pic_width % dsc->slice_width) { pr_err("DSI: pic_width %d has to be multiple of slice %d\n", pic_width, dsc->slice_width); diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c index 896f369fdd53..2ca1a7ca3659 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c @@ -455,7 +455,7 @@ static enum drm_mode_status dsi_mgr_bridge_mode_valid(struct drm_bridge *bridge, return MODE_ERROR; } - return msm_dsi_host_check_dsc(host, mode); + return msm_dsi_host_check_dsc(host, mode, IS_BONDED_DSI()); } static const struct drm_bridge_funcs dsi_mgr_bridge_funcs = {