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(unknown [58.22.7.114]) by zwqz-smtp-mta-g0-0 (Coremail) with SMTP id _____wDXlCOJWVNlbG5MDA--.55303S2; Tue, 14 Nov 2023 19:27:08 +0800 (CST) From: Andy Yan To: heiko@sntech.de Cc: hjc@rock-chips.com, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, devicetree@vger.kernel.org, sebastian.reichel@collabora.com, kever.yang@rock-chips.com, chris.obbard@collabora.com, s.hauer@pengutronix.de, Andy Yan Subject: [PATCH 01/11] drm/rockchip: move output interface related definition to rockchip_drm_drv.h Date: Tue, 14 Nov 2023 19:27:04 +0800 Message-Id: <20231114112704.1770880-1-andyshrk@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231114112534.1770731-1-andyshrk@163.com> References: <20231114112534.1770731-1-andyshrk@163.com> MIME-Version: 1.0 X-CM-TRANSID: _____wDXlCOJWVNlbG5MDA--.55303S2 X-Coremail-Antispam: 1Uf129KBjvJXoWxtFW3Zw17XF4DCr1xZr45trb_yoW3GFyrpa 1DAryjvrW7CF42qrnrAFs3Ar4fta1qyayxCr97W3WavF1Ikr1DG3sxWws5Xr9xXr1xAFy2 krsrG34UZFW2gr7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07jSD73UUUUU= X-Originating-IP: [58.22.7.114] X-CM-SenderInfo: 5dqg52xkunqiywtou0bp/xtbBnA0oXlghlUycewAAsg X-Spam-Status: No, score=0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,RCVD_IN_SORBS_WEB, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Tue, 14 Nov 2023 03:29:04 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782538679565447681 X-GMAIL-MSGID: 1782538679565447681 From: Andy Yan The output interface related definition can shared between vop and vop2, move them to rockchip_drm_drv.h can avoid duplicated definition. Signed-off-by: Andy Yan --- drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 1 - drivers/gpu/drm/rockchip/cdn-dp-core.c | 1 - drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c | 1 - drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c | 1 - drivers/gpu/drm/rockchip/inno_hdmi.c | 1 - drivers/gpu/drm/rockchip/rk3066_hdmi.c | 1 - drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 17 +++++++++++++++++ drivers/gpu/drm/rockchip/rockchip_drm_vop.h | 12 +----------- drivers/gpu/drm/rockchip/rockchip_drm_vop2.h | 16 +--------------- drivers/gpu/drm/rockchip/rockchip_lvds.c | 1 - drivers/gpu/drm/rockchip/rockchip_rgb.c | 1 - 11 files changed, 19 insertions(+), 34 deletions(-) diff --git a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c index 84aa811ca1e9..bd08d57486fe 100644 --- a/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c +++ b/drivers/gpu/drm/rockchip/analogix_dp-rockchip.c @@ -30,7 +30,6 @@ #include #include "rockchip_drm_drv.h" -#include "rockchip_drm_vop.h" #define RK3288_GRF_SOC_CON6 0x25c #define RK3288_EDP_LCDC_SEL BIT(5) diff --git a/drivers/gpu/drm/rockchip/cdn-dp-core.c b/drivers/gpu/drm/rockchip/cdn-dp-core.c index 21254e4e107a..a855c45ae7f3 100644 --- a/drivers/gpu/drm/rockchip/cdn-dp-core.c +++ b/drivers/gpu/drm/rockchip/cdn-dp-core.c @@ -24,7 +24,6 @@ #include "cdn-dp-core.h" #include "cdn-dp-reg.h" -#include "rockchip_drm_vop.h" static inline struct cdn_dp_device *connector_to_dp(struct drm_connector *connector) { diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c index 6396f9324dab..4cc8ed8f4fbd 100644 --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi-rockchip.c @@ -26,7 +26,6 @@ #include #include "rockchip_drm_drv.h" -#include "rockchip_drm_vop.h" #define DSI_PHY_RSTZ 0xa0 #define PHY_DISFORCEPLL 0 diff --git a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c index 341550199111..fe33092abbe7 100644 --- a/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c +++ b/drivers/gpu/drm/rockchip/dw_hdmi-rockchip.c @@ -18,7 +18,6 @@ #include #include "rockchip_drm_drv.h" -#include "rockchip_drm_vop.h" #define RK3228_GRF_SOC_CON2 0x0408 #define RK3228_HDMI_SDAIN_MSK BIT(14) diff --git a/drivers/gpu/drm/rockchip/inno_hdmi.c b/drivers/gpu/drm/rockchip/inno_hdmi.c index 6e5b922a121e..f6d819803c0e 100644 --- a/drivers/gpu/drm/rockchip/inno_hdmi.c +++ b/drivers/gpu/drm/rockchip/inno_hdmi.c @@ -23,7 +23,6 @@ #include #include "rockchip_drm_drv.h" -#include "rockchip_drm_vop.h" #include "inno_hdmi.h" diff --git a/drivers/gpu/drm/rockchip/rk3066_hdmi.c b/drivers/gpu/drm/rockchip/rk3066_hdmi.c index fa6e592e0276..78136d0c5a65 100644 --- a/drivers/gpu/drm/rockchip/rk3066_hdmi.c +++ b/drivers/gpu/drm/rockchip/rk3066_hdmi.c @@ -17,7 +17,6 @@ #include "rk3066_hdmi.h" #include "rockchip_drm_drv.h" -#include "rockchip_drm_vop.h" #define DEFAULT_PLLA_RATE 30000000 diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h index aeb03a57240f..3d8ab2defa1b 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h @@ -20,6 +20,23 @@ #define ROCKCHIP_MAX_CONNECTOR 2 #define ROCKCHIP_MAX_CRTC 4 +/* + * display output interface supported by rockchip lcdc + */ +#define ROCKCHIP_OUT_MODE_P888 0 +#define ROCKCHIP_OUT_MODE_BT1120 0 +#define ROCKCHIP_OUT_MODE_P666 1 +#define ROCKCHIP_OUT_MODE_P565 2 +#define ROCKCHIP_OUT_MODE_BT656 5 +#define ROCKCHIP_OUT_MODE_S888 8 +#define ROCKCHIP_OUT_MODE_S888_DUMMY 12 +#define ROCKCHIP_OUT_MODE_YUV420 14 +/* for use special outface */ +#define ROCKCHIP_OUT_MODE_AAAA 15 + +/* output flags */ +#define ROCKCHIP_OUTPUT_DSI_DUAL BIT(0) + struct drm_device; struct drm_connector; struct iommu_domain; diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h index 4b2daefeb8c1..43d9c9191b7a 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop.h @@ -277,17 +277,7 @@ struct vop_data { /* dst alpha ctrl define */ #define DST_FACTOR_M0(x) (((x) & 0x7) << 6) -/* - * display output interface supported by rockchip lcdc - */ -#define ROCKCHIP_OUT_MODE_P888 0 -#define ROCKCHIP_OUT_MODE_P666 1 -#define ROCKCHIP_OUT_MODE_P565 2 -/* for use special outface */ -#define ROCKCHIP_OUT_MODE_AAAA 15 - -/* output flags */ -#define ROCKCHIP_OUTPUT_DSI_DUAL BIT(0) + enum alpha_mode { ALPHA_STRAIGHT, diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h index 56fd31e05238..7175f46a2014 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h @@ -7,10 +7,9 @@ #ifndef _ROCKCHIP_DRM_VOP2_H #define _ROCKCHIP_DRM_VOP2_H -#include "rockchip_drm_vop.h" - #include #include +#include "rockchip_drm_vop.h" #define VOP_FEATURE_OUTPUT_10BIT BIT(0) @@ -166,19 +165,6 @@ struct vop2_data { #define WB_YRGB_FIFO_FULL_INTR BIT(18) #define WB_COMPLETE_INTR BIT(19) -/* - * display output interface supported by rockchip lcdc - */ -#define ROCKCHIP_OUT_MODE_P888 0 -#define ROCKCHIP_OUT_MODE_BT1120 0 -#define ROCKCHIP_OUT_MODE_P666 1 -#define ROCKCHIP_OUT_MODE_P565 2 -#define ROCKCHIP_OUT_MODE_BT656 5 -#define ROCKCHIP_OUT_MODE_S888 8 -#define ROCKCHIP_OUT_MODE_S888_DUMMY 12 -#define ROCKCHIP_OUT_MODE_YUV420 14 -/* for use special outface */ -#define ROCKCHIP_OUT_MODE_AAAA 15 enum vop_csc_format { CSC_BT601L, diff --git a/drivers/gpu/drm/rockchip/rockchip_lvds.c b/drivers/gpu/drm/rockchip/rockchip_lvds.c index f0f47e9abf5a..59341654ec32 100644 --- a/drivers/gpu/drm/rockchip/rockchip_lvds.c +++ b/drivers/gpu/drm/rockchip/rockchip_lvds.c @@ -27,7 +27,6 @@ #include #include "rockchip_drm_drv.h" -#include "rockchip_drm_vop.h" #include "rockchip_lvds.h" #define DISPLAY_OUTPUT_RGB 0 diff --git a/drivers/gpu/drm/rockchip/rockchip_rgb.c b/drivers/gpu/drm/rockchip/rockchip_rgb.c index c677b71ae516..dbfbde24698e 100644 --- a/drivers/gpu/drm/rockchip/rockchip_rgb.c +++ b/drivers/gpu/drm/rockchip/rockchip_rgb.c @@ -19,7 +19,6 @@ #include #include "rockchip_drm_drv.h" -#include "rockchip_drm_vop.h" #include "rockchip_rgb.h" struct rockchip_rgb { From patchwork Tue Nov 14 11:27:16 2023 Content-Type: text/plain; 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(unknown [58.22.7.114]) by zwqz-smtp-mta-g3-0 (Coremail) with SMTP id _____wA3nruVWVNlhUdEDA--.55205S2; Tue, 14 Nov 2023 19:27:20 +0800 (CST) From: Andy Yan To: heiko@sntech.de Cc: hjc@rock-chips.com, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, devicetree@vger.kernel.org, sebastian.reichel@collabora.com, kever.yang@rock-chips.com, chris.obbard@collabora.com, s.hauer@pengutronix.de, Andy Yan Subject: [PATCH 02/11] Revert "drm/rockchip: vop2: Use regcache_sync() to fix suspend/resume" Date: Tue, 14 Nov 2023 19:27:16 +0800 Message-Id: <20231114112716.1770940-1-andyshrk@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231114112534.1770731-1-andyshrk@163.com> References: <20231114112534.1770731-1-andyshrk@163.com> MIME-Version: 1.0 X-CM-TRANSID: _____wA3nruVWVNlhUdEDA--.55205S2 X-Coremail-Antispam: 1Uf129KBjvJXoW7Cw1rGr1xXF4xCFy7tr45trb_yoW8CryxpF W7AryYqr4IgFWjqw1kAF4UAFyYyrnFyay3Crn7K3WfZr13Krn2yrn8GF1UZF98Ar1xur42 yFs7ta47CFW7uFJanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07jo4E_UUUUU= X-Originating-IP: [58.22.7.114] X-CM-SenderInfo: 5dqg52xkunqiywtou0bp/xtbBnA0oXlghlUycewABsh X-Spam-Status: No, score=0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,RCVD_IN_SORBS_WEB, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Tue, 14 Nov 2023 03:28:32 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782538637000993678 X-GMAIL-MSGID: 1782538637000993678 From: Andy Yan This reverts commit b63a553e8f5aa6574eeb535a551817a93c426d8c. regcache_sync will try to reload the configuration in regcache to hardware, but the registers of 4 Cluster windows and Esmart1/2/3 on the upcoming rk3588 can not be set successfully before internal PD power on. Also it's better to keep the hardware register as it is before we really enable it. So let's revert this version, and keep the first version: commit afa965a45e01 ("drm/rockchip: vop2: fix suspend/resume") Signed-off-by: Andy Yan --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 6862fb146ace..4d7d5032d96b 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -217,6 +217,8 @@ struct vop2 { struct vop2_win win[]; }; +static const struct regmap_config vop2_regmap_config; + static struct vop2_video_port *to_vop2_video_port(struct drm_crtc *crtc) { return container_of(crtc, struct vop2_video_port, crtc); @@ -878,7 +880,11 @@ static void vop2_enable(struct vop2 *vop2) return; } - regcache_sync(vop2->map); + ret = regmap_reinit_cache(vop2->map, &vop2_regmap_config); + if (ret) { + drm_err(vop2->drm, "failed to reinit cache: %d\n", ret); + return; + } if (vop2->data->soc_id == 3566) vop2_writel(vop2, RK3568_OTP_WIN_EN, 1); @@ -908,8 +914,6 @@ static void vop2_disable(struct vop2 *vop2) pm_runtime_put_sync(vop2->dev); - regcache_mark_dirty(vop2->map); - clk_disable_unprepare(vop2->aclk); clk_disable_unprepare(vop2->hclk); } From patchwork Tue Nov 14 11:27:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Yan X-Patchwork-Id: 164844 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b909:0:b0:403:3b70:6f57 with SMTP id t9csp1792728vqg; Tue, 14 Nov 2023 03:29:21 -0800 (PST) X-Google-Smtp-Source: AGHT+IFqqBaj4raMAqUkVWb+Q5GkkU8E3OeTxv6MgW/Ra1uTPUo0zLE1MPOt1OjpVtb17bmk7Y0N X-Received: by 2002:a05:6a00:8d82:b0:6c3:468c:6caa with SMTP id im2-20020a056a008d8200b006c3468c6caamr3507499pfb.6.1699961360770; Tue, 14 Nov 2023 03:29:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699961360; cv=none; d=google.com; s=arc-20160816; b=mzuPLjhwc2O8CNoafzz52AY1JcHbEpfOQO+B69nJbEHiHtpVeXYJ53E9SJNdC+hD82 SmABKER9IMytYS8h9kuqN5vp8sbSJnT7Qvc+Z3az5nxGzKjJXCRcT4S/yecDn157W7Oh KDhOppBH9qO49cYxogNvzRg8kfnSem23f2vK618TN0g8D0ybii2rypSbE2N9Quuj+Sab kZYjW0OGoYxyJqSmmTa+tldo1cR24HvL628BjsqE+33kBFumHYN+tjq46DPt3OAENmDt sx6uoEZT3Hk+rXPb6JcAY8biq9BU8g6QAboCeWnihXVyXaywBZte9lVV5wHxTfJKVFm5 S2hw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=pLzXI2slUOYfzkpdlZfDQQ/XzOt7ReXHj5ulSz8OfE0=; fh=cjsv5ohN1TaMP82Yqeh0WKQ1fJXsn/LNnakMe8VYEy4=; b=HY2GTL8VE8sAdzAbyansNHMczLsQLccE2QN2dF7mzztMkgJsJtIAcRjWpo9JdQmiRM 6xnjw/VjpmvKqol5i9hcqZg1h60zO1R7YnpWbu9vlrIrMs5OcOL2v01alRbGlASYUci3 EvCZPecnMpWV8X/88CdDh6qkQETcgAQ5BoGg8DA3SsNaOp9cFf5ZvH7xUgdbwQ0BjXLa pO9a8CV3fEBnI3qtuF3WN7n5bqMkjwPc0J6eRPezVxUzlNuCoAkWEACJNizfen+LtBuF /AbbL8CRrD2ezLf1FrNyy17l+30ooUcPdQEmKLxtoUuy/U9ZPwu1X3wSb+pyBk3XWxSb XY2A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@163.com header.s=s110527 header.b=P5G590wF; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=163.com Received: from agentk.vger.email (agentk.vger.email. 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(unknown [58.22.7.114]) by zwqz-smtp-mta-g4-1 (Coremail) with SMTP id _____wDn7_6iWVNlDXBpDA--.55740S2; Tue, 14 Nov 2023 19:27:34 +0800 (CST) From: Andy Yan To: heiko@sntech.de Cc: hjc@rock-chips.com, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, devicetree@vger.kernel.org, sebastian.reichel@collabora.com, kever.yang@rock-chips.com, chris.obbard@collabora.com, s.hauer@pengutronix.de, Andy Yan Subject: [PATCH 03/11] drm/rockchip: vop2: set half_block_en bit in all mode Date: Tue, 14 Nov 2023 19:27:29 +0800 Message-Id: <20231114112729.1770998-1-andyshrk@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231114112534.1770731-1-andyshrk@163.com> References: <20231114112534.1770731-1-andyshrk@163.com> MIME-Version: 1.0 X-CM-TRANSID: _____wDn7_6iWVNlDXBpDA--.55740S2 X-Coremail-Antispam: 1Uf129KBjvJXoWxXF47tw47Cr4xJFW5ZrW5Wrg_yoW5ZrWrpr 47ArWDKr4Ut3WjgFZ7JrZ8ZF4akws7Ka17XrZxKwnaqrWak3yDW3WkKF9rArZ8tryfuFW8 ZFn3CrW7urWIyF7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07jSwZ7UUUUU= X-Originating-IP: [58.22.7.114] X-CM-SenderInfo: 5dqg52xkunqiywtou0bp/xtbBnAsoXlghlUye3AAAsD X-Spam-Status: No, score=0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,RCVD_IN_SORBS_WEB, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Tue, 14 Nov 2023 03:29:17 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782538683727802191 X-GMAIL-MSGID: 1782538683727802191 From: Andy Yan At first we thought the half_block_en bit in AFBCD_CTRL register only work in afbc mode. But the fact is that it control the line buffer in all mode(afbc/tile/line), so we need configure it in all case. Signed-off-by: Andy Yan --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 25 ++++++++++++++------ 1 file changed, 18 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 4d7d5032d96b..0f7b68c5fdf2 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -516,6 +516,18 @@ static bool rockchip_vop2_mod_supported(struct drm_plane *plane, u32 format, return vop2_convert_afbc_format(format) >= 0; } +/* + * 0: Full mode, 16 lines for one tail + * 1: half block mode, 8 lines one tail + */ +static bool vop2_half_block_enable(struct drm_plane_state *pstate) +{ + if (pstate->rotation & (DRM_MODE_ROTATE_270 | DRM_MODE_ROTATE_90)) + return false; + else + return true; +} + static u32 vop2_afbc_transform_offset(struct drm_plane_state *pstate, bool afbc_half_block_en) { @@ -1139,6 +1151,7 @@ static void vop2_plane_atomic_update(struct drm_plane *plane, bool rotate_90 = pstate->rotation & DRM_MODE_ROTATE_90; struct rockchip_gem_object *rk_obj; unsigned long offset; + bool half_block_en; bool afbc_en; dma_addr_t yrgb_mst; dma_addr_t uv_mst; @@ -1231,6 +1244,7 @@ static void vop2_plane_atomic_update(struct drm_plane *plane, dsp_info = (dsp_h - 1) << 16 | ((dsp_w - 1) & 0xffff); format = vop2_convert_format(fb->format->format); + half_block_en = vop2_half_block_enable(pstate); drm_dbg(vop2->drm, "vp%d update %s[%dx%d->%dx%d@%dx%d] fmt[%p4cc_%s] addr[%pad]\n", vp->id, win->data->name, actual_w, actual_h, dsp_w, dsp_h, @@ -1238,6 +1252,9 @@ static void vop2_plane_atomic_update(struct drm_plane *plane, &fb->format->format, afbc_en ? "AFBC" : "", &yrgb_mst); + if (vop2_cluster_window(win)) + vop2_win_write(win, VOP2_WIN_AFBC_HALF_BLOCK_EN, half_block_en); + if (afbc_en) { u32 stride; @@ -1278,13 +1295,7 @@ static void vop2_plane_atomic_update(struct drm_plane *plane, vop2_win_write(win, VOP2_WIN_AFBC_UV_SWAP, uv_swap); vop2_win_write(win, VOP2_WIN_AFBC_AUTO_GATING_EN, 0); vop2_win_write(win, VOP2_WIN_AFBC_BLOCK_SPLIT_EN, 0); - if (pstate->rotation & (DRM_MODE_ROTATE_270 | DRM_MODE_ROTATE_90)) { - vop2_win_write(win, VOP2_WIN_AFBC_HALF_BLOCK_EN, 0); - transform_offset = vop2_afbc_transform_offset(pstate, false); - } else { - vop2_win_write(win, VOP2_WIN_AFBC_HALF_BLOCK_EN, 1); - transform_offset = vop2_afbc_transform_offset(pstate, true); - } + transform_offset = vop2_afbc_transform_offset(pstate, half_block_en); vop2_win_write(win, VOP2_WIN_AFBC_HDR_PTR, yrgb_mst); vop2_win_write(win, VOP2_WIN_AFBC_PIC_SIZE, act_info); vop2_win_write(win, VOP2_WIN_AFBC_TRANSFORM_OFFSET, transform_offset); From patchwork Tue Nov 14 11:27:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Yan X-Patchwork-Id: 164842 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b909:0:b0:403:3b70:6f57 with SMTP id t9csp1792606vqg; Tue, 14 Nov 2023 03:29:02 -0800 (PST) X-Google-Smtp-Source: AGHT+IF8aAt9vXTEu8FtIDglyonJQ9EHOXEccmg2Tzf9JvopCMG7YPQIymgE3a9JuVGyqOJy23yM X-Received: by 2002:a05:6830:2b10:b0:6d6:47c7:1abb with SMTP id l16-20020a0568302b1000b006d647c71abbmr2025775otv.22.1699961341962; Tue, 14 Nov 2023 03:29:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699961341; cv=none; d=google.com; s=arc-20160816; b=kvWHngRwdIpcl7fDPqyGaWRwKAufUdm5fMWr64LkXUGmusLDR+8EOBHYFl9xTglvo6 iWrFgLu/HOXCDhlQxbIhKojE7eKqJu29yjbTz3sftN+Jop4QDpeuMw6APen4rtyCLk5m rn5osYuFzngYm8nj/0eVFJu8CHI3O9r1WciHgvAHTcokKlWlDAEYrKoNESivODpNEZ4V t5OzmGP/jhqUD4G0TgIGu8yXDW5VgcKdQN8bEXBn27VKyCboF9RxY9fUqsOUKosZvgk/ 2rzo2G6lUwEua4HsDtt6t+8icchCyRgdBDjfNkEsQGVpxr9mZJp7yVIfP5Nm1wtzplbA 2Asw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=4fsvHLLIllNYap7ogZZzNxpS2uJ/Rut3Yt8ehtoDXa0=; fh=cjsv5ohN1TaMP82Yqeh0WKQ1fJXsn/LNnakMe8VYEy4=; b=SkpoKetDIidvGKgWccdzV8owQx9qbcy91x5xGCGcSdJWwEFEcW9hdDe+udZxxN46wd ei/A3HHb2us/Q0D+rtOtLHHVV4kMDN329OMwRt4SdCKJ2sFfQ8tYhVWnNOapKYuFCc/G NX8kJtIKhB/hR8xq1IJ2vIdGN4Sc6ouNi3weeKXTSUxpjRVIFmYAJRPiF8LqnemQv6xJ pyCUB/hR2uXAT+s3e2UlPR4zFuPJBaqb/0Yfzex13izlFtGeGUvkOQWVXHPSkhahYM0f 7PZ/XRcGXRhL2OUzep8fh2kd2xdHW/eFKbjxi6ooyWVBy9dvnVpgH5IY+PB7XS7tt54Y d9LQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@163.com header.s=s110527 header.b=hsFgS82T; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=163.com Received: from snail.vger.email (snail.vger.email. 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(unknown [58.22.7.114]) by zwqz-smtp-mta-g4-3 (Coremail) with SMTP id _____wB3H6uvWVNl3TYPBQ--.53935S2; Tue, 14 Nov 2023 19:27:47 +0800 (CST) From: Andy Yan To: heiko@sntech.de Cc: hjc@rock-chips.com, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, devicetree@vger.kernel.org, sebastian.reichel@collabora.com, kever.yang@rock-chips.com, chris.obbard@collabora.com, s.hauer@pengutronix.de, Andy Yan Subject: [PATCH 04/11] drm/rockchip: vop2: clear afbc en and transform bit for cluster window at linear mode Date: Tue, 14 Nov 2023 19:27:42 +0800 Message-Id: <20231114112742.1771060-1-andyshrk@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231114112534.1770731-1-andyshrk@163.com> References: <20231114112534.1770731-1-andyshrk@163.com> MIME-Version: 1.0 X-CM-TRANSID: _____wB3H6uvWVNl3TYPBQ--.53935S2 X-Coremail-Antispam: 1Uf129KBjvdXoWrKr47Aw18Jr1fZryrur1DGFg_yoWkGrX_Wa 47uwnxGF1v9wn8Cw1UA343CrZFyan29F4rGa18t3Z8XF1kZw40y3s7Xw17Wr45uF4rCr4D GayUWF13uFnxGjkaLaAFLSUrUUUUUb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUvcSsGvfC2KfnxnUUI43ZEXa7IU0AMaUUUUUU== X-Originating-IP: [58.22.7.114] X-CM-SenderInfo: 5dqg52xkunqiywtou0bp/xtbBnBcoXlghlUyfxQAAsH X-Spam-Status: No, score=-0.6 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_BL,RCVD_IN_MSPIKE_L4, RCVD_IN_SORBS_WEB,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 14 Nov 2023 03:29:01 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782538663653109223 X-GMAIL-MSGID: 1782538663653109223 From: Andy Yan The enable bit and transform offset of cluster windows should be cleared when it work at linear mode, or we may have a iommu fault issue. Signed-off-by: Andy Yan --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 0f7b68c5fdf2..02b76a85f22f 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -1307,6 +1307,11 @@ static void vop2_plane_atomic_update(struct drm_plane *plane, vop2_win_write(win, VOP2_WIN_AFBC_ROTATE_270, rotate_270); vop2_win_write(win, VOP2_WIN_AFBC_ROTATE_90, rotate_90); } else { + if (vop2_cluster_window(win)) { + vop2_win_write(win, VOP2_WIN_AFBC_ENABLE, 0); + vop2_win_write(win, VOP2_WIN_AFBC_TRANSFORM_OFFSET, 0); + } + vop2_win_write(win, VOP2_WIN_YRGB_VIR, DIV_ROUND_UP(fb->pitches[0], 4)); } From patchwork Tue Nov 14 11:27:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Yan X-Patchwork-Id: 164841 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b909:0:b0:403:3b70:6f57 with SMTP id t9csp1792581vqg; Tue, 14 Nov 2023 03:29:00 -0800 (PST) X-Google-Smtp-Source: AGHT+IGHxt8w/Kg95VhgGHoDqXkkN6LBENdOTbXEHvoVZxvXOsC5gMJ+tSDp5fCeRjyN993jC46A X-Received: by 2002:a05:6a00:1b57:b0:692:b429:390 with SMTP id o23-20020a056a001b5700b00692b4290390mr9633559pfv.29.1699961340072; Tue, 14 Nov 2023 03:29:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699961340; cv=none; d=google.com; s=arc-20160816; b=Ga18dhHB3v8T91c/rdqwK9Z1uGvwFMwvTeJEImP7W58uO6PAtZHSOsTHX6N0Tq3JhT f/lh2EJXjmIKh1oDTl/ccBQidTzT44+fQTYX1IrQ4vT9m+Fvipzbvn7R68aMCZEmdSUO h91gZ4c0PNTEXEmkFBOCjnzflGYWyA8SDW0UaJSsDgIvjPCdqTkHyVai/j0ExePwZ0lY +/nUm3U5tngyi1S6emiAtOf4SfmvVvriAHnL9FbEei/XVw5Ox2YrMiMC0Z+BXuxCD5XC QRjjib7IBhoV/1x+ZhuRjysRWxdVhcQ5uwzTyT5qTfSQ77Mntkq23PBZjDxxEb5ZBZhc ZYyA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=eL7XaKoTvsgV8FMEksNVSVxinzDqlWY3ZoES2KnTqts=; fh=cjsv5ohN1TaMP82Yqeh0WKQ1fJXsn/LNnakMe8VYEy4=; b=caoHAbjulh2YwAQ11jb03JBxJMgjToSfLayBBjTFGP0ZaawB93lHtvigIVDUbdkCnX udjPr9WaebJLK29P0uqJ870/44ofB0oGg98IfwwEu9WejzsIAKXxgxOnzjoW6dUehmn1 fXI40fCSs/Ay7cNmdU10SOO0Icisw/EuD5pkzAxX3cYcNdTbLBd7oLr47Rv5rf4Ijt7O iW10WtvAppALNpOuPLbfEgSsJr2XC6tzUt8Nwbi9Z8YziQ7HRn0dpo13I9yPP0wEcy5J LRaj47VZfKfNm0IxOdaMO4kGoEM1Ho2O/Fmrbd1jJqRgvedB36S5ABF2/iiJeZnOWNG1 UDBA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@163.com header.s=s110527 header.b=goVn9VFn; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=163.com Received: from snail.vger.email (snail.vger.email. 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(unknown [58.22.7.114]) by zwqz-smtp-mta-g2-3 (Coremail) with SMTP id _____wDXv8e8WVNlyRphDA--.55517S2; Tue, 14 Nov 2023 19:28:00 +0800 (CST) From: Andy Yan To: heiko@sntech.de Cc: hjc@rock-chips.com, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, devicetree@vger.kernel.org, sebastian.reichel@collabora.com, kever.yang@rock-chips.com, chris.obbard@collabora.com, s.hauer@pengutronix.de, Andy Yan Subject: [PATCH 05/11] drm/rockchip: vop2: Set YUV/RGB overlay mode Date: Tue, 14 Nov 2023 19:27:55 +0800 Message-Id: <20231114112755.1771120-1-andyshrk@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231114112534.1770731-1-andyshrk@163.com> References: <20231114112534.1770731-1-andyshrk@163.com> MIME-Version: 1.0 X-CM-TRANSID: _____wDXv8e8WVNlyRphDA--.55517S2 X-Coremail-Antispam: 1Uf129KBjvJXoWxZF4xCFyUKw1DZF4xCFWfZrb_yoW5tF4Dpw n7ZryYgrWDKF4qgw1kJF98ZF4Skws2yay7Grn7Ca43uas0gr1DW3Z8uas8AFsrXry7uryY yrZFkrWYyF4I9r7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07jo1vsUUUUU= X-Originating-IP: [58.22.7.114] X-CM-SenderInfo: 5dqg52xkunqiywtou0bp/1tbiTB4oXmI0cP18BwACsG X-Spam-Status: No, score=-0.6 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_SORBS_WEB,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 14 Nov 2023 03:28:58 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782538662138883030 X-GMAIL-MSGID: 1782538662138883030 From: Andy Yan Set overlay mode register according to the output mode is yuv or rgb. Signed-off-by: Andy Yan --- drivers/gpu/drm/rockchip/rockchip_drm_drv.h | 1 + drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 19 ++++++++++++++++--- 2 files changed, 17 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h index 3d8ab2defa1b..7a58c5c9d4ec 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_drv.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_drv.h @@ -51,6 +51,7 @@ struct rockchip_crtc_state { u32 bus_format; u32 bus_flags; int color_space; + bool yuv_overlay; }; #define to_rockchip_crtc_state(s) \ container_of(s, struct rockchip_crtc_state, base) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 02b76a85f22f..33743e21cafe 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -1607,6 +1607,8 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, vop2->enable_count++; + vcstate->yuv_overlay = is_yuv_output(vcstate->bus_format); + vop2_crtc_enable_irq(vp, VP_INT_POST_BUF_EMPTY); polflags = 0; @@ -1634,7 +1636,7 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, if (vop2_output_uv_swap(vcstate->bus_format, vcstate->output_mode)) dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_RB_SWAP; - if (is_yuv_output(vcstate->bus_format)) + if (vcstate->yuv_overlay) dsp_ctrl |= RK3568_VP_DSP_CTRL__POST_DSP_OUT_R2Y; vop2_dither_setup(crtc, &dsp_ctrl); @@ -1943,10 +1945,12 @@ static void vop2_setup_layer_mixer(struct vop2_video_port *vp) u16 hdisplay; u32 bg_dly; u32 pre_scan_dly; + u32 ovl_ctrl; int i; struct vop2_video_port *vp0 = &vop2->vps[0]; struct vop2_video_port *vp1 = &vop2->vps[1]; struct vop2_video_port *vp2 = &vop2->vps[2]; + struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(vp->crtc.state); adjusted_mode = &vp->crtc.state->adjusted_mode; hsync_len = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; @@ -1959,7 +1963,14 @@ static void vop2_setup_layer_mixer(struct vop2_video_port *vp) pre_scan_dly = ((bg_dly + (hdisplay >> 1) - 1) << 16) | hsync_len; vop2_vp_write(vp, RK3568_VP_PRE_SCAN_HTIMING, pre_scan_dly); - vop2_writel(vop2, RK3568_OVL_CTRL, 0); + ovl_ctrl = vop2_readl(vop2, RK3568_OVL_CTRL); + if (vcstate->yuv_overlay) + ovl_ctrl |= BIT(vp->id); + else + ovl_ctrl &= ~BIT(vp->id); + + vop2_writel(vop2, RK3568_OVL_CTRL, ovl_ctrl); + port_sel = vop2_readl(vop2, RK3568_OVL_PORT_SEL); port_sel &= RK3568_OVL_PORT_SEL__SEL_PORT; @@ -2031,9 +2042,11 @@ static void vop2_setup_layer_mixer(struct vop2_video_port *vp) layer_sel |= RK3568_OVL_LAYER_SEL__LAYER(nlayer + ofs, 5); } + ovl_ctrl |= RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD; + vop2_writel(vop2, RK3568_OVL_LAYER_SEL, layer_sel); vop2_writel(vop2, RK3568_OVL_PORT_SEL, port_sel); - vop2_writel(vop2, RK3568_OVL_CTRL, RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD); + vop2_writel(vop2, RK3568_OVL_CTRL, ovl_ctrl); } static void vop2_setup_dly_for_windows(struct vop2 *vop2) From patchwork Tue Nov 14 11:28:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Yan X-Patchwork-Id: 164845 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b909:0:b0:403:3b70:6f57 with SMTP id t9csp1792753vqg; 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(unknown [58.22.7.114]) by zwqz-smtp-mta-g3-2 (Coremail) with SMTP id _____wD3n4LIWVNlHihjDA--.55772S2; Tue, 14 Nov 2023 19:28:11 +0800 (CST) From: Andy Yan To: heiko@sntech.de Cc: hjc@rock-chips.com, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, devicetree@vger.kernel.org, sebastian.reichel@collabora.com, kever.yang@rock-chips.com, chris.obbard@collabora.com, s.hauer@pengutronix.de, Andy Yan Subject: [PATCH 06/11] drm/rockchip: vop2: rename grf to sys_grf Date: Tue, 14 Nov 2023 19:28:07 +0800 Message-Id: <20231114112807.1771180-1-andyshrk@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231114112534.1770731-1-andyshrk@163.com> References: <20231114112534.1770731-1-andyshrk@163.com> MIME-Version: 1.0 X-CM-TRANSID: _____wD3n4LIWVNlHihjDA--.55772S2 X-Coremail-Antispam: 1Uf129KBjvJXoW7AFW7tFy3Ww1DKw4DurW5trb_yoW8CF15pa sxAFWjgr47GrZFq3WvkFs8uFW3Kwn7CayIk3WIk3Za934xtryDKFs8W3W5JrW3trnruF4a y3yqyry3CFW7Jr7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07jSOJnUUUUU= X-Originating-IP: [58.22.7.114] X-CM-SenderInfo: 5dqg52xkunqiywtou0bp/1tbiTBAoXmI0cP19aAAAsk X-Spam-Status: No, score=-0.6 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_BL,RCVD_IN_MSPIKE_L4, RCVD_IN_SORBS_WEB,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 14 Nov 2023 03:29:24 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782538688150236580 X-GMAIL-MSGID: 1782538688150236580 From: Andy Yan The vop2 need to reference more grf(system grf, vop grf, vo0/1 grf,etc) in the upcoming rk3588. So we rename the current system grf to sys_grf. Signed-off-by: Andy Yan --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 33743e21cafe..0d7dc543bef3 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -190,7 +190,7 @@ struct vop2 { void __iomem *regs; struct regmap *map; - struct regmap *grf; + struct regmap *sys_grf; /* physical map length of vop2 register */ u32 len; @@ -1498,9 +1498,9 @@ static void rk3568_set_intf_mux(struct vop2_video_port *vp, int id, dip &= ~RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL; dip |= FIELD_PREP(RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL, polflags); if (polflags & POLFLAG_DCLK_INV) - regmap_write(vop2->grf, RK3568_GRF_VO_CON1, BIT(3 + 16) | BIT(3)); + regmap_write(vop2->sys_grf, RK3568_GRF_VO_CON1, BIT(3 + 16) | BIT(3)); else - regmap_write(vop2->grf, RK3568_GRF_VO_CON1, BIT(3 + 16)); + regmap_write(vop2->sys_grf, RK3568_GRF_VO_CON1, BIT(3 + 16)); break; case ROCKCHIP_VOP2_EP_HDMI0: die &= ~RK3568_SYS_DSP_INFACE_EN_HDMI_MUX; @@ -2759,7 +2759,7 @@ static int vop2_bind(struct device *dev, struct device *master, void *data) return PTR_ERR(vop2->lut_regs); } - vop2->grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf"); + vop2->sys_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf"); vop2->hclk = devm_clk_get(vop2->dev, "hclk"); if (IS_ERR(vop2->hclk)) { From patchwork Tue Nov 14 11:28:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Yan X-Patchwork-Id: 164854 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b909:0:b0:403:3b70:6f57 with SMTP id t9csp1794027vqg; Tue, 14 Nov 2023 03:31:43 -0800 (PST) X-Google-Smtp-Source: AGHT+IFFC0J4bwSrIfpWLLRAyDVgf4OW4E0OOPuVEJVi+Gi28f3LZbSL+XmVX/kGRdaMCR8aX6rR X-Received: by 2002:a17:902:c40f:b0:1cc:7100:2d62 with SMTP id k15-20020a170902c40f00b001cc71002d62mr2588720plk.39.1699961503579; Tue, 14 Nov 2023 03:31:43 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699961503; cv=none; d=google.com; s=arc-20160816; b=SCGOgmOAJ9wvEGUznZ5S9i/OtPFUZot4O7ctHCnJdEbjA+3dQyEnnCBcCAx1K+AM9E P+ciYlsIces5mlB4bsC+uA5CdHhLk/ilGRNKrGxYcTOl6dSEXNMVd3KAja3G8Q7vH/MB 0atSe0PejcCDVuGdC09KbnSCu9MV/aY1V5tWhdq5isRKJFCcFaWQD68BKjoSPevgG6ly yi+1pY6QjXhG7j5a5WjaYFhHD0pLHuD+3tsC3pqBGcJYx0Ue6QibXgChqTNXmXvFrei2 xHuc/GMJWLMhFx4sGeikqGdqsTBvgLvgkl15FLQ4FAPhFmJpHqsdQqj8gC/M8zi3Ol7h A3zQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=+qJQzSNuwveCVk6IeGOImzTHjvxdDU1zu6KXYVYxyLc=; fh=cjsv5ohN1TaMP82Yqeh0WKQ1fJXsn/LNnakMe8VYEy4=; b=t/g2ElyBE7sEaMDhUF5+uaCLvuE5tEt+p97tNvKLkhmqhYY40pTO+9hTJMti9zzOzl 02zNto7817dSt/iMgSMzDftIDZdlKETjqqwxvz609bqYbgsZfYU7dmSFu5T4i74sTh6u YHbSWG7FyhLzTAJ1T16h48JFaqSntsj/wM+wuYzjg22RJmW2LJ4bMtnXFTvLJVq0Pvmm hAB+hsVlT6AAwBBzbs6iJcrMrAP0i2JoMDu3wv4meXj+pvfm15F38vprqDpVxyhPW8Wq gYy7RjAFHaE6lFA3L3G0YxziMLSWEavHR4qS4kHws0rBxtXO81Vyl60gppLZkvI0z9tY 5KDw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@163.com header.s=s110527 header.b=cmKt0NUU; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=163.com Received: from snail.vger.email (snail.vger.email. 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(unknown [58.22.7.114]) by zwqz-smtp-mta-g0-2 (Coremail) with SMTP id _____wD3X_PVWVNldxVuBQ--.54859S2; Tue, 14 Nov 2023 19:28:24 +0800 (CST) From: Andy Yan To: heiko@sntech.de Cc: hjc@rock-chips.com, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, devicetree@vger.kernel.org, sebastian.reichel@collabora.com, kever.yang@rock-chips.com, chris.obbard@collabora.com, s.hauer@pengutronix.de, Andy Yan Subject: [PATCH 07/11] dt-bindings: soc: rockchip: add rk3588 vop/vo syscon Date: Tue, 14 Nov 2023 19:28:20 +0800 Message-Id: <20231114112820.1771240-1-andyshrk@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231114112534.1770731-1-andyshrk@163.com> References: <20231114112534.1770731-1-andyshrk@163.com> MIME-Version: 1.0 X-CM-TRANSID: _____wD3X_PVWVNldxVuBQ--.54859S2 X-Coremail-Antispam: 1Uf129KBjvdXoW7GrWkAF4UAr4rZrWUtF1xAFb_yoWfJrgE9a 4xZ3WUuFW8GryFgw1qyayIk3Z8A3Z2kF1kCa1jyF4kCaykZrZ8KF95Jw1avr15uF4fuw1f uF1kWrWUCFnxGjkaLaAFLSUrUUUUUb8apTn2vfkv8UJUUUU8Yxn0WfASr-VFAUDa7-sFnT 9fnUUvcSsGvfC2KfnxnUUI43ZEXa7IU8iSdPUUUUU== X-Originating-IP: [58.22.7.114] X-CM-SenderInfo: 5dqg52xkunqiywtou0bp/xtbBnAEoXlghlUyjWgAAsy X-Spam-Status: No, score=-0.6 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,RCVD_IN_SORBS_WEB,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 14 Nov 2023 03:30:23 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782538833288952307 X-GMAIL-MSGID: 1782538833288952307 From: Andy Yan Add VOP and VO GRF syscon compatibles for RK3588 Signed-off-by: Andy Yan Acked-by: Rob Herring --- Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml index e4fa6a07b4fa..26db4f48ff62 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml @@ -28,6 +28,8 @@ properties: - rockchip,rk3588-sys-grf - rockchip,rk3588-pcie3-phy-grf - rockchip,rk3588-pcie3-pipe-grf + - rockchip,rk3588-vo-grf + - rockchip,rk3588-vop-grf - rockchip,rv1108-usbgrf - const: syscon - items: From patchwork Tue Nov 14 11:28:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Yan X-Patchwork-Id: 164863 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b909:0:b0:403:3b70:6f57 with SMTP id t9csp1794178vqg; Tue, 14 Nov 2023 03:31:59 -0800 (PST) X-Google-Smtp-Source: AGHT+IERBFHSbirxxAxk7+SYC1s6UlHWfjUn5fyuOo/hxsWk+YFvu645trRKn8tMNrN3lmlBkxFf X-Received: by 2002:a17:90a:1918:b0:280:3f33:64d8 with SMTP id 24-20020a17090a191800b002803f3364d8mr10773884pjg.21.1699961519431; Tue, 14 Nov 2023 03:31:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699961519; cv=none; d=google.com; s=arc-20160816; b=DKaZE7BRvVK+rsczkHHjL5BXptywu6uzXHIyiRJKrV9x43Vw5BGU2UIW9WyScsd4RQ q8043CObYdXZAOVvYetiiklsIVi0y8B9+F+4GysV8xhgMYEwdPRsO695mspRFU1BCnya YLZRYToEGR7QWk2tOCb0jRmzkCJeGtx4hO5NpeJdcqA6PWaUMiOEeuPbPGbikHFZSDzI KHW/Ne0/u9KA4YUp0bxIDywi8r6ylN8mabwUMUkY5rJxbTQs0Aq0ZdpVgjls67QttBoK 3PzWkwlG5wRRBsSn7qU9/gWV090rfq41mS7Cef928vLMfk3E+8PhqS1e9P9TQSTZ4HvG bz2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=TcUYWrUE6dSsZ+mpwiaV36VQAkvGr8J4nvY6L0HP74E=; fh=cjsv5ohN1TaMP82Yqeh0WKQ1fJXsn/LNnakMe8VYEy4=; b=UzzAxOahqVU2hHKO0DaOOs5GcWn0vahETtYDJCyCzlJx99R/d+AR94Xjd8wnPe/Fs7 NPkdMbFNhqCI78VlD/DJ45PA4FBU6QUhZkgmQ4l4VjmkWNhZSOGzhi7Py+MVPoy6PWv7 cNvEceT9Wvs9T75UPToITYyi9C7B9GKJOgR9bDeUSjfQkp3EfDk4OWoSxyAo26vV+Rcf NprjWknAkfMhd1riovLRBv9c44kPzXTEk2wHNyfxnl/FqYzaC0WIqSuPKSYtxHOJlo0B 0n0pPyidwdqNYFYnvrLZ+Ko6VpyaXleJlcZ8FW078PIoSGW0+ufw+0cu6vvuuHXuCS+m sPsQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@163.com header.s=s110527 header.b=nFJQc2HN; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=163.com Received: from snail.vger.email (snail.vger.email. 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(unknown [58.22.7.114]) by zwqz-smtp-mta-g4-2 (Coremail) with SMTP id _____wD3_ujqWVNlGxp1DA--.55932S2; Tue, 14 Nov 2023 19:28:47 +0800 (CST) From: Andy Yan To: heiko@sntech.de Cc: hjc@rock-chips.com, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, devicetree@vger.kernel.org, sebastian.reichel@collabora.com, kever.yang@rock-chips.com, chris.obbard@collabora.com, s.hauer@pengutronix.de, Andy Yan Subject: [PATCH 08/11] dt-bindings: display: vop2: Add rk3588 support Date: Tue, 14 Nov 2023 19:28:41 +0800 Message-Id: <20231114112841.1771312-1-andyshrk@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231114112534.1770731-1-andyshrk@163.com> References: <20231114112534.1770731-1-andyshrk@163.com> MIME-Version: 1.0 X-CM-TRANSID: _____wD3_ujqWVNlGxp1DA--.55932S2 X-Coremail-Antispam: 1Uf129KBjvJXoW7WFyUGF4fXF13Zr48Zr1fJFb_yoW8uF43pa s5C34UJryfGr13Xw1ktwn5Cw43KFs7uw4UtrsrXrsrta4aqwsYqF4a9wn8WayUCFn7Za42 9FWDua4fGF17ZF7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07jweOLUUUUU= X-Originating-IP: [58.22.7.114] X-CM-SenderInfo: 5dqg52xkunqiywtou0bp/xtbBnAEoXlghlUyjWgACsw X-Spam-Status: No, score=-0.6 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_BL,RCVD_IN_MSPIKE_L4, RCVD_IN_SORBS_WEB,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 14 Nov 2023 03:31:08 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782538850020053517 X-GMAIL-MSGID: 1782538850020053517 From: Andy Yan The vop2 on rk3588 is similar to which on rk356x but with 4 video outputs and need to reference more grf modules. Signed-off-by: Andy Yan --- .../display/rockchip/rockchip-vop2.yaml | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml index b60b90472d42..c333c651da1a 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip-vop2.yaml @@ -20,6 +20,7 @@ properties: enum: - rockchip,rk3566-vop - rockchip,rk3568-vop + - rockchip,rk3588-vop reg: items: @@ -48,6 +49,8 @@ properties: - description: Pixel clock for video port 0. - description: Pixel clock for video port 1. - description: Pixel clock for video port 2. + - description: Pixel clock for video port 4. + - description: Peripheral clock for vop on rk3588. clock-names: items: @@ -56,12 +59,29 @@ properties: - const: dclk_vp0 - const: dclk_vp1 - const: dclk_vp2 + - const: dclk_vp3 + - const: pclk_vop rockchip,grf: $ref: /schemas/types.yaml#/definitions/phandle description: Phandle to GRF regs used for misc control + rockchip,vo-grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to VO GRF regs used for misc control, required for rk3588 + + rockchip,vop-grf: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to VOP GRF regs used for misc control, required for rk3588 + + rockchip,pmu: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to PMU regs used for misc control, required for rk3588 + ports: $ref: /schemas/graph.yaml#/properties/ports @@ -81,6 +101,11 @@ properties: description: Output endpoint of VP2 + port@3: + $ref: /schemas/graph.yaml#/properties/port + description: + Output endpoint of VP3 + iommus: maxItems: 1 From patchwork Tue Nov 14 11:28:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Yan X-Patchwork-Id: 164865 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b909:0:b0:403:3b70:6f57 with SMTP id t9csp1794919vqg; Tue, 14 Nov 2023 03:33:36 -0800 (PST) X-Google-Smtp-Source: AGHT+IEtRXL/9DmI5XB6RY3Zn1WgLTo0C5KgtXO+hRw6KGQ9y1iR0eXx2y7Tv/NXw/0+ttBEF+4J X-Received: by 2002:a05:6a21:9988:b0:186:10d6:cc64 with SMTP id ve8-20020a056a21998800b0018610d6cc64mr7066329pzb.44.1699961616373; Tue, 14 Nov 2023 03:33:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699961616; cv=none; d=google.com; s=arc-20160816; b=tT/E8+SfjYdogZLrXDdP0f7oD9S0EEnvYIk1eorAWZcRaQaOmgBI5HVW0Zx/e2QUiW cQIkoQsxIxL+xvF5cWxy7wu37Yapp0lOXqMZNi7XvkxRtmBSfJ8WWXveBWe9t9FWThKC 1Qo94dzcnCSO9eAKSs4KhbI9dPOBIeA/qWj2jk0ADCH7F1Xlq4oTjL7ESvgX9favJg7g PvE2Sc5TQVY0jFQ5OejsMDz+0WzbCtieTUI7SsQujPH/0AKYRLDLQtUa39MfylB3lnga soBbu/WnI08FyFi4+irSXFSb+Kv7WK2+f8DOF3CDrzHGzBGZBGluBfYfQCxCClmtQZ4y UtDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=JJDkv24hHzhL3K17KTAhcbp3d3fqONP6I9J86CC5jUY=; fh=cjsv5ohN1TaMP82Yqeh0WKQ1fJXsn/LNnakMe8VYEy4=; b=PNSUb8EKsB71D+DgVqDRcs8pAuqju3i4OvvSHhUOdhs4LzSchnmMvbB7ddep9q8b0E a9PZDXbiBzAIS0D2kwx5C3xxjA2ycKKqe5FzqkftZkzaj+SUOUnnHQTjrVWmXMEhakFh pMLndWWeLRcGc6MLJpnQL9ydS5rX1fBRB5p25R/0j0jPrC5hnuHHRa5VgDtcUYo422y8 v48vyXxZHqhp5W5arfcX4/CZGk7KvgDscPE5gbWNrTuLyg6YktVfpruq+aBVwtgliXee 1vthgDKA7Vb+sHdEaFyBZuxW9wRK71GFwQuHlLWCNj2LmIPSEclIrYe5LsWPrthg1DM5 RvDA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@163.com header.s=s110527 header.b=Tw0zY38+; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=163.com Received: from agentk.vger.email (agentk.vger.email. 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(unknown [58.22.7.114]) by zwqz-smtp-mta-g3-2 (Coremail) with SMTP id _____wDXHyv4WVNlSjNjDA--.57954S2; Tue, 14 Nov 2023 19:29:00 +0800 (CST) From: Andy Yan To: heiko@sntech.de Cc: hjc@rock-chips.com, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, devicetree@vger.kernel.org, sebastian.reichel@collabora.com, kever.yang@rock-chips.com, chris.obbard@collabora.com, s.hauer@pengutronix.de, Andy Yan Subject: [PATCH 09/11] drm/rockchip: vop2: Add support for rk3588 Date: Tue, 14 Nov 2023 19:28:55 +0800 Message-Id: <20231114112855.1771372-1-andyshrk@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231114112534.1770731-1-andyshrk@163.com> References: <20231114112534.1770731-1-andyshrk@163.com> MIME-Version: 1.0 X-CM-TRANSID: _____wDXHyv4WVNlSjNjDA--.57954S2 X-Coremail-Antispam: 1Uf129KBjvAXoWfXFy8Wr1rtr4UCFW5GF17ZFb_yoW5CF1kXo W7C3W3Xw1rtw1fCwsrWr1Sqa43uw4xAa1xurZrZws3XanIgw4UKryIqasFvF12y3yakFW3 Ar1vqw1rXFWfA3Wxn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UbIYCTnIWIevJa73UjIFyTuYvjxU31vVDUUUU X-Originating-IP: [58.22.7.114] X-CM-SenderInfo: 5dqg52xkunqiywtou0bp/1tbiEAAoXl8YMdm7pQAAsX X-Spam-Status: No, score=0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,RCVD_IN_SORBS_WEB, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Tue, 14 Nov 2023 03:33:17 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782538951655716218 X-GMAIL-MSGID: 1782538951655716218 From: Andy Yan VOP2 on rk3588: Four video ports: VP0 Max 4096x2160 VP1 Max 4096x2160 VP2 Max 4096x2160 VP3 Max 2048x1080 4 4K Cluster windows with AFBC/line RGB and AFBC-only YUV support 4 4K Esmart windows with line RGB/YUV support Signed-off-by: Andy Yan --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 324 ++++++++++++++++++- drivers/gpu/drm/rockchip/rockchip_drm_vop2.h | 57 ++++ drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 215 ++++++++++++ include/dt-bindings/soc/rockchip,vop2.h | 4 + 4 files changed, 593 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index 0d7dc543bef3..ba61c0233937 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -191,6 +191,9 @@ struct vop2 { struct regmap *map; struct regmap *sys_grf; + struct regmap *vop_grf; + struct regmap *vo1_grf; + struct regmap *sys_pmu; /* physical map length of vop2 register */ u32 len; @@ -209,6 +212,7 @@ struct vop2 { unsigned int enable_count; struct clk *hclk; struct clk *aclk; + struct clk *pclk; /* optional internal rgb encoder */ struct rockchip_rgb *rgb; @@ -217,6 +221,13 @@ struct vop2 { struct vop2_win win[]; }; +#define vop2_output_if_is_hdmi(x) (x == ROCKCHIP_VOP2_EP_HDMI0 || x == ROCKCHIP_VOP2_EP_HDMI1) +#define vop2_output_if_is_dp(x) (x == ROCKCHIP_VOP2_EP_DP0 || x == ROCKCHIP_VOP2_EP_DP1) +#define vop2_output_if_is_edp(x) (x == ROCKCHIP_VOP2_EP_EDP0 || x == ROCKCHIP_VOP2_EP_EDP1) +#define vop2_output_if_is_mipi(x) (x == ROCKCHIP_VOP2_EP_MIPI0 || x == ROCKCHIP_VOP2_EP_MIPI1) +#define vop2_output_if_is_lvds(x) (x == ROCKCHIP_VOP2_EP_LVDS0 || x == ROCKCHIP_VOP2_EP_LVDS1) +#define vop2_output_if_is_dpi(x) (x == ROCKCHIP_VOP2_EP_RGB0) + static const struct regmap_config vop2_regmap_config; static struct vop2_video_port *to_vop2_video_port(struct drm_crtc *crtc) @@ -271,9 +282,12 @@ static bool vop2_cluster_window(const struct vop2_win *win) static void vop2_cfg_done(struct vop2_video_port *vp) { struct vop2 *vop2 = vp->vop2; + u32 val; - regmap_set_bits(vop2->map, RK3568_REG_CFG_DONE, - BIT(vp->id) | RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN); + val = BIT(vp->id) | (BIT(vp->id) << 16) | + RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN; + + regmap_set_bits(vop2->map, RK3568_REG_CFG_DONE, val); } static void vop2_win_disable(struct vop2_win *win) @@ -863,13 +877,32 @@ static int vop2_core_clks_prepare_enable(struct vop2 *vop2) goto err; } + ret = clk_prepare_enable(vop2->pclk); + if (ret < 0) { + drm_err(vop2->drm, "failed to enable pclk - %d\n", ret); + goto err1; + } + return 0; +err1: + clk_disable_unprepare(vop2->aclk); err: clk_disable_unprepare(vop2->hclk); return ret; } +static void vop2_power_domain_all_on(struct vop2 *vop2) +{ + u32 pd; + + pd = vop2_readl(vop2, RK3588_SYS_PD_CTRL); + pd &= ~(VOP2_PD_CLUSTER0 | VOP2_PD_CLUSTER1 | VOP2_PD_CLUSTER2 | + VOP2_PD_CLUSTER3 | VOP2_PD_ESMART); + + vop2_writel(vop2, RK3588_SYS_PD_CTRL, pd); +} + static void vop2_enable(struct vop2 *vop2) { int ret; @@ -901,6 +934,9 @@ static void vop2_enable(struct vop2 *vop2) if (vop2->data->soc_id == 3566) vop2_writel(vop2, RK3568_OTP_WIN_EN, 1); + if (vop2->data->soc_id == 3588) + vop2_power_domain_all_on(vop2); + vop2_writel(vop2, RK3568_REG_CFG_DONE, RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN); /* @@ -926,6 +962,7 @@ static void vop2_disable(struct vop2 *vop2) pm_runtime_put_sync(vop2->dev); + clk_disable_unprepare(vop2->pclk); clk_disable_unprepare(vop2->aclk); clk_disable_unprepare(vop2->hclk); } @@ -1293,7 +1330,11 @@ static void vop2_plane_atomic_update(struct drm_plane *plane, vop2_win_write(win, VOP2_WIN_AFBC_ENABLE, 1); vop2_win_write(win, VOP2_WIN_AFBC_FORMAT, afbc_format); vop2_win_write(win, VOP2_WIN_AFBC_UV_SWAP, uv_swap); - vop2_win_write(win, VOP2_WIN_AFBC_AUTO_GATING_EN, 0); + if (vop2->data->soc_id == 3566 || vop2->data->soc_id == 3568) + vop2_win_write(win, VOP2_WIN_AFBC_AUTO_GATING_EN, 0); + else + vop2_win_write(win, VOP2_WIN_AFBC_AUTO_GATING_EN, 1); + vop2_win_write(win, VOP2_WIN_AFBC_BLOCK_SPLIT_EN, 0); transform_offset = vop2_afbc_transform_offset(pstate, half_block_en); vop2_win_write(win, VOP2_WIN_AFBC_HDR_PTR, yrgb_mst); @@ -1481,10 +1522,10 @@ static void vop2_post_config(struct drm_crtc *crtc) vop2_vp_write(vp, RK3568_VP_DSP_BG, 0); } -static void rk3568_set_intf_mux(struct vop2_video_port *vp, int id, - u32 polflags) +static unsigned long rk3568_set_intf_mux(struct vop2_video_port *vp, int id, u32 polflags) { struct vop2 *vop2 = vp->vop2; + struct drm_crtc *crtc = &vp->crtc; u32 die, dip; die = vop2_readl(vop2, RK3568_DSP_IF_EN); @@ -1546,13 +1587,257 @@ static void rk3568_set_intf_mux(struct vop2_video_port *vp, int id, break; default: drm_err(vop2->drm, "Invalid interface id %d on vp%d\n", id, vp->id); - return; + return 0; + } + + dip |= RK3568_DSP_IF_POL__CFG_DONE_IMD; + + vop2_writel(vop2, RK3568_DSP_IF_EN, die); + vop2_writel(vop2, RK3568_DSP_IF_POL, dip); + + return crtc->state->adjusted_mode.crtc_clock * 1000LL; +} + +/* + * calc the dclk on rk3588 + * the available div of dclk is 1, 2, 4 + */ +static unsigned long vop2_calc_dclk(unsigned long child_clk, unsigned long max_dclk) +{ + if (child_clk * 4 <= max_dclk) + return child_clk * 4; + else if (child_clk * 2 <= max_dclk) + return child_clk * 2; + else if (child_clk <= max_dclk) + return child_clk; + else + return 0; +} + +/* + * 4 pixclk/cycle on rk3588 + * RGB/eDP/HDMI: if_pixclk >= dclk_core + * DP: dp_pixclk = dclk_out <= dclk_core + * DSI: mipi_pixclk <= dclk_out <= dclk_core + */ +static unsigned long vop2_calc_cru_cfg(struct vop2_video_port *vp, int id, + int *dclk_core_div, int *dclk_out_div, + int *if_pixclk_div, int *if_dclk_div) +{ + struct vop2 *vop2 = vp->vop2; + struct drm_crtc *crtc = &vp->crtc; + struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode; + struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state); + int output_mode = vcstate->output_mode; + unsigned long v_pixclk = adjusted_mode->crtc_clock * 1000LL; /* video timing pixclk */ + unsigned long dclk_core_rate = v_pixclk >> 2; + unsigned long dclk_rate = v_pixclk; + unsigned long dclk_out_rate; + unsigned long if_dclk_rate; + unsigned long if_pixclk_rate; + int K = 1; + + if (vop2_output_if_is_hdmi(id)) { + /* + * K = 2: dclk_core = if_pixclk_rate > if_dclk_rate + * K = 1: dclk_core = hdmie_edp_dclk > if_pixclk_rate + */ + if (output_mode == ROCKCHIP_OUT_MODE_YUV420) { + dclk_rate = dclk_rate >> 1; + K = 2; + } + + if_pixclk_rate = (dclk_core_rate << 1) / K; + if_dclk_rate = dclk_core_rate / K; + + *if_pixclk_div = dclk_rate / if_pixclk_rate; + *if_dclk_div = dclk_rate / if_dclk_rate; + *dclk_core_div = dclk_rate / dclk_core_rate; + } else if (vop2_output_if_is_edp(id)) { + /* edp_pixclk = edp_dclk > dclk_core */ + if_pixclk_rate = v_pixclk / K; + if_dclk_rate = v_pixclk / K; + dclk_rate = if_pixclk_rate * K; + *dclk_core_div = dclk_rate / dclk_core_rate; + *if_pixclk_div = dclk_rate / if_pixclk_rate; + *if_dclk_div = *if_pixclk_div; + } else if (vop2_output_if_is_dp(id)) { + if (output_mode == ROCKCHIP_OUT_MODE_YUV420) + dclk_out_rate = v_pixclk >> 3; + else + dclk_out_rate = v_pixclk >> 2; + + dclk_rate = vop2_calc_dclk(dclk_out_rate, 600000); + if (!dclk_rate) { + drm_err(vop2->drm, "DP dclk_out_rate out of range, dclk_out_rate: %ld KHZ\n", + dclk_out_rate); + return -EINVAL; + } + *dclk_out_div = dclk_rate / dclk_out_rate; + *dclk_core_div = dclk_rate / dclk_core_rate; + } else if (vop2_output_if_is_mipi(id)) { + if_pixclk_rate = dclk_core_rate / K; + /* dclk_core = dclk_out * K = if_pixclk * K = v_pixclk / 4 */ + dclk_out_rate = if_pixclk_rate; + /* dclk_rate = N * dclk_core_rate N = (1,2,4 ), we get a little factor here */ + dclk_rate = vop2_calc_dclk(dclk_out_rate, 600000); + if (!dclk_rate) { + drm_err(vop2->drm, "MIPI dclk out of range, dclk_out_rate: %ld KHZ\n", + dclk_out_rate); + return -EINVAL; + } + *dclk_out_div = dclk_rate / dclk_out_rate; + *dclk_core_div = dclk_rate / dclk_core_rate; + *if_pixclk_div = 1; /*mipi pixclk == dclk_out*/ + } else if (vop2_output_if_is_dpi(id)) { + dclk_rate = v_pixclk; + *dclk_core_div = dclk_rate / dclk_core_rate; + } + + *if_pixclk_div = ilog2(*if_pixclk_div); + *if_dclk_div = ilog2(*if_dclk_div); + *dclk_core_div = ilog2(*dclk_core_div); + *dclk_out_div = ilog2(*dclk_out_div); + + drm_dbg(vop2->drm, "dclk:%ld, pixclk_div;%d,dclk_div:%d\n", + dclk_rate, *if_pixclk_div, *if_dclk_div); + + return dclk_rate; +} + +/* + * MIPI port mux on rk3588: + * 0: Video Port2 + * 1: Video Port3 + * 3: Video Port 1(MIPI1 only) + */ +static u32 rk3588_get_mipi_port_mux(int vp_id) +{ + if (vp_id == 1) + return 3; + else if (vp_id == 3) + return 1; + else + return 0; +} + +static u32 rk3588_get_hdmi_pol(u32 flags) +{ + u32 val; + + val = (flags & DRM_MODE_FLAG_NHSYNC) ? BIT(HSYNC_POSITIVE) : 0; + val |= (flags & DRM_MODE_FLAG_NVSYNC) ? BIT(VSYNC_POSITIVE) : 0; + + return val; +} + +static unsigned long rk3588_set_intf_mux(struct vop2_video_port *vp, int id, u32 polflags) +{ + struct vop2 *vop2 = vp->vop2; + int dclk_core_div, dclk_out_div, if_pixclk_div, if_dclk_div; + unsigned long clock; + u32 die, dip, div, vp_clk_div, val; + + clock = vop2_calc_cru_cfg(vp, id, &dclk_core_div, &dclk_out_div, + &if_pixclk_div, &if_dclk_div); + + vp_clk_div = FIELD_PREP(RK3588_VP_CLK_CTRL__DCLK_CORE_DIV, dclk_core_div); + vp_clk_div |= FIELD_PREP(RK3588_VP_CLK_CTRL__DCLK_OUT_DIV, dclk_out_div); + + die = vop2_readl(vop2, RK3568_DSP_IF_EN); + dip = vop2_readl(vop2, RK3568_DSP_IF_POL); + div = vop2_readl(vop2, RK3568_DSP_IF_CTRL); + + switch (id) { + case ROCKCHIP_VOP2_EP_HDMI0: + div |= FIELD_PREP(RK3588_DSP_IF_EDP_HDMI0_DCLK_DIV, if_dclk_div); + div |= FIELD_PREP(RK3588_DSP_IF_EDP_HDMI0_PCLK_DIV, if_pixclk_div); + die &= ~RK3588_SYS_DSP_INFACE_EN_EDP_HDMI0_MUX; + die |= RK3588_SYS_DSP_INFACE_EN_HDMI0 | + FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_EDP_HDMI0_MUX, vp->id); + val = rk3588_get_hdmi_pol(polflags); + regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, HIWORD_UPDATE(1, 1, 1)); + regmap_write(vop2->vo1_grf, RK3588_GRF_VO1_CON0, HIWORD_UPDATE(val, 6, 5)); + break; + case ROCKCHIP_VOP2_EP_HDMI1: + div |= FIELD_PREP(RK3588_DSP_IF_EDP_HDMI1_DCLK_DIV, if_dclk_div); + div |= FIELD_PREP(RK3588_DSP_IF_EDP_HDMI1_PCLK_DIV, if_pixclk_div); + die &= ~RK3588_SYS_DSP_INFACE_EN_EDP_HDMI1_MUX; + die |= RK3588_SYS_DSP_INFACE_EN_HDMI1 | + FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_EDP_HDMI1_MUX, vp->id); + val = rk3588_get_hdmi_pol(polflags); + regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, HIWORD_UPDATE(1, 4, 4)); + regmap_write(vop2->vo1_grf, RK3588_GRF_VO1_CON0, HIWORD_UPDATE(val, 8, 7)); + break; + case ROCKCHIP_VOP2_EP_EDP0: + div |= FIELD_PREP(RK3588_DSP_IF_EDP_HDMI0_DCLK_DIV, if_dclk_div); + div |= FIELD_PREP(RK3588_DSP_IF_EDP_HDMI0_PCLK_DIV, if_pixclk_div); + die &= ~RK3588_SYS_DSP_INFACE_EN_EDP_HDMI0_MUX; + die |= RK3588_SYS_DSP_INFACE_EN_EDP0 | + FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_EDP_HDMI0_MUX, vp->id); + regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, HIWORD_UPDATE(1, 0, 0)); + break; + case ROCKCHIP_VOP2_EP_EDP1: + div |= FIELD_PREP(RK3588_DSP_IF_EDP_HDMI0_DCLK_DIV, if_dclk_div); + div |= FIELD_PREP(RK3588_DSP_IF_EDP_HDMI0_PCLK_DIV, if_pixclk_div); + die &= ~RK3588_SYS_DSP_INFACE_EN_EDP_HDMI1_MUX; + die |= RK3588_SYS_DSP_INFACE_EN_EDP1 | + FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_EDP_HDMI1_MUX, vp->id); + regmap_write(vop2->vop_grf, RK3588_GRF_VOP_CON2, HIWORD_UPDATE(1, 3, 3)); + break; + case ROCKCHIP_VOP2_EP_MIPI0: + div |= FIELD_PREP(RK3588_DSP_IF_MIPI0_PCLK_DIV, if_pixclk_div); + die &= ~RK3588_SYS_DSP_INFACE_EN_MIPI0_MUX; + val = rk3588_get_mipi_port_mux(vp->id); + die |= RK3588_SYS_DSP_INFACE_EN_MIPI0 | + FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_MIPI0_MUX, !!val); + break; + case ROCKCHIP_VOP2_EP_MIPI1: + div |= FIELD_PREP(RK3588_DSP_IF_MIPI1_PCLK_DIV, if_pixclk_div); + die &= ~RK3588_SYS_DSP_INFACE_EN_MIPI1_MUX; + val = rk3588_get_mipi_port_mux(vp->id); + die |= RK3588_SYS_DSP_INFACE_EN_MIPI1 | + FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_MIPI1_MUX, val); + break; + case ROCKCHIP_VOP2_EP_DP0: + die &= ~RK3588_SYS_DSP_INFACE_EN_DP0_MUX; + die |= RK3588_SYS_DSP_INFACE_EN_DP0 | + FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_DP0_MUX, vp->id); + dip &= ~RK3588_DSP_IF_POL__DP0_PIN_POL; + dip |= FIELD_PREP(RK3588_DSP_IF_POL__DP0_PIN_POL, polflags); + break; + case ROCKCHIP_VOP2_EP_DP1: + die &= ~RK3588_SYS_DSP_INFACE_EN_MIPI1_MUX; + die |= RK3588_SYS_DSP_INFACE_EN_MIPI1 | + FIELD_PREP(RK3588_SYS_DSP_INFACE_EN_MIPI1_MUX, vp->id); + dip &= ~RK3588_DSP_IF_POL__DP1_PIN_POL; + dip |= FIELD_PREP(RK3588_DSP_IF_POL__DP1_PIN_POL, polflags); + break; + default: + drm_err(vop2->drm, "Invalid interface id %d on vp%d\n", id, vp->id); + return 0; } dip |= RK3568_DSP_IF_POL__CFG_DONE_IMD; + vop2_vp_write(vp, RK3588_VP_CLK_CTRL, vp_clk_div); vop2_writel(vop2, RK3568_DSP_IF_EN, die); + vop2_writel(vop2, RK3568_DSP_IF_CTRL, div); vop2_writel(vop2, RK3568_DSP_IF_POL, dip); + + return clock; +} + +static unsigned long vop2_set_intf_mux(struct vop2_video_port *vp, int ep_id, u32 polflags) +{ + struct vop2 *vop2 = vp->vop2; + + if (vop2->data->soc_id == 3566 || vop2->data->soc_id == 3568) + return rk3568_set_intf_mux(vp, ep_id, polflags); + else if (vop2->data->soc_id == 3588) + return rk3588_set_intf_mux(vp, ep_id, polflags); + else + return 0; } static int us_to_vertical_line(struct drm_display_mode *mode, int us) @@ -1622,7 +1907,7 @@ static void vop2_crtc_atomic_enable(struct drm_crtc *crtc, drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) { struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder); - rk3568_set_intf_mux(vp, rkencoder->crtc_endpoint_id, polflags); + clock = vop2_set_intf_mux(vp, rkencoder->crtc_endpoint_id, polflags); } if (vcstate->output_mode == ROCKCHIP_OUT_MODE_AAAA && @@ -2011,6 +2296,14 @@ static void vop2_setup_layer_mixer(struct vop2_video_port *vp) port_sel &= ~RK3568_OVL_PORT_SEL__CLUSTER1; port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__CLUSTER1, vp->id); break; + case ROCKCHIP_VOP2_CLUSTER2: + port_sel &= ~RK3588_OVL_PORT_SEL__CLUSTER2; + port_sel |= FIELD_PREP(RK3588_OVL_PORT_SEL__CLUSTER2, vp->id); + break; + case ROCKCHIP_VOP2_CLUSTER3: + port_sel &= ~RK3588_OVL_PORT_SEL__CLUSTER3; + port_sel |= FIELD_PREP(RK3588_OVL_PORT_SEL__CLUSTER3, vp->id); + break; case ROCKCHIP_VOP2_ESMART0: port_sel &= ~RK3568_OVL_PORT_SEL__ESMART0; port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__ESMART0, vp->id); @@ -2019,6 +2312,14 @@ static void vop2_setup_layer_mixer(struct vop2_video_port *vp) port_sel &= ~RK3568_OVL_PORT_SEL__ESMART1; port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__ESMART1, vp->id); break; + case ROCKCHIP_VOP2_ESMART2: + port_sel &= ~RK3588_OVL_PORT_SEL__ESMART2; + port_sel |= FIELD_PREP(RK3588_OVL_PORT_SEL__ESMART2, vp->id); + break; + case ROCKCHIP_VOP2_ESMART3: + port_sel &= ~RK3588_OVL_PORT_SEL__ESMART3; + port_sel |= FIELD_PREP(RK3588_OVL_PORT_SEL__ESMART3, vp->id); + break; case ROCKCHIP_VOP2_SMART0: port_sel &= ~RK3568_OVL_PORT_SEL__SMART0; port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__SMART0, vp->id); @@ -2760,6 +3061,9 @@ static int vop2_bind(struct device *dev, struct device *master, void *data) } vop2->sys_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf"); + vop2->vop_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,vop-grf"); + vop2->vo1_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,vo1-grf"); + vop2->sys_pmu = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pmu"); vop2->hclk = devm_clk_get(vop2->dev, "hclk"); if (IS_ERR(vop2->hclk)) { @@ -2773,6 +3077,12 @@ static int vop2_bind(struct device *dev, struct device *master, void *data) return PTR_ERR(vop2->aclk); } + vop2->pclk = devm_clk_get_optional(vop2->dev, "pclk_vop"); + if (IS_ERR(vop2->pclk)) { + drm_err(vop2->drm, "failed to get pclk source\n"); + return PTR_ERR(vop2->pclk); + } + vop2->irq = platform_get_irq(pdev, 0); if (vop2->irq < 0) { drm_err(vop2->drm, "cannot find irq for vop2\n"); diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h index 7175f46a2014..2fffe580b215 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.h @@ -16,6 +16,7 @@ #define WIN_FEATURE_AFBDC BIT(0) #define WIN_FEATURE_CLUSTER BIT(1) +#define HIWORD_UPDATE(v, h, l) ((GENMASK(h, l) << 16) | ((v) << (l))) /* * the delay number of a window in different mode. */ @@ -38,6 +39,18 @@ enum vop2_scale_down_mode { VOP2_SCALE_DOWN_AVG, }; +/* + * vop2 internal power domain id, + * should be all none zero, 0 will be treat as invalid; + */ +#define VOP2_PD_CLUSTER0 BIT(0) +#define VOP2_PD_CLUSTER1 BIT(1) +#define VOP2_PD_CLUSTER2 BIT(2) +#define VOP2_PD_CLUSTER3 BIT(3) +#define VOP2_PD_DSC_8K BIT(5) +#define VOP2_PD_DSC_4K BIT(6) +#define VOP2_PD_ESMART BIT(7) + enum vop2_win_regs { VOP2_WIN_ENABLE, VOP2_WIN_FORMAT, @@ -192,6 +205,11 @@ enum dst_factor_mode { }; #define RK3568_GRF_VO_CON1 0x0364 + +#define RK3588_GRF_SOC_CON1 0x0304 +#define RK3588_GRF_VOP_CON2 0x08 +#define RK3588_GRF_VO1_CON0 0x00 + /* System registers definition */ #define RK3568_REG_CFG_DONE 0x000 #define RK3568_VERSION_INFO 0x004 @@ -200,6 +218,7 @@ enum dst_factor_mode { #define RK3568_DSP_IF_EN 0x028 #define RK3568_DSP_IF_CTRL 0x02c #define RK3568_DSP_IF_POL 0x030 +#define RK3588_SYS_PD_CTRL 0x034 #define RK3568_WB_CTRL 0x40 #define RK3568_WB_XSCAL_FACTOR 0x44 #define RK3568_WB_YRGB_MST 0x48 @@ -223,6 +242,7 @@ enum dst_factor_mode { #define RK3568_VP_DSP_CTRL 0x00 #define RK3568_VP_MIPI_CTRL 0x04 #define RK3568_VP_COLOR_BAR_CTRL 0x08 +#define RK3588_VP_CLK_CTRL 0x0C #define RK3568_VP_3D_LUT_CTRL 0x10 #define RK3568_VP_3D_LUT_MST 0x20 #define RK3568_VP_DSP_BG 0x2C @@ -364,6 +384,9 @@ enum dst_factor_mode { #define RK3568_VP_DSP_CTRL__CORE_DCLK_DIV BIT(4) #define RK3568_VP_DSP_CTRL__OUT_MODE GENMASK(3, 0) +#define RK3588_VP_CLK_CTRL__DCLK_OUT_DIV GENMASK(3, 2) +#define RK3588_VP_CLK_CTRL__DCLK_CORE_DIV GENMASK(1, 0) + #define RK3568_VP_POST_SCL_CTRL__VSCALEDOWN BIT(1) #define RK3568_VP_POST_SCL_CTRL__HSCALEDOWN BIT(0) @@ -382,11 +405,37 @@ enum dst_factor_mode { #define RK3568_SYS_DSP_INFACE_EN_HDMI BIT(1) #define RK3568_SYS_DSP_INFACE_EN_RGB BIT(0) +#define RK3588_SYS_DSP_INFACE_EN_MIPI1_MUX GENMASK(22, 21) +#define RK3588_SYS_DSP_INFACE_EN_MIPI0_MUX GENMASK(20, 20) +#define RK3588_SYS_DSP_INFACE_EN_EDP_HDMI1_MUX GENMASK(19, 18) +#define RK3588_SYS_DSP_INFACE_EN_EDP_HDMI0_MUX GENMASK(17, 16) +#define RK3588_SYS_DSP_INFACE_EN_DP1_MUX GENMASK(15, 14) +#define RK3588_SYS_DSP_INFACE_EN_DP0_MUX GENMASK(13, 12) +#define RK3588_SYS_DSP_INFACE_EN_DPI GENMASK(9, 8) +#define RK3588_SYS_DSP_INFACE_EN_MIPI1 BIT(7) +#define RK3588_SYS_DSP_INFACE_EN_MIPI0 BIT(6) +#define RK3588_SYS_DSP_INFACE_EN_HDMI1 BIT(5) +#define RK3588_SYS_DSP_INFACE_EN_EDP1 BIT(4) +#define RK3588_SYS_DSP_INFACE_EN_HDMI0 BIT(3) +#define RK3588_SYS_DSP_INFACE_EN_EDP0 BIT(2) +#define RK3588_SYS_DSP_INFACE_EN_DP1 BIT(1) +#define RK3588_SYS_DSP_INFACE_EN_DP0 BIT(0) + +#define RK3588_DSP_IF_MIPI1_PCLK_DIV GENMASK(27, 26) +#define RK3588_DSP_IF_MIPI0_PCLK_DIV GENMASK(25, 24) +#define RK3588_DSP_IF_EDP_HDMI1_PCLK_DIV GENMASK(22, 22) +#define RK3588_DSP_IF_EDP_HDMI1_DCLK_DIV GENMASK(21, 20) +#define RK3588_DSP_IF_EDP_HDMI0_PCLK_DIV GENMASK(18, 18) +#define RK3588_DSP_IF_EDP_HDMI0_DCLK_DIV GENMASK(17, 16) + #define RK3568_DSP_IF_POL__MIPI_PIN_POL GENMASK(19, 16) #define RK3568_DSP_IF_POL__EDP_PIN_POL GENMASK(15, 12) #define RK3568_DSP_IF_POL__HDMI_PIN_POL GENMASK(7, 4) #define RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL GENMASK(3, 0) +#define RK3588_DSP_IF_POL__DP1_PIN_POL GENMASK(14, 12) +#define RK3588_DSP_IF_POL__DP0_PIN_POL GENMASK(10, 8) + #define RK3568_VP0_MIPI_CTRL__DCLK_DIV2_PHASE_LOCK BIT(5) #define RK3568_VP0_MIPI_CTRL__DCLK_DIV2 BIT(4) @@ -407,8 +456,12 @@ enum dst_factor_mode { #define RK3568_OVL_PORT_SEL__SEL_PORT GENMASK(31, 16) #define RK3568_OVL_PORT_SEL__SMART1 GENMASK(31, 30) #define RK3568_OVL_PORT_SEL__SMART0 GENMASK(29, 28) +#define RK3588_OVL_PORT_SEL__ESMART3 GENMASK(31, 30) +#define RK3588_OVL_PORT_SEL__ESMART2 GENMASK(29, 28) #define RK3568_OVL_PORT_SEL__ESMART1 GENMASK(27, 26) #define RK3568_OVL_PORT_SEL__ESMART0 GENMASK(25, 24) +#define RK3588_OVL_PORT_SEL__CLUSTER3 GENMASK(23, 22) +#define RK3588_OVL_PORT_SEL__CLUSTER2 GENMASK(21, 20) #define RK3568_OVL_PORT_SEL__CLUSTER1 GENMASK(19, 18) #define RK3568_OVL_PORT_SEL__CLUSTER0 GENMASK(17, 16) #define RK3568_OVL_PORT_SET__PORT2_MUX GENMASK(11, 8) @@ -421,6 +474,10 @@ enum dst_factor_mode { #define RK3568_CLUSTER_DLY_NUM__CLUSTER0_1 GENMASK(15, 8) #define RK3568_CLUSTER_DLY_NUM__CLUSTER0_0 GENMASK(7, 0) +#define RK3568_CLUSTER_WIN_CTRL0__WIN0_EN BIT(0) + +#define RK3568_SMART_REGION0_CTRL__WIN0_EN BIT(0) + #define RK3568_SMART_DLY_NUM__SMART1 GENMASK(31, 24) #define RK3568_SMART_DLY_NUM__SMART0 GENMASK(23, 16) #define RK3568_SMART_DLY_NUM__ESMART1 GENMASK(15, 8) diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c index 22288ad7f326..4745a9260cf8 100644 --- a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c +++ b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c @@ -34,6 +34,28 @@ static const uint32_t formats_cluster[] = { DRM_FORMAT_Y210, /* yuv422_10bit non-Linear mode only */ }; +static const uint32_t formats_esmart[] = { + DRM_FORMAT_XRGB8888, + DRM_FORMAT_ARGB8888, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_ABGR8888, + DRM_FORMAT_RGB888, + DRM_FORMAT_BGR888, + DRM_FORMAT_RGB565, + DRM_FORMAT_BGR565, + DRM_FORMAT_NV12, /* yuv420_8bit linear mode, 2 plane */ + DRM_FORMAT_NV21, /* yvu420_8bit linear mode, 2 plane */ + DRM_FORMAT_NV16, /* yuv422_8bit linear mode, 2 plane */ + DRM_FORMAT_NV61, /* yvu422_8bit linear mode, 2 plane */ + DRM_FORMAT_NV24, /* yuv444_8bit linear mode, 2 plane */ + DRM_FORMAT_NV42, /* yvu444_8bit linear mode, 2 plane */ + DRM_FORMAT_NV15, /* yuv420_10bit linear mode, 2 plane, no padding */ + DRM_FORMAT_YVYU, /* yuv422_8bit[YVYU] linear mode */ + DRM_FORMAT_VYUY, /* yuv422_8bit[VYUY] linear mode */ + DRM_FORMAT_YUYV, /* yuv422_8bit[YUYV] linear mode */ + DRM_FORMAT_UYVY, /* yuv422_8bit[UYVY] linear mode */ +}; + static const uint32_t formats_rk356x_esmart[] = { DRM_FORMAT_XRGB8888, DRM_FORMAT_ARGB8888, @@ -234,6 +256,186 @@ static const struct vop2_win_data rk3568_vop_win_data[] = { }, }; +static const struct vop2_video_port_data rk3588_vop_video_ports[] = { + { + .id = 0, + .feature = VOP_FEATURE_OUTPUT_10BIT, + .gamma_lut_len = 1024, + .cubic_lut_len = 9 * 9 * 9, /* 9x9x9 */ + .max_output = { 4096, 2304 }, + /* hdr2sdr sdr2hdr hdr2hdr sdr2sdr */ + .pre_scan_max_dly = { 76, 65, 65, 54 }, + .offset = 0xc00, + }, { + .id = 1, + .feature = VOP_FEATURE_OUTPUT_10BIT, + .gamma_lut_len = 1024, + .cubic_lut_len = 729, /* 9x9x9 */ + .max_output = { 4096, 2304 }, + .pre_scan_max_dly = { 76, 65, 65, 54 }, + .offset = 0xd00, + }, { + .id = 2, + .feature = VOP_FEATURE_OUTPUT_10BIT, + .gamma_lut_len = 1024, + .cubic_lut_len = 17 * 17 * 17, /* 17x17x17 */ + .max_output = { 4096, 2304 }, + .pre_scan_max_dly = { 52, 52, 52, 52 }, + .offset = 0xe00, + }, { + .id = 3, + .gamma_lut_len = 1024, + .max_output = { 2048, 1536 }, + .pre_scan_max_dly = { 52, 52, 52, 52 }, + .offset = 0xf00, + }, +}; + +/* + * rk3588 vop with 4 cluster, 4 esmart win. + * Every cluster can work as 4K win or split into two win. + * All win in cluster support AFBCD. + * + * Every esmart win and smart win support 4 Multi-region. + * + * Scale filter mode: + * + * * Cluster: bicubic for horizontal scale up, others use bilinear + * * ESmart: + * * nearest-neighbor/bilinear/bicubic for scale up + * * nearest-neighbor/bilinear/average for scale down + * + * AXI Read ID assignment: + * Two AXI bus: + * AXI0 is a read/write bus with a higher performance. + * AXI1 is a read only bus. + * + * Every window on a AXI bus must assigned two unique + * read id(yrgb_id/uv_id, valid id are 0x1~0xe). + * + * AXI0: + * Cluster0/1, Esmart0/1, WriteBack + * + * AXI 1: + * Cluster2/3, Esmart2/3 + * + */ +static const struct vop2_win_data rk3588_vop_win_data[] = { + { + .name = "Cluster0-win0", + .phys_id = ROCKCHIP_VOP2_CLUSTER0, + .base = 0x1000, + .formats = formats_cluster, + .nformats = ARRAY_SIZE(formats_cluster), + .format_modifiers = format_modifiers_afbc, + .layer_sel_id = 0, + .supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 | + DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y, + .max_upscale_factor = 4, + .max_downscale_factor = 4, + .dly = { 4, 26, 29 }, + .type = DRM_PLANE_TYPE_PRIMARY, + .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER, + }, { + .name = "Cluster1-win0", + .phys_id = ROCKCHIP_VOP2_CLUSTER1, + .base = 0x1200, + .formats = formats_cluster, + .nformats = ARRAY_SIZE(formats_cluster), + .format_modifiers = format_modifiers_afbc, + .layer_sel_id = 1, + .supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 | + DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y, + .type = DRM_PLANE_TYPE_PRIMARY, + .max_upscale_factor = 4, + .max_downscale_factor = 4, + .dly = { 4, 26, 29 }, + .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER, + }, { + .name = "Cluster2-win0", + .phys_id = ROCKCHIP_VOP2_CLUSTER2, + .base = 0x1400, + .formats = formats_cluster, + .nformats = ARRAY_SIZE(formats_cluster), + .format_modifiers = format_modifiers_afbc, + .layer_sel_id = 4, + .supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 | + DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y, + .type = DRM_PLANE_TYPE_PRIMARY, + .max_upscale_factor = 4, + .max_downscale_factor = 4, + .dly = { 4, 26, 29 }, + .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER, + }, { + .name = "Cluster3-win0", + .phys_id = ROCKCHIP_VOP2_CLUSTER3, + .base = 0x1600, + .formats = formats_cluster, + .nformats = ARRAY_SIZE(formats_cluster), + .format_modifiers = format_modifiers_afbc, + .layer_sel_id = 5, + .supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 | + DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y, + .type = DRM_PLANE_TYPE_PRIMARY, + .max_upscale_factor = 4, + .max_downscale_factor = 4, + .dly = { 4, 26, 29 }, + .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER, + }, { + .name = "Esmart0-win0", + .phys_id = ROCKCHIP_VOP2_ESMART0, + .formats = formats_esmart, + .nformats = ARRAY_SIZE(formats_esmart), + .format_modifiers = format_modifiers, + .base = 0x1800, + .layer_sel_id = 2, + .supported_rotations = DRM_MODE_REFLECT_Y, + .type = DRM_PLANE_TYPE_OVERLAY, + .max_upscale_factor = 8, + .max_downscale_factor = 8, + .dly = { 23, 45, 48 }, + }, { + .name = "Esmart1-win0", + .phys_id = ROCKCHIP_VOP2_ESMART1, + .formats = formats_esmart, + .nformats = ARRAY_SIZE(formats_esmart), + .format_modifiers = format_modifiers, + .base = 0x1a00, + .layer_sel_id = 3, + .supported_rotations = DRM_MODE_REFLECT_Y, + .type = DRM_PLANE_TYPE_OVERLAY, + .max_upscale_factor = 8, + .max_downscale_factor = 8, + .dly = { 23, 45, 48 }, + }, { + .name = "Esmart2-win0", + .phys_id = ROCKCHIP_VOP2_ESMART2, + .base = 0x1c00, + .formats = formats_esmart, + .nformats = ARRAY_SIZE(formats_esmart), + .format_modifiers = format_modifiers, + .layer_sel_id = 6, + .supported_rotations = DRM_MODE_REFLECT_Y, + .type = DRM_PLANE_TYPE_OVERLAY, + .max_upscale_factor = 8, + .max_downscale_factor = 8, + .dly = { 23, 45, 48 }, + }, { + .name = "Esmart3-win0", + .phys_id = ROCKCHIP_VOP2_ESMART3, + .formats = formats_esmart, + .nformats = ARRAY_SIZE(formats_esmart), + .format_modifiers = format_modifiers, + .base = 0x1e00, + .layer_sel_id = 7, + .supported_rotations = DRM_MODE_REFLECT_Y, + .type = DRM_PLANE_TYPE_OVERLAY, + .max_upscale_factor = 8, + .max_downscale_factor = 8, + .dly = { 23, 45, 48 }, + }, +}; + static const struct vop2_data rk3566_vop = { .nr_vps = 3, .max_input = { 4096, 2304 }, @@ -254,6 +456,16 @@ static const struct vop2_data rk3568_vop = { .soc_id = 3568, }; +static const struct vop2_data rk3588_vop = { + .nr_vps = 4, + .max_input = { 4096, 4320 }, + .max_output = { 4096, 4320 }, + .vp = rk3588_vop_video_ports, + .win = rk3588_vop_win_data, + .win_size = ARRAY_SIZE(rk3588_vop_win_data), + .soc_id = 3588, +}; + static const struct of_device_id vop2_dt_match[] = { { .compatible = "rockchip,rk3566-vop", @@ -261,6 +473,9 @@ static const struct of_device_id vop2_dt_match[] = { }, { .compatible = "rockchip,rk3568-vop", .data = &rk3568_vop, + }, { + .compatible = "rockchip,rk3588-vop", + .data = &rk3588_vop }, { }, }; diff --git a/include/dt-bindings/soc/rockchip,vop2.h b/include/dt-bindings/soc/rockchip,vop2.h index 6e66a802b96a..668f199df9f0 100644 --- a/include/dt-bindings/soc/rockchip,vop2.h +++ b/include/dt-bindings/soc/rockchip,vop2.h @@ -10,5 +10,9 @@ #define ROCKCHIP_VOP2_EP_LVDS0 5 #define ROCKCHIP_VOP2_EP_MIPI1 6 #define ROCKCHIP_VOP2_EP_LVDS1 7 +#define ROCKCHIP_VOP2_EP_HDMI1 8 +#define ROCKCHIP_VOP2_EP_EDP1 9 +#define ROCKCHIP_VOP2_EP_DP0 10 +#define ROCKCHIP_VOP2_EP_DP1 11 #endif /* __DT_BINDINGS_ROCKCHIP_VOP2_H */ From patchwork Tue Nov 14 11:29:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Yan X-Patchwork-Id: 164866 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b909:0:b0:403:3b70:6f57 with SMTP id t9csp1795119vqg; Tue, 14 Nov 2023 03:34:03 -0800 (PST) X-Google-Smtp-Source: AGHT+IGHDGowT3MNNx8auQOICym2fd3xHsqfPYkMKQP+IDeOMHpGEhJC36czCMUfAQT/7J7z87lG X-Received: by 2002:a17:902:e850:b0:1cc:5a65:c535 with SMTP id t16-20020a170902e85000b001cc5a65c535mr2448606plg.6.1699961643543; Tue, 14 Nov 2023 03:34:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699961643; cv=none; d=google.com; s=arc-20160816; b=Xivz1x2vZyac+SPbtHXOnbFH2UOQqgIYUpGzjZXvnm3b70wH9QcZr90/zKmrDoKCHx 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(unknown [58.22.7.114]) by zwqz-smtp-mta-g1-2 (Coremail) with SMTP id _____wDX_60HWlNlij9PDA--.55607S2; Tue, 14 Nov 2023 19:29:14 +0800 (CST) From: Andy Yan To: heiko@sntech.de Cc: hjc@rock-chips.com, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, devicetree@vger.kernel.org, sebastian.reichel@collabora.com, kever.yang@rock-chips.com, chris.obbard@collabora.com, s.hauer@pengutronix.de, Andy Yan Subject: [PATCH 10/11] drm/rockchip: vop2: Add debugfs support Date: Tue, 14 Nov 2023 19:29:10 +0800 Message-Id: <20231114112910.1771437-1-andyshrk@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231114112534.1770731-1-andyshrk@163.com> References: <20231114112534.1770731-1-andyshrk@163.com> MIME-Version: 1.0 X-CM-TRANSID: _____wDX_60HWlNlij9PDA--.55607S2 X-Coremail-Antispam: 1Uf129KBjvAXoWfJw18WFy7GF1fXF4DGFyUZFb_yoW8GF43Go Z2vF9Yvw40kr10qw4kCw18Zayfua10ya1Ikw1DKF4DZa15Gw1Ykr47Kw17AF1xXr45Ar4U Xwnaq3WfXr48Ja1rn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UbIYCTnIWIevJa73UjIFyTuYvjxU4kucDUUUU X-Originating-IP: [58.22.7.114] X-CM-SenderInfo: 5dqg52xkunqiywtou0bp/xtbBnA4oXlghlUym7wAAsN X-Spam-Status: No, score=0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,RCVD_IN_SORBS_WEB, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Tue, 14 Nov 2023 03:33:53 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782538980369702702 X-GMAIL-MSGID: 1782538980369702702 From: Andy Yan /sys/kernel/debug/dri/vop2/summary: dump vop display state /sys/kernel/debug/dri/vop2/regs: dump whole vop registers /sys/kernel/debug/dri/vop2/active_regs: only dump the registers of activated modules Signed-off-by: Andy Yan --- drivers/gpu/drm/rockchip/rockchip_drm_vop2.c | 399 +++++++++++++++++++ 1 file changed, 399 insertions(+) diff --git a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c index ba61c0233937..292a8a9de21d 100644 --- a/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c +++ b/drivers/gpu/drm/rockchip/rockchip_drm_vop2.c @@ -27,6 +27,7 @@ #include #include #include +#include #include #include @@ -187,6 +188,7 @@ struct vop2 { */ u32 registered_num_wins; + struct resource *res; void __iomem *regs; struct regmap *map; @@ -228,6 +230,44 @@ struct vop2 { #define vop2_output_if_is_lvds(x) (x == ROCKCHIP_VOP2_EP_LVDS0 || x == ROCKCHIP_VOP2_EP_LVDS1) #define vop2_output_if_is_dpi(x) (x == ROCKCHIP_VOP2_EP_RGB0) +struct vop2_regs_dump { + const char *name; + u32 base; + u32 en_reg; + u32 en_val; + u32 en_mask; +}; + +/* + * bus-format types. + */ +struct drm_bus_format_enum_list { + int type; + const char *name; +}; + +static const struct drm_bus_format_enum_list drm_bus_format_enum_list[] = { + { DRM_MODE_CONNECTOR_Unknown, "Unknown" }, + { MEDIA_BUS_FMT_RGB565_1X16, "RGB565_1X16" }, + { MEDIA_BUS_FMT_RGB666_1X18, "RGB666_1X18" }, + { MEDIA_BUS_FMT_RGB666_1X24_CPADHI, "RGB666_1X24_CPADHI" }, + { MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, "RGB666_1X7X3_SPWG" }, + { MEDIA_BUS_FMT_YUV8_1X24, "YUV8_1X24" }, + { MEDIA_BUS_FMT_UYYVYY8_0_5X24, "UYYVYY8_0_5X24" }, + { MEDIA_BUS_FMT_YUV10_1X30, "YUV10_1X30" }, + { MEDIA_BUS_FMT_UYYVYY10_0_5X30, "UYYVYY10_0_5X30" }, + { MEDIA_BUS_FMT_RGB888_3X8, "RGB888_3X8" }, + { MEDIA_BUS_FMT_RGB888_1X24, "RGB888_1X24" }, + { MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, "RGB888_1X7X4_SPWG" }, + { MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, "RGB888_1X7X4_JEIDA" }, + { MEDIA_BUS_FMT_UYVY8_2X8, "UYVY8_2X8" }, + { MEDIA_BUS_FMT_YUYV8_1X16, "YUYV8_1X16" }, + { MEDIA_BUS_FMT_UYVY8_1X16, "UYVY8_1X16" }, + { MEDIA_BUS_FMT_RGB101010_1X30, "RGB101010_1X30" }, + { MEDIA_BUS_FMT_YUYV10_1X20, "YUYV10_1X20" }, +}; +static DRM_ENUM_NAME_FN(drm_get_bus_format_name, drm_bus_format_enum_list) + static const struct regmap_config vop2_regmap_config; static struct vop2_video_port *to_vop2_video_port(struct drm_crtc *crtc) @@ -2447,6 +2487,363 @@ static const struct drm_crtc_helper_funcs vop2_crtc_helper_funcs = { .atomic_disable = vop2_crtc_atomic_disable, }; +static void vop2_dump_connector_on_crtc(struct drm_crtc *crtc, struct seq_file *s) +{ + struct drm_connector_list_iter conn_iter; + struct drm_connector *connector; + + drm_connector_list_iter_begin(crtc->dev, &conn_iter); + drm_for_each_connector_iter(connector, &conn_iter) { + if (crtc->state->connector_mask & drm_connector_mask(connector)) + seq_printf(s, " Connector: %s\n", connector->name); + + } + drm_connector_list_iter_end(&conn_iter); +} + +static int vop2_plane_state_dump(struct seq_file *s, struct drm_plane *plane) +{ + struct vop2_win *win = to_vop2_win(plane); + struct drm_plane_state *pstate = plane->state; + struct drm_rect *src, *dst; + struct drm_framebuffer *fb; + struct drm_gem_object *obj; + struct rockchip_gem_object *rk_obj; + bool xmirror; + bool ymirror; + bool rotate_270; + bool rotate_90; + dma_addr_t fb_addr; + int i; + + seq_printf(s, " %s: %s\n", win->data->name, pstate->crtc ? "ACTIVE" : "DISABLED"); + if (!pstate || !pstate->fb) + return 0; + + fb = pstate->fb; + src = &pstate->src; + dst = &pstate->dst; + xmirror = pstate->rotation & DRM_MODE_REFLECT_X ? true : false; + ymirror = pstate->rotation & DRM_MODE_REFLECT_Y ? true : false; + rotate_270 = pstate->rotation & DRM_MODE_ROTATE_270; + rotate_90 = pstate->rotation & DRM_MODE_ROTATE_90; + + seq_printf(s, "\twin_id: %d\n", win->win_id); + + seq_printf(s, "\tformat: %p4cc%s glb_alpha[0x%x]\n", + &fb->format->format, + drm_is_afbc(fb->modifier) ? "[AFBC]" : "", + pstate->alpha >> 8); + seq_printf(s, "\trotate: xmirror: %d ymirror: %d rotate_90: %d rotate_270: %d\n", + xmirror, ymirror, rotate_90, rotate_270); + seq_printf(s, "\tzpos: %d\n", pstate->normalized_zpos); + seq_printf(s, "\tsrc: pos[%d, %d] rect[%d x %d]\n", src->x1 >> 16, + src->y1 >> 16, drm_rect_width(src) >> 16, + drm_rect_height(src) >> 16); + seq_printf(s, "\tdst: pos[%d, %d] rect[%d x %d]\n", dst->x1, dst->y1, + drm_rect_width(dst), drm_rect_height(dst)); + + for (i = 0; i < fb->format->num_planes; i++) { + obj = fb->obj[0]; + rk_obj = to_rockchip_obj(obj); + fb_addr = rk_obj->dma_addr + fb->offsets[0]; + + seq_printf(s, "\tbuf[%d]: addr: %pad pitch: %d offset: %d\n", + i, &fb_addr, fb->pitches[i], fb->offsets[i]); + } + + return 0; +} + +static int vop2_crtc_state_dump(struct drm_crtc *crtc, struct seq_file *s) +{ + struct vop2_video_port *vp = to_vop2_video_port(crtc); + struct drm_crtc_state *cstate = crtc->state; + struct rockchip_crtc_state *vcstate; + struct drm_display_mode *mode; + struct drm_plane *plane; + bool interlaced; + + seq_printf(s, "Video Port%d: %s\n", vp->id, !cstate ? + "DISABLED" : cstate->active ? "ACTIVE" : "DISABLED"); + + if (!cstate || !cstate->active) + return 0; + + mode = &crtc->state->adjusted_mode; + vcstate = to_rockchip_crtc_state(cstate); + interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); + + vop2_dump_connector_on_crtc(crtc, s); + seq_printf(s, "\tbus_format[%x]: %s\n", vcstate->bus_format, + drm_get_bus_format_name(vcstate->bus_format)); + seq_printf(s, "\toutput_mode[%x]", vcstate->output_mode); + seq_printf(s, " color_space[%d]\n", vcstate->color_space); + seq_printf(s, " Display mode: %dx%d%s%d\n", + mode->hdisplay, mode->vdisplay, interlaced ? "i" : "p", + drm_mode_vrefresh(mode)); + seq_printf(s, "\tclk[%d] real_clk[%d] type[%x] flag[%x]\n", + mode->clock, mode->crtc_clock, mode->type, mode->flags); + seq_printf(s, "\tH: %d %d %d %d\n", mode->hdisplay, mode->hsync_start, + mode->hsync_end, mode->htotal); + seq_printf(s, "\tV: %d %d %d %d\n", mode->vdisplay, mode->vsync_start, + mode->vsync_end, mode->vtotal); + + drm_atomic_crtc_for_each_plane(plane, crtc) { + vop2_plane_state_dump(s, plane); + } + + return 0; +} + +static int vop2_summary_show(struct seq_file *s, void *data) +{ + struct drm_info_node *node = s->private; + struct drm_minor *minor = node->minor; + struct drm_device *drm_dev = minor->dev; + struct drm_crtc *crtc; + + drm_modeset_lock_all(drm_dev); + drm_for_each_crtc(crtc, drm_dev) { + vop2_crtc_state_dump(crtc, s); + } + drm_modeset_unlock_all(drm_dev); + + return 0; +} + +static void vop2_regs_print(struct vop2 *vop2, struct seq_file *s, struct vop2_regs_dump *dump) +{ + resource_size_t start; + const int reg_num = 0x110 / 4; + u32 val; + int i; + + if (dump->en_mask) { + val = vop2_readl(vop2, dump->base + dump->en_reg); + if ((val & dump->en_mask) != dump->en_val) + return; + } + seq_printf(s, "\n%s:\n", dump->name); + + start = vop2->res->start + dump->base; + for (i = 0; i < reg_num;) { + seq_printf(s, "%08x: %08x %08x %08x %08x\n", (u32)start + i * 4, + vop2_readl(vop2, dump->base + (4 * i)), + vop2_readl(vop2, dump->base + (4 * (i + 1))), + vop2_readl(vop2, dump->base + (4 * (i + 2))), + vop2_readl(vop2, dump->base + (4 * (i + 3)))); + i += 4; + } + +} + +static int vop2_regs_show(struct seq_file *s, void *arg) +{ + struct drm_info_node *node = s->private; + struct vop2 *vop2 = (struct vop2 *)node->info_ent->data; + struct drm_minor *minor = node->minor; + struct drm_device *drm_dev = minor->dev; + + struct vop2_regs_dump dump; + + drm_modeset_lock_all(drm_dev); + + if (vop2->enable_count) { + dump.en_mask = 0; + + dump.name = "SYS"; + dump.base = RK3568_REG_CFG_DONE; + vop2_regs_print(vop2, s, &dump); + + dump.name = "OVL"; + dump.base = RK3568_OVL_CTRL; + vop2_regs_print(vop2, s, &dump); + + dump.name = "VP0"; + dump.base = 0x0c00; + vop2_regs_print(vop2, s, &dump); + + dump.name = "VP1"; + dump.base = 0x0c00 + 0x100; + vop2_regs_print(vop2, s, &dump); + + dump.name = "VP2"; + dump.base = 0x0c00 + 0x200; + vop2_regs_print(vop2, s, &dump); + if (vop2->data->soc_id == 3588) { + dump.name = "VP3"; + dump.base = 0x0c00 + 0x300; + vop2_regs_print(vop2, s, &dump); + } + dump.name = "Cluster0"; + dump.base = 0x1000; + vop2_regs_print(vop2, s, &dump); + + dump.name = "Cluster1"; + dump.base = 0x1000 + 0x200; + vop2_regs_print(vop2, s, &dump); + if (vop2->data->soc_id == 3588) { + dump.name = "Cluster2"; + dump.base = 0x1000 + 0x400; + vop2_regs_print(vop2, s, &dump); + + dump.name = "Cluster3"; + dump.base = 0x1000 + 0x600; + vop2_regs_print(vop2, s, &dump); + } + dump.name = "Esmart0"; + dump.base = 0x1000 + 0x800; + vop2_regs_print(vop2, s, &dump); + + dump.name = "Esmart1"; + dump.base = 0x1000 + 0xa00; + vop2_regs_print(vop2, s, &dump); + + dump.name = "Esmart2"; + if (vop2->data->soc_id == 3566 || vop2->data->soc_id == 3568) + dump.name = "Smart0"; + dump.base = 0x1000 + 0xc00; + vop2_regs_print(vop2, s, &dump); + + dump.name = "Esmart3"; + if (vop2->data->soc_id == 3566 || vop2->data->soc_id == 3568) + dump.name = "Smart1"; + dump.base = 0x1000 + 0xe00; + vop2_regs_print(vop2, s, &dump); + } else { + seq_printf(s, "VOP disabled:\n"); + } + drm_modeset_unlock_all(drm_dev); + + return 0; +} + +static int vop2_active_regs_show(struct seq_file *s, void *data) +{ + struct drm_info_node *node = s->private; + struct vop2 *vop2 = (struct vop2 *)node->info_ent->data; + struct drm_minor *minor = node->minor; + struct drm_device *drm_dev = minor->dev; + + struct vop2_regs_dump dump; + + drm_modeset_lock_all(drm_dev); + if (vop2->enable_count) { + dump.en_mask = 0; + + dump.name = "SYS"; + dump.base = RK3568_REG_CFG_DONE; + vop2_regs_print(vop2, s, &dump); + + dump.name = "OVL"; + dump.base = RK3568_OVL_CTRL; + vop2_regs_print(vop2, s, &dump); + + dump.name = "VP0"; + dump.base = 0x0c00; + dump.en_mask = RK3568_VP_DSP_CTRL__STANDBY; + dump.en_reg = RK3568_VP_DSP_CTRL; + dump.en_val = 0; + vop2_regs_print(vop2, s, &dump); + + dump.name = "VP1"; + dump.base = 0x0c00 + 0x100; + vop2_regs_print(vop2, s, &dump); + + dump.name = "VP2"; + dump.base = 0x0c00 + 0x200; + vop2_regs_print(vop2, s, &dump); + if (vop2->data->soc_id == 3588) { + dump.name = "VP3"; + dump.base = 0x0c00 + 0x300; + vop2_regs_print(vop2, s, &dump); + } + + dump.en_mask = RK3568_CLUSTER_WIN_CTRL0__WIN0_EN; + dump.en_reg = RK3568_CLUSTER_WIN_CTRL0; + dump.en_val = 1; + + dump.name = "Cluster0"; + dump.base = 0x1000; + vop2_regs_print(vop2, s, &dump); + + dump.name = "Cluster1"; + dump.base = 0x1000 + 0x200; + vop2_regs_print(vop2, s, &dump); + if (vop2->data->soc_id == 3588) { + dump.name = "Cluster2"; + dump.base = 0x1000 + 0x400; + vop2_regs_print(vop2, s, &dump); + + dump.name = "Cluster3"; + dump.base = 0x1000 + 0x600; + vop2_regs_print(vop2, s, &dump); + } + + dump.name = "Esmart0"; + dump.base = 0x1000 + 0x800; + dump.en_mask = RK3568_SMART_REGION0_CTRL__WIN0_EN; + dump.en_reg = RK3568_SMART_REGION0_CTRL; + dump.en_val = 1; + vop2_regs_print(vop2, s, &dump); + + dump.name = "Esmart1"; + dump.base = 0x1000 + 0xa00; + vop2_regs_print(vop2, s, &dump); + + dump.name = "Esmart2"; + if (vop2->data->soc_id == 3566 || vop2->data->soc_id == 3568) + dump.name = "Smart0"; + dump.base = 0x1000 + 0xc00; + vop2_regs_print(vop2, s, &dump); + + dump.name = "Esmart3"; + if (vop2->data->soc_id == 3566 || vop2->data->soc_id == 3568) + dump.name = "Smart1"; + dump.base = 0x1000 + 0xe00; + vop2_regs_print(vop2, s, &dump); + } else { + seq_printf(s, "VOP disabled:\n"); + } + drm_modeset_unlock_all(drm_dev); + + return 0; +} + +static struct drm_info_list vop2_debugfs_list[] = { + { "summary", vop2_summary_show, 0, NULL }, + { "active_regs", vop2_active_regs_show, 0, NULL }, + { "regs", vop2_regs_show, 0, NULL }, +}; + +static void vop2_debugfs_init(struct vop2 *vop2, struct drm_minor *minor) +{ + struct dentry *root; + unsigned int i; + + root = debugfs_create_dir("vop2", minor->debugfs_root); + if (!IS_ERR(root)) { + for (i = 0; i < ARRAY_SIZE(vop2_debugfs_list); i++) + vop2_debugfs_list[i].data = vop2; + + drm_debugfs_create_files(vop2_debugfs_list, + ARRAY_SIZE(vop2_debugfs_list), + root, minor); + } +} + +static int vop2_crtc_late_register(struct drm_crtc *crtc) +{ + struct vop2_video_port *vp = to_vop2_video_port(crtc); + struct vop2 *vop2 = vp->vop2; + + if (drm_crtc_index(crtc) == 0) + vop2_debugfs_init(vop2, crtc->dev->primary); + + return 0; +} + static struct drm_crtc_state *vop2_crtc_duplicate_state(struct drm_crtc *crtc) { struct rockchip_crtc_state *vcstate; @@ -2496,6 +2893,7 @@ static const struct drm_crtc_funcs vop2_crtc_funcs = { .atomic_destroy_state = vop2_crtc_destroy_state, .enable_vblank = vop2_crtc_enable_vblank, .disable_vblank = vop2_crtc_disable_vblank, + .late_register = vop2_crtc_late_register, }; static irqreturn_t vop2_isr(int irq, void *data) @@ -3040,6 +3438,7 @@ static int vop2_bind(struct device *dev, struct device *master, void *data) return -EINVAL; } + vop2->res = res; vop2->regs = devm_ioremap_resource(dev, res); if (IS_ERR(vop2->regs)) return PTR_ERR(vop2->regs); From patchwork Tue Nov 14 11:29:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andy Yan X-Patchwork-Id: 164864 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b909:0:b0:403:3b70:6f57 with SMTP id t9csp1794436vqg; Tue, 14 Nov 2023 03:32:32 -0800 (PST) X-Google-Smtp-Source: AGHT+IFxBBSuWPttqlOf0oJ0T+mMd3gGsmncbtuDLt4zY5XfV/KWceKS139EIRt4NZKJNXptUTZb X-Received: by 2002:a17:90b:3886:b0:27f:fa7a:a7b with SMTP id mu6-20020a17090b388600b0027ffa7a0a7bmr11258683pjb.33.1699961551965; Tue, 14 Nov 2023 03:32:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699961551; cv=none; d=google.com; s=arc-20160816; b=Wf7itUlKjIBzMNKaGtVmyLhc7froZKUHFkta7u8LwHb8rQ7wHhLppJJelUfH/dU30e /TwJBZ3lcMPDH7AnlHNo6cZRoOSwF8XMC0lGP4IlK3HajyHSrYRsI3y9Ze11jyMFLiqg TqPabPmW426xuiK5HL/4gqPqYMU2j+xLGf+HqWgI3O8xMM5eEBD7z+ariDehjL+SChEN uU//R1BKoxRmu9hULp8E1MNzD+S/+8Clzna3H+UR+lDgHT1AboqWZu6nAIRWXHE3gTIm gSUKnU/J+A8lw839JfXboOOYysb5U2hB7Wxa5VjA7NrdiFxtzW+RToTfBPOQx8T4ZBO8 2WfQ== ARC-Message-Signature: i=1; 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(unknown [58.22.7.114]) by zwqz-smtp-mta-g0-3 (Coremail) with SMTP id _____wDHB40TWlNl6HtrDA--.55386S2; Tue, 14 Nov 2023 19:29:27 +0800 (CST) From: Andy Yan To: heiko@sntech.de Cc: hjc@rock-chips.com, dri-devel@lists.freedesktop.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, krzysztof.kozlowski+dt@linaro.org, robh+dt@kernel.org, devicetree@vger.kernel.org, sebastian.reichel@collabora.com, kever.yang@rock-chips.com, chris.obbard@collabora.com, s.hauer@pengutronix.de, Andy Yan Subject: [PATCH 11/11] arm64: dts: rockchip: Add vop on rk3588 Date: Tue, 14 Nov 2023 19:29:23 +0800 Message-Id: <20231114112923.1771498-1-andyshrk@163.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231114112534.1770731-1-andyshrk@163.com> References: <20231114112534.1770731-1-andyshrk@163.com> MIME-Version: 1.0 X-CM-TRANSID: _____wDHB40TWlNl6HtrDA--.55386S2 X-Coremail-Antispam: 1Uf129KBjvJXoWxuF1rWF1rAw48ur4kGFWxZwb_yoW5Zr1fpa sruFWrJr4kuF1Iqws8KrWvqrWkAanYka1kKwn7CFy0yr1SyryDKFWfur1fJasrXr48Aanr tFsFyryUtrsxX3DanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07jD-BNUUUUU= X-Originating-IP: [58.22.7.114] X-CM-SenderInfo: 5dqg52xkunqiywtou0bp/1tbiEBcoXl8YMdm9RAAAsn X-Spam-Status: No, score=0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,FREEMAIL_FORGED_FROMDOMAIN,FREEMAIL_FROM, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,RCVD_IN_SORBS_WEB, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Tue, 14 Nov 2023 03:32:29 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782538884495735545 X-GMAIL-MSGID: 1782538884495735545 From: Andy Yan Add vop dt node for rk3588. Signed-off-by: Andy Yan --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 96 +++++++++++++++++++++++ 1 file changed, 96 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 7064c0e9179f..c1007b1cbead 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -362,6 +362,11 @@ spll: clock-0 { #clock-cells = <0>; }; + display_subsystem: display-subsystem { + compatible = "rockchip,display-subsystem"; + ports = <&vop_out>; + }; + timer { compatible = "arm,armv8-timer"; interrupts = , @@ -474,6 +479,16 @@ sys_grf: syscon@fd58c000 { reg = <0x0 0xfd58c000 0x0 0x1000>; }; + vop_grf: syscon@fd5a4000 { + compatible = "rockchip,rk3588-vop-grf", "syscon"; + reg = <0x0 0xfd5a4000 0x0 0x2000>; + }; + + vo1_grf: syscon@fd5a8000 { + compatible = "rockchip,rk3588-vo-grf", "syscon"; + reg = <0x0 0xfd5a8000 0x0 0x100>; + }; + php_grf: syscon@fd5b0000 { compatible = "rockchip,rk3588-php-grf", "syscon"; reg = <0x0 0xfd5b0000 0x0 0x1000>; @@ -593,6 +608,87 @@ i2c0: i2c@fd880000 { status = "disabled"; }; + vop: vop@fdd90000 { + compatible = "rockchip,rk3588-vop"; + reg = <0x0 0xfdd90000 0x0 0x4200>, <0x0 0xfdd95000 0x0 0x1000>; + reg-names = "vop", "gamma_lut"; + interrupts = ; + clocks = <&cru ACLK_VOP>, + <&cru HCLK_VOP>, + <&cru DCLK_VOP0>, + <&cru DCLK_VOP1>, + <&cru DCLK_VOP2>, + <&cru DCLK_VOP3>, + <&cru PCLK_VOP_ROOT>; + clock-names = "aclk", + "hclk", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2", + "dclk_vp3", + "pclk_vop"; + resets = <&cru SRST_A_VOP>, + <&cru SRST_H_VOP>, + <&cru SRST_D_VOP0>, + <&cru SRST_D_VOP1>, + <&cru SRST_D_VOP2>, + <&cru SRST_D_VOP3>; + reset-names = "axi", + "ahb", + "dclk_vp0", + "dclk_vp1", + "dclk_vp2", + "dclk_vp3"; + iommus = <&vop_mmu>; + power-domains = <&power RK3588_PD_VOP>; + rockchip,grf = <&sys_grf>; + rockchip,vop-grf = <&vop_grf>; + rockchip,vo1-grf = <&vo1_grf>; + rockchip,pmu = <&pmu>; + + status = "disabled"; + vop_out: ports { + #address-cells = <1>; + #size-cells = <0>; + + vp0: port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + vp1: port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + vp2: port@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + vp3: port@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + }; + + vop_mmu: iommu@fdd97e00 { + compatible = "rockchip,rk3568-iommu"; + reg = <0x0 0xfdd97e00 0x0 0x100>, <0x0 0xfdd97f00 0x0 0x100>; + interrupts = ; + interrupt-names = "vop_mmu"; + clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>; + clock-names = "aclk", "iface"; + #iommu-cells = <0>; + power-domains = <&power RK3588_PD_VOP>; + status = "disabled"; + }; + uart0: serial@fd890000 { compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart"; reg = <0x0 0xfd890000 0x0 0x100>;