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[2620:137:e000::1:20]) by mx.google.com with ESMTP id hd31-20020a170907969f00b0078266dc4b8csi18663769ejc.719.2022.11.09.00.30.47; Wed, 09 Nov 2022 00:31:11 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=K+P7tZlf; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230124AbiKII3F (ORCPT + 99 others); Wed, 9 Nov 2022 03:29:05 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40896 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229987AbiKII2j (ORCPT ); Wed, 9 Nov 2022 03:28:39 -0500 Received: from mail-pf1-x433.google.com (mail-pf1-x433.google.com [IPv6:2607:f8b0:4864:20::433]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5A6AFFED; Wed, 9 Nov 2022 00:28:23 -0800 (PST) Received: by mail-pf1-x433.google.com with SMTP id m6so16087377pfb.0; Wed, 09 Nov 2022 00:28:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=a04oUGY9n3fJGrXo8icImVtwc+ewjypnXhaaNSDY1GQ=; b=K+P7tZlfLXA88kzJjIIjZZPjUJaBHbJmrzVN6PYRfi1Oa6oMruscZ3MQ8qCz2hQg0E ML3j/csqsCnwbY8AJpY0g/t9XkiTZbL7pvFRmXrzHM0k2miDCOk/m++Jm9usTJAgOVqC BvyHk5STlaPWgpWPglqWGrIrH4C8GzHonSRQT8yeMs7tx4XYislMnOSSd8+sZETkI4io cGtTmNt+9NNhvaITYBOPXYAKq4efcw1YFlAOTWJRjS43Wu7fWhbazjR2j6+J4+RG71EY BBeVo6He1aShlfX9OjrTNRVkCTBhjfO/ueCvE+OHNUpXX4YOELeZvIXlYJ998QHCWH80 X+WQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=a04oUGY9n3fJGrXo8icImVtwc+ewjypnXhaaNSDY1GQ=; b=pDFIzOlghFrMxUt516ISdIpMHqkLd2soNhXrmXjY26CO/z3huq5zZvLME87LrYQCkx lEh1Uy5WONSFMbaqG0Rr3S3FAKKSCBUgnSQn5UY8AYvTv76hhlC7dKPj42vCvgjjRTCU Nc0IzrPVKAO7XHhoGIJHXJkEtj2FO5Fcp+s/IjiwN/MPfBNC6lFl2MxgP/UuBJsMlvto yUwtmiGGaYP0X0r67Ad1OzKOrB1W84mrPROH1KeMd4aa75WQowlU9JUsr4ARASKgasIE Nm9g984eGdB7tnUFZVOechGSXxxhu2yWn5kd63UGTXZ/IDJCf11fr1IIvZQTTdo78nG5 dvyQ== X-Gm-Message-State: ACrzQf3zZfhFJgB1W+Va0L/iaUHsgy57AakfiQ8m/MiwYnxdvcQuISWj X1WaQ0dlgI8feqQikS5PCjY= X-Received: by 2002:a63:1f13:0:b0:455:80ce:6d36 with SMTP id f19-20020a631f13000000b0045580ce6d36mr52181566pgf.111.1667982502775; Wed, 09 Nov 2022 00:28:22 -0800 (PST) Received: from localhost.localdomain ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id b14-20020a63d30e000000b00470537b9b0asm6587700pgg.51.2022.11.09.00.28.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 09 Nov 2022 00:28:22 -0800 (PST) From: Like Xu X-Google-Original-From: Like Xu To: Sean Christopherson , Paolo Bonzini Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org Subject: [PATCH v3 1/3] KVM: x86/pmu: Disable guest PEBS on hybird cpu due to heterogeneity Date: Wed, 9 Nov 2022 16:28:00 +0800 Message-Id: <20221109082802.27543-2-likexu@tencent.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221109082802.27543-1-likexu@tencent.com> References: <20221109082802.27543-1-likexu@tencent.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_FROM, RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749006597828425948?= X-GMAIL-MSGID: =?utf-8?q?1749006597828425948?= From: Like Xu From vPMU enabling perspective, KVM does not have proper support for hybird x86 core. The reported perf_capabilities value (e.g. the format of pebs record) depends on the type of cpu the kvm-intel module is init. When a vcpu of one pebs format migrates to a vcpu of another pebs format, the incorrect parsing of pebs records by guest can make profiling data analysis extremely problematic. The safe way to fix this is to disable this part of the support until the guest recognizes that it is running on the hybird cpu, which is appropriate at the moment given that x86 hybrid architectures are not heavily touted in the data center market. Signed-off-by: Like Xu --- arch/x86/kvm/vmx/capabilities.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/arch/x86/kvm/vmx/capabilities.h b/arch/x86/kvm/vmx/capabilities.h index cd2ac9536c99..ea0498684048 100644 --- a/arch/x86/kvm/vmx/capabilities.h +++ b/arch/x86/kvm/vmx/capabilities.h @@ -392,7 +392,9 @@ static inline bool vmx_pt_mode_is_host_guest(void) static inline bool vmx_pebs_supported(void) { - return boot_cpu_has(X86_FEATURE_PEBS) && kvm_pmu_cap.pebs_ept; + return boot_cpu_has(X86_FEATURE_PEBS) && + !boot_cpu_has(X86_FEATURE_HYBRID_CPU) && + kvm_pmu_cap.pebs_ept; } static inline bool cpu_has_notify_vmexit(void) From patchwork Wed Nov 9 08:28:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 17393 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp216684wru; Wed, 9 Nov 2022 00:31:16 -0800 (PST) X-Google-Smtp-Source: AA0mqf4wB0GXuRd1+nY9XlbK2V/mu06TJpxkKu+4i+Rb3aAVB6fiz+4/Tao7dGzjnz5EeyDGRKlK X-Received: by 2002:a17:907:7e95:b0:78d:e9cf:82c7 with SMTP id qb21-20020a1709077e9500b0078de9cf82c7mr4638350ejc.724.1667982676671; Wed, 09 Nov 2022 00:31:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1667982676; cv=none; d=google.com; s=arc-20160816; b=mu2Vrh8WNb8q/6GdoZdpeRFMunYuyynlu15Gl/UD+N87oE2gYFMFhZi+Xkd/E9iFJF /jFWBFurK+u39odwU01XNZpU/P6vC1e5Is/JIz3H08pi2RVEjyyXoItP+jPEHyvIRXDh uypDtSNH8vs/aNCyPf7XL5LRPIBhw45xTVdF+VpGwbCuit1YuvwIz4+le5qHpff75pSS hwRQUrk+THEhgsf1nSThsq9Xs653TWaRNicPk9lGro5Nb7Oz7wysDRwRpAIH+wP6h6Cd 2oIUJXv9b3c5yFCw0JZOnFmjQjbt5VMkNk8fc0DUVnncT71Ecx8qp7XCqHfTSvIBi5wL vqAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=gfUfiLMSDty5pKmQVoXHf+IXuNDCfniw4Yx5uF+cedc=; b=N61AMpdIe5ysDr4/ArLFbCDUQiX8DVf0DtpXE+6tNKaj45/dWAWfhMPZ02SwUIsYau sTKGcA97zoaz3GizWjzxPXNied1x59C9jlRgzaVnXO1LwYgxUMI3Id5PFUu3ny3nN+mW ZDy6PylYKADq97NJLetxFbSoRGvky9BlZtP+j0dY4TOUIdEb6DsGywSX5UCmmyA+49J2 EqBXd4rEed13DJGY/rRSQ/JdOXr/erCDIWNPdAg+6Ol3VE95Fjrgezde7EEjxIF/3p2l m0jPUKvcfqQs/jC31VcuJ28zO+uUCl2PScOfyBV797cb/MAn3tz82FnmnBBDuWIjCiWY 9BZQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=PnI7rvNS; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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Upon triggering a PEBS assist, there will be a finite delay between the time the counter overflows and when the microcode starts to carry out its data collection obligations. Even if the delay is constant in core clock space, it invariably manifest as variable "skids" in instruction address space. On the Ice Lake Server, the Precise Distribution of Instructions Retire (PDIR) facility mitigates the "skid" problem by providing an early indication of when the counter is about to overflow. On SPR, the PDIR counter available (Fixed 0) is unchanged, but the capability is enhanced to Instruction-Accurate PDIR (PDIR++), where PEBS is taken on the next instruction after the one that caused the overflow. SPR also introduces a new Precise Distribution (PDist) facility only on general programmable counter 0. Per Intel SDM, PDist eliminates any skid or shadowing effects from PEBS. With PDist, the PEBS record will be generated precisely upon completion of the instruction or operation that causes the counter to overflow (there is no "wait for next occurrence" by default). In terms of KVM handling, when guest accesses those special counters, the KVM needs to request the same index counters via the perf_event kernel subsystem to ensure that the guest uses the correct pebs hardware counter (PRIR++ or PDist). This is mainly achieved by adjusting the event precise level to the maximum, where the semantics of this magic number is mainly defined by the internal software context of perf_event and it's also backwards compatible as part of the user space interface. Opportunistically, refine confusing comments on TNT+, as the only ones that currently support pebs_ept are Ice Lake server and SPR (GLC+). Signed-off-by: Like Xu --- arch/x86/kvm/pmu.c | 45 +++++++++++++++++++++++++++++++++------------ 1 file changed, 33 insertions(+), 12 deletions(-) diff --git a/arch/x86/kvm/pmu.c b/arch/x86/kvm/pmu.c index 935c9d80ab50..3df48fc34e97 100644 --- a/arch/x86/kvm/pmu.c +++ b/arch/x86/kvm/pmu.c @@ -28,9 +28,18 @@ struct x86_pmu_capability __read_mostly kvm_pmu_cap; EXPORT_SYMBOL_GPL(kvm_pmu_cap); -static const struct x86_cpu_id vmx_icl_pebs_cpu[] = { +/* Precise Distribution of Instructions Retired (PDIR) */ +static const struct x86_cpu_id vmx_pebs_pdir_cpu[] = { X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, NULL), X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, NULL), + /* Instruction-Accurate PDIR (PDIR++) */ + X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, NULL), + {} +}; + +/* Precise Distribution (PDist) */ +static const struct x86_cpu_id vmx_pebs_pdist_cpu[] = { + X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, NULL), {} }; @@ -155,6 +164,28 @@ static void kvm_perf_overflow(struct perf_event *perf_event, kvm_make_request(KVM_REQ_PMU, pmc->vcpu); } +static u64 pmc_get_pebs_precise_level(struct kvm_pmc *pmc) +{ + /* + * For some model specific pebs counters with special capabilities + * (PDIR, PDIR++, PDIST), KVM needs to raise the event precise + * level to the maximum value (currently 3, backwards compatible) + * so that the perf subsystem would assign specific hardware counter + * with that capability for vPMC. + */ + if ((pmc->idx == 0 && x86_match_cpu(vmx_pebs_pdist_cpu)) || + (pmc->idx == 32 && x86_match_cpu(vmx_pebs_pdir_cpu))) + return 3; + + /* + * The non-zero precision level of guest event makes the ordinary + * guest event becomes a guest PEBS event and triggers the host + * PEBS PMI handler to determine whether the PEBS overflow PMI + * comes from the host counters or the guest. + */ + return 1; +} + static int pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type, u64 config, bool exclude_user, bool exclude_kernel, bool intr) @@ -186,22 +217,12 @@ static int pmc_reprogram_counter(struct kvm_pmc *pmc, u32 type, u64 config, } if (pebs) { /* - * The non-zero precision level of guest event makes the ordinary - * guest event becomes a guest PEBS event and triggers the host - * PEBS PMI handler to determine whether the PEBS overflow PMI - * comes from the host counters or the guest. - * * For most PEBS hardware events, the difference in the software * precision levels of guest and host PEBS events will not affect * the accuracy of the PEBS profiling result, because the "event IP" * in the PEBS record is calibrated on the guest side. - * - * On Icelake everything is fine. Other hardware (GLC+, TNT+) that - * could possibly care here is unsupported and needs changes. */ - attr.precise_ip = 1; - if (x86_match_cpu(vmx_icl_pebs_cpu) && pmc->idx == 32) - attr.precise_ip = 3; + attr.precise_ip = pmc_get_pebs_precise_level(pmc); } event = perf_event_create_kernel_counter(&attr, -1, current, From patchwork Wed Nov 9 08:28:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Like Xu X-Patchwork-Id: 17394 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp216727wru; Wed, 9 Nov 2022 00:31:22 -0800 (PST) X-Google-Smtp-Source: AMsMyM7Ld0HSdoHub5+at3dVsjt382lRRKVmybnBxrngfzm4vzH4+sbxKMASYfT0SdEW3k53v6CJ X-Received: by 2002:a17:907:3105:b0:7ae:34e5:e619 with SMTP id wl5-20020a170907310500b007ae34e5e619mr23891449ejb.516.1667982682448; Wed, 09 Nov 2022 00:31:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1667982682; cv=none; d=google.com; s=arc-20160816; b=k3VWKfxj4S0d9j5uMttLKZGD2h3U5pI/VSKx7ynbw+kPQJ2ESdNNIAInFqwRTYLG6H hUPAv+ZDDgbj/uS3s2I7onpGrVMn+ko+Z7G01NlmFz4h1nAvdwTi3pxeuJptdLfHeoQy zvu9AaKtu8HD29F5glinx5qHFzvCQkIVaaBxIlhoJW1UvRQq+QiSBxbBOITuokxHQ0aU fTsJjyMEpjnM41iqTcrOE3QC0fj9XiydD5rr5vUxHWHho6Spxq6Wmw9uPkBDOUOy5s88 2T9u1BkQI/S4cNV4HWKEpfZt/3yi+xV4NaNBThpZTYHuH3xPo1eZfkLlttzyTUwzI2Ys njMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=rsRdQU8Ady+UGmrXI+CqXDPucP2vHJde8y88ZmpGZsM=; b=xk/QJCRZia11atlkunHTsGRj2xLREcq46pBcgWW7Pz6JVZVVlpgA9v3H0qtGZQ9rLi uwD289FfEsCHzy6og/3U0H225epFh+/dk4msXArXAVVBiH714+LZsGAhWP0grROnSQoR hUQl4Es4c6Xd1BP64nlcbbn0D9A/XiLevG5BqnkBjvGCRxxIP294/pxVDSsH2kGih6uo N2BkCU4tJ0NklmeIqS46i1r0NNcI+eg8t9NTEi/6iWTVXTormCqacQLX9/yUz6UxzVqn WXY2BkxdfS7R6pqLE3ksobjWPa5KT7bSpuy6isk7SqADQjG0fgqT9EeEYv4Fm/M/s3/N Mh/w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gmail.com header.s=20210112 header.b=LKISIc2c; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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Currently the only in-kernel user of this capability is KVM, which has very limited support for hybrid core pmu, so ADL and its successors do not currently expose this capability. When both hybrid core and PEBS format 5 are present, KVM will decide on its own merits. Cc: Peter Zijlstra Cc: linux-perf-users@vger.kernel.org Suggested-by: Kan Liang Signed-off-by: Like Xu Reviewed-by: Kan Liang Acked-by: Peter Zijlstra (Intel) --- Nit: This change is proposed to be applied via the KVM tree. arch/x86/events/intel/core.c | 1 + arch/x86/events/intel/ds.c | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c index a646a5f9a235..15e061fbb2f3 100644 --- a/arch/x86/events/intel/core.c +++ b/arch/x86/events/intel/core.c @@ -6350,6 +6350,7 @@ __init int intel_pmu_init(void) x86_pmu.pebs_constraints = intel_spr_pebs_event_constraints; x86_pmu.extra_regs = intel_spr_extra_regs; x86_pmu.limit_period = spr_limit_period; + x86_pmu.pebs_ept = 1; x86_pmu.pebs_aliases = NULL; x86_pmu.pebs_prec_dist = true; x86_pmu.pebs_block = true; diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c index 7839507b3844..185e66b4ce31 100644 --- a/arch/x86/events/intel/ds.c +++ b/arch/x86/events/intel/ds.c @@ -2293,8 +2293,10 @@ void __init intel_ds_init(void) x86_pmu.large_pebs_flags |= PERF_SAMPLE_TIME; break; - case 4: case 5: + x86_pmu.pebs_ept = 1; + fallthrough; + case 4: x86_pmu.drain_pebs = intel_pmu_drain_pebs_icl; x86_pmu.pebs_record_size = sizeof(struct pebs_basic); if (x86_pmu.intel_cap.pebs_baseline) {