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[2620:137:e000::1:20]) by mx.google.com with ESMTP id iw5-20020a170903044500b00186c37272a6si15625418plb.178.2022.11.08.23.36.04; Tue, 08 Nov 2022 23:36:18 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=SAcaJ7gr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229772AbiKIHfo (ORCPT + 99 others); Wed, 9 Nov 2022 02:35:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42618 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229530AbiKIHfm (ORCPT ); Wed, 9 Nov 2022 02:35:42 -0500 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F6AB1AF08; Tue, 8 Nov 2022 23:35:37 -0800 (PST) X-UUID: e6ccc4b1ab0347dd88563f77eb9b12e9-20221109 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:Message-ID:Date:Subject:CC:To:From; bh=9k9uk4PP+p/ezx83CEQ8H7xrIryZqMyMXaSUInDHGYI=; b=SAcaJ7grows0j199lNHgbQLtWukDIPjB987Z9eC0Bekpv4iY8jicYxD0d8yaY7D9bZ0Y/Hp9fQuFH+AM0w35kXrWh0jGTexCFVrkkw5r2dmmZMy7eoR3hGHIS1ouK8oR9k9kioAPaYWMu8L3guge7BbQtf2wMeSDm41Xeur9PZM=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.12,REQID:142ee2fc-1dba-4584-8981-dc99586e8ea9,IP:0,U RL:0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:70 X-CID-INFO: VERSION:1.1.12,REQID:142ee2fc-1dba-4584-8981-dc99586e8ea9,IP:0,URL :0,TC:0,Content:-25,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTI ON:quarantine,TS:70 X-CID-META: VersionHash:62cd327,CLOUDID:75d498fa-5f3f-42f2-9a97-16904f30874b,B ulkID:221109153533NP9T1N9V,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48,TC:n il,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: e6ccc4b1ab0347dd88563f77eb9b12e9-20221109 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1864707884; Wed, 09 Nov 2022 15:35:32 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Wed, 9 Nov 2022 15:35:31 +0800 Received: from localhost.localdomain (10.17.3.154) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Wed, 9 Nov 2022 15:35:30 +0800 From: Yunfei Dong To: Yunfei Dong , Rob Herring , Chen-Yu Tsai , Hans Verkuil , AngeloGioacchino Del Regno , Benjamin Gaignard , Tiffany Lin CC: Mauro Carvalho Chehab , Matthias Brugger , Hsin-Yi Wang , Daniel Vetter , Steve Cho , , , , , , Subject: [PATCH 1/3] media: dt-bindings: media: mediatek: vcodec: Fix clock num not correctly Date: Wed, 9 Nov 2022 15:35:27 +0800 Message-ID: <20221109073529.26765-1-yunfei.dong@mediatek.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS, T_SPF_TEMPERROR,UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749003144779550784?= X-GMAIL-MSGID: =?utf-8?q?1749003144779550784?= mt8195 and mt8192 have different clock numbers, can't write 'clocks' and 'clock-names' with const value. Move 'assigned-clocks' and 'assigned-clock-parents' to parent node. Signed-off-by: Yunfei Dong --- .../media/mediatek,vcodec-subdev-decoder.yaml | 119 +++++++++++------- 1 file changed, 72 insertions(+), 47 deletions(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml index c4f20acdc1f8..794012853834 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml @@ -89,23 +89,33 @@ properties: ranges: true + clocks: + minItems: 1 + maxItems: 5 + + clock-names: + minItems: 1 + maxItems: 5 + + assigned-clocks: + maxItems: 1 + + assigned-clock-parents: + maxItems: 1 + # Required child node: patternProperties: - '^vcodec-lat@[0-9a-f]+$': + '^vcodec-lat-soc@[0-9a-f]+$': type: object properties: compatible: enum: - - mediatek,mtk-vcodec-lat - mediatek,mtk-vcodec-lat-soc reg: maxItems: 1 - interrupts: - maxItems: 1 - iommus: minItems: 1 maxItems: 32 @@ -114,22 +124,55 @@ patternProperties: Refer to bindings/iommu/mediatek,iommu.yaml. clocks: + minItems: 1 maxItems: 5 clock-names: - items: - - const: sel - - const: soc-vdec - - const: soc-lat - - const: vdec - - const: top + minItems: 1 + maxItems: 5 - assigned-clocks: + power-domains: maxItems: 1 - assigned-clock-parents: + required: + - compatible + - reg + - iommus + - clocks + - clock-names + - power-domains + + additionalProperties: false + + '^vcodec-lat@[0-9a-f]+$': + type: object + + properties: + compatible: + enum: + - mediatek,mtk-vcodec-lat + + reg: + maxItems: 1 + + interrupts: maxItems: 1 + iommus: + minItems: 1 + maxItems: 32 + description: | + List of the hardware port in respective IOMMU block for current Socs. + Refer to bindings/iommu/mediatek,iommu.yaml. + + clocks: + minItems: 1 + maxItems: 5 + + clock-names: + minItems: 1 + maxItems: 5 + power-domains: maxItems: 1 @@ -139,8 +182,6 @@ patternProperties: - iommus - clocks - clock-names - - assigned-clocks - - assigned-clock-parents - power-domains additionalProperties: false @@ -166,15 +207,12 @@ patternProperties: Refer to bindings/iommu/mediatek,iommu.yaml. clocks: + minItems: 1 maxItems: 5 clock-names: - items: - - const: sel - - const: soc-vdec - - const: soc-lat - - const: vdec - - const: top + minItems: 1 + maxItems: 5 assigned-clocks: maxItems: 1 @@ -188,12 +226,9 @@ patternProperties: required: - compatible - reg - - interrupts - iommus - clocks - clock-names - - assigned-clocks - - assigned-clock-parents - power-domains additionalProperties: false @@ -205,17 +240,10 @@ required: - mediatek,scp - dma-ranges - ranges - -if: - properties: - compatible: - contains: - enum: - - mediatek,mtk-vcodec-lat - -then: - required: - - interrupts + - clocks + - clock-names + - assigned-clocks + - assigned-clock-parents additionalProperties: false @@ -241,6 +269,11 @@ examples: #size-cells = <2>; ranges = <0 0 0 0x16000000 0 0x40000>; reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */ + clocks = <&topckgen CLK_TOP_VDEC_SEL>, + <&topckgen CLK_TOP_MAINPLL_D4>; + clock-names = "sel", "top"; + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; vcodec-lat@10000 { compatible = "mediatek,mtk-vcodec-lat"; reg = <0 0x10000 0 0x800>; @@ -253,14 +286,10 @@ examples: <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>, <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>, <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>; - clocks = <&topckgen CLK_TOP_VDEC_SEL>, - <&vdecsys_soc CLK_VDEC_SOC_VDEC>, + clocks = <&vdecsys_soc CLK_VDEC_SOC_VDEC>, <&vdecsys_soc CLK_VDEC_SOC_LAT>, - <&vdecsys_soc CLK_VDEC_SOC_LARB1>, - <&topckgen CLK_TOP_MAINPLL_D4>; + <&vdecsys_soc CLK_VDEC_SOC_LARB1>; clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top"; - assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>; }; @@ -279,14 +308,10 @@ examples: <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>, <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>, <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>; - clocks = <&topckgen CLK_TOP_VDEC_SEL>, - <&vdecsys CLK_VDEC_VDEC>, + clocks = <&vdecsys CLK_VDEC_VDEC>, <&vdecsys CLK_VDEC_LAT>, - <&vdecsys CLK_VDEC_LARB1>, - <&topckgen CLK_TOP_MAINPLL_D4>; + <&vdecsys CLK_VDEC_LARB1>; clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top"; - assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>; - assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>; power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>; }; }; From patchwork Wed Nov 9 07:35:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?WXVuZmVpIERvbmcgKOiRo+S6kemjnik=?= X-Patchwork-Id: 17374 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp198573wru; Tue, 8 Nov 2022 23:36:19 -0800 (PST) X-Google-Smtp-Source: AMsMyM4GSVyKwIjhlYnR1X4y0tJMW4KjjqLJe0hHBFP73yT/W0BsStZzcwg2Gbc3uXAm70UGb/Hu X-Received: by 2002:a17:902:f252:b0:186:9efb:7203 with SMTP id j18-20020a170902f25200b001869efb7203mr58617642plc.12.1667979379228; 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Changing the max reg value from 1 to 2. Signed-off-by: Yunfei Dong --- .../bindings/media/mediatek,vcodec-subdev-decoder.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml index 794012853834..1697feb1f854 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml @@ -61,7 +61,7 @@ properties: - mediatek,mt8195-vcodec-dec reg: - maxItems: 1 + maxItems: 2 iommus: minItems: 1 From patchwork Wed Nov 9 07:35:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?WXVuZmVpIERvbmcgKOiRo+S6kemjnik=?= X-Patchwork-Id: 17375 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp205225wru; Tue, 8 Nov 2022 23:57:09 -0800 (PST) X-Google-Smtp-Source: AMsMyM5ytwhrPyI+83AFevzsb+287zXp8xDVYykVoUg+vNiSFWsTs2LTaRmd6y5EhzCrVsDMosDA X-Received: by 2002:a17:902:c40a:b0:186:ba20:76fa with SMTP id k10-20020a170902c40a00b00186ba2076famr59903065plk.55.1667980629403; Tue, 08 Nov 2022 23:57:09 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1667980629; cv=none; d=google.com; s=arc-20160816; b=BdWcoznkLndiF4EKcwDRRg4t8BmSLZD/KsaZNS1U+9fNWCyoyUPXICH59Y1bZ5B0E2 bhD0Wamq+9xrhSOTWzxdO9Br+Im84agXz9B4h4Nuq6jXwwn3F5Lvq/33+y+I5MOean4k U43gg7ncqeGIdAGDOgOzXtVLY/AKwM1Gt8b9mY0Ulf9WR3huxdkT+swY4AI9bBMr/7cp meqAaFKNReeg4ZpC2vzBhYsKKJwlqKkUbb5qiJfLzT0ty6jb5WAuylboxZF9nJacvTCX vE+0zJMsmAD7HL1eeVvcsCIktkLbbW8pRIbCMthQXXR2xFmcsDef7oNTX16MUJrhb/on MyUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=FVr/w7/wOLRWDOkFgdIIqFh4IiDRfiBAxHj4ct/E3/A=; b=UPOvyDp1JrWPI774aBGW36z+JTh5kECdkQyzy83W/Bv/iRh9KX7pW/De/Jnobq8jB1 CFTRkApve8iEdRsNbKXtIbq9yArebc+AUqlUNG+oPk+hM3eN4pWj5hCKs0mNlgEyTO4K jDyxSXUxdwJCUoq+qpMZsZFxe7ploNTfVhuZ5rHzEOuJRg5oVgtYrGh5ykEVx6z+pBeA uS8Ba8kOFZyNzXyLI6l4rpYnHGy88EsRFbSclrJjzG76vu46c1812u2QEDOAmwXYZNWW qOCDEbtEkPGQFlMmQYFn/KWOsZjdjIcH2ZBbb2qGbXv7MRoxA7+zN+/+PkEk839uUkDg 6dog== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=fkfOdTNo; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Yunfei Dong --- dtbs_check pass. --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 63 ++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 905d1a90b406..ffabf91d4273 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -1874,6 +1874,69 @@ power-domains = <&spm MT8195_POWER_DOMAIN_CAM>; }; + video-codec@18000000 { + compatible = "mediatek,mt8195-vcodec-dec"; + mediatek,scp = <&scp>; + iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>; + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>; + #address-cells = <2>; + #size-cells = <2>; + reg = <0 0x18000000 0 0x1000>, /* VDEC_SYS */ + <0 0x18004000 0 0x1000>; /* VDEC_RACING_CTRL */ + ranges = <0 0 0 0x18000000 0 0x26000>; + clocks = <&topckgen CLK_TOP_VDEC>, + <&topckgen CLK_TOP_UNIVPLL_D4>; + clock-names = "vdec-sel", "top"; + assigned-clocks = <&topckgen CLK_TOP_VDEC>; + assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>; + + vcodec-lat-soc@2000 { + compatible = "mediatek,mtk-vcodec-lat-soc"; + reg = <0 0x2000 0 0x800>; /* VDEC_MISC */ + iommus = <&iommu_vpp M4U_PORT_L23_VDEC_UFO_ENC_EXT>, + <&iommu_vpp M4U_PORT_L23_VDEC_RDMA_EXT>; + clocks = <&vdecsys_soc CLK_VDEC_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_LAT>; + clock-names = "vdec-soc-vdec", "vdec-soc-lat"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; + }; + + vcodec-lat@10000 { + compatible = "mediatek,mtk-vcodec-lat"; + reg = <0 0x10000 0 0x800>; /* VDEC_MISC */ + interrupts = ; + iommus = <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD_EXT>, + <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_VLD2_EXT>, + <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_AVC_MC_EXT>, + <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_PRED_RD_EXT>, + <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_TILE_EXT>, + <&iommu_vdo M4U_PORT_L24_VDEC_LAT0_WDMA_EXT>; + clocks = <&vdecsys_soc CLK_VDEC_SOC_VDEC>, + <&vdecsys_soc CLK_VDEC_SOC_LAT>; + clock-names = "vdec-soc-vdec", "vdec-soc-lat"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>; + }; + + vcodec-core@25000 { + compatible = "mediatek,mtk-vcodec-core"; + reg = <0 0x25000 0 0x1000>; /* VDEC_CORE_MISC */ + interrupts = ; + iommus = <&iommu_vdo M4U_PORT_L21_VDEC_MC_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_UFO_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_PP_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_PRED_RD_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_PRED_WR_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_PPWRAP_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_TILE_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_VLD_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_VLD2_EXT>, + <&iommu_vdo M4U_PORT_L21_VDEC_AVC_MV_EXT>; + clocks = <&vdecsys CLK_VDEC_VDEC>, <&vdecsys CLK_VDEC_LAT>; + clock-names = "vdec-vdec", "vdec-lat"; + power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>; + }; + }; + larb24: larb@1800d000 { compatible = "mediatek,mt8195-smi-larb"; reg = <0 0x1800d000 0 0x1000>;