From patchwork Fri Nov 10 07:14:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Jin Ma X-Patchwork-Id: 163778 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b129:0:b0:403:3b70:6f57 with SMTP id q9csp940051vqs; Thu, 9 Nov 2023 23:15:15 -0800 (PST) X-Google-Smtp-Source: AGHT+IEVhWqQSWQVEKwHD0sEHLO+tgf9PrnnTbFCmEvWpeA9VsRD/iyDsNWKB+jOrxeTpaFeW+la X-Received: by 2002:ac5:cdcc:0:b0:4a1:8aa1:8dcd with SMTP id u12-20020ac5cdcc000000b004a18aa18dcdmr3530076vkn.15.1699600515621; Thu, 09 Nov 2023 23:15:15 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1699600515; cv=pass; d=google.com; s=arc-20160816; b=CzqVJboGGcr4Vua22OyYa7P9+z7j454mHWPckV4tYv4HWyEImaaCHil3x+4ZE27jcC rTeUP1vIJEGruq+DuCwcPZukgDierc2Sjd3fNLNXnAYM3pnKZsNOP0VSft5De6PDz/AP 63Z2z8aHPFDbL+Q+kAcWGbS6jhXamm1iilsu0b755rNOngFhmHLNHAHcBf1teWb1dLSp 9xLD46Sl01Mll1CZlooZP35ZM2WUlY5P3yrlmm3YCraKKOBjBGEwmrWsH3evZ3Yvzh8X /Sj+E6Y2rWI+VZCOPr7uSbwIkNPg1w9FCFnj0N+PQF4ceLcNOV26gw+46IurVp9Q43pK WrTw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:message-id:date:subject:cc:to:from:arc-filter :dmarc-filter:delivered-to; bh=033qtkQEIbo8S+DTJpiNup+BdOasScYWEXtHN7vd808=; fh=x5gxLd9wvo785cZPveRPDhh/P9PrW2TV3/a5uvbVtCk=; b=WnYtlpVYSK3wSEz6w+SjiDgwWuvvGj2ZNccJIvQmqAmss5aFIDZ2LNppvEuKtva7Xb UHNR701QYUZU08ucW6YEh7bEDYLUGOFQ8U43zb1mQjOT+IegqU8cBbiLadfW0GZvNiEC VZ3geIdhfu3gG61qVqKzafG16if4VFNY/qxuSyvnk19U93BylBb88QhbkBCGqRrry1SG wdhBvlI8CAA4O8rfopgVN9TAYazXZocRmYxYwybTIVUAvQbNh9+fyOu/+YzyS4IPFicl x7nD5BtpByFbu1mGlVjzbbgv9QPdiOyl1ro1E+nQGPNLwQqMJCnA5k1SjBSp+lEVtJ5T kmOA== ARC-Authentication-Results: i=2; mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=alibaba.com Received: from server2.sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id c21-20020ac87d95000000b004195e83ec9esi4018198qtd.325.2023.11.09.23.15.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Nov 2023 23:15:15 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=alibaba.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 646C73857359 for ; Fri, 10 Nov 2023 07:15:15 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from out30-132.freemail.mail.aliyun.com (out30-132.freemail.mail.aliyun.com [115.124.30.132]) by sourceware.org (Postfix) with ESMTPS id AA7DF3858D38 for ; Fri, 10 Nov 2023 07:14:49 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org AA7DF3858D38 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=linux.alibaba.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=linux.alibaba.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org AA7DF3858D38 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=115.124.30.132 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699600492; cv=none; b=JAYEsp2ZXh9yiEnk+Ao+GQTEAC0FJR6np3psXwjXRdU1FXtYs9/UBIFyEL4cU/5FwXZmQL6aq5BYyFiU72jvL3XLRkChjwE1XWAEyH++PobOk8sS0nQrGgo8pw6i7d9BCUMakKo3wZkOpOkqZhj6Vasg0u/E0jEg1PQ6BerV/5I= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699600492; c=relaxed/simple; bh=EUD1r5KZUzb2hV+VmoiGk2tE+r7tqkElrWaE74kvvI8=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=v3gPs8oxgZDlFcDTaIsCVGCnRzVh4K9HwvN0sRjnfAQ8zlj/Rq4yheWIhY9yADOAfmYbB1eye2uC173G+rr+KSyL6Y4293UXJPeuG6OcCOXmAl4Rp2sx4mzj6e3HoEgxyVYRlC51wi3tjTaEDLNwyLH6oH8lSJgRI8LGb+unt9M= ARC-Authentication-Results: i=1; server2.sourceware.org X-Alimail-AntiSpam: AC=PASS; BC=-1|-1; BR=01201311R111e4; CH=green; DM=||false|; DS=||; FP=0|-1|-1|-1|0|-1|-1|-1; HT=ay29a033018046059; MF=jinma@linux.alibaba.com; NM=1; PH=DS; RN=4; SR=0; TI=SMTPD_---0Vw3j7uU_1699600479; Received: from localhost.localdomain(mailfrom:jinma@linux.alibaba.com fp:SMTPD_---0Vw3j7uU_1699600479) by smtp.aliyun-inc.com; Fri, 10 Nov 2023 15:14:42 +0800 From: Jin Ma To: gcc-patches@gcc.gnu.org Cc: christoph.muellner@vrull.eu, jinma.contrib@gmail.com, Jin Ma Subject: [PATCH] RISC-V: Fix bug that XTheadMemPair extension caused fcsr not to be saved and restored before and after interrupt. Date: Fri, 10 Nov 2023 15:14:31 +0800 Message-Id: <20231110071431.1580-1-jinma@linux.alibaba.com> X-Mailer: git-send-email 2.21.0 MIME-Version: 1.0 X-Spam-Status: No, score=-19.2 required=5.0 tests=BAYES_00, ENV_AND_HDR_SPF_MATCH, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, LIKELY_SPAM_BODY, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY, USER_IN_DEF_SPF_WL autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782160310251323455 X-GMAIL-MSGID: 1782160310251323455 The t0 register is used as a temporary register for interrupts, so it needs special treatment. It is necessary to avoid using "th.ldd" in the interrupt program to stop the subsequent operation of the t0 register, so they need to exchange positions in the function "riscv_for_each_saved_reg". gcc/ChangeLog: * config/riscv/riscv.cc (riscv_for_each_saved_reg): Place the interrupt operation before the XTheadMemPair. Reviewed-by: Christoph Müllner --- gcc/config/riscv/riscv.cc | 56 +++++++++---------- .../riscv/xtheadmempair-interrupt-fcsr.c | 18 ++++++ 2 files changed, 46 insertions(+), 28 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/xtheadmempair-interrupt-fcsr.c base-commit: e7f4040d9d6ec40c48ada940168885d7dde03af9 diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index e25692b86fc..fa2d4d4b779 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -6346,6 +6346,34 @@ riscv_for_each_saved_reg (poly_int64 sp_offset, riscv_save_restore_fn fn, && riscv_is_eh_return_data_register (regno)) continue; + /* In an interrupt function, save and restore some necessary CSRs in the stack + to avoid changes in CSRs. */ + if (regno == RISCV_PROLOGUE_TEMP_REGNUM + && cfun->machine->interrupt_handler_p + && ((TARGET_HARD_FLOAT && cfun->machine->frame.fmask) + || (TARGET_ZFINX + && (cfun->machine->frame.mask & ~(1 << RISCV_PROLOGUE_TEMP_REGNUM))))) + { + unsigned int fcsr_size = GET_MODE_SIZE (SImode); + if (!epilogue) + { + riscv_save_restore_reg (word_mode, regno, offset, fn); + offset -= fcsr_size; + emit_insn (gen_riscv_frcsr (RISCV_PROLOGUE_TEMP (SImode))); + riscv_save_restore_reg (SImode, RISCV_PROLOGUE_TEMP_REGNUM, + offset, riscv_save_reg); + } + else + { + riscv_save_restore_reg (SImode, RISCV_PROLOGUE_TEMP_REGNUM, + offset - fcsr_size, riscv_restore_reg); + emit_insn (gen_riscv_fscsr (RISCV_PROLOGUE_TEMP (SImode))); + riscv_save_restore_reg (word_mode, regno, offset, fn); + offset -= fcsr_size; + } + continue; + } + if (TARGET_XTHEADMEMPAIR) { /* Get the next reg/offset pair. */ @@ -6376,34 +6404,6 @@ riscv_for_each_saved_reg (poly_int64 sp_offset, riscv_save_restore_fn fn, } } - /* In an interrupt function, save and restore some necessary CSRs in the stack - to avoid changes in CSRs. */ - if (regno == RISCV_PROLOGUE_TEMP_REGNUM - && cfun->machine->interrupt_handler_p - && ((TARGET_HARD_FLOAT && cfun->machine->frame.fmask) - || (TARGET_ZFINX - && (cfun->machine->frame.mask & ~(1 << RISCV_PROLOGUE_TEMP_REGNUM))))) - { - unsigned int fcsr_size = GET_MODE_SIZE (SImode); - if (!epilogue) - { - riscv_save_restore_reg (word_mode, regno, offset, fn); - offset -= fcsr_size; - emit_insn (gen_riscv_frcsr (RISCV_PROLOGUE_TEMP (SImode))); - riscv_save_restore_reg (SImode, RISCV_PROLOGUE_TEMP_REGNUM, - offset, riscv_save_reg); - } - else - { - riscv_save_restore_reg (SImode, RISCV_PROLOGUE_TEMP_REGNUM, - offset - fcsr_size, riscv_restore_reg); - emit_insn (gen_riscv_fscsr (RISCV_PROLOGUE_TEMP (SImode))); - riscv_save_restore_reg (word_mode, regno, offset, fn); - offset -= fcsr_size; - } - continue; - } - riscv_save_restore_reg (word_mode, regno, offset, fn); } diff --git a/gcc/testsuite/gcc.target/riscv/xtheadmempair-interrupt-fcsr.c b/gcc/testsuite/gcc.target/riscv/xtheadmempair-interrupt-fcsr.c new file mode 100644 index 00000000000..d06f05f5c7c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xtheadmempair-interrupt-fcsr.c @@ -0,0 +1,18 @@ +/* Verify that fcsr instructions emitted. */ +/* { dg-do compile } */ +/* { dg-require-effective-target hard_float } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-g" "-Oz" "-Os" "-flto" } } */ +/* { dg-options "-march=rv64gc_xtheadmempair -mtune=thead-c906 -funwind-tables" { target { rv64 } } } */ +/* { dg-options "-march=rv32gc_xtheadmempair -mtune=thead-c906 -funwind-tables" { target { rv32 } } } */ + + +extern int foo (void); + +void __attribute__ ((interrupt)) +sub (void) +{ + foo (); +} + +/* { dg-final { scan-assembler-times "frcsr\t" 1 } } */ +/* { dg-final { scan-assembler-times "fscsr\t" 1 } } */