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[8.43.85.97]) by mx.google.com with ESMTPS id k7-20020a0cfa47000000b00670c7fd09dfsi3752950qvo.279.2023.11.09.17.52.32 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Nov 2023 17:52:32 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=EivlnNWW; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 261FD385828D for ; Fri, 10 Nov 2023 01:52:32 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.136]) by sourceware.org (Postfix) with ESMTPS id 10D653858D38 for ; Fri, 10 Nov 2023 01:52:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 10D653858D38 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 10D653858D38 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.55.52.136 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699581128; cv=none; b=wOT5ELPmBScqODGVHu779jQDQL++2687dnNqhQsM3ngLmcBGEM5M4D5Ya4Y89uKUueIvDoojaaSKKv0qkDCs3gUK3ajrSUvaatbo206B/gmnBc4oUVkWaLV5G6dJOJ46bT82mPOXPf5E9dW+kAQQEuHWgCzfAaDcDnPkHO9s71o= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699581128; c=relaxed/simple; bh=Z3rsihp7HsdyO0slSjnyeX9C/OGlnH6bsSoqycNUAF0=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=LXQ1FzWhZfDwldAlnmNCAASDiQdkmVIk7I8Bh/MyjSvAFmj6RUffKG+x8FhigtFnB4vUju8MC2gPxKXx4L4hn9dkYlYlfjPxfVPuq0nzOGsnz41dw0f3OxxM7AwaSgjHksh/P/ICv0sm9S95HTagn37+B5lSnX3bRedejMXQ2WM= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1699581127; x=1731117127; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=Z3rsihp7HsdyO0slSjnyeX9C/OGlnH6bsSoqycNUAF0=; b=EivlnNWWLe7dbsUDPJ+HtJI5sYvGEh80MgmsuI5tEIpbpYzN948NJZK+ UboMcBzcygG43WH5s+EH7mNJPmKQjffVUFjTwL1DZBlowMQS6OgXlsclK +bOcBO0hsybhnVDp2E9AXJIMLWppW4dumvhvMKpgjshTFDwgY+KEadQO2 txaIHcUB2T/QAguIu9BY2UusE+ZldXGWzlDvboaY3DggkNhyjPhTF3N/k GT5NmUQMx3KqO2XvSfDJUp3RHk0H0b9oA14n4vjHrE4PMBMIl1P+zs242 BqK0vufjeLvLc3bRNdiV9xnRp6yvK7RWicZK1+gHbIHFgsTymEQqIOCtd Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10889"; a="369447362" X-IronPort-AV: E=Sophos;i="6.03,291,1694761200"; d="scan'208";a="369447362" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Nov 2023 17:52:05 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.03,291,1694761200"; d="scan'208";a="4717993" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orviesa002.jf.intel.com with ESMTP; 09 Nov 2023 17:52:03 -0800 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 4D6CF10056EF; Fri, 10 Nov 2023 09:52:02 +0800 (CST) From: liuhongt To: gcc-patches@gcc.gnu.org Cc: crazylht@gmail.com, hjl.tools@gmail.com Subject: [PATCH] Simplify vector ((VCE?(a cmp b ? -1 : 0)) < 0) ? c : d to just (VCE:a cmp VCE:b) ? c : d. Date: Fri, 10 Nov 2023 09:52:02 +0800 Message-Id: <20231110015202.650942-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782140006544951992 X-GMAIL-MSGID: 1782140006544951992 When I'm working on PR112443, I notice there's some misoptimizations: after we fold _mm{,256}_blendv_epi8/pd/ps into gimple, the backend fails to combine it back to v{,p}blendv{v,ps,pd} since the pattern is too complicated, so I think maybe we should hanlde it in the gimple level. The dump is like _1 = c_3(D) >= { 0, 0, 0, 0 }; _2 = VEC_COND_EXPR <_1, { -1, -1, -1, -1 }, { 0, 0, 0, 0 }>; _7 = VIEW_CONVERT_EXPR(_2); _8 = VIEW_CONVERT_EXPR(b_6(D)); _9 = VIEW_CONVERT_EXPR(a_5(D)); _10 = _7 < { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; _11 = VEC_COND_EXPR <_10, _8, _9>; It can be optimized to _6 = VIEW_CONVERT_EXPR(b_4(D)); _7 = VIEW_CONVERT_EXPR(a_3(D)); _10 = VIEW_CONVERT_EXPR(c_1(D)); _5 = _10 >= { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; _8 = VEC_COND_EXPR <_5, _6, _7>; _9 = VIEW_CONVERT_EXPR<__m256i>(_8); since _7 is either -1 or 0, _7 < 0 should is euqal to _1 = c_3(D) > { 0, 0, 0, 0 }; The patch add a gimple pattern to handle that. Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,} Ok for trunk? gcc/ChangeLog: * match.pd (VCE:(a cmp b ? -1 : 0) < 0) ? c : d ---> (VCE:a cmp VCE:b) ? c : d): New gimple simplication. gcc/testsuite/ChangeLog: * gcc.target/i386/avx512vl-blendv-3.c: New test. * gcc.target/i386/blendv-3.c: New test. --- gcc/match.pd | 17 +++++++ .../gcc.target/i386/avx512vl-blendv-3.c | 6 +++ gcc/testsuite/gcc.target/i386/blendv-3.c | 46 +++++++++++++++++++ 3 files changed, 69 insertions(+) create mode 100644 gcc/testsuite/gcc.target/i386/avx512vl-blendv-3.c create mode 100644 gcc/testsuite/gcc.target/i386/blendv-3.c diff --git a/gcc/match.pd b/gcc/match.pd index dbc811b2b38..e6f9c4fa1fd 100644 --- a/gcc/match.pd +++ b/gcc/match.pd @@ -5170,6 +5170,23 @@ DEFINE_INT_AND_FLOAT_ROUND_FN (RINT) (if (optimize_vectors_before_lowering_p () && types_match (@0, @3)) (vec_cond (bit_and @0 (bit_not @3)) @2 @1))) +(for cmp (simple_comparison) + (simplify + (vec_cond + (lt@4 (view_convert?@5 (vec_cond (cmp @0 @1) + integer_all_onesp + integer_zerop)) + integer_zerop) @2 @3) + (if (VECTOR_INTEGER_TYPE_P (TREE_TYPE (@0)) + && VECTOR_INTEGER_TYPE_P (TREE_TYPE (@5)) + && TYPE_SIGN (TREE_TYPE (@0)) == TYPE_SIGN (TREE_TYPE (@5)) + && VECTOR_TYPE_P (type)) + (with { + tree itype = TREE_TYPE (@5); + tree vbtype = TREE_TYPE (@4);} + (vec_cond (cmp:vbtype (view_convert:itype @0) + (view_convert:itype @1)) @2 @3))))) + /* c1 ? c2 ? a : b : b --> (c1 & c2) ? a : b */ (simplify (vec_cond @0 (vec_cond:s @1 @2 @3) @3) diff --git a/gcc/testsuite/gcc.target/i386/avx512vl-blendv-3.c b/gcc/testsuite/gcc.target/i386/avx512vl-blendv-3.c new file mode 100644 index 00000000000..2777e72ab5f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512vl-blendv-3.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512vl -mavx512bw -O2" } */ +/* { dg-final { scan-assembler-times {vp?blendv(?:b|p[sd])[ \t]*} 6 } } */ +/* { dg-final { scan-assembler-not {vpcmp} } } */ + +#include "blendv-3.c" diff --git a/gcc/testsuite/gcc.target/i386/blendv-3.c b/gcc/testsuite/gcc.target/i386/blendv-3.c new file mode 100644 index 00000000000..fa0fb067a73 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/blendv-3.c @@ -0,0 +1,46 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -O2" } */ +/* { dg-final { scan-assembler-times {vp?blendv(?:b|p[sd])[ \t]*} 6 } } */ +/* { dg-final { scan-assembler-not {vpcmp} } } */ + +#include + +__m256i +foo (__m256i a, __m256i b, __m256i c) +{ + return _mm256_blendv_epi8 (a, b, ~c < 0); +} + +__m256d +foo1 (__m256d a, __m256d b, __m256i c) +{ + __m256i d = ~c < 0; + return _mm256_blendv_pd (a, b, (__m256d)d); +} + +__m256 +foo2 (__m256 a, __m256 b, __m256i c) +{ + __m256i d = ~c < 0; + return _mm256_blendv_ps (a, b, (__m256)d); +} + +__m128i +foo4 (__m128i a, __m128i b, __m128i c) +{ + return _mm_blendv_epi8 (a, b, ~c < 0); +} + +__m128d +foo5 (__m128d a, __m128d b, __m128i c) +{ + __m128i d = ~c < 0; + return _mm_blendv_pd (a, b, (__m128d)d); +} + +__m128 +foo6 (__m128 a, __m128 b, __m128i c) +{ + __m128i d = ~c < 0; + return _mm_blendv_ps (a, b, (__m128)d); +}