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[8.43.85.97]) by mx.google.com with ESMTPS id qd11-20020ad4480b000000b0066d121fdf87si3779053qvb.206.2023.11.09.17.42.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Nov 2023 17:42:47 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=I57YUKwy; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0C9883857806 for ; Fri, 10 Nov 2023 01:42:47 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.151]) by sourceware.org (Postfix) with ESMTPS id D34D73858C39 for ; Fri, 10 Nov 2023 01:42:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D34D73858C39 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org D34D73858C39 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.55.52.151 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699580542; cv=none; b=qKxbP4yQA/Zo9S8iXpFxH7Bk4rwBW3iBqAE9yDR7oxNHro00DRVGPa81HgELPz0r0X6NJrrKWfqDAlf7bkK+yqmGUeqny6ZSu9zcnAEPdpzi3YHYOgx42uJ9KbFm/Qyrux5I75BYBaiis0hhB8NFKjHgnIKR851btg21kAz0oiE= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699580542; c=relaxed/simple; bh=eugZSfwr/Vgw1UMg41QaVLPQRXFltAtdgRzEP65WQ7s=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=l4NZwFVlVwtlWruO37KalSYpoacHNjgflAhwLcwgHx0ilVZ7Z5WV0nG+yI+lIjVzcvuDG/+RHvxIFf3bU4lQ5B6ConCi5vcQDz3OzhSsXphQBI3hrQieBo2ByMyPXr+ftIV17I9zWY0Wq97cee1Y8JqRMZZuQ6N0JbaPpXOMico= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1699580535; x=1731116535; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=eugZSfwr/Vgw1UMg41QaVLPQRXFltAtdgRzEP65WQ7s=; b=I57YUKwyown3ZoH2S5QHHuDhO3hihPD3JklaFQyeE0iN63FlA7P60whZ ZI7DRsng4Crdu3AUbczYdjiLYWnJUzZ7EM1/anMdYLeQILbixy+Q4an0R 3iDVKsVPEExcyTxCIexbPh4RrdWGkbWgqXvJYi3OIW83nDd2SY5nimo6k TTFbwR0gCte/fPpkzZ5QzkMOpC5KrwhTw+ycFcT3eWFU0R7QI1QGQO8wt UtySB5LlBqcn7+DVkObiBIMjIEJvDdZf1jX1PL1Xf8xkgtK3diClGyrmo ZRa7DVADHb1ahLEzbo5NUUurvKlDDVujqjQEDRzVVGyy2i+u0xlh4fSx/ g==; X-IronPort-AV: E=McAfee;i="6600,9927,10889"; a="370320510" X-IronPort-AV: E=Sophos;i="6.03,291,1694761200"; d="scan'208";a="370320510" Received: from fmviesa002.fm.intel.com ([10.60.135.142]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Nov 2023 17:42:14 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.03,291,1694761200"; d="scan'208";a="4895944" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmviesa002.fm.intel.com with ESMTP; 09 Nov 2023 17:42:01 -0800 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 7746110056F5; Fri, 10 Nov 2023 09:42:00 +0800 (CST) From: Haochen Jiang To: gcc-patches@gcc.gnu.org Cc: hongtao.liu@intel.com, ubizjak@gmail.com Subject: [PATCH] Initial support for AVX10.1 Date: Fri, 10 Nov 2023 09:41:58 +0800 Message-Id: <20231110014158.371690-2-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20231110014158.371690-1-haochen.jiang@intel.com> References: <20231110014158.371690-1-haochen.jiang@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-10.4 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_NUMSUBJECT, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782139393050077230 X-GMAIL-MSGID: 1782139393050077230 gcc/ChangeLog: * common/config/i386/cpuinfo.h (get_available_features): Add avx10_set and version and detect avx10.1. (cpu_indicator_init): Handle avx10.1-512. * common/config/i386/i386-common.cc (OPTION_MASK_ISA2_AVX10_1_256_SET): New. (OPTION_MASK_ISA2_AVX10_1_256_SET): Ditto. (OPTION_MASK_ISA2_AVX10_1_512_UNSET): Ditto. (OPTION_MASK_ISA2_AVX10_1_512_UNSET): Ditto. (OPTION_MASK_ISA2_AVX2_UNSET): Modify for AVX10.1. (ix86_handle_option): Handle -mavx10.1-256 and -mavx10.1-512. Add indicator for explicit no-avx512 and no-avx10.1 options. * common/config/i386/i386-cpuinfo.h (enum processor_features): Add FEATURE_AVX10_1_256 and FEATURE_AVX10_1_512. * common/config/i386/i386-isas.h: Add ISA_NAME_TABLE_ENTRY for AVX10_1_256 and AVX10_1_512. * config/i386/cpuid.h (bit_AVX10): New. (bit_AVX10_256): Ditto. (bit_AVX10_512): Ditto. * config/i386/driver-i386.cc (check_avx10_avx512_features): New. (host_detect_local_cpu): Do not append "-mno-" options under specific scenarios to avoid emitting a warning. * config/i386/i386-isa.def (EVEX512): Add DEF_PTA(EVEX512). (AVX10_1_256): Add DEF_PTA(AVX10_1_256). (AVX10_1_512): Add DEF_PTA(AVX10_1_512). * config/i386/i386-options.cc (isa2_opts): Add -mavx10.1-256 and -mavx10.1-512. (ix86_function_specific_save): Save explicit no indicator. (ix86_function_specific_restore): Restore explicit no indicator. (ix86_valid_target_attribute_inner_p): Handle avx10.1, avx10.1-256 and avx10.1-512. (ix86_valid_target_attribute_tree): Handle avx512 function attributes with avx10.1 command line option. (ix86_option_override_internal): Handle AVX10.1 options. * config/i386/i386.h: Add PTA_EVEX512 for AVX512 target machines. * config/i386/i386.opt: Add variable ix86_no_avx512_explicit and ix86_no_avx10_1_explicit, option -mavx10.1, -mavx10.1-256 and -mavx10.1-512. * doc/extend.texi: Document avx10.1, avx10.1-256 and avx10.1-512. * doc/invoke.texi: Document -mavx10.1, -mavx10.1-256 and -mavx10.1-512. * doc/sourcebuild.texi: Document target avx10.1, avx10.1-256 and avx10.1-512. gcc/testsuite/ChangeLog: * gcc.target/i386/avx10_1-1.c: New test. * gcc.target/i386/avx10_1-10.c: Ditto. * gcc.target/i386/avx10_1-11.c: Ditto. * gcc.target/i386/avx10_1-12.c: Ditto. * gcc.target/i386/avx10_1-13.c: Ditto. * gcc.target/i386/avx10_1-14.c: Ditto. * gcc.target/i386/avx10_1-15.c: Ditto. * gcc.target/i386/avx10_1-16.c: Ditto. * gcc.target/i386/avx10_1-17.c: Ditto. * gcc.target/i386/avx10_1-18.c: Ditto. * gcc.target/i386/avx10_1-19.c: Ditto. * gcc.target/i386/avx10_1-2.c: Ditto. * gcc.target/i386/avx10_1-20.c: Ditto. * gcc.target/i386/avx10_1-21.c: Ditto. * gcc.target/i386/avx10_1-22.c: Ditto. * gcc.target/i386/avx10_1-23.c: Ditto. * gcc.target/i386/avx10_1-3.c: Ditto. * gcc.target/i386/avx10_1-4.c: Ditto. * gcc.target/i386/avx10_1-5.c: Ditto. * gcc.target/i386/avx10_1-6.c: Ditto. * gcc.target/i386/avx10_1-7.c: Ditto. * gcc.target/i386/avx10_1-8.c: Ditto. * gcc.target/i386/avx10_1-9.c: Ditto. --- gcc/common/config/i386/cpuinfo.h | 33 ++++++ gcc/common/config/i386/i386-common.cc | 55 ++++++++- gcc/common/config/i386/i386-cpuinfo.h | 2 + gcc/common/config/i386/i386-isas.h | 3 + gcc/config/i386/cpuid.h | 5 + gcc/config/i386/driver-i386.cc | 43 ++++++- gcc/config/i386/i386-isa.def | 3 + gcc/config/i386/i386-options.cc | 132 +++++++++++++++++++-- gcc/config/i386/i386.h | 2 +- gcc/config/i386/i386.opt | 30 +++++ gcc/doc/extend.texi | 15 +++ gcc/doc/invoke.texi | 17 ++- gcc/doc/sourcebuild.texi | 9 ++ gcc/testsuite/gcc.target/i386/avx10_1-1.c | 22 ++++ gcc/testsuite/gcc.target/i386/avx10_1-10.c | 6 + gcc/testsuite/gcc.target/i386/avx10_1-11.c | 6 + gcc/testsuite/gcc.target/i386/avx10_1-12.c | 6 + gcc/testsuite/gcc.target/i386/avx10_1-13.c | 13 ++ gcc/testsuite/gcc.target/i386/avx10_1-14.c | 13 ++ gcc/testsuite/gcc.target/i386/avx10_1-15.c | 13 ++ gcc/testsuite/gcc.target/i386/avx10_1-16.c | 13 ++ gcc/testsuite/gcc.target/i386/avx10_1-17.c | 13 ++ gcc/testsuite/gcc.target/i386/avx10_1-18.c | 13 ++ gcc/testsuite/gcc.target/i386/avx10_1-19.c | 13 ++ gcc/testsuite/gcc.target/i386/avx10_1-2.c | 13 ++ gcc/testsuite/gcc.target/i386/avx10_1-20.c | 13 ++ gcc/testsuite/gcc.target/i386/avx10_1-21.c | 6 + gcc/testsuite/gcc.target/i386/avx10_1-22.c | 13 ++ gcc/testsuite/gcc.target/i386/avx10_1-23.c | 13 ++ gcc/testsuite/gcc.target/i386/avx10_1-3.c | 13 ++ gcc/testsuite/gcc.target/i386/avx10_1-4.c | 13 ++ gcc/testsuite/gcc.target/i386/avx10_1-5.c | 5 + gcc/testsuite/gcc.target/i386/avx10_1-6.c | 13 ++ gcc/testsuite/gcc.target/i386/avx10_1-7.c | 5 + gcc/testsuite/gcc.target/i386/avx10_1-8.c | 4 + gcc/testsuite/gcc.target/i386/avx10_1-9.c | 6 + 36 files changed, 579 insertions(+), 18 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-1.c create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-10.c create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-11.c create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-12.c create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-13.c create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-14.c create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-15.c create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-16.c create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-17.c create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-18.c create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-19.c create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-2.c create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-20.c create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-21.c create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-22.c create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-23.c create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-3.c create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-4.c create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-5.c create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-6.c create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-7.c create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-8.c create mode 100644 gcc/testsuite/gcc.target/i386/avx10_1-9.c diff --git a/gcc/common/config/i386/cpuinfo.h b/gcc/common/config/i386/cpuinfo.h index 7d25479eb89..f90fb4d56a2 100644 --- a/gcc/common/config/i386/cpuinfo.h +++ b/gcc/common/config/i386/cpuinfo.h @@ -715,6 +715,9 @@ get_available_features (struct __processor_model *cpu_model, int apx_usable = 0; /* Check if KL is usable. */ int has_kl = 0; + /* Record AVX10 version. */ + int avx10_set = 0; + int version = 0; if ((ecx & bit_OSXSAVE)) { /* Check if XMM, YMM, OPMASK, upper 256 bits of ZMM0-ZMM15 and @@ -941,6 +944,9 @@ get_available_features (struct __processor_model *cpu_model, { if (eax & bit_AVX512BF16) set_feature (FEATURE_AVX512BF16); + /* AVX10 has the same XSTATE with AVX512. */ + if (edx & bit_AVX10) + avx10_set = 1; } if (amx_usable) { @@ -992,6 +998,33 @@ get_available_features (struct __processor_model *cpu_model, } } + /* Get Advanced Features at level 0x24 (eax = 0x24). */ + if (avx10_set && max_cpuid_level >= 0x24) + { + __cpuid (0x24, eax, ebx, ecx, edx); + version = ebx & 0xff; + if (ebx & bit_AVX10_256) + switch (version) + { + case 1: + set_feature (FEATURE_AVX10_1_256); + break; + default: + set_feature (FEATURE_AVX10_1_256); + break; + } + if (ebx & bit_AVX10_512) + switch (version) + { + case 1: + set_feature (FEATURE_AVX10_1_512); + break; + default: + set_feature (FEATURE_AVX10_1_512); + break; + } + } + /* Check cpuid level of extended features. */ __cpuid (0x80000000, ext_level, ebx, ecx, edx); diff --git a/gcc/common/config/i386/i386-common.cc b/gcc/common/config/i386/i386-common.cc index 1b09499cd26..f101e4dd461 100644 --- a/gcc/common/config/i386/i386-common.cc +++ b/gcc/common/config/i386/i386-common.cc @@ -126,6 +126,9 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA2_APX_F_SET OPTION_MASK_ISA2_APX_F #define OPTION_MASK_ISA2_EVEX512_SET OPTION_MASK_ISA2_EVEX512 #define OPTION_MASK_ISA2_USER_MSR_SET OPTION_MASK_ISA2_USER_MSR +#define OPTION_MASK_ISA2_AVX10_1_256_SET OPTION_MASK_ISA2_AVX10_1_256 +#define OPTION_MASK_ISA2_AVX10_1_512_SET \ + (OPTION_MASK_ISA2_AVX10_1_256_SET | OPTION_MASK_ISA2_AVX10_1_512) /* SSE4 includes both SSE4.1 and SSE4.2. -msse4 should be the same as -msse4.2. */ @@ -235,7 +238,8 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA2_AVX2_UNSET \ (OPTION_MASK_ISA2_AVXIFMA_UNSET | OPTION_MASK_ISA2_AVXVNNI_UNSET \ | OPTION_MASK_ISA2_AVXVNNIINT8_UNSET | OPTION_MASK_ISA2_AVXNECONVERT_UNSET \ - | OPTION_MASK_ISA2_AVXVNNIINT16_UNSET | OPTION_MASK_ISA2_AVX512F_UNSET) + | OPTION_MASK_ISA2_AVXVNNIINT16_UNSET | OPTION_MASK_ISA2_AVX512F_UNSET \ + | OPTION_MASK_ISA2_AVX10_1_256_UNSET) #define OPTION_MASK_ISA_AVX512F_UNSET \ (OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD_UNSET \ | OPTION_MASK_ISA_AVX512PF_UNSET | OPTION_MASK_ISA_AVX512ER_UNSET \ @@ -315,6 +319,9 @@ along with GCC; see the file COPYING3. If not see #define OPTION_MASK_ISA2_APX_F_UNSET OPTION_MASK_ISA2_APX_F #define OPTION_MASK_ISA2_EVEX512_UNSET OPTION_MASK_ISA2_EVEX512 #define OPTION_MASK_ISA2_USER_MSR_UNSET OPTION_MASK_ISA2_USER_MSR +#define OPTION_MASK_ISA2_AVX10_1_256_UNSET \ + (OPTION_MASK_ISA2_AVX10_1_256 | OPTION_MASK_ISA2_AVX10_1_512_UNSET) +#define OPTION_MASK_ISA2_AVX10_1_512_UNSET OPTION_MASK_ISA2_AVX10_1_512 /* SSE4 includes both SSE4.1 and SSE4.2. -mno-sse4 should the same as -mno-sse4.1. */ @@ -616,6 +623,7 @@ ix86_handle_option (struct gcc_options *opts, opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512F_UNSET; opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512F_UNSET; opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512F_UNSET; + opts->x_ix86_no_avx512_explicit = 1; } return true; @@ -629,6 +637,7 @@ ix86_handle_option (struct gcc_options *opts, { opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512CD_UNSET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512CD_UNSET; + opts->x_ix86_no_avx512_explicit = 1; } return true; @@ -903,6 +912,7 @@ ix86_handle_option (struct gcc_options *opts, { opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI2_UNSET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI2_UNSET; + opts->x_ix86_no_avx512_explicit = 1; } return true; @@ -918,6 +928,7 @@ ix86_handle_option (struct gcc_options *opts, { opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512FP16_UNSET; opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512FP16_UNSET; + opts->x_ix86_no_avx512_explicit = 1; } return true; @@ -931,6 +942,7 @@ ix86_handle_option (struct gcc_options *opts, { opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VNNI_UNSET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VNNI_UNSET; + opts->x_ix86_no_avx512_explicit = 1; } return true; @@ -946,6 +958,7 @@ ix86_handle_option (struct gcc_options *opts, opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VPOPCNTDQ_UNSET; + opts->x_ix86_no_avx512_explicit = 1; } return true; @@ -960,6 +973,7 @@ ix86_handle_option (struct gcc_options *opts, opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512BITALG_UNSET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BITALG_UNSET; + opts->x_ix86_no_avx512_explicit = 1; } return true; @@ -975,6 +989,7 @@ ix86_handle_option (struct gcc_options *opts, { opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BF16_UNSET; opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BF16_UNSET; + opts->x_ix86_no_avx512_explicit = 1; } return true; @@ -1042,6 +1057,7 @@ ix86_handle_option (struct gcc_options *opts, { opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512DQ_UNSET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512DQ_UNSET; + opts->x_ix86_no_avx512_explicit = 1; } return true; @@ -1057,6 +1073,7 @@ ix86_handle_option (struct gcc_options *opts, opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512BW_UNSET; opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX512BW_UNSET; opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX512BW_UNSET; + opts->x_ix86_no_avx512_explicit = 1; } return true; @@ -1070,6 +1087,7 @@ ix86_handle_option (struct gcc_options *opts, { opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VL_UNSET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VL_UNSET; + opts->x_ix86_no_avx512_explicit = 1; } return true; @@ -1083,6 +1101,7 @@ ix86_handle_option (struct gcc_options *opts, { opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512IFMA_UNSET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512IFMA_UNSET; + opts->x_ix86_no_avx512_explicit = 1; } return true; @@ -1096,6 +1115,7 @@ ix86_handle_option (struct gcc_options *opts, { opts->x_ix86_isa_flags &= ~OPTION_MASK_ISA_AVX512VBMI_UNSET; opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX512VBMI_UNSET; + opts->x_ix86_no_avx512_explicit = 1; } return true; @@ -1372,6 +1392,7 @@ ix86_handle_option (struct gcc_options *opts, { opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_EVEX512_UNSET; opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_EVEX512_UNSET; + opts->x_ix86_no_avx512_explicit = 1; } return true; @@ -1388,6 +1409,38 @@ ix86_handle_option (struct gcc_options *opts, } return true; + case OPT_mavx10_1_256: + if (value) + { + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_1_256_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_256_SET; + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET; + opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET; + } + else + { + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_1_256_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_256_UNSET; + opts->x_ix86_no_avx10_1_explicit = 1; + } + return true; + + case OPT_mavx10_1_512: + if (value) + { + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_AVX10_1_512_SET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_512_SET; + opts->x_ix86_isa_flags |= OPTION_MASK_ISA_AVX2_SET; + opts->x_ix86_isa_flags_explicit |= OPTION_MASK_ISA_AVX2_SET; + } + else + { + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_AVX10_1_512_UNSET; + opts->x_ix86_isa_flags2_explicit |= OPTION_MASK_ISA2_AVX10_1_512_UNSET; + opts->x_ix86_no_avx10_1_explicit = 1; + } + return true; + case OPT_mfma: if (value) { diff --git a/gcc/common/config/i386/i386-cpuinfo.h b/gcc/common/config/i386/i386-cpuinfo.h index a0552ef99a2..38fa7650de2 100644 --- a/gcc/common/config/i386/i386-cpuinfo.h +++ b/gcc/common/config/i386/i386-cpuinfo.h @@ -266,6 +266,8 @@ enum processor_features FEATURE_SM4, FEATURE_APX_F, FEATURE_USER_MSR, + FEATURE_AVX10_1_256, + FEATURE_AVX10_1_512, CPU_FEATURE_MAX }; diff --git a/gcc/common/config/i386/i386-isas.h b/gcc/common/config/i386/i386-isas.h index 6875924994d..a7b7c52394e 100644 --- a/gcc/common/config/i386/i386-isas.h +++ b/gcc/common/config/i386/i386-isas.h @@ -193,4 +193,7 @@ ISA_NAMES_TABLE_START ISA_NAMES_TABLE_ENTRY("sm4", FEATURE_SM4, P_NONE, "-msm4") ISA_NAMES_TABLE_ENTRY("apxf", FEATURE_APX_F, P_NONE, "-mapxf") ISA_NAMES_TABLE_ENTRY("usermsr", FEATURE_USER_MSR, P_NONE, "-musermsr") + ISA_NAMES_TABLE_ENTRY("avx10.1", FEATURE_AVX10_1_256, P_NONE, "-mavx10.1") + ISA_NAMES_TABLE_ENTRY("avx10.1-256", FEATURE_AVX10_1_256, P_NONE, "-mavx10.1-256") + ISA_NAMES_TABLE_ENTRY("avx10.1-512", FEATURE_AVX10_1_512, P_NONE, "-mavx10.1-512") ISA_NAMES_TABLE_END diff --git a/gcc/config/i386/cpuid.h b/gcc/config/i386/cpuid.h index 75ef2718204..d1fc93ec91e 100644 --- a/gcc/config/i386/cpuid.h +++ b/gcc/config/i386/cpuid.h @@ -150,6 +150,7 @@ #define bit_AVXVNNIINT16 (1 << 10) #define bit_PREFETCHI (1 << 14) #define bit_USER_MSR (1 << 15) +#define bit_AVX10 (1 << 19) #define bit_APX_F (1 << 21) /* Extended State Enumeration Sub-leaf (%eax == 0xd, %ecx == 1) */ @@ -166,6 +167,10 @@ #define bit_AESKLE ( 1<<0 ) #define bit_WIDEKL ( 1<<2 ) +/* AVX10 sub leaf (%eax == 0x24) */ +/* %ebx */ +#define bit_AVX10_256 (1 << 17) +#define bit_AVX10_512 (1 << 18) /* Signatures for different CPU implementations as returned in uses of cpuid with level 0. */ diff --git a/gcc/config/i386/driver-i386.cc b/gcc/config/i386/driver-i386.cc index 55d40450c6d..ae67efc49c3 100644 --- a/gcc/config/i386/driver-i386.cc +++ b/gcc/config/i386/driver-i386.cc @@ -369,6 +369,42 @@ detect_caches_intel (bool xeon_mp, unsigned max_level, return describe_cache (level1, level2); } +/* Extended features */ +#define has_feature(f) \ + has_cpu_feature (&cpu_model, cpu_features2, f) + +/* We will emit a warning when using AVX10.1 and AVX512 options with one + enabled and the other disabled. Add this function to avoid push "-mno-" + options under this scenario for -march=native. */ + +bool check_avx10_avx512_features (__processor_model &cpu_model, + unsigned int (&cpu_features2)[SIZE_OF_CPU_FEATURES], + const enum processor_features feature) +{ + if (has_feature (FEATURE_AVX512F) + && ((feature == FEATURE_AVX10_1_256) + || (feature == FEATURE_AVX10_1_512))) + return false; + + if (has_feature (FEATURE_AVX10_1_256) + && ((feature == FEATURE_AVX512F) + || (feature == FEATURE_AVX512CD) + || (feature == FEATURE_AVX512DQ) + || (feature == FEATURE_AVX512BW) + || (feature == FEATURE_AVX512VL) + || (feature == FEATURE_AVX512IFMA) + || (feature == FEATURE_AVX512VBMI) + || (feature == FEATURE_AVX512VBMI2) + || (feature == FEATURE_AVX512VNNI) + || (feature == FEATURE_AVX512VPOPCNTDQ) + || (feature == FEATURE_AVX512BITALG) + || (feature == FEATURE_AVX512FP16) + || (feature == FEATURE_AVX512BF16))) + return false; + + return true; +} + /* This will be called by the spec parser in gcc.cc when it sees a %:local_cpu_detect(args) construct. Currently it will be called with either "arch [32|64]" or "tune [32|64]" as argument @@ -447,10 +483,6 @@ const char *host_detect_local_cpu (int argc, const char **argv) } } - /* Extended features */ -#define has_feature(f) \ - has_cpu_feature (&cpu_model, cpu_features2, f) - if (vendor == VENDOR_AMD) { unsigned int name; @@ -868,7 +900,8 @@ const char *host_detect_local_cpu (int argc, const char **argv) options = concat (options, " ", isa_names_table[i].option, NULL); } - else + else if (check_avx10_avx512_features (cpu_model, cpu_features2, + isa_names_table[i].feature)) options = concat (options, neg_option, isa_names_table[i].option + 2, NULL); } diff --git a/gcc/config/i386/i386-isa.def b/gcc/config/i386/i386-isa.def index 991df5e2ef0..f730aa27a18 100644 --- a/gcc/config/i386/i386-isa.def +++ b/gcc/config/i386/i386-isa.def @@ -123,3 +123,6 @@ DEF_PTA(SHA512) DEF_PTA(SM4) DEF_PTA(APX_F) DEF_PTA(USER_MSR) +DEF_PTA(EVEX512) +DEF_PTA(AVX10_1_256) +DEF_PTA(AVX10_1_512) diff --git a/gcc/config/i386/i386-options.cc b/gcc/config/i386/i386-options.cc index df7d24352d1..dd5df559c84 100644 --- a/gcc/config/i386/i386-options.cc +++ b/gcc/config/i386/i386-options.cc @@ -258,7 +258,9 @@ static struct ix86_target_opts isa2_opts[] = { "-msha512", OPTION_MASK_ISA2_SHA512 }, { "-msm4", OPTION_MASK_ISA2_SM4 }, { "-mevex512", OPTION_MASK_ISA2_EVEX512 }, - { "-musermsr", OPTION_MASK_ISA2_USER_MSR } + { "-musermsr", OPTION_MASK_ISA2_USER_MSR }, + { "-mavx10.1-256", OPTION_MASK_ISA2_AVX10_1_256 }, + { "-mavx10.1-512", OPTION_MASK_ISA2_AVX10_1_512 } }; static struct ix86_target_opts isa_opts[] = { @@ -705,6 +707,8 @@ ix86_function_specific_save (struct cl_target_option *ptr, ptr->x_ix86_apx_features = opts->x_ix86_apx_features; ptr->x_ix86_isa_flags_explicit = opts->x_ix86_isa_flags_explicit; ptr->x_ix86_isa_flags2_explicit = opts->x_ix86_isa_flags2_explicit; + ptr->x_ix86_no_avx512_explicit = opts->x_ix86_no_avx512_explicit; + ptr->x_ix86_no_avx10_1_explicit = opts->x_ix86_no_avx10_1_explicit; ptr->x_recip_mask_explicit = opts->x_recip_mask_explicit; ptr->x_ix86_arch_string = opts->x_ix86_arch_string; ptr->x_ix86_tune_string = opts->x_ix86_tune_string; @@ -847,6 +851,8 @@ ix86_function_specific_restore (struct gcc_options *opts, opts->x_ix86_apx_features = ptr->x_ix86_apx_features; opts->x_ix86_isa_flags_explicit = ptr->x_ix86_isa_flags_explicit; opts->x_ix86_isa_flags2_explicit = ptr->x_ix86_isa_flags2_explicit; + opts->x_ix86_no_avx512_explicit = ptr->x_ix86_no_avx512_explicit; + opts->x_ix86_no_avx10_1_explicit = ptr->x_ix86_no_avx10_1_explicit; opts->x_recip_mask_explicit = ptr->x_recip_mask_explicit; opts->x_ix86_arch_string = ptr->x_ix86_arch_string; opts->x_ix86_tune_string = ptr->x_ix86_tune_string; @@ -1125,6 +1131,9 @@ ix86_valid_target_attribute_inner_p (tree fndecl, tree args, char *p_strings[], IX86_ATTR_ISA ("apxf", OPT_mapxf), IX86_ATTR_ISA ("evex512", OPT_mevex512), IX86_ATTR_ISA ("usermsr", OPT_musermsr), + IX86_ATTR_ISA ("avx10.1", OPT_mavx10_1_256), + IX86_ATTR_ISA ("avx10.1-256", OPT_mavx10_1_256), + IX86_ATTR_ISA ("avx10.1-512", OPT_mavx10_1_512), /* enum options */ IX86_ATTR_ENUM ("fpmath=", OPT_mfpmath_), @@ -1411,6 +1420,17 @@ ix86_valid_target_attribute_tree (tree fndecl, tree args, target_clone_attr)) return error_mark_node; + /* AVX10.1-256 will enable only 256 bit AVX512F features by setting all + AVX512 related ISA flags and not setting EVEX512. When it is used + with avx512 related function attribute, we need to enable 512 bit to + align with the command line behavior. Manually set EVEX512 for this + scenario. */ + if ((def->x_ix86_isa_flags2 & OPTION_MASK_ISA2_AVX10_1_256) + && (opts->x_ix86_isa_flags & OPTION_MASK_ISA_AVX512F) + && !(def->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_EVEX512) + && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_EVEX512)) + opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_EVEX512; + /* If the changed options are different from the default, rerun ix86_option_override_internal, and then save the options away. The string options are attribute options, and will be undone @@ -1421,7 +1441,10 @@ ix86_valid_target_attribute_tree (tree fndecl, tree args, || option_strings[IX86_FUNCTION_SPECIFIC_ARCH] || option_strings[IX86_FUNCTION_SPECIFIC_TUNE] || enum_opts_set.x_ix86_fpmath - || enum_opts_set.x_prefer_vector_width_type) + || enum_opts_set.x_prefer_vector_width_type + || (!(def->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_AVX10_1_256) + && (opts->x_ix86_isa_flags2_explicit + & OPTION_MASK_ISA2_AVX10_1_256))) { /* If we are using the default tune= or arch=, undo the string assigned, and use the default. */ @@ -1963,7 +1986,7 @@ ix86_option_override_internal (bool main_args_p, struct gcc_options *opts_set) { unsigned int i; - unsigned HOST_WIDE_INT ix86_arch_mask; + unsigned HOST_WIDE_INT ix86_arch_mask, avx512_isa_flags, avx512_isa_flags2; const bool ix86_tune_specified = (opts->x_ix86_tune_string != NULL); /* -mrecip options. */ @@ -1982,6 +2005,14 @@ ix86_option_override_internal (bool main_args_p, { "vec-sqrt", RECIP_MASK_VEC_SQRT }, }; + avx512_isa_flags = OPTION_MASK_ISA_AVX512F | OPTION_MASK_ISA_AVX512CD + | OPTION_MASK_ISA_AVX512DQ | OPTION_MASK_ISA_AVX512BW + | OPTION_MASK_ISA_AVX512VL | OPTION_MASK_ISA_AVX512IFMA + | OPTION_MASK_ISA_AVX512VBMI | OPTION_MASK_ISA_AVX512VBMI2 + | OPTION_MASK_ISA_AVX512VNNI | OPTION_MASK_ISA_AVX512VPOPCNTDQ + | OPTION_MASK_ISA_AVX512BITALG; + avx512_isa_flags2 = OPTION_MASK_ISA2_AVX512FP16 + | OPTION_MASK_ISA2_AVX512BF16; /* Turn off both OPTION_MASK_ABI_64 and OPTION_MASK_ABI_X32 if TARGET_64BIT_DEFAULT is true and TARGET_64BIT is false. */ @@ -2590,12 +2621,99 @@ ix86_option_override_internal (bool main_args_p, &= ~((OPTION_MASK_ISA_BMI | OPTION_MASK_ISA_BMI2 | OPTION_MASK_ISA_TBM) & ~opts->x_ix86_isa_flags_explicit); - /* Set EVEX512 target if it is not explicitly set - when AVX512 is enabled. */ - if (TARGET_AVX512F_P(opts->x_ix86_isa_flags) - && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_EVEX512)) + /* Emit a warning if AVX10.1 options is used with AVX512/EVEX512 options except + for the following option combinations: + 1. Both AVX10.1-512 and AVX512 with 512 bit vector width are enabled with no + explicit disable on other AVX512 features. + 2. Both AVX10.1-256 and AVX512 w/o 512 bit vector width are enabled with no + explicit disable on other AVX512 features. + 3. Both AVX10.1 and AVX512 are disabled. */ + if (TARGET_AVX10_1_512_P (opts->x_ix86_isa_flags2)) + { + if (opts->x_ix86_no_avx512_explicit + && (((~(avx512_isa_flags & opts->x_ix86_isa_flags) + & (avx512_isa_flags & opts->x_ix86_isa_flags_explicit))) + || ((~((avx512_isa_flags2 | OPTION_MASK_ISA2_EVEX512) + & opts->x_ix86_isa_flags2) + & ((avx512_isa_flags2 | OPTION_MASK_ISA2_EVEX512) + & opts->x_ix86_isa_flags2_explicit))))) + warning (0, "%<-mno-evex512%> or %<-mno-avx512XXX%> cannot disable " + "AVX10 instructions when AVX10.1-512 is available"); + } + else if (TARGET_AVX10_1_256_P (opts->x_ix86_isa_flags2)) + { + if (TARGET_EVEX512_P (opts->x_ix86_isa_flags2) + && (OPTION_MASK_ISA2_EVEX512 & opts->x_ix86_isa_flags2_explicit)) + { + if (!TARGET_AVX512F_P (opts->x_ix86_isa_flags) + || !(OPTION_MASK_ISA_AVX512F & opts->x_ix86_isa_flags_explicit)) + { + /* We should not emit 512 bit instructions under AVX10.1-256 + when EVEX512 is enabled w/o any AVX512 features enabled. + Disable EVEX512 bit for this. */ + warning (0, "Using %<-mevex512%> without any AVX512 features " + "enabled together with AVX10.1 only will not enable " + "any AVX512 or AVX10.1-512 features, using 256 as " + "max vector size"); + opts->x_ix86_isa_flags2 &= ~OPTION_MASK_ISA2_EVEX512; + } + else + warning (0, "Vector size conflicts between AVX10.1 and AVX512, " + "using 512 as max vector size"); + } + else if (TARGET_AVX512F_P (opts->x_ix86_isa_flags) + && !(OPTION_MASK_ISA2_EVEX512 + & opts->x_ix86_isa_flags2_explicit)) + warning (0, "Vector size conflicts between AVX10.1 and AVX512, using " + "512 as max vector size"); + else if (opts->x_ix86_no_avx512_explicit + && (((~(avx512_isa_flags & opts->x_ix86_isa_flags) + & (avx512_isa_flags & opts->x_ix86_isa_flags_explicit))) + || ((~(avx512_isa_flags2 & opts->x_ix86_isa_flags2) + & (avx512_isa_flags2 + & opts->x_ix86_isa_flags2_explicit))))) + warning (0, "%<-mno-avx512XXX%> cannot disable AVX10 instructions " + "when AVX10 is available"); + } + else if (TARGET_AVX512F_P (opts->x_ix86_isa_flags) + && (OPTION_MASK_ISA_AVX512F & opts->x_ix86_isa_flags_explicit)) + { + if (opts->x_ix86_no_avx10_1_explicit + && ((OPTION_MASK_ISA2_AVX10_1_256 | OPTION_MASK_ISA2_AVX10_1_512) + & opts->x_ix86_isa_flags2_explicit)) + { + warning (0, "%<-mno-avx10.1, -mno-avx10.1-256, -mno-avx10.1-512%> " + "cannot disable AVX512 instructions when " + "%<-mavx512XXX%>"); + /* Reset those unset AVX512 flags set by AVX10 options when AVX10 is + disabled. */ + if (OPTION_MASK_ISA2_AVX10_1_256 & opts->x_ix86_isa_flags2_explicit) + { + opts->x_ix86_isa_flags = (~avx512_isa_flags + & opts->x_ix86_isa_flags) + | (avx512_isa_flags & opts->x_ix86_isa_flags_explicit); + opts->x_ix86_isa_flags2 = (~avx512_isa_flags + & opts->x_ix86_isa_flags2) + | (avx512_isa_flags2 & opts->x_ix86_isa_flags2_explicit); + } + } + } + + /* Set EVEX512 if one of the following conditions meets: + 1. AVX512 is enabled while EVEX512 is not explicitly set/unset. + 2. AVX10.1-512 is enabled. */ + if (TARGET_AVX10_1_512_P (opts->x_ix86_isa_flags2) + || (TARGET_AVX512F_P (opts->x_ix86_isa_flags) + && !(opts->x_ix86_isa_flags2_explicit & OPTION_MASK_ISA2_EVEX512))) opts->x_ix86_isa_flags2 |= OPTION_MASK_ISA2_EVEX512; + /* Enable all AVX512 related ISAs when AVX10.1 is enabled. */ + if (TARGET_AVX10_1_256_P (opts->x_ix86_isa_flags2)) + { + opts->x_ix86_isa_flags |= avx512_isa_flags; + opts->x_ix86_isa_flags2 |= avx512_isa_flags2; + } + /* Disable AVX512{PF,ER,4VNNIW,4FAMPS} for -mno-evex512. */ if (!TARGET_EVEX512_P(opts->x_ix86_isa_flags2)) { diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index a56367a947b..fe264d142f0 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -2374,7 +2374,7 @@ constexpr wide_int_bitmask PTA_CASCADELAKE = PTA_SKYLAKE_AVX512 constexpr wide_int_bitmask PTA_COOPERLAKE = PTA_CASCADELAKE | PTA_AVX512BF16; constexpr wide_int_bitmask PTA_CANNONLAKE = PTA_SKYLAKE | PTA_AVX512F | PTA_AVX512CD | PTA_AVX512VL | PTA_AVX512BW | PTA_AVX512DQ | PTA_PKU - | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA; + | PTA_AVX512VBMI | PTA_AVX512IFMA | PTA_SHA | PTA_EVEX512; constexpr wide_int_bitmask PTA_ICELAKE_CLIENT = PTA_CANNONLAKE | PTA_AVX512VNNI | PTA_GFNI | PTA_VAES | PTA_AVX512VBMI2 | PTA_VPCLMULQDQ | PTA_AVX512BITALG | PTA_RDPID | PTA_AVX512VPOPCNTDQ; diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt index 0c3b8f4b621..b81c968876e 100644 --- a/gcc/config/i386/i386.opt +++ b/gcc/config/i386/i386.opt @@ -36,6 +36,13 @@ HOST_WIDE_INT ix86_isa_flags_explicit Variable HOST_WIDE_INT ix86_isa_flags2_explicit +; Indicate if AVX512 and AVX10.1 are explicitly set no. +Variable +int ix86_no_avx512_explicit = 0 + +Variable +int ix86_no_avx10_1_explicit = 0 + ; Additional target flags Variable int ix86_target_flags @@ -96,6 +103,14 @@ HOST_WIDE_INT x_ix86_isa_flags2_explicit TargetSave HOST_WIDE_INT x_ix86_isa_flags_explicit +;; which flags were passed by the user +TargetSave +HOST_WIDE_INT x_ix86_no_avx512_explicit + +;; which flags were passed by the user +TargetSave +HOST_WIDE_INT x_ix86_no_avx10_1_explicit + ;; whether -mtune was not specified TargetSave unsigned char tune_defaulted @@ -1348,3 +1363,18 @@ Support 512 bit vector built-in functions and code generation. musermsr Target Mask(ISA2_USER_MSR) Var(ix86_isa_flags2) Save Support USER_MSR built-in functions and code generation. + +mavx10.1-256 +Target Mask(ISA2_AVX10_1_256) Var(ix86_isa_flags2) Save +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, +and AVX10.1 built-in functions and code generation. + +mavx10.1-512 +Target Mask(ISA2_AVX10_1_512) Var(ix86_isa_flags2) Save +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, +and AVX10.1-512 built-in functions and code generation. + +mavx10.1 +Target Alias(mavx10.1-256) +Support MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, AVX, AVX2, +and AVX10.1 built-in functions and code generation. diff --git a/gcc/doc/extend.texi b/gcc/doc/extend.texi index fa7402813e7..a4ce2f46d85 100644 --- a/gcc/doc/extend.texi +++ b/gcc/doc/extend.texi @@ -7283,6 +7283,21 @@ Enable/disable the generation of the SM4 instructions. @itemx no-usermsr Enable/disable the generation of the USER_MSR instructions. +@cindex @code{target("avx10.1")} function attribute, x86 +@item avx10.1 +@itemx no-avx10.1 +Enable/disable the generation of the AVX10.1 instructions. + +@cindex @code{target("avx10.1-256")} function attribute, x86 +@item avx10.1-256 +@itemx no-avx10.1-256 +Enable/disable the generation of the AVX10.1 instructions. + +@cindex @code{target("avx10.1-512")} function attribute, x86 +@item avx10.1-512 +@itemx no-avx10.1-512 +Enable/disable the generation of the AVX10.1 512 bit instructions. + @cindex @code{target("cld")} function attribute, x86 @item cld @itemx no-cld diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 6e776a0faa1..7b98f93bd6a 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -1449,7 +1449,7 @@ See RS/6000 and PowerPC Options. -mamx-tile -mamx-int8 -mamx-bf16 -muintr -mhreset -mavxvnni -mavx512fp16 -mavxifma -mavxvnniint8 -mavxneconvert -mcmpccxadd -mamx-fp16 -mprefetchi -mraoint -mamx-complex -mavxvnniint16 -msm3 -msha512 -msm4 -mapxf --musermsr +-musermsr -mavx10.1 -mavx10.1-256 -mavx10.1-512 -mcldemote -mms-bitfields -mno-align-stringops -minline-all-stringops -minline-stringops-dynamically -mstringop-strategy=@var{alg} -mkl -mwidekl @@ -34027,6 +34027,15 @@ preferred alignment to @option{-mpreferred-stack-boundary=2}. @need 200 @opindex musermsr @itemx -musermsr +@need 200 +@opindex mavx10.1 +@itemx -mavx10.1 +@need 200 +@opindex mavx10.1-256 +@itemx -mavx10.1-256 +@need 200 +@opindex mavx10.1-512 +@itemx -mavx10.1-512 These switches enable the use of instructions in the MMX, SSE, AVX512ER, AVX512CD, AVX512VL, AVX512BW, AVX512DQ, AVX512IFMA, AVX512VBMI, SHA, AES, PCLMUL, CLFLUSHOPT, CLWB, FSGSBASE, PTWRITE, RDRND, F16C, FMA, PCONFIG, @@ -34037,9 +34046,9 @@ GFNI, VAES, WAITPKG, VPCLMULQDQ, AVX512BITALG, MOVDIRI, MOVDIR64B, AVX512BF16, ENQCMD, AVX512VPOPCNTDQ, AVX5124FMAPS, AVX512VNNI, AVX5124VNNIW, SERIALIZE, UINTR, HRESET, AMXTILE, AMXINT8, AMXBF16, KL, WIDEKL, AVXVNNI, AVX512-FP16, AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AMX-FP16, PREFETCHI, RAOINT, -AMX-COMPLEX, AVXVNNIINT16, SM3, SHA512, SM4, APX_F, USER_MSR or CLDEMOTE -extended instruction sets. Each has a corresponding @option{-mno-} option -to disable use of these instructions. +AMX-COMPLEX, AVXVNNIINT16, SM3, SHA512, SM4, APX_F, USER_MSR, AVX10.1 or +CLDEMOTE extended instruction sets. Each has a corresponding @option{-mno-} +option to disable use of these instructions. These extensions are also available as built-in functions: see @ref{x86 Built-in Functions}, for details of the functions enabled and diff --git a/gcc/doc/sourcebuild.texi b/gcc/doc/sourcebuild.texi index c20af31c642..8dfd8435811 100644 --- a/gcc/doc/sourcebuild.texi +++ b/gcc/doc/sourcebuild.texi @@ -2496,6 +2496,15 @@ Target supports compiling @code{avx} instructions. @item avx_runtime Target supports the execution of @code{avx} instructions. +@item avx10.1 +Target supports the execution of @code{avx10.1} instructions. + +@item avx10.1-256 +Target supports the execution of @code{avx10.1} instructions. + +@item avx10.1-512 +Target supports the execution of @code{avx10.1-512} instructions. + @item avx2 Target supports compiling @code{avx2} instructions. diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-1.c b/gcc/testsuite/gcc.target/i386/avx10_1-1.c new file mode 100644 index 00000000000..cfd9662bb13 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10_1-1.c @@ -0,0 +1,22 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -march=x86-64 -mavx10.1" } */ + +#include + +void +f1 () +{ + register __m256d a __asm ("ymm17"); + register __m256d b __asm ("ymm16"); + a = _mm256_add_pd (a, b); + asm volatile ("" : "+v" (a)); +} + +void +f2 () +{ + register __m128d a __asm ("xmm17"); + register __m128d b __asm ("xmm16"); + a = _mm_add_pd (a, b); + asm volatile ("" : "+v" (a)); +} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-10.c b/gcc/testsuite/gcc.target/i386/avx10_1-10.c new file mode 100644 index 00000000000..0db5240a30f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10_1-10.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64 -mavx10.1-512 -mavx512f -mno-evex512" } */ +/* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10 instructions when AVX10.1-512 is available" "" { target *-*-* } 0 } */ +/* { dg-final { scan-assembler "%zmm" } } */ + +#include "avx10_1-2.c" diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-11.c b/gcc/testsuite/gcc.target/i386/avx10_1-11.c new file mode 100644 index 00000000000..c0ad4fc27fa --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10_1-11.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64 -mavx10.1-512 -mno-avx512f" } */ +/* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10 instructions when AVX10.1-512 is available" "" { target *-*-* } 0 } */ +/* { dg-final { scan-assembler "%zmm" } } */ + +#include "avx10_1-2.c" diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-12.c b/gcc/testsuite/gcc.target/i386/avx10_1-12.c new file mode 100644 index 00000000000..61f0e4db61b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10_1-12.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64 -mno-avx10.1-512 -mavx512f" } */ +/* { dg-warning "'-mno-avx10.1, -mno-avx10.1-256, -mno-avx10.1-512' cannot disable AVX512 instructions when '-mavx512XXX'" "" { target *-*-* } 0 } */ +/* { dg-final { scan-assembler "%zmm" } } */ + +#include "avx10_1-2.c" diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-13.c b/gcc/testsuite/gcc.target/i386/avx10_1-13.c new file mode 100644 index 00000000000..8a111190025 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10_1-13.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64 -mavx10.1" } */ +/* { dg-final { scan-assembler "%zmm" } } */ + +typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); + +__attribute__ ((target ("avx512f"))) __m512d +foo () +{ /* { dg-warning "Vector size conflicts between AVX10.1 and AVX512, using 512 as max vector size" } */ + __m512d a, b; + a = a + b; + return a; +} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-14.c b/gcc/testsuite/gcc.target/i386/avx10_1-14.c new file mode 100644 index 00000000000..03222a7a031 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10_1-14.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64 -mavx512f" } */ +/* { dg-final { scan-assembler "%zmm" } } */ + +typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); + +__attribute__ ((target ("avx10.1"))) __m512d +foo () +{ /* { dg-warning "Vector size conflicts between AVX10.1 and AVX512, using 512 as max vector size" } */ + __m512d a, b; + a = a + b; + return a; +} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-15.c b/gcc/testsuite/gcc.target/i386/avx10_1-15.c new file mode 100644 index 00000000000..d1731f09a45 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10_1-15.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64 -mavx10.1-512" } */ +/* { dg-final { scan-assembler "%zmm" } } */ + +typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); + +__attribute__ ((target ("avx512f,no-evex512"))) __m512d +foo () +{ /* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10 instructions when AVX10.1-512 is available" } */ + __m512d a, b; + a = a + b; + return a; +} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-16.c b/gcc/testsuite/gcc.target/i386/avx10_1-16.c new file mode 100644 index 00000000000..f5f3ff8127e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10_1-16.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64 -mavx512f -mno-evex512" } */ +/* { dg-final { scan-assembler "%zmm" } } */ + +typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); + +__attribute__ ((target ("avx10.1-512"))) __m512d +foo () +{ /* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10 instructions when AVX10.1-512 is available" } */ + __m512d a, b; + a = a + b; + return a; +} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-17.c b/gcc/testsuite/gcc.target/i386/avx10_1-17.c new file mode 100644 index 00000000000..a19230f597b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10_1-17.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64 -mavx512f" } */ +/* { dg-final { scan-assembler "%zmm" } } */ + +typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); + +__attribute__ ((target ("no-avx10.1"))) __m512d +foo () +{ /* { dg-warning "'-mno-avx10.1, -mno-avx10.1-256, -mno-avx10.1-512' cannot disable AVX512 instructions when '-mavx512XXX'" } */ + __m512d a, b; + a = a + b; + return a; +} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-18.c b/gcc/testsuite/gcc.target/i386/avx10_1-18.c new file mode 100644 index 00000000000..c50fd2bb29b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10_1-18.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64 -mavx10.1-512" } */ +/* { dg-final { scan-assembler "%zmm" } } */ + +typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); + +__attribute__ ((target ("no-avx512f"))) __m512d +foo () +{ /* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10 instructions when AVX10.1-512 is available" } */ + __m512d a, b; + a = a + b; + return a; +} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-19.c b/gcc/testsuite/gcc.target/i386/avx10_1-19.c new file mode 100644 index 00000000000..7aacc15aad9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10_1-19.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64 -mno-avx10.1-512" } */ +/* { dg-final { scan-assembler "%zmm" } } */ + +typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); + +__attribute__ ((target ("avx512f"))) __m512d +foo () +{ /* { dg-warning "'-mno-avx10.1, -mno-avx10.1-256, -mno-avx10.1-512' cannot disable AVX512 instructions when '-mavx512XXX'" } */ + __m512d a, b; + a = a + b; + return a; +} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-2.c b/gcc/testsuite/gcc.target/i386/avx10_1-2.c new file mode 100644 index 00000000000..0b3991dcf74 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10_1-2.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64 -mavx10.1-512" } */ +/* { dg-final { scan-assembler "%zmm" } } */ + +typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); + +__m512d +foo () +{ + __m512d a, b; + a = a + b; + return a; +} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-20.c b/gcc/testsuite/gcc.target/i386/avx10_1-20.c new file mode 100644 index 00000000000..d63c6b40d80 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10_1-20.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64 -mno-avx512f" } */ +/* { dg-final { scan-assembler "%zmm" } } */ + +typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); + +__attribute__ ((target ("avx10.1-512"))) __m512d +foo () +{ /* { dg-warning "'-mno-evex512' or '-mno-avx512XXX' cannot disable AVX10 instructions when AVX10.1-512 is available" } */ + __m512d a, b; + a = a + b; + return a; +} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-21.c b/gcc/testsuite/gcc.target/i386/avx10_1-21.c new file mode 100644 index 00000000000..27a7265df61 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10_1-21.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64 -mavx10.1 -mevex512 -Wno-psabi" } */ +/* { dg-warning "Using '-mevex512' without any AVX512 features enabled together with AVX10.1 only will not enable any AVX512 or AVX10.1-512 features, using 256 as max vector size" "" { target *-*-* } 0 } */ +/* { dg-final { scan-assembler-not "%zmm" } } */ + +#include "avx10_1-2.c" diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-22.c b/gcc/testsuite/gcc.target/i386/avx10_1-22.c new file mode 100644 index 00000000000..796262283d6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10_1-22.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64 -mavx10.1 -Wno-psabi" } */ +/* { dg-final { scan-assembler-not "%zmm" } } */ + +typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); + +__attribute__ ((target ("evex512"))) __m512d +foo () +{ /* { dg-warning "Using '-mevex512' without any AVX512 features enabled together with AVX10.1 only will not enable any AVX512 or AVX10.1-512 features, using 256 as max vector size" "" { target *-*-* } 0 } */ + __m512d a, b; + a = a + b; + return a; +} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-23.c b/gcc/testsuite/gcc.target/i386/avx10_1-23.c new file mode 100644 index 00000000000..6e8d64d0f34 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10_1-23.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64 -mevex512 -Wno-psabi" } */ +/* { dg-final { scan-assembler-not "%zmm" } } */ + +typedef double __m512d __attribute__ ((__vector_size__ (64), __may_alias__)); + +__attribute__ ((target ("avx10.1"))) __m512d +foo () +{ /* { dg-warning "Using '-mevex512' without any AVX512 features enabled together with AVX10.1 only will not enable any AVX512 or AVX10.1-512 features, using 256 as max vector size" "" { target *-*-* } 0 } */ + __m512d a, b; + a = a + b; + return a; +} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-3.c b/gcc/testsuite/gcc.target/i386/avx10_1-3.c new file mode 100644 index 00000000000..3be988a1a62 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10_1-3.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64 -mavx10.1" } */ + +#include + +int +foo (int c) +{ + register int a __asm ("k7") = c; + int b = foo (a); + asm volatile ("" : "+k" (b)); + return b; +} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-4.c b/gcc/testsuite/gcc.target/i386/avx10_1-4.c new file mode 100644 index 00000000000..68cbf197d61 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10_1-4.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64 -mavx10.1-512" } */ + +#include + +long long +foo (long long c) +{ + register long long a __asm ("k7") = c; + long long b = foo (a); + asm volatile ("" : "+k" (b)); + return b; +} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-5.c b/gcc/testsuite/gcc.target/i386/avx10_1-5.c new file mode 100644 index 00000000000..20b78ea9510 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10_1-5.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-O0 -march=x86-64 -mavx10.1 -Wno-psabi" } */ +/* { dg-final { scan-assembler-not ".%zmm" } } */ + +#include "avx10_1-2.c" diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-6.c b/gcc/testsuite/gcc.target/i386/avx10_1-6.c new file mode 100644 index 00000000000..827c80ce51e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10_1-6.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=x86-64 -mavx10.1" } */ + +#include + +long long +foo (long long c) +{ + register long long a __asm ("k7") = c; + long long b = foo (a); + asm volatile ("" : "+k" (b)); /* { dg-error "inconsistent operand constraints in an 'asm'" } */ + return b; +} diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-7.c b/gcc/testsuite/gcc.target/i386/avx10_1-7.c new file mode 100644 index 00000000000..afce2905421 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10_1-7.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64 -mavx10.1-512 -mavx512f" } */ +/* { dg-final { scan-assembler "%zmm" } } */ + +#include "avx10_1-2.c" diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-8.c b/gcc/testsuite/gcc.target/i386/avx10_1-8.c new file mode 100644 index 00000000000..69b6c6a3e1a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10_1-8.c @@ -0,0 +1,4 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-march=x86-64 -mavx10.1 -mavx512f -mno-evex512" } */ + +#include "avx10_1-1.c" diff --git a/gcc/testsuite/gcc.target/i386/avx10_1-9.c b/gcc/testsuite/gcc.target/i386/avx10_1-9.c new file mode 100644 index 00000000000..8e838277962 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx10_1-9.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-march=x86-64 -mavx10.1-256 -mavx512f" } */ +/* { dg-warning "Vector size conflicts between AVX10.1 and AVX512, using 512 as max vector size" "" { target *-*-* } 0 } */ +/* { dg-final { scan-assembler "%zmm" } } */ + +#include "avx10_1-2.c"