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[8.43.85.97]) by mx.google.com with ESMTPS id t7-20020a05620a450700b00773ba88c3bdsi3765885qkp.226.2023.11.09.15.34.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Nov 2023 15:34:07 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 30739385C6F5 for ; Thu, 9 Nov 2023 23:34:07 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbguseast3.qq.com (smtpbguseast3.qq.com [54.243.244.52]) by sourceware.org (Postfix) with ESMTPS id AC1C13858D37 for ; Thu, 9 Nov 2023 23:33:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org AC1C13858D37 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org AC1C13858D37 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=54.243.244.52 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699572824; cv=none; b=pGiAnIOQX3kY6CHbJ92fUK2RJPfMCbPqrL0aiw6Gs14kYrA/3TPg4M0loNpipNJh+Z7e1A7kIBGpwpZFoxv2h6uJAqxh0aPCagkja0/htdLN0gJXLqs6ax6MWOHy+yHKBz93Rk3MmSllbss52vfEpczb1b7170DWqF4hgWObvmw= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699572824; c=relaxed/simple; bh=xbobsLRQq9EU7yrUGhwnPclcnm/bmzTMuG6idXiLAEs=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=GZ6jZfX+EooWJHq9+XgWl7uiITC12tXC7Ogz/Idf1DcPg3Ut8SNvd/F0PlgUuq6Tk5WvvGzUAaMALqrvQSz0nNswfJ47/DfPRzQStug00tJzQxwM/qjIBy2OyuQ7lB0O6qBoH27GFpJOzPGl1K9Zm4cWOWDJ+IUWU4TQ1VryC6A= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp80t1699572808trx71ai2 Received: from rios-cad122.hadoop.rioslab.org ( [58.60.1.26]) by bizesmtp.qq.com (ESMTP) with id ; Fri, 10 Nov 2023 07:33:26 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: 9z+eS2uTOl/X447JxEjd1aEw6CqskLCodwjMQr+HgX+L99cVoWaC+yQiNOivL znWbrVaMWEx05OUE+Vp1bM17L5iomhBY50OUGXpKde6jrFpjF4KvvA3wECyesOB6EwRFvIh ZUoM7h/L6oBf81sQgKOFzi2Slqiz8Co/wkVnYLt+2hurq33t3IQXvDkkzfRfTlED9beKqYp tZ0ioouYVJ5BhznkE6cw/VJ+eOSqkeqG51BUotzCtrfmaOxFq46maTlgZRfLUUsTzS7495a TTNBs6zhSmPgxNAQ97HyX2MZLK42KaAdv0jklMM6/IrH9pYCKfbgQqYPWzhmIy1EZYRv5jw gVFbTfpIclfoHz78LYNHjawGCubPTI8UEqCTP/m5t8hHqRJHZWtZrVBi8z3IP8NyKztLQes X-QQ-GoodBg: 2 X-BIZMAIL-ID: 14777157960262091470 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Move cond_copysign from combine pattern to autovec pattern Date: Fri, 10 Nov 2023 07:33:25 +0800 Message-Id: <20231109233325.2189755-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782131297979077271 X-GMAIL-MSGID: 1782131297979077271 Since cond_copysign has been support into match.pd (middle-end). We don't need to support conditional copysign by RTL combine pass. Instead, we can support it by direct explicit cond_copysign optab. conditional copysign tests are already available in the testsuite. No need to add tests. gcc/ChangeLog: * config/riscv/autovec-opt.md (*cond_copysign): Remove. * config/riscv/autovec.md (cond_copysign): New pattern. --- gcc/config/riscv/autovec-opt.md | 22 ---------------------- gcc/config/riscv/autovec.md | 22 ++++++++++++++++++++++ 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/gcc/config/riscv/autovec-opt.md b/gcc/config/riscv/autovec-opt.md index 3c87e66ea49..986ac6e9181 100644 --- a/gcc/config/riscv/autovec-opt.md +++ b/gcc/config/riscv/autovec-opt.md @@ -486,28 +486,6 @@ } [(set_attr "type" "vector")]) -;; Combine vfsgnj.vv + vcond_mask -(define_insn_and_split "*cond_copysign" - [(set (match_operand:V_VLSF 0 "register_operand") - (if_then_else:V_VLSF - (match_operand: 1 "register_operand") - (unspec:V_VLSF - [(match_operand:V_VLSF 2 "register_operand") - (match_operand:V_VLSF 3 "register_operand")] UNSPEC_VCOPYSIGN) - (match_operand:V_VLSF 4 "register_operand")))] - "TARGET_VECTOR && can_create_pseudo_p ()" - "#" - "&& 1" - [(const_int 0)] -{ - insn_code icode = code_for_pred (UNSPEC_VCOPYSIGN, mode); - rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[4], - gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; - riscv_vector::expand_cond_len_binop (icode, ops); - DONE; -} -[(set_attr "type" "vector")]) - ;; Combine vnsra + vcond_mask (define_insn_and_split "*cond_vtrunc" [(set (match_operand: 0 "register_operand") diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 973dc4ac235..33722ea1139 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -1808,6 +1808,28 @@ DONE; }) +;; ------------------------------------------------------------------------- +;; ---- [FP] Conditional copysign operations +;; ------------------------------------------------------------------------- +;; Includes: +;; - vfsgnj +;; ------------------------------------------------------------------------- + +(define_expand "cond_copysign" + [(match_operand:V_VLSF 0 "register_operand") + (match_operand: 1 "register_operand") + (match_operand:V_VLSF 2 "register_operand") + (match_operand:V_VLSF 3 "register_operand") + (match_operand:V_VLSF 4 "register_operand")] + "TARGET_VECTOR" +{ + insn_code icode = code_for_pred (UNSPEC_VCOPYSIGN, mode); + rtx ops[] = {operands[0], operands[1], operands[2], operands[3], operands[4], + gen_int_mode (GET_MODE_NUNITS (mode), Pmode)}; + riscv_vector::expand_cond_len_binop (icode, ops); + DONE; +}) + ;; ------------------------------------------------------------------------- ;; ---- [INT] Conditional ternary operations ;; -------------------------------------------------------------------------