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[2620:137:e000::3:3]) by mx.google.com with ESMTPS id pf9-20020a17090b1d8900b00278f81e54cdsi2812909pjb.19.2023.11.09.13.51.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Nov 2023 13:51:48 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) client-ip=2620:137:e000::3:3; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id E5E38830388C; Thu, 9 Nov 2023 13:51:45 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234755AbjKIVva (ORCPT + 30 others); Thu, 9 Nov 2023 16:51:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52286 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234659AbjKIVvY (ORCPT ); Thu, 9 Nov 2023 16:51:24 -0500 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D080B4482; Thu, 9 Nov 2023 13:51:21 -0800 (PST) Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.96.2) (envelope-from ) id 1r1Cve-0003UV-2f; Thu, 09 Nov 2023 21:51:10 +0000 Date: Thu, 9 Nov 2023 21:51:07 +0000 From: Daniel Golle To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Felix Fietkau , John Crispin , Sean Wang , Mark Lee , Lorenzo Bianconi , Matthias Brugger , AngeloGioacchino Del Regno , Andrew Lunn , Heiner Kallweit , Russell King , Alexander Couzens , Daniel Golle , Philipp Zabel , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org Subject: [RFC PATCH 2/8] phy: add driver for MediaTek pextp 10GE SerDes PHY Message-ID: <0b112d39251b35b5d7975833ad6b4ab4717c029a.1699565880.git.daniel@makrotopia.org> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Thu, 09 Nov 2023 13:51:45 -0800 (PST) X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782124861282083481 X-GMAIL-MSGID: 1782124861282083481 Add driver for MediaTek's pextp 10 Gigabit/s Ethernet SerDes PHY which can be found in the MT7988 SoC. The PHY can operates only in PHY_MODE_ETHERNET, the submode is one of PHY_INTERFACE_MODE_* corresponding to the supported modes: * USXGMII * 10GBase-R * 5GBase-R * 2500Base-X * 1000Base-X * Cisco SGMII (MAC side) In order to work-around a performance issue present on the first of two PEXTP present in MT7988 special tuning is applied which can be selected by adding the mediatek,usxgmii-performance-errata property to the device tree node. There is no documentation what-so-ever for the pextp registers and this driver is based on a GPL licensed implementation found in MediaTek's SDK. Signed-off-by: Daniel Golle --- MAINTAINERS | 1 + drivers/phy/mediatek/Kconfig | 11 + drivers/phy/mediatek/Makefile | 1 + drivers/phy/mediatek/phy-mtk-pextp.c | 355 +++++++++++++++++++++++++++ 4 files changed, 368 insertions(+) create mode 100644 drivers/phy/mediatek/phy-mtk-pextp.c diff --git a/MAINTAINERS b/MAINTAINERS index 7b151710e8c58..6499acd8f3874 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -13527,6 +13527,7 @@ L: netdev@vger.kernel.org S: Maintained F: drivers/net/phy/mediatek-ge-soc.c F: drivers/net/phy/mediatek-ge.c +F: drivers/phy/mediatek/phy-mediatek-pextp.c MEDIATEK I2C CONTROLLER DRIVER M: Qii Wang diff --git a/drivers/phy/mediatek/Kconfig b/drivers/phy/mediatek/Kconfig index 3125ecb5d119f..a7749a6d96541 100644 --- a/drivers/phy/mediatek/Kconfig +++ b/drivers/phy/mediatek/Kconfig @@ -13,6 +13,17 @@ config PHY_MTK_PCIE callback for PCIe GEN3 port, it supports software efuse initialization. +config PHY_MTK_PEXTP + tristate "MediaTek PEXTP Driver" + depends on ARCH_MEDIATEK || COMPILE_TEST + depends on OF && OF_ADDRESS + depends on HAS_IOMEM + select GENERIC_PHY + help + Say 'Y' here to add support for MediaTek pextp PHY driver. + The driver provides access to the Ethernet SerDes PHY supporting + various 1GE, 2.5GE, 5GE and 10GE modes. + config PHY_MTK_TPHY tristate "MediaTek T-PHY Driver" depends on ARCH_MEDIATEK || COMPILE_TEST diff --git a/drivers/phy/mediatek/Makefile b/drivers/phy/mediatek/Makefile index c9a50395533eb..ca60c7b9b02ac 100644 --- a/drivers/phy/mediatek/Makefile +++ b/drivers/phy/mediatek/Makefile @@ -8,6 +8,7 @@ obj-$(CONFIG_PHY_MTK_PCIE) += phy-mtk-pcie.o obj-$(CONFIG_PHY_MTK_TPHY) += phy-mtk-tphy.o obj-$(CONFIG_PHY_MTK_UFS) += phy-mtk-ufs.o obj-$(CONFIG_PHY_MTK_XSPHY) += phy-mtk-xsphy.o +obj-$(CONFIG_PHY_MTK_PEXTP) += phy-mtk-pextp.o phy-mtk-hdmi-drv-y := phy-mtk-hdmi.o phy-mtk-hdmi-drv-y += phy-mtk-hdmi-mt2701.o diff --git a/drivers/phy/mediatek/phy-mtk-pextp.c b/drivers/phy/mediatek/phy-mtk-pextp.c new file mode 100644 index 0000000000000..272bff4f37a96 --- /dev/null +++ b/drivers/phy/mediatek/phy-mtk-pextp.c @@ -0,0 +1,355 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* MediaTek 10GE SerDes PHY driver + * + * Copyright (c) 2023 Daniel Golle + * based on mtk_usxgmii.c found in MediaTek's SDK released under GPL-2.0 + * Copyright (c) 2022 MediaTek Inc. + * Author: Henry Yen + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct mtk_pextp_phy { + void __iomem *base; + struct device *dev; + struct reset_control *reset; + struct clk *clk; + bool da_war; +}; + +static inline bool mtk_interface_mode_is_xgmii(phy_interface_t interface) +{ + switch (interface) { + case PHY_INTERFACE_MODE_INTERNAL: + case PHY_INTERFACE_MODE_USXGMII: + case PHY_INTERFACE_MODE_10GBASER: + case PHY_INTERFACE_MODE_5GBASER: + return true; + default: + return false; + } +} + +static void mtk_pextp_setup(struct mtk_pextp_phy *pextp, phy_interface_t interface) +{ + bool is_10g = (interface == PHY_INTERFACE_MODE_10GBASER || + interface == PHY_INTERFACE_MODE_USXGMII); + bool is_2p5g = (interface == PHY_INTERFACE_MODE_2500BASEX); + bool is_5g = (interface == PHY_INTERFACE_MODE_5GBASER); + + dev_dbg(pextp->dev, "setting up for mode %s\n", phy_modes(interface)); + + /* Setup operation mode */ + if (is_10g) + iowrite32(0x00C9071C, pextp->base + 0x9024); + else + iowrite32(0x00D9071C, pextp->base + 0x9024); + + if (is_5g) + iowrite32(0xAAA5A5AA, pextp->base + 0x2020); + else + iowrite32(0xAA8585AA, pextp->base + 0x2020); + + if (is_2p5g || is_5g || is_10g) { + iowrite32(0x0C020707, pextp->base + 0x2030); + iowrite32(0x0E050F0F, pextp->base + 0x2034); + iowrite32(0x00140032, pextp->base + 0x2040); + } else { + iowrite32(0x0C020207, pextp->base + 0x2030); + iowrite32(0x0E05050F, pextp->base + 0x2034); + iowrite32(0x00200032, pextp->base + 0x2040); + } + + if (is_2p5g || is_10g) + iowrite32(0x00C014AA, pextp->base + 0x50F0); + else if (is_5g) + iowrite32(0x00C018AA, pextp->base + 0x50F0); + else + iowrite32(0x00C014BA, pextp->base + 0x50F0); + + if (is_5g) { + iowrite32(0x3777812B, pextp->base + 0x50E0); + iowrite32(0x005C9CFF, pextp->base + 0x506C); + iowrite32(0x9DFAFAFA, pextp->base + 0x5070); + iowrite32(0x273F3F3F, pextp->base + 0x5074); + iowrite32(0xA8883868, pextp->base + 0x5078); + iowrite32(0x14661466, pextp->base + 0x507C); + } else { + iowrite32(0x3777C12B, pextp->base + 0x50E0); + iowrite32(0x005F9CFF, pextp->base + 0x506C); + iowrite32(0x9D9DFAFA, pextp->base + 0x5070); + iowrite32(0x27273F3F, pextp->base + 0x5074); + iowrite32(0xA7883C68, pextp->base + 0x5078); + iowrite32(0x11661166, pextp->base + 0x507C); + } + + if (is_2p5g || is_10g) { + iowrite32(0x0E000AAF, pextp->base + 0x5080); + iowrite32(0x08080D0D, pextp->base + 0x5084); + iowrite32(0x02030909, pextp->base + 0x5088); + } else if (is_5g) { + iowrite32(0x0E001ABF, pextp->base + 0x5080); + iowrite32(0x080B0D0D, pextp->base + 0x5084); + iowrite32(0x02050909, pextp->base + 0x5088); + } else { + iowrite32(0x0E000EAF, pextp->base + 0x5080); + iowrite32(0x08080E0D, pextp->base + 0x5084); + iowrite32(0x02030B09, pextp->base + 0x5088); + } + + if (is_5g) { + iowrite32(0x0C000000, pextp->base + 0x50E4); + iowrite32(0x04000000, pextp->base + 0x50E8); + } else { + iowrite32(0x0C0C0000, pextp->base + 0x50E4); + iowrite32(0x04040000, pextp->base + 0x50E8); + } + + if (is_2p5g || mtk_interface_mode_is_xgmii(interface)) + iowrite32(0x0F0F0C06, pextp->base + 0x50EC); + else + iowrite32(0x0F0F0606, pextp->base + 0x50EC); + + if (is_5g) { + iowrite32(0x50808C8C, pextp->base + 0x50A8); + iowrite32(0x18000000, pextp->base + 0x6004); + } else { + iowrite32(0x506E8C8C, pextp->base + 0x50A8); + iowrite32(0x18190000, pextp->base + 0x6004); + } + + if (is_10g) + iowrite32(0x01423342, pextp->base + 0x00F8); + else if (is_5g) + iowrite32(0x00A132A1, pextp->base + 0x00F8); + else if (is_2p5g) + iowrite32(0x009C329C, pextp->base + 0x00F8); + else + iowrite32(0x00FA32FA, pextp->base + 0x00F8); + + /* Force SGDT_OUT off and select PCS */ + if (mtk_interface_mode_is_xgmii(interface)) + iowrite32(0x80201F20, pextp->base + 0x00F4); + else + iowrite32(0x80201F21, pextp->base + 0x00F4); + + /* Force GLB_CKDET_OUT */ + iowrite32(0x00050C00, pextp->base + 0x0030); + + /* Force AEQ on */ + iowrite32(0x02002800, pextp->base + 0x0070); + ndelay(1020); + + /* Setup DA default value */ + iowrite32(0x00000020, pextp->base + 0x30B0); + iowrite32(0x00008A01, pextp->base + 0x3028); + iowrite32(0x0000A884, pextp->base + 0x302C); + iowrite32(0x00083002, pextp->base + 0x3024); + if (mtk_interface_mode_is_xgmii(interface)) { + iowrite32(0x00022220, pextp->base + 0x3010); + iowrite32(0x0F020A01, pextp->base + 0x5064); + iowrite32(0x06100600, pextp->base + 0x50B4); + if (interface == PHY_INTERFACE_MODE_USXGMII) + iowrite32(0x40704000, pextp->base + 0x3048); + else + iowrite32(0x47684100, pextp->base + 0x3048); + } else { + iowrite32(0x00011110, pextp->base + 0x3010); + iowrite32(0x40704000, pextp->base + 0x3048); + } + + if (!mtk_interface_mode_is_xgmii(interface) && !is_2p5g) + iowrite32(0x0000C000, pextp->base + 0x3064); + + if (interface == PHY_INTERFACE_MODE_USXGMII) { + iowrite32(0xA8000000, pextp->base + 0x3050); + iowrite32(0x000000AA, pextp->base + 0x3054); + } else if (mtk_interface_mode_is_xgmii(interface)) { + iowrite32(0x00000000, pextp->base + 0x3050); + iowrite32(0x00000000, pextp->base + 0x3054); + } else { + iowrite32(0xA8000000, pextp->base + 0x3050); + iowrite32(0x000000AA, pextp->base + 0x3054); + } + + if (mtk_interface_mode_is_xgmii(interface)) + iowrite32(0x00000F00, pextp->base + 0x306C); + else if (is_2p5g) + iowrite32(0x22000F00, pextp->base + 0x306C); + else + iowrite32(0x20200F00, pextp->base + 0x306C); + + if (interface == PHY_INTERFACE_MODE_10GBASER && pextp->da_war) + iowrite32(0x0007B400, pextp->base + 0xA008); + + if (mtk_interface_mode_is_xgmii(interface)) + iowrite32(0x00040000, pextp->base + 0xA060); + else + iowrite32(0x00050000, pextp->base + 0xA060); + + if (is_10g) + iowrite32(0x00000001, pextp->base + 0x90D0); + else if (is_5g) + iowrite32(0x00000003, pextp->base + 0x90D0); + else if (is_2p5g) + iowrite32(0x00000005, pextp->base + 0x90D0); + else + iowrite32(0x00000007, pextp->base + 0x90D0); + + /* Release reset */ + iowrite32(0x0200E800, pextp->base + 0x0070); + usleep_range(150, 500); + + /* Switch to P0 */ + iowrite32(0x0200C111, pextp->base + 0x0070); + ndelay(1020); + iowrite32(0x0200C101, pextp->base + 0x0070); + usleep_range(15, 50); + + if (mtk_interface_mode_is_xgmii(interface)) { + /* Switch to Gen3 */ + iowrite32(0x0202C111, pextp->base + 0x0070); + } else { + /* Switch to Gen2 */ + iowrite32(0x0201C111, pextp->base + 0x0070); + } + ndelay(1020); + if (mtk_interface_mode_is_xgmii(interface)) + iowrite32(0x0202C101, pextp->base + 0x0070); + else + iowrite32(0x0201C101, pextp->base + 0x0070); + usleep_range(100, 500); + iowrite32(0x00000030, pextp->base + 0x30B0); + if (mtk_interface_mode_is_xgmii(interface)) + iowrite32(0x80201F00, pextp->base + 0x00F4); + else + iowrite32(0x80201F01, pextp->base + 0x00F4); + + iowrite32(0x30000000, pextp->base + 0x3040); + usleep_range(400, 1000); +} + +static int mtk_pextp_set_mode(struct phy *phy, enum phy_mode mode, int submode) +{ + struct mtk_pextp_phy *pextp = phy_get_drvdata(phy); + + if (mode != PHY_MODE_ETHERNET) + return -EINVAL; + + switch (submode) { + case PHY_INTERFACE_MODE_1000BASEX: + case PHY_INTERFACE_MODE_2500BASEX: + case PHY_INTERFACE_MODE_SGMII: + case PHY_INTERFACE_MODE_5GBASER: + case PHY_INTERFACE_MODE_10GBASER: + case PHY_INTERFACE_MODE_USXGMII: + mtk_pextp_setup(pextp, submode); + return 0; + default: + return -EINVAL; + } +} + +static int mtk_pextp_reset(struct phy *phy) +{ + struct mtk_pextp_phy *pextp = phy_get_drvdata(phy); + + reset_control_assert(pextp->reset); + usleep_range(100, 500); + reset_control_deassert(pextp->reset); + mdelay(10); + + return 0; +} + +static int mtk_pextp_power_on(struct phy *phy) +{ + struct mtk_pextp_phy *pextp = phy_get_drvdata(phy); + + return clk_prepare_enable(pextp->clk); +} + +static int mtk_pextp_power_off(struct phy *phy) +{ + struct mtk_pextp_phy *pextp = phy_get_drvdata(phy); + + clk_disable_unprepare(pextp->clk); + + return 0; +} + +static const struct phy_ops mtk_pextp_ops = { + .power_on = mtk_pextp_power_on, + .power_off = mtk_pextp_power_off, + .set_mode = mtk_pextp_set_mode, + .reset = mtk_pextp_reset, + .owner = THIS_MODULE, +}; + +static int mtk_pextp_probe(struct platform_device *pdev) +{ + struct device_node *np = pdev->dev.of_node; + struct phy_provider *phy_provider; + struct mtk_pextp_phy *pextp; + struct phy *phy; + + if (!np) + return -ENODEV; + + pextp = devm_kzalloc(&pdev->dev, sizeof(*pextp), GFP_KERNEL); + if (!pextp) + return -ENOMEM; + + pextp->base = devm_of_iomap(&pdev->dev, np, 0, NULL); + if (!pextp->base) + return -EIO; + + pextp->dev = &pdev->dev; + pextp->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(pextp->clk)) + return PTR_ERR(pextp->clk); + + pextp->reset = devm_reset_control_get_exclusive(&pdev->dev, NULL); + if (IS_ERR(pextp->reset)) + return PTR_ERR(pextp->reset); + + pextp->da_war = of_property_read_bool(np, "mediatek,usxgmii-performance-errata"); + + phy = devm_phy_create(&pdev->dev, NULL, &mtk_pextp_ops); + if (IS_ERR(phy)) + return PTR_ERR(phy); + + phy_set_drvdata(phy, pextp); + + phy_provider = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(phy_provider); +} + +static const struct of_device_id mtk_pextp_match[] = { + { .compatible = "mediatek,mt7988-xfi-pextp", }, + { } +}; +MODULE_DEVICE_TABLE(of, mtk_pextp_match); + +static struct platform_driver mtk_pextp_driver = { + .probe = mtk_pextp_probe, + .driver = { + .name = "mtk-pextp", + .of_match_table = mtk_pextp_match, + }, +}; +module_platform_driver(mtk_pextp_driver); + +MODULE_DESCRIPTION("MediaTek pextp SerDes PHY driver"); +MODULE_AUTHOR("Daniel Golle "); +MODULE_LICENSE("GPL"); From patchwork Thu Nov 9 21:51:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Golle X-Patchwork-Id: 163613 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b129:0:b0:403:3b70:6f57 with SMTP id q9csp727674vqs; Thu, 9 Nov 2023 13:52:15 -0800 (PST) X-Google-Smtp-Source: AGHT+IGH7MEBtUfZa+wSV6Hwwo4IwFjZB+IWXeYf2ptx+rQEGXof2a40Zho6RsdRjKXjs2XUBuQq X-Received: by 2002:a17:90a:ba0f:b0:27d:375d:c16e with SMTP id s15-20020a17090aba0f00b0027d375dc16emr2863732pjr.42.1699566735297; Thu, 09 Nov 2023 13:52:15 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699566735; cv=none; d=google.com; s=arc-20160816; b=mpCI0xhkaHdiIuANgh4dct9TygOjysuvDKFxXt4ouuLSjN1xwnfBRReM5iAYSiWTzj ka8vSu+EkyaLOYOcZLtavtX8jAyRqkF+8OAt5J3EyyF/xjUKOpzGZ/iqxsm+9z/fVQeu KsT439au9gePZxgoBkcw2/hCsc1PHJw3ms7mIU42Y4VPDY0lwLVw7FSFWzZDBH7CC+rc 0PPExdLn+smlUTr0dj9/H0jKl93q68viNGLQvvcgFZTVQhvIwioIAZCldCErsUq8MtVK 8zy/O5jvkD5SSEyp2KcijXYt/3jUWi+/mn/lMkgcTHSz38EtIY5E/Koq4ufZuDxopahR 2UCQ== ARC-Message-Signature: i=1; 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[23.128.96.33]) by mx.google.com with ESMTPS id pc17-20020a17090b3b9100b00278eb61c0ebsi2716874pjb.118.2023.11.09.13.52.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Nov 2023 13:52:15 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) client-ip=23.128.96.33; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id 6B7A383038A2; Thu, 9 Nov 2023 13:52:11 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234657AbjKIVvs (ORCPT + 30 others); Thu, 9 Nov 2023 16:51:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37650 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345281AbjKIVvj (ORCPT ); Thu, 9 Nov 2023 16:51:39 -0500 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 56AE8420F; Thu, 9 Nov 2023 13:51:37 -0800 (PST) Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.96.2) (envelope-from ) id 1r1Cvu-0003Vy-0e; Thu, 09 Nov 2023 21:51:26 +0000 Date: Thu, 9 Nov 2023 21:51:22 +0000 From: Daniel Golle To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Felix Fietkau , John Crispin , Sean Wang , Mark Lee , Lorenzo Bianconi , Matthias Brugger , AngeloGioacchino Del Regno , Andrew Lunn , Heiner Kallweit , Russell King , Alexander Couzens , Daniel Golle , Philipp Zabel , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org Subject: [RFC PATCH 3/8] net: pcs: pcs-mtk-lynxi: use 2500Base-X without AN Message-ID: <091e466912f1333bb76d23e95dc6019c9b71645f.1699565880.git.daniel@makrotopia.org> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Thu, 09 Nov 2023 13:52:11 -0800 (PST) X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782124888822619234 X-GMAIL-MSGID: 1782124888822619234 Using 2500Base-T SFP modules e.g. on the BananaPi R3 requires manually disabling auto-negotiation, e.g. using ethtool. While a proper fix using SFP quirks is being discussed upstream, bring a work-around to restore user experience to what it was before the switch to the dedicated SGMII PCS driver. Signed-off-by: Daniel Golle --- drivers/net/pcs/pcs-mtk-lynxi.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/drivers/net/pcs/pcs-mtk-lynxi.c b/drivers/net/pcs/pcs-mtk-lynxi.c index 8501dd365279b..6204448d8eac6 100644 --- a/drivers/net/pcs/pcs-mtk-lynxi.c +++ b/drivers/net/pcs/pcs-mtk-lynxi.c @@ -92,14 +92,23 @@ static void mtk_pcs_lynxi_get_state(struct phylink_pcs *pcs, struct phylink_link_state *state) { struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs); - unsigned int bm, adv; + unsigned int bm, bmsr, adv; /* Read the BMSR and LPA */ regmap_read(mpcs->regmap, SGMSYS_PCS_CONTROL_1, &bm); - regmap_read(mpcs->regmap, SGMSYS_PCS_ADVERTISE, &adv); + bmsr = FIELD_GET(SGMII_BMSR, bm); + + if (state->interface == PHY_INTERFACE_MODE_2500BASEX) { + state->link = !!(bmsr & BMSR_LSTATUS); + state->an_complete = !!(bmsr & BMSR_ANEGCOMPLETE); + state->speed = SPEED_2500; + state->duplex = DUPLEX_FULL; + + return; + } - phylink_mii_c22_pcs_decode_state(state, FIELD_GET(SGMII_BMSR, bm), - FIELD_GET(SGMII_LPA, adv)); + regmap_read(mpcs->regmap, SGMSYS_PCS_ADVERTISE, &adv); + phylink_mii_c22_pcs_decode_state(state, bmsr, FIELD_GET(SGMII_LPA, adv)); } static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned int neg_mode, @@ -129,7 +138,8 @@ static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned int neg_mode, if (neg_mode & PHYLINK_PCS_NEG_INBAND) sgm_mode |= SGMII_REMOTE_FAULT_DIS; - if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) { + if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED && + interface != PHY_INTERFACE_MODE_2500BASEX) { if (interface == PHY_INTERFACE_MODE_SGMII) sgm_mode |= SGMII_SPEED_DUPLEX_AN; bmcr = BMCR_ANENABLE; From patchwork Thu Nov 9 21:51:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Golle X-Patchwork-Id: 163614 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b129:0:b0:403:3b70:6f57 with SMTP id q9csp727706vqs; Thu, 9 Nov 2023 13:52:19 -0800 (PST) X-Google-Smtp-Source: AGHT+IFdLfxSDZnvM3mJVq7902rvtsEtYWXeBbU3WnpESRF3K7w0MtgQkH1GfT+GSZcRLqumdsex X-Received: by 2002:a17:902:f7cc:b0:1cc:361b:7b10 with SMTP id h12-20020a170902f7cc00b001cc361b7b10mr5688220plw.24.1699566739356; Thu, 09 Nov 2023 13:52:19 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699566739; cv=none; d=google.com; s=arc-20160816; b=yAt0ptm/rbFTKEIpoR7snEt8GCuOeN/cC+SGNuldR5m/olM6acIK7XnRlYo3GIF7dO o5IARq7DDAJEPC8jcYBhBDLwH+UUvxC7XgzyPYzpYvBKyCOfDivG4G1fTnHKR8dQ3PAl IpmTE1RmeFglMH7s4tRAYNEMxKr4Rf7H+DEE2Ek9I3KGXABxT1q4r1+Dt3mNX+86tvUf 5f06eDybmGI5lvlJhJfKgOhKAdfRJTt+WezuC3KnNdYTxCmHdL1K88Ug6EDmZbFOQ16q VKZPUsE+azZwwkUTPijRIXM3pZiJAsra+sNz1WuE2YmozfNaayZosBF5vjoDyGNJNAvR o9Vw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:in-reply-to:content-disposition:mime-version :references:message-id:subject:to:from:date; bh=Kb+2yvlTQrGKxKDtG+tM4Xj4phSgbeCggxJFtRdqXbc=; fh=9GVzMIks0k0Waq6W0HUSHcdxejYnykUnl93AUDny5kk=; b=UbMpHqJheVhUwOuGWMn0C6A7R5I3k3k52QuRkLXB0p6+VF9o0dCxRXLf0SfXvdePPd oV9/rBFbMiqtl5e9HC2K8L2qwsWF3ReKwgOPK/USB64hX/exe/smJg+Z+6rj+RICyJ2P 19iwpMt4a6+D96YgYlv/ZK9OCwAKhhAlFmkAD3KAqUv0R7y9mWSKIV5hrOL2HibMrRP7 yH14TEpk3tAYEk/CA1mSzzbFJFF9ykmmxpjFOCfKFWmMER4DVEN00+iX4Q+iW2R0eccJ UxLTPan9tEJkftW9bZdWtRsPTy+ZJVV7ML9jHphoykkUVnVclzfbybTENRr5WY353Wzs AsaQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from agentk.vger.email (agentk.vger.email. [2620:137:e000::3:2]) by mx.google.com with ESMTPS id x12-20020a170902ec8c00b001c6183af4d3si6522500plg.332.2023.11.09.13.52.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Nov 2023 13:52:19 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) client-ip=2620:137:e000::3:2; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by agentk.vger.email (Postfix) with ESMTP id B59EB829B3E4; Thu, 9 Nov 2023 13:52:16 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at agentk.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345320AbjKIVwC (ORCPT + 30 others); Thu, 9 Nov 2023 16:52:02 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52262 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234801AbjKIVvv (ORCPT ); Thu, 9 Nov 2023 16:51:51 -0500 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6581B44B3; Thu, 9 Nov 2023 13:51:49 -0800 (PST) Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.96.2) (envelope-from ) id 1r1Cw6-0003XH-0Q; Thu, 09 Nov 2023 21:51:38 +0000 Date: Thu, 9 Nov 2023 21:51:34 +0000 From: Daniel Golle To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Felix Fietkau , John Crispin , Sean Wang , Mark Lee , Lorenzo Bianconi , Matthias Brugger , AngeloGioacchino Del Regno , Andrew Lunn , Heiner Kallweit , Russell King , Alexander Couzens , Daniel Golle , Philipp Zabel , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org Subject: [RFC PATCH 4/8] net: pcs: pcs-mtk-lynxi: allow calling with NULL advertising Message-ID: <0dcc5efc480b640d184046ba405a44bada88f88b.1699565880.git.daniel@makrotopia.org> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Thu, 09 Nov 2023 13:52:16 -0800 (PST) X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782124892936296510 X-GMAIL-MSGID: 1782124892936296510 Allow calling pcs_config with advertising set to NULL and in this case keep the previously assigned advertisement. Signed-off-by: Daniel Golle --- drivers/net/pcs/pcs-mtk-lynxi.c | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/net/pcs/pcs-mtk-lynxi.c b/drivers/net/pcs/pcs-mtk-lynxi.c index 6204448d8eac6..1372653c3d422 100644 --- a/drivers/net/pcs/pcs-mtk-lynxi.c +++ b/drivers/net/pcs/pcs-mtk-lynxi.c @@ -81,6 +81,7 @@ struct mtk_pcs_lynxi { phy_interface_t interface; struct phylink_pcs pcs; u32 flags; + int advertise; }; static struct mtk_pcs_lynxi *pcs_to_mtk_pcs_lynxi(struct phylink_pcs *pcs) @@ -121,11 +122,19 @@ static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned int neg_mode, unsigned int rgc3, sgm_mode, bmcr; int advertise, link_timer; - advertise = phylink_mii_c22_pcs_encode_advertisement(interface, - advertising); - if (advertise < 0) - return advertise; + if (advertising) { + advertise = phylink_mii_c22_pcs_encode_advertisement(interface, + advertising); + if (advertise < 0) + return advertise; + mpcs->advertise = advertise; + } else { + if (mpcs->advertise < 0) + return -EINVAL; + + advertise = mpcs->advertise; + } /* Clearing IF_MODE_BIT0 switches the PCS to BASE-X mode, and * we assume that fixes it's speed at bitrate = line rate (in * other words, 1000Mbps or 2500Mbps). @@ -299,6 +308,7 @@ struct phylink_pcs *mtk_pcs_lynxi_create(struct device *dev, mpcs->pcs.neg_mode = true; mpcs->pcs.poll = true; mpcs->interface = PHY_INTERFACE_MODE_NA; + mpcs->advertise = -1; return &mpcs->pcs; } From patchwork Thu Nov 9 21:51:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Golle X-Patchwork-Id: 163616 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b129:0:b0:403:3b70:6f57 with SMTP id q9csp728235vqs; Thu, 9 Nov 2023 13:53:43 -0800 (PST) X-Google-Smtp-Source: AGHT+IFGef4Kfmp+rMAWp/Yu9RyZflCIGezw/13obod2p+sxeyxNxoxsq//NkqW1pI+TI9dHQqH3 X-Received: by 2002:a05:6a21:33a9:b0:184:9f3d:f7dd with SMTP id yy41-20020a056a2133a900b001849f3df7ddmr6370055pzb.29.1699566822929; Thu, 09 Nov 2023 13:53:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699566822; cv=none; d=google.com; s=arc-20160816; b=S6WlnFND70cPiRhfX3WXQY/H4QqTyLGZiH17sddIa0fbJS6FJ7O721zwdlJFA8Ec62 gExamRvYtkq8MwfsufaPAiMUe5lhlWE3WTFAnux21P9acwFqZmNbZvGAVcMdJd49jrQr YFUXFJpH+eTqnfO/pJZe2ctgZHHS9OcczYObIrm6b4A5L5lBOlPhjqSH3WIR4NheJGGH O38KEzZdqN7Ox+hGZiBE09ed8qXK03n2bad5k4SrstFwKgpMx/sH0dDc5hrQIo/5nNBo 693g7uZSrRp2BVLKdhKD4NRBZw9KqpbgcZywTuxvmmQ5XuOvuXVSszxqa6QK5NesE9O2 hp9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:in-reply-to:content-disposition:mime-version :references:message-id:subject:to:from:date; bh=ZM+SCmKkNB/P4aatmpnUY/Tqe989m6CqxBgRf6EbxDE=; fh=9GVzMIks0k0Waq6W0HUSHcdxejYnykUnl93AUDny5kk=; b=zuZcZh+Jf4alx4aII77dxXDaqEguTZZ8DCWIS2JRh516Wd/flC+gg0eI18I1Q3xxVB 3xDzbmjlXu5r81bu4XW2xndnT6UG7JpXe8auODuVhnyiJHVnmP7kQk6TenSt6m+qwhQS Q8MYPAP8jiZ918ttWVOgiqb5izzzCfh5GQP75JS4q+xe3y2nWREBSs64SbcLxxaEX8nZ KSGvNgbYcWWmgDO63SGBReWmNKaHhEgX4XY1JMpfwa+c+p5rKuVSWwQapZxKytt914RQ hLkZYdOhpiz8ddHY06hkloYqWioYBd6xsaFducyDtMTriI8HwV7kWbBWdCjgvLlBGCCd 3zyQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from fry.vger.email (fry.vger.email. [2620:137:e000::3:8]) by mx.google.com with ESMTPS id s191-20020a632cc8000000b005b7dd20f8c1si7651940pgs.20.2023.11.09.13.53.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Nov 2023 13:53:42 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) client-ip=2620:137:e000::3:8; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by fry.vger.email (Postfix) with ESMTP id BCD6780E4A00; Thu, 9 Nov 2023 13:52:47 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at fry.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345297AbjKIVwM (ORCPT + 30 others); Thu, 9 Nov 2023 16:52:12 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47652 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345330AbjKIVwE (ORCPT ); Thu, 9 Nov 2023 16:52:04 -0500 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5B46C1FDF; Thu, 9 Nov 2023 13:52:02 -0800 (PST) Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.96.2) (envelope-from ) id 1r1CwI-0003Y5-34; Thu, 09 Nov 2023 21:51:51 +0000 Date: Thu, 9 Nov 2023 21:51:47 +0000 From: Daniel Golle To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Felix Fietkau , John Crispin , Sean Wang , Mark Lee , Lorenzo Bianconi , Matthias Brugger , AngeloGioacchino Del Regno , Andrew Lunn , Heiner Kallweit , Russell King , Alexander Couzens , Daniel Golle , Philipp Zabel , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org Subject: [RFC PATCH 5/8] dt-bindings: net: pcs: add bindings for MediaTek USXGMII PCS Message-ID: <2dff6aff7006573d3232ec2ddd93c1792740d4d3.1699565880.git.daniel@makrotopia.org> References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Thu, 09 Nov 2023 13:52:47 -0800 (PST) X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782124980614995384 X-GMAIL-MSGID: 1782124980614995384 MediaTek's USXGMII can be found in the MT7988 SoC. We need to access it in order to configure and monitor the Ethernet SerDes link in USXGMII, 10GBase-R and 5GBase-R mode. By including a wrapped legacy 1000Base-X/2500Base-X/Cisco SGMII LynxI PCS as well, those interface modes are also available. Signed-off-by: Daniel Golle --- .../bindings/net/pcs/mediatek,usxgmii.yaml | 105 ++++++++++++++++++ 1 file changed, 105 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml diff --git a/Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml b/Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml new file mode 100644 index 0000000000000..199cf47859e31 --- /dev/null +++ b/Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/pcs/mediatek,usxgmii.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek USXGMII PCS + +maintainers: + - Daniel Golle + +description: + The MediaTek USXGMII PCS provides physical link control and status + for USXGMII, 10GBase-R and 5GBase-R links on the SerDes interfaces + provided by the PEXTP PHY. + In order to also support legacy 2500Base-X, 1000Base-X and Cisco + SGMII an existing mediatek,*-sgmiisys LynxI PCS is wrapped to + provide those interfaces modes on the same SerDes interfaces shared + with the USXGMII PCS. + +properties: + $nodename: + pattern: "^pcs@[0-9a-f]+$" + + compatible: + const: mediatek,mt7988-usxgmiisys + + reg: + maxItems: 1 + + clocks: + items: + - description: USXGMII top-level clock + - description: SGMII top-level clock + - description: SGMII subsystem TX clock + - description: SGMII subsystem RX clock + - description: XFI PLL clock + + clock-names: + items: + - const: usxgmii + - const: sgmii_sel + - const: sgmii_tx + - const: sgmii_rx + - const: xfi_pll + + phys: + items: + - description: PEXTP SerDes PHY + + mediatek,sgmiisys: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the syscon node of the corresponding SGMII LynxI PCS. + + resets: + items: + - description: XFI reset + - description: SGMII reset + + reset-names: + items: + - const: xfi + - const: sgmii + + "#pcs-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - phys + - mediatek,sgmiisys + - resets + - reset-names + - "#pcs-cells" + +additionalProperties: false + +examples: + - | + #include + #include + soc { + #address-cells = <2>; + #size-cells = <2>; + usxgmiisys0: pcs@10080000 { + compatible = "mediatek,mt7988-usxgmiisys"; + reg = <0 0x10080000 0 0x1000>; + clocks = <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>, + <&topckgen CLK_TOP_SGM_0_SEL>, + <&sgmiisys0 CLK_SGM0_TX_EN>, + <&sgmiisys0 CLK_SGM0_RX_EN>, + <&xfi_pll CLK_XFIPLL_PLL_EN>; + clock-names = "usxgmii", "sgmii_sel", "sgmii_tx", "sgmii_rx", "xfi_pll"; + resets = <&watchdog MT7988_TOPRGU_XFI0_GRST>, + <&watchdog MT7988_TOPRGU_SGMII0_GRST>; + reset-names = "xfi", "sgmii"; + phys = <&xfi_pextp0>; + mediatek,sgmiisys = <&sgmiisys0>; + #pcs-cells = <0>; + }; + }; From patchwork Thu Nov 9 21:52:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Golle X-Patchwork-Id: 163615 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b129:0:b0:403:3b70:6f57 with SMTP id q9csp728146vqs; Thu, 9 Nov 2023 13:53:29 -0800 (PST) X-Google-Smtp-Source: AGHT+IHeugjY/8KYMvRremU6TwwOkUR4qBhbyFr9nybbX+yANckayYBfRzGmtL4HgcGKYFgThVbw X-Received: by 2002:a9d:7ad1:0:b0:6c6:50d0:1104 with SMTP id m17-20020a9d7ad1000000b006c650d01104mr6021601otn.27.1699566809500; Thu, 09 Nov 2023 13:53:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699566809; cv=none; d=google.com; s=arc-20160816; b=woiQ1iSZ1Q7QzthH20He/jaYeEg+eZMHxl2gA6bOdF3nR6agAWugntN2WCryIWOvNA sHi0jOwqr6t4FquDP5fwZ7qWK+lsYclhMkcD0VhIDym59LDUsdCR4E+vSvmJr5Sw/ft4 LQAdiMbxtIHc4+SvphgAnICgf5NPGkit+0hVlVSfYbrUhibUyPGY7Xd4L2Zhxt9YPmHU UeSuvBfn1nLChIU8J2gedvuWeEdF+oKYazAbGkLUwNysdkWG9HGomtl3dmAcEZJ3gNKV BDjU/plLa4y1nOwnFeYKuG7Bc3lRozlhgMZ92GaPKnHdpcjUhndp5l4PCeg8c9W4J6b+ Y52w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:in-reply-to:content-disposition:mime-version :references:message-id:subject:to:from:date; bh=SVwc/Y8Pq8Ul6FZvgitLjyCqTq/k9+wbnwlGd0tbbRM=; fh=9GVzMIks0k0Waq6W0HUSHcdxejYnykUnl93AUDny5kk=; b=FPQICfKBsDOW3WoBVXPkYLeapm15IpTuu0c9WxA1zu8gL/DwRFNWz6LF0EUKG0HZMg FizQiannRrylzyfxxrhkWAPVVfOZdLYLgCYze+Qya4NmseRd3pQPB19X7pzP23sMZWM9 O6CGK9wtXQtxuWt2b8XLisRridHnHKvRnQD32b4RQF/FXZNwDJPBL2iuTuywKVyDy90u yCYwPLPNkPpDh1k7QTmWExFVHJ4dDivVB5crnsWmKxrltFrvKX3wIseIIJZznxMeLgwp z6BYtJWLRy9IEeLqt4ZFmywbvP4SyS/0qc8WG4HfpoT1aabPiMHdpivhsda5YHiNt4O/ Yg+Q== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from lipwig.vger.email (lipwig.vger.email. [23.128.96.33]) by mx.google.com with ESMTPS id v135-20020a63618d000000b0055c1760dd8esi8071069pgb.380.2023.11.09.13.53.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 09 Nov 2023 13:53:29 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) client-ip=23.128.96.33; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id A068A807C564; Thu, 9 Nov 2023 13:53:05 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234775AbjKIVwd (ORCPT + 30 others); Thu, 9 Nov 2023 16:52:33 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57434 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234801AbjKIVw0 (ORCPT ); Thu, 9 Nov 2023 16:52:26 -0500 Received: from pidgin.makrotopia.org (pidgin.makrotopia.org [185.142.180.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D592544B0; Thu, 9 Nov 2023 13:52:23 -0800 (PST) Received: from local by pidgin.makrotopia.org with esmtpsa (TLS1.3:TLS_AES_256_GCM_SHA384:256) (Exim 4.96.2) (envelope-from ) id 1r1Cwf-0003ZR-1R; Thu, 09 Nov 2023 21:52:13 +0000 Date: Thu, 9 Nov 2023 21:52:09 +0000 From: Daniel Golle To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chunfeng Yun , Vinod Koul , Kishon Vijay Abraham I , Felix Fietkau , John Crispin , Sean Wang , Mark Lee , Lorenzo Bianconi , Matthias Brugger , AngeloGioacchino Del Regno , Andrew Lunn , Heiner Kallweit , Russell King , Alexander Couzens , Daniel Golle , Philipp Zabel , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org Subject: [RFC PATCH 7/8] dt-bindings: net: mediatek,net: fix and complete mt7988-eth binding Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Thu, 09 Nov 2023 13:53:05 -0800 (PST) X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782124966811800365 X-GMAIL-MSGID: 1782124966811800365 Remove clocks which were copied from the vendor driver but are now taken care of by dedicated drivers for PCS and PHY in the upstream driver. Also remove mediatek,sgmiisys phandle which isn't required on MT7988 because we use pcs-handle on the MAC nodes instead. Last but not least, add an example for MT7988. Fixes: c94a9aabec36 ("dt-bindings: net: mediatek,net: add mt7988-eth binding") Signed-off-by: Daniel Golle --- .../devicetree/bindings/net/mediatek,net.yaml | 171 +++++++++++++++--- 1 file changed, 142 insertions(+), 29 deletions(-) diff --git a/Documentation/devicetree/bindings/net/mediatek,net.yaml b/Documentation/devicetree/bindings/net/mediatek,net.yaml index e74502a0afe86..c0f7bb6f3ef8d 100644 --- a/Documentation/devicetree/bindings/net/mediatek,net.yaml +++ b/Documentation/devicetree/bindings/net/mediatek,net.yaml @@ -27,9 +27,6 @@ properties: - mediatek,mt7988-eth - ralink,rt5350-eth - reg: - maxItems: 1 - clocks: true clock-names: true @@ -115,6 +112,9 @@ allOf: - mediatek,mt7623-eth then: properties: + reg: + maxItems: 1 + interrupts: maxItems: 3 @@ -149,6 +149,9 @@ allOf: - mediatek,mt7621-eth then: properties: + reg: + maxItems: 1 + interrupts: maxItems: 1 @@ -174,6 +177,9 @@ allOf: const: mediatek,mt7622-eth then: properties: + reg: + maxItems: 1 + interrupts: maxItems: 3 @@ -215,6 +221,9 @@ allOf: const: mediatek,mt7629-eth then: properties: + reg: + maxItems: 1 + interrupts: maxItems: 3 @@ -257,6 +266,9 @@ allOf: const: mediatek,mt7981-eth then: properties: + reg: + maxItems: 1 + interrupts: minItems: 4 @@ -295,6 +307,9 @@ allOf: const: mediatek,mt7986-eth then: properties: + reg: + maxItems: 1 + interrupts: minItems: 4 @@ -333,36 +348,32 @@ allOf: const: mediatek,mt7988-eth then: properties: + reg: + maxItems: 2 + minItems: 2 + interrupts: minItems: 4 + maxItems: 4 clocks: - minItems: 34 - maxItems: 34 + minItems: 24 + maxItems: 24 clock-names: items: - - const: crypto + - const: xgp1 + - const: xgp2 + - const: xgp3 - const: fe - const: gp2 - const: gp1 - const: gp3 + - const: esw + - const: crypto - const: ethwarp_wocpu2 - const: ethwarp_wocpu1 - const: ethwarp_wocpu0 - - const: esw - - const: netsys0 - - const: netsys1 - - const: sgmii_tx250m - - const: sgmii_rx250m - - const: sgmii2_tx250m - - const: sgmii2_rx250m - - const: top_usxgmii0_sel - - const: top_usxgmii1_sel - - const: top_sgm0_sel - - const: top_sgm1_sel - - const: top_xfi_phy0_xtal_sel - - const: top_xfi_phy1_xtal_sel - const: top_eth_gmii_sel - const: top_eth_refck_50m_sel - const: top_eth_sys_200m_sel @@ -375,18 +386,9 @@ allOf: - const: top_netsys_sync_250m_sel - const: top_netsys_ppefb_250m_sel - const: top_netsys_warp_sel - - const: wocpu1 - - const: wocpu0 - - const: xgp1 - - const: xgp2 - - const: xgp3 - - mediatek,sgmiisys: - minItems: 2 - maxItems: 2 patternProperties: - "^mac@[0-1]$": + "^mac@[0-2]$": type: object unevaluatedProperties: false allOf: @@ -577,3 +579,114 @@ examples: }; }; }; + + - | + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + ethernet@15100000 { + compatible = "mediatek,mt7988-eth"; + reg = <0 0x15100000 0 0x80000>, <0 0x15400000 0 0x380000>; + interrupts = , + , + , + ; + + clocks = <ðsys CLK_ETHDMA_XGP1_EN>, + <ðsys CLK_ETHDMA_XGP2_EN>, + <ðsys CLK_ETHDMA_XGP3_EN>, + <ðsys CLK_ETHDMA_FE_EN>, + <ðsys CLK_ETHDMA_GP2_EN>, + <ðsys CLK_ETHDMA_GP1_EN>, + <ðsys CLK_ETHDMA_GP3_EN>, + <ðsys CLK_ETHDMA_ESW_EN>, + <ðsys CLK_ETHDMA_CRYPT0_EN>, + <ðwarp CLK_ETHWARP_WOCPU2_EN>, + <ðwarp CLK_ETHWARP_WOCPU1_EN>, + <ðwarp CLK_ETHWARP_WOCPU0_EN>, + <&topckgen CLK_TOP_ETH_GMII_SEL>, + <&topckgen CLK_TOP_ETH_REFCK_50M_SEL>, + <&topckgen CLK_TOP_ETH_SYS_200M_SEL>, + <&topckgen CLK_TOP_ETH_SYS_SEL>, + <&topckgen CLK_TOP_ETH_XGMII_SEL>, + <&topckgen CLK_TOP_ETH_MII_SEL>, + <&topckgen CLK_TOP_NETSYS_SEL>, + <&topckgen CLK_TOP_NETSYS_500M_SEL>, + <&topckgen CLK_TOP_NETSYS_PAO_2X_SEL>, + <&topckgen CLK_TOP_NETSYS_SYNC_250M_SEL>, + <&topckgen CLK_TOP_NETSYS_PPEFB_250M_SEL>, + <&topckgen CLK_TOP_NETSYS_WARP_SEL>; + + clock-names = "xgp1", "xgp2", "xgp3", "fe", "gp2", "gp1", + "gp3", "esw", "crypto", + "ethwarp_wocpu2", "ethwarp_wocpu1", + "ethwarp_wocpu0", "top_eth_gmii_sel", + "top_eth_refck_50m_sel", "top_eth_sys_200m_sel", + "top_eth_sys_sel", "top_eth_xgmii_sel", + "top_eth_mii_sel", "top_netsys_sel", + "top_netsys_500m_sel", "top_netsys_pao_2x_sel", + "top_netsys_sync_250m_sel", + "top_netsys_ppefb_250m_sel", + "top_netsys_warp_sel"; + assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>, + <&topckgen CLK_TOP_NETSYS_GSW_SEL>, + <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>, + <&topckgen CLK_TOP_USXGMII_SBUS_1_SEL>, + <&topckgen CLK_TOP_SGM_0_SEL>, + <&topckgen CLK_TOP_SGM_1_SEL>; + assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>, + <&topckgen CLK_TOP_NET1PLL_D4>, + <&topckgen CLK_TOP_NET1PLL_D8_D4>, + <&topckgen CLK_TOP_NET1PLL_D8_D4>, + <&apmixedsys CLK_APMIXED_SGMPLL>, + <&apmixedsys CLK_APMIXED_SGMPLL>; + mediatek,ethsys = <ðsys>; + mediatek,infracfg = <&topmisc>; + #address-cells = <1>; + #size-cells = <0>; + + mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "internal"; + status = "disabled"; + + fixed-link { + speed = <10000>; + full-duplex; + pause; + }; + }; + + mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + status = "disabled"; + pcs-handle = <&usxgmiisys1>; + }; + + mac@2 { + compatible = "mediatek,eth-mac"; + reg = <2>; + status = "disabled"; + pcs-handle = <&usxgmiisys0>; + }; + + mdio_bus: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + + /* internal 2.5G PHY */ + int_2p5g_phy: ethernet-phy@15 { + reg = <15>; + compatible = "ethernet-phy-ieee802.3-c45"; + phy-mode = "internal"; + }; + }; + }; + };