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Thu, 09 Nov 2023 13:22:00 -0800 (PST) X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782122994504482121 X-GMAIL-MSGID: 1782122994504482121 Using help macro fsl_edma_set(get)_tcd() to handle difference field size. This is not function change and prepare for 64bit tcd in imx95. Signed-off-by: Frank Li --- drivers/dma/fsl-edma-common.c | 61 ++++++++++++++++++----------------- drivers/dma/fsl-edma-common.h | 20 ++++++++++++ 2 files changed, 51 insertions(+), 30 deletions(-) diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c index 6a3abe5b17908..1cd9cf51b16eb 100644 --- a/drivers/dma/fsl-edma-common.c +++ b/drivers/dma/fsl-edma-common.c @@ -358,10 +358,10 @@ static size_t fsl_edma_desc_residue(struct fsl_edma_chan *fsl_chan, /* calculate the total size in this desc */ for (len = i = 0; i < fsl_chan->edesc->n_tcds; i++) { - nbytes = le32_to_cpu(edesc->tcd[i].vtcd->nbytes); + nbytes = fsl_edma_get_tcd_to_cpu(fsl_chan, edesc->tcd[i].vtcd, nbytes); if (nbytes & (EDMA_V3_TCD_NBYTES_DMLOE | EDMA_V3_TCD_NBYTES_SMLOE)) nbytes = EDMA_V3_TCD_NBYTES_MLOFF_NBYTES(nbytes); - len += nbytes * le16_to_cpu(edesc->tcd[i].vtcd->biter); + len += nbytes * fsl_edma_get_tcd_to_cpu(fsl_chan, edesc->tcd[i].vtcd, biter); } if (!in_progress) @@ -374,16 +374,16 @@ static size_t fsl_edma_desc_residue(struct fsl_edma_chan *fsl_chan, /* figure out the finished and calculate the residue */ for (i = 0; i < fsl_chan->edesc->n_tcds; i++) { - nbytes = le32_to_cpu(edesc->tcd[i].vtcd->nbytes); + nbytes = fsl_edma_get_tcd_to_cpu(fsl_chan, edesc->tcd[i].vtcd, nbytes); if (nbytes & (EDMA_V3_TCD_NBYTES_DMLOE | EDMA_V3_TCD_NBYTES_SMLOE)) nbytes = EDMA_V3_TCD_NBYTES_MLOFF_NBYTES(nbytes); - size = nbytes * le16_to_cpu(edesc->tcd[i].vtcd->biter); + size = nbytes * fsl_edma_get_tcd_to_cpu(fsl_chan, edesc->tcd[i].vtcd, biter); if (dir == DMA_MEM_TO_DEV) - dma_addr = le32_to_cpu(edesc->tcd[i].vtcd->saddr); + dma_addr = fsl_edma_get_tcd_to_cpu(fsl_chan, edesc->tcd[i].vtcd, saddr); else - dma_addr = le32_to_cpu(edesc->tcd[i].vtcd->daddr); + dma_addr = fsl_edma_get_tcd_to_cpu(fsl_chan, edesc->tcd[i].vtcd, daddr); len -= size; if (cur_addr >= dma_addr && cur_addr < dma_addr + size) { @@ -439,26 +439,26 @@ static void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan, */ edma_write_tcdreg(fsl_chan, 0, csr); - edma_write_tcdreg(fsl_chan, tcd->saddr, saddr); - edma_write_tcdreg(fsl_chan, tcd->daddr, daddr); + edma_write_tcdreg(fsl_chan, fsl_edma_get_tcd(fsl_chan, tcd, saddr), saddr); + edma_write_tcdreg(fsl_chan, fsl_edma_get_tcd(fsl_chan, tcd, daddr), daddr); - edma_write_tcdreg(fsl_chan, tcd->attr, attr); - edma_write_tcdreg(fsl_chan, tcd->soff, soff); + edma_write_tcdreg(fsl_chan, fsl_edma_get_tcd(fsl_chan, tcd, attr), attr); + edma_write_tcdreg(fsl_chan, fsl_edma_get_tcd(fsl_chan, tcd, soff), soff); - edma_write_tcdreg(fsl_chan, tcd->nbytes, nbytes); - edma_write_tcdreg(fsl_chan, tcd->slast, slast); + edma_write_tcdreg(fsl_chan, fsl_edma_get_tcd(fsl_chan, tcd, nbytes), nbytes); + edma_write_tcdreg(fsl_chan, fsl_edma_get_tcd(fsl_chan, tcd, slast), slast); - edma_write_tcdreg(fsl_chan, tcd->citer, citer); - edma_write_tcdreg(fsl_chan, tcd->biter, biter); - edma_write_tcdreg(fsl_chan, tcd->doff, doff); + edma_write_tcdreg(fsl_chan, fsl_edma_get_tcd(fsl_chan, tcd, citer), citer); + edma_write_tcdreg(fsl_chan, fsl_edma_get_tcd(fsl_chan, tcd, biter), biter); + edma_write_tcdreg(fsl_chan, fsl_edma_get_tcd(fsl_chan, tcd, doff), doff); - edma_write_tcdreg(fsl_chan, tcd->dlast_sga, dlast_sga); + edma_write_tcdreg(fsl_chan, fsl_edma_get_tcd(fsl_chan, tcd, dlast_sga), dlast_sga); - csr = le16_to_cpu(tcd->csr); + csr = fsl_edma_get_tcd_to_cpu(fsl_chan, tcd, csr); if (fsl_chan->is_sw) { csr |= EDMA_TCD_CSR_START; - tcd->csr = cpu_to_le16(csr); + fsl_edma_set_tcd_to_le(fsl_chan, tcd, csr, csr); } /* @@ -473,7 +473,7 @@ static void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan, edma_writel_chreg(fsl_chan, edma_readl_chreg(fsl_chan, ch_csr), ch_csr); - edma_write_tcdreg(fsl_chan, tcd->csr, csr); + edma_write_tcdreg(fsl_chan, fsl_edma_get_tcd(fsl_chan, tcd, csr), csr); } static inline @@ -493,12 +493,12 @@ void fsl_edma_fill_tcd(struct fsl_edma_chan *fsl_chan, * So we put the value in little endian in memory, waiting * for fsl_edma_set_tcd_regs doing the swap. */ - tcd->saddr = cpu_to_le32(src); - tcd->daddr = cpu_to_le32(dst); + fsl_edma_set_tcd_to_le(fsl_chan, tcd, src, saddr); + fsl_edma_set_tcd_to_le(fsl_chan, tcd, dst, daddr); - tcd->attr = cpu_to_le16(attr); + fsl_edma_set_tcd_to_le(fsl_chan, tcd, attr, attr); - tcd->soff = cpu_to_le16(soff); + fsl_edma_set_tcd_to_le(fsl_chan, tcd, soff, soff); if (fsl_chan->is_multi_fifo) { /* set mloff to support multiple fifo */ @@ -515,15 +515,16 @@ void fsl_edma_fill_tcd(struct fsl_edma_chan *fsl_chan, } } - tcd->nbytes = cpu_to_le32(nbytes); - tcd->slast = cpu_to_le32(slast); + fsl_edma_set_tcd_to_le(fsl_chan, tcd, nbytes, nbytes); + fsl_edma_set_tcd_to_le(fsl_chan, tcd, slast, slast); - tcd->citer = cpu_to_le16(EDMA_TCD_CITER_CITER(citer)); - tcd->doff = cpu_to_le16(doff); + fsl_edma_set_tcd_to_le(fsl_chan, tcd, EDMA_TCD_CITER_CITER(citer), citer); + fsl_edma_set_tcd_to_le(fsl_chan, tcd, doff, doff); - tcd->dlast_sga = cpu_to_le32(dlast_sga); + fsl_edma_set_tcd_to_le(fsl_chan, tcd, dlast_sga, dlast_sga); + + fsl_edma_set_tcd_to_le(fsl_chan, tcd, EDMA_TCD_BITER_BITER(biter), biter); - tcd->biter = cpu_to_le16(EDMA_TCD_BITER_BITER(biter)); if (major_int) csr |= EDMA_TCD_CSR_INT_MAJOR; @@ -539,7 +540,7 @@ void fsl_edma_fill_tcd(struct fsl_edma_chan *fsl_chan, if (fsl_chan->is_sw) csr |= EDMA_TCD_CSR_START; - tcd->csr = cpu_to_le16(csr); + fsl_edma_set_tcd_to_le(fsl_chan, tcd, csr, csr); } static struct fsl_edma_desc *fsl_edma_alloc_desc(struct fsl_edma_chan *fsl_chan, diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h index bb5221158a770..72104d775e562 100644 --- a/drivers/dma/fsl-edma-common.h +++ b/drivers/dma/fsl-edma-common.h @@ -246,6 +246,26 @@ struct fsl_edma_engine { edma_writel(chan->edma, val, \ (void __iomem *)&(container_of(chan->tcd, struct fsl_edma3_ch_reg, tcd)->__name)) +#define fsl_edma_get_tcd(_chan, _tcd, _field) ((_tcd)->_field) + +#define fsl_edma_le_to_cpu(x) \ +(sizeof(x) == sizeof(u32) ? le32_to_cpu(x) : le16_to_cpu(x)) + +#define fsl_edma_get_tcd_to_cpu(_chan, _tcd, _field) \ +fsl_edma_le_to_cpu(fsl_edma_get_tcd(_chan, _tcd, _field)) + +#define fsl_edma_set_tcd_to_le(_fsl_chan, _tcd, _val, _field) \ +do { \ + switch (sizeof((_tcd)->_field)) { \ + case sizeof(u32): \ + (_tcd)->_field = cpu_to_le32(_val); \ + break; \ + case sizeof(u16): \ + (_tcd)->_field = cpu_to_le16(_val); \ + break; \ + } \ +} while (0) + /* * R/W functions for big- or little-endian registers: * The eDMA controller's endian is independent of the CPU core's endian. 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Thu, 09 Nov 2023 13:22:07 -0800 (PST) X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782123006610017916 X-GMAIL-MSGID: 1782123006610017916 iMX95 move channel mux register to management page address space. This prepare to support iMX95. Add mux_addr in struct fsl_edma_chan. No function change. Signed-off-by: Frank Li --- drivers/dma/fsl-edma-common.c | 6 +++--- drivers/dma/fsl-edma-common.h | 3 +++ drivers/dma/fsl-edma-main.c | 3 +++ 3 files changed, 9 insertions(+), 3 deletions(-) diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c index 1cd9cf51b16eb..d29824ed7c80f 100644 --- a/drivers/dma/fsl-edma-common.c +++ b/drivers/dma/fsl-edma-common.c @@ -97,8 +97,8 @@ static void fsl_edma3_enable_request(struct fsl_edma_chan *fsl_chan) * ch_mux: With the exception of 0, attempts to write a value * already in use will be forced to 0. */ - if (!edma_readl_chreg(fsl_chan, ch_mux)) - edma_writel_chreg(fsl_chan, fsl_chan->srcid, ch_mux); + if (!edma_readl(fsl_chan->edma, fsl_chan->mux_addr)) + edma_writel(fsl_chan->edma, fsl_chan->srcid, fsl_chan->mux_addr); } val = edma_readl_chreg(fsl_chan, ch_csr); @@ -134,7 +134,7 @@ static void fsl_edma3_disable_request(struct fsl_edma_chan *fsl_chan) flags = fsl_edma_drvflags(fsl_chan); if (flags & FSL_EDMA_DRV_HAS_CHMUX) - edma_writel_chreg(fsl_chan, 0, ch_mux); + edma_writel(fsl_chan->edma, 0, fsl_chan->mux_addr); val &= ~EDMA_V3_CH_CSR_ERQ; edma_writel_chreg(fsl_chan, val, ch_csr); diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h index 72104d775e562..6c738c5cad118 100644 --- a/drivers/dma/fsl-edma-common.h +++ b/drivers/dma/fsl-edma-common.h @@ -145,6 +145,7 @@ struct fsl_edma_chan { enum dma_data_direction dma_dir; char chan_name[32]; struct fsl_edma_hw_tcd __iomem *tcd; + void __iomem *mux_addr; u32 real_count; struct work_struct issue_worker; struct platform_device *pdev; @@ -206,6 +207,8 @@ struct fsl_edma_drvdata { u32 chreg_off; u32 chreg_space_sz; u32 flags; + u32 mux_off; /* channel mux register offset */ + u32 mux_skip; /* how much skip for each channel */ int (*setup_irq)(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma); }; diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c index 4635e16d7705e..8e5ddeb5e887f 100644 --- a/drivers/dma/fsl-edma-main.c +++ b/drivers/dma/fsl-edma-main.c @@ -356,6 +356,8 @@ static struct fsl_edma_drvdata imx93_data4 = { .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA4, .chreg_space_sz = 0x8000, .chreg_off = 0x10000, + .mux_off = 0x10000 + offsetof(struct fsl_edma3_ch_reg, ch_mux), + .mux_skip = 0x8000, .setup_irq = fsl_edma3_irq_init, }; @@ -530,6 +532,7 @@ static int fsl_edma_probe(struct platform_device *pdev) offsetof(struct fsl_edma3_ch_reg, tcd) : 0; fsl_chan->tcd = fsl_edma->membase + i * drvdata->chreg_space_sz + drvdata->chreg_off + len; + fsl_chan->mux_addr = fsl_edma->membase + drvdata->mux_off + i * drvdata->mux_skip; fsl_chan->pdev = pdev; vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev); From patchwork Thu Nov 9 21:20:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 163602 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b129:0:b0:403:3b70:6f57 with SMTP id q9csp714592vqs; Thu, 9 Nov 2023 13:22:20 -0800 (PST) X-Google-Smtp-Source: AGHT+IF2tEnHH7YYo54Vx6zxPTtw3kV80PVCAkYhRdHcodiZwO+016ZHyDWA63gwFH4PfZqG214j X-Received: by 2002:a17:903:124e:b0:1cc:636f:f376 with SMTP id u14-20020a170903124e00b001cc636ff376mr6381337plh.44.1699564940076; Thu, 09 Nov 2023 13:22:20 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1699564940; cv=pass; d=google.com; s=arc-20160816; b=Tl7ir+P6u6xXWuVTSqe95QeV1UM9isZn/NmEXI0RczCLYDFAJXBEbL7k6SRkuuK2ny VexDqUeNFyutHRnxA/gsWoBBuhyNjUa/Ala7/9HC+ti7ViXs7Pu7FSWv0vFRkYjYEc98 P7ui/SdUZpbqvwX/iICXA+XyHAql6IVLNGUmDHrAg+OGMg1QvhaU8F1Va73dSX5hZTJA 109fwEXUYCCNVsRW4nWSY48BnfwgnR8s3ImCeMnEsRHmj5gv8WC0johM8mcrOZWa8Sq9 NMkobYAeFPZ26NMNdZeuj5oPTHeqYNPUEdVMaNuv4SvEFCQ9ohg0jZLiHvlOghDfBG7b pH6w== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:content-transfer-encoding :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=hJn9rPmEqPh8qns19uoLafsVSH2809OkuewFxQ1wgEY=; fh=uBQHzVZ5UgbfO36xwrofoy0zecNPRzFGe9e6ZiwAHPI=; b=gfIH8ciux1IrDR4hDRIF5XfzUWGq5RGVVeG2015wCpC0T3+lDAT+EhTbmZ0ADBxUnI lGsi/r162WGdhIKX3yPqoXl57JrJfIp0rLBs+x76iHDrVjKWnmLGiCTxpHP1xbXvVaDH L5FBDDpMIG/YEimhYcWvBtnB/e0/ulWevhB0RrN0MSCDKMJ2b02XCTzoOuS5sOrZP2wU 11OXR5pwQ5+3rXy95WSSZACQ7595oTE2H9AwolfdkoFn2aSVc/Xtydc5oqYpsz+svudV WgUlKrJYqQJ8X/59gpG6qhOYur2O/NknLg2iz7tkQtpFsxLQXnf4IygMPUzEBLoPErjT czJg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@nxp.com header.s=selector2 header.b=VEACC52d; arc=pass (i=1 spf=pass spfdomain=nxp.com dkim=pass dkdomain=nxp.com dmarc=pass fromdomain=nxp.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from lipwig.vger.email (lipwig.vger.email. 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Thu, 09 Nov 2023 13:22:17 -0800 (PST) X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782123006476199769 X-GMAIL-MSGID: 1782123006476199769 Add the compatible string 'fsl,imx95-edma5' to support the i.MX95's eDMA, which features 64-bit physical address support. Signed-off-by: Frank Li Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/dma/fsl,edma.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/dma/fsl,edma.yaml b/Documentation/devicetree/bindings/dma/fsl,edma.yaml index 437db0c62339f..aa51d278cb67b 100644 --- a/Documentation/devicetree/bindings/dma/fsl,edma.yaml +++ b/Documentation/devicetree/bindings/dma/fsl,edma.yaml @@ -25,6 +25,7 @@ properties: - fsl,imx8qm-edma - fsl,imx93-edma3 - fsl,imx93-edma4 + - fsl,imx95-edma5 - items: - const: fsl,ls1028a-edma - const: fsl,vf610-edma @@ -83,6 +84,7 @@ allOf: - fsl,imx8qm-edma - fsl,imx93-edma3 - fsl,imx93-edma4 + - fsl,imx95-edma5 then: properties: "#dma-cells": From patchwork Thu Nov 9 21:20:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 163604 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b129:0:b0:403:3b70:6f57 with SMTP id q9csp714601vqs; Thu, 9 Nov 2023 13:22:21 -0800 (PST) X-Google-Smtp-Source: AGHT+IEI6DJRZGF6mfdtPcCLLKSSIEcQCbc74dCWg5Kv554LgxGqbD0a6TD9i21IMsaTaprLUjlZ X-Received: by 2002:a17:902:6bc5:b0:1cc:3bd3:73e4 with SMTP id m5-20020a1709026bc500b001cc3bd373e4mr6089299plt.4.1699564941302; Thu, 09 Nov 2023 13:22:21 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1699564941; cv=pass; d=google.com; s=arc-20160816; b=SICZuGUsxSLQmmcdijmfwAdY2pjvZSd6I45ZlvYSzs82CoOWWO0JaOgH6NUvHc17hQ VILw6bWUzmyqIgd02YdZnHYLN+XRNyKQKr1yVkBU/kcMWo18FSzBwLq/7q0UdepuLRR8 MRLSwTUn+okfdyEy/O90WHxxi3NG+36iZXR90vfMvObRcDFjybVqxKWuxexAI7tH1Czc +ZSJmwIViMw5XHpTP/oILvlE5JonjCmM+rPiZCk+IizJEQRgw0PqwuoOxZeMhi9C7Gz+ Tc6fAnU8+tx8pis6OKygZMY4KbE6r/JRHPrHzF7OCHsSmsTkajO2Bald5TIxSDXSz8YM Z6EA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:content-transfer-encoding :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=tQoHzXE3TwYgEcIHzl8oBzc/noDppXKryI9BbNaAIgY=; fh=uBQHzVZ5UgbfO36xwrofoy0zecNPRzFGe9e6ZiwAHPI=; b=MKnz485VWQu9Q6uOXweFKDzlZFXQPqqvKgyMI57ibnqvNLKT455Ah5c5R5izXvNh79 pz+6xTLj6xV6SzVGxXaVgI6hxv2/QBQtTvXWXWJwD8rkzEB00fYdWMGvpOTKs0IswYuS 7wn/i9+tEY4eYNfsGqgltDCBZo7vdtvOzNJ9p++h6Q+2v9gcXGLsZBnSVHwYmzhHgBuN YyBDiPAtgWVK4JCo3q0JeJOYungQ9JNgi1xzKZBF4x9CRxvOg/iXDBkPDupmo7q6SE8d vz43VPVLfBKVNoY1K8tpDCiPE1zw9BOZRCdkFJFdcKqNWLvjliwnMPVPtGu6VWXqG2+C uboA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@nxp.com header.s=selector2 header.b=OFfaF2ay; arc=pass (i=1 spf=pass spfdomain=nxp.com dkim=pass dkdomain=nxp.com dmarc=pass fromdomain=nxp.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from agentk.vger.email (agentk.vger.email. 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Thu, 09 Nov 2023 13:22:18 -0800 (PST) X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782123007472651618 X-GMAIL-MSGID: 1782123007472651618 In i.MX95's edma version 5, the TCD structure is extended to support 64-bit addresses for fields like saddr and daddr. To prevent code duplication, employ help macros to handle the fields, as the field names remain the same between TCD and TCD64. Change local variables related to TCD addresses from 'u32' to 'dma_addr_t' to accept 64-bit DMA addresses. Change 'vtcd' type to 'void *' to avoid direct use. Use helper macros to access the TCD fields correctly. Call 'dma_set_mask_and_coherent(64)' when TCD64 is supported. Signed-off-by: Frank Li --- drivers/dma/fsl-edma-common.c | 18 +++--- drivers/dma/fsl-edma-common.h | 109 +++++++++++++++++++++++++++++----- drivers/dma/fsl-edma-main.c | 14 +++++ 3 files changed, 119 insertions(+), 22 deletions(-) diff --git a/drivers/dma/fsl-edma-common.c b/drivers/dma/fsl-edma-common.c index d29824ed7c80f..47ab4db3d98ec 100644 --- a/drivers/dma/fsl-edma-common.c +++ b/drivers/dma/fsl-edma-common.c @@ -426,8 +426,7 @@ enum dma_status fsl_edma_tx_status(struct dma_chan *chan, return fsl_chan->status; } -static void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan, - struct fsl_edma_hw_tcd *tcd) +static void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan, void *tcd) { u16 csr = 0; @@ -478,9 +477,9 @@ static void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan, static inline void fsl_edma_fill_tcd(struct fsl_edma_chan *fsl_chan, - struct fsl_edma_hw_tcd *tcd, u32 src, u32 dst, - u16 attr, u16 soff, u32 nbytes, u32 slast, u16 citer, - u16 biter, u16 doff, u32 dlast_sga, bool major_int, + struct fsl_edma_hw_tcd *tcd, dma_addr_t src, dma_addr_t dst, + u16 attr, u16 soff, u32 nbytes, dma_addr_t slast, u16 citer, + u16 biter, u16 doff, dma_addr_t dlast_sga, bool major_int, bool disable_req, bool enable_sg) { struct dma_slave_config *cfg = &fsl_chan->cfg; @@ -581,8 +580,9 @@ struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic( dma_addr_t dma_buf_next; bool major_int = true; int sg_len, i; - u32 src_addr, dst_addr, last_sg, nbytes; + dma_addr_t src_addr, dst_addr, last_sg; u16 soff, doff, iter; + u32 nbytes; if (!is_slave_direction(direction)) return NULL; @@ -654,8 +654,9 @@ struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg( struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); struct fsl_edma_desc *fsl_desc; struct scatterlist *sg; - u32 src_addr, dst_addr, last_sg, nbytes; + dma_addr_t src_addr, dst_addr, last_sg; u16 soff, doff, iter; + u32 nbytes; int i; if (!is_slave_direction(direction)) @@ -804,7 +805,8 @@ int fsl_edma_alloc_chan_resources(struct dma_chan *chan) struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan); fsl_chan->tcd_pool = dma_pool_create("tcd_pool", chan->device->dev, - sizeof(struct fsl_edma_hw_tcd), + fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_TCD64 ? + sizeof(struct fsl_edma_hw_tcd64) : sizeof(struct fsl_edma_hw_tcd), 32, 0); return 0; } diff --git a/drivers/dma/fsl-edma-common.h b/drivers/dma/fsl-edma-common.h index 6c738c5cad118..5357dccdc1a40 100644 --- a/drivers/dma/fsl-edma-common.h +++ b/drivers/dma/fsl-edma-common.h @@ -87,6 +87,20 @@ struct fsl_edma_hw_tcd { __le16 biter; }; +struct fsl_edma_hw_tcd64 { + __le64 saddr; + __le16 soff; + __le16 attr; + __le32 nbytes; + __le64 slast; + __le64 daddr; + __le64 dlast_sga; + __le16 doff; + __le16 citer; + __le16 csr; + __le16 biter; +} __packed; + struct fsl_edma3_ch_reg { __le32 ch_csr; __le32 ch_es; @@ -96,7 +110,10 @@ struct fsl_edma3_ch_reg { __le32 ch_mux; __le32 ch_mattr; /* edma4, reserved for edma3 */ __le32 ch_reserved; - struct fsl_edma_hw_tcd tcd; + union { + struct fsl_edma_hw_tcd tcd; + struct fsl_edma_hw_tcd tcd64; + }; } __packed; /* @@ -125,7 +142,7 @@ struct edma_regs { struct fsl_edma_sw_tcd { dma_addr_t ptcd; - struct fsl_edma_hw_tcd *vtcd; + void *vtcd; }; struct fsl_edma_chan { @@ -144,7 +161,7 @@ struct fsl_edma_chan { u32 dma_dev_size; enum dma_data_direction dma_dir; char chan_name[32]; - struct fsl_edma_hw_tcd __iomem *tcd; + void __iomem *tcd; void __iomem *mux_addr; u32 real_count; struct work_struct issue_worker; @@ -188,6 +205,7 @@ struct fsl_edma_desc { #define FSL_EDMA_DRV_CLEAR_DONE_E_SG BIT(13) /* Need clean CHn_CSR DONE before enable TCD's MAJORELINK */ #define FSL_EDMA_DRV_CLEAR_DONE_E_LINK BIT(14) +#define FSL_EDMA_DRV_TCD64 BIT(15) #define FSL_EDMA_DRV_EDMA3 (FSL_EDMA_DRV_SPLIT_REG | \ FSL_EDMA_DRV_BUS_8BYTE | \ @@ -231,15 +249,44 @@ struct fsl_edma_engine { struct fsl_edma_chan chans[] __counted_by(n_chans); }; +#define edma_read_tcdreg_c(chan, _tcd, __name) \ +(sizeof(_tcd->__name) == sizeof(u64) ? \ + edma_readq(chan->edma, &_tcd->__name) : \ + ((sizeof(_tcd->__name) == sizeof(u32)) ? \ + edma_readl(chan->edma, &_tcd->__name) : \ + edma_readw(chan->edma, &_tcd->__name) \ + )) + #define edma_read_tcdreg(chan, __name) \ -(sizeof(chan->tcd->__name) == sizeof(u32) ? \ - edma_readl(chan->edma, &chan->tcd->__name) : \ - edma_readw(chan->edma, &chan->tcd->__name)) +((fsl_edma_drvflags(chan) & FSL_EDMA_DRV_TCD64) ? \ + edma_read_tcdreg_c(chan, ((struct fsl_edma_hw_tcd64 *)chan->tcd), __name) : \ + edma_read_tcdreg_c(chan, ((struct fsl_edma_hw_tcd *)chan->tcd), __name) \ +) -#define edma_write_tcdreg(chan, val, __name) \ -(sizeof(chan->tcd->__name) == sizeof(u32) ? \ - edma_writel(chan->edma, (u32 __force)val, &chan->tcd->__name) : \ - edma_writew(chan->edma, (u16 __force)val, &chan->tcd->__name)) +#define edma_write_tcdreg_c(chan, _tcd, _val, __name) \ +do { \ + switch (sizeof(_tcd->__name)) { \ + case sizeof(u64): \ + edma_writeq(chan->edma, (u64 __force)_val, &_tcd->__name); \ + break; \ + case sizeof(u32): \ + edma_writel(chan->edma, (u32 __force)_val, &_tcd->__name); \ + break; \ + case sizeof(u16): \ + edma_writew(chan->edma, (u16 __force)_val, &_tcd->__name); \ + break; \ + case sizeof(u8): \ + edma_writeb(chan->edma, _val, &_tcd->__name); \ + break; \ + } \ +} while (0) + +#define edma_write_tcdreg(chan, val, __name) \ +do { if (fsl_edma_drvflags(chan) & FSL_EDMA_DRV_TCD64) \ + edma_write_tcdreg_c(chan, ((struct fsl_edma_hw_tcd64 *)chan->tcd), val, __name);\ + else \ + edma_write_tcdreg_c(chan, ((struct fsl_edma_hw_tcd *)chan->tcd), val, __name); \ +} while (0) #define edma_readl_chreg(chan, __name) \ edma_readl(chan->edma, \ @@ -249,17 +296,24 @@ struct fsl_edma_engine { edma_writel(chan->edma, val, \ (void __iomem *)&(container_of(chan->tcd, struct fsl_edma3_ch_reg, tcd)->__name)) -#define fsl_edma_get_tcd(_chan, _tcd, _field) ((_tcd)->_field) +#define fsl_edma_get_tcd(_chan, _tcd, _field) \ +(fsl_edma_drvflags(_chan) & FSL_EDMA_DRV_TCD64 ? (((struct fsl_edma_hw_tcd64 *)_tcd)->_field) : \ + (((struct fsl_edma_hw_tcd *)_tcd)->_field)) #define fsl_edma_le_to_cpu(x) \ -(sizeof(x) == sizeof(u32) ? le32_to_cpu(x) : le16_to_cpu(x)) +(sizeof(x) == sizeof(u64) ? le64_to_cpu(x) : \ + (sizeof(x) == sizeof(u32) ? le32_to_cpu(x) : le16_to_cpu(x))) + #define fsl_edma_get_tcd_to_cpu(_chan, _tcd, _field) \ fsl_edma_le_to_cpu(fsl_edma_get_tcd(_chan, _tcd, _field)) -#define fsl_edma_set_tcd_to_le(_fsl_chan, _tcd, _val, _field) \ +#define fsl_edma_set_tcd_to_le_c(_tcd, _val, _field) \ do { \ - switch (sizeof((_tcd)->_field)) { \ + switch (sizeof((_tcd)->_field)) { \ + case sizeof(u64): \ + (_tcd)->_field = cpu_to_le64(_val); \ + break; \ case sizeof(u32): \ (_tcd)->_field = cpu_to_le32(_val); \ break; \ @@ -269,12 +323,29 @@ do { \ } \ } while (0) +#define fsl_edma_set_tcd_to_le(_chan, _tcd, _val, _field) \ +do { \ + if (fsl_edma_drvflags(_chan) & FSL_EDMA_DRV_TCD64) \ + fsl_edma_set_tcd_to_le_c((struct fsl_edma_hw_tcd64 *)_tcd, _val, _field); \ + else \ + fsl_edma_set_tcd_to_le_c((struct fsl_edma_hw_tcd *)_tcd, _val, _field); \ +} while (0) + /* * R/W functions for big- or little-endian registers: * The eDMA controller's endian is independent of the CPU core's endian. * For the big-endian IP module, the offset for 8-bit or 16-bit registers * should also be swapped opposite to that in little-endian IP. */ +static inline u64 edma_readq(struct fsl_edma_engine *edma, void __iomem *addr) +{ + /* ioread64 and ioread64be was not defined at some platform */ + if (edma->big_endian) + return swab64(readq(addr)); + else + return readq(addr); +} + static inline u32 edma_readl(struct fsl_edma_engine *edma, void __iomem *addr) { if (edma->big_endian) @@ -320,6 +391,16 @@ static inline void edma_writel(struct fsl_edma_engine *edma, iowrite32(val, addr); } +static inline void edma_writeq(struct fsl_edma_engine *edma, + u64 val, void __iomem *addr) +{ + /* iowrite64 and iowrite64be was not defined at some platform */ + if (edma->big_endian) + writeq(swab64(val), addr); + else + writeq(val, addr); +} + static inline struct fsl_edma_chan *to_fsl_edma_chan(struct dma_chan *chan) { return container_of(chan, struct fsl_edma_chan, vchan.chan); diff --git a/drivers/dma/fsl-edma-main.c b/drivers/dma/fsl-edma-main.c index 8e5ddeb5e887f..84a5e0666d4f2 100644 --- a/drivers/dma/fsl-edma-main.c +++ b/drivers/dma/fsl-edma-main.c @@ -361,6 +361,16 @@ static struct fsl_edma_drvdata imx93_data4 = { .setup_irq = fsl_edma3_irq_init, }; +static struct fsl_edma_drvdata imx95_data5 = { + .flags = FSL_EDMA_DRV_HAS_CHMUX | FSL_EDMA_DRV_HAS_DMACLK | FSL_EDMA_DRV_EDMA4 | + FSL_EDMA_DRV_TCD64, + .chreg_space_sz = 0x8000, + .chreg_off = 0x10000, + .mux_off = 0x200, + .mux_skip = sizeof(u32), + .setup_irq = fsl_edma3_irq_init, +}; + static const struct of_device_id fsl_edma_dt_ids[] = { { .compatible = "fsl,vf610-edma", .data = &vf610_data}, { .compatible = "fsl,ls1028a-edma", .data = &ls1028a_data}, @@ -369,6 +379,7 @@ static const struct of_device_id fsl_edma_dt_ids[] = { { .compatible = "fsl,imx8qm-adma", .data = &imx8qm_audio_data}, { .compatible = "fsl,imx93-edma3", .data = &imx93_data3}, { .compatible = "fsl,imx93-edma4", .data = &imx93_data4}, + { .compatible = "fsl,imx95-edma5", .data = &imx95_data5}, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, fsl_edma_dt_ids); @@ -510,6 +521,9 @@ static int fsl_edma_probe(struct platform_device *pdev) return ret; } + if (drvdata->flags & FSL_EDMA_DRV_TCD64) + dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); + INIT_LIST_HEAD(&fsl_edma->dma_dev.channels); for (i = 0; i < fsl_edma->n_chans; i++) { struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i];