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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AMS1EPF00000041.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR08MB8138 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_LOTSOFHASH, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782085562949050137 X-GMAIL-MSGID: 1782085562949050137 The availability of tme intrinsics was previously gated at both initialisation time (using global target options) and usage time (accounting for function-specific target options). This patch removes the check at initialisation time, and also moves the intrinsics out of the header file to allow for better error messages (matching the existing error messages for SVE intrinsics). gcc/ChangeLog: PR target/112108 * config/aarch64/aarch64-builtins.cc (aarch64_init_tme_builtins): (aarch64_general_init_builtins): Remove feature check. (aarch64_check_general_builtin_call): New. (aarch64_expand_builtin_tme): Check feature availability. * config/aarch64/aarch64-c.cc (aarch64_check_builtin_call): Add check for non-SVE builtins. * config/aarch64/aarch64-protos.h (aarch64_check_general_builtin_call): New prototype. * config/aarch64/arm_acle.h (__tstart, __tcommit, __tcancel) (__ttest): Remove. (_TMFAILURE_*): Define unconditionally. gcc/testsuite/ChangeLog: PR target/112108 * gcc.target/aarch64/acle/tme_guard-1.c: New test. * gcc.target/aarch64/acle/tme_guard-2.c: New test. * gcc.target/aarch64/acle/tme_guard-3.c: New test. * gcc.target/aarch64/acle/tme_guard-4.c: New test. diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc index 11a9ba2256f105d8cb9cdc4d6decb5b2be3d69af..ac0259a892e16adb5b241032ac3df1e7ab5370ef 100644 --- a/gcc/config/aarch64/aarch64-builtins.cc +++ b/gcc/config/aarch64/aarch64-builtins.cc @@ -1765,19 +1765,19 @@ aarch64_init_tme_builtins (void) = build_function_type_list (void_type_node, uint64_type_node, NULL); aarch64_builtin_decls[AARCH64_TME_BUILTIN_TSTART] - = aarch64_general_add_builtin ("__builtin_aarch64_tstart", + = aarch64_general_add_builtin ("__tstart", ftype_uint64_void, AARCH64_TME_BUILTIN_TSTART); aarch64_builtin_decls[AARCH64_TME_BUILTIN_TTEST] - = aarch64_general_add_builtin ("__builtin_aarch64_ttest", + = aarch64_general_add_builtin ("__ttest", ftype_uint64_void, AARCH64_TME_BUILTIN_TTEST); aarch64_builtin_decls[AARCH64_TME_BUILTIN_TCOMMIT] - = aarch64_general_add_builtin ("__builtin_aarch64_tcommit", + = aarch64_general_add_builtin ("__tcommit", ftype_void_void, AARCH64_TME_BUILTIN_TCOMMIT); aarch64_builtin_decls[AARCH64_TME_BUILTIN_TCANCEL] - = aarch64_general_add_builtin ("__builtin_aarch64_tcancel", + = aarch64_general_add_builtin ("__tcancel", ftype_void_uint64, AARCH64_TME_BUILTIN_TCANCEL); } @@ -2034,8 +2034,7 @@ aarch64_general_init_builtins (void) if (!TARGET_ILP32) aarch64_init_pauth_hint_builtins (); - if (TARGET_TME) - aarch64_init_tme_builtins (); + aarch64_init_tme_builtins (); if (TARGET_MEMTAG) aarch64_init_memtag_builtins (); @@ -2137,6 +2136,24 @@ aarch64_check_required_extensions (location_t location, tree fndecl, gcc_unreachable (); } +bool aarch64_check_general_builtin_call (location_t location, + unsigned int fcode) +{ + tree fndecl = aarch64_builtin_decls[fcode]; + switch (fcode) + { + case AARCH64_TME_BUILTIN_TSTART: + case AARCH64_TME_BUILTIN_TCOMMIT: + case AARCH64_TME_BUILTIN_TTEST: + case AARCH64_TME_BUILTIN_TCANCEL: + return aarch64_check_required_extensions (location, fndecl, + AARCH64_FL_TME, false); + + default: + break; + } + return true; +} typedef enum { @@ -2559,6 +2576,11 @@ aarch64_expand_fcmla_builtin (tree exp, rtx target, int fcode) static rtx aarch64_expand_builtin_tme (int fcode, tree exp, rtx target) { + tree fndecl = aarch64_builtin_decls[fcode]; + if (!aarch64_check_required_extensions (EXPR_LOCATION (exp), fndecl, + AARCH64_FL_TME, false)) + return target; + switch (fcode) { case AARCH64_TME_BUILTIN_TSTART: diff --git a/gcc/config/aarch64/aarch64-c.cc b/gcc/config/aarch64/aarch64-c.cc index ab8844f6049dc95b97648b651bfcd3a4ccd3ca0b..6b6bd77e9e66cd2d9a211387e07d3e20d935fb1a 100644 --- a/gcc/config/aarch64/aarch64-c.cc +++ b/gcc/config/aarch64/aarch64-c.cc @@ -339,7 +339,7 @@ aarch64_check_builtin_call (location_t loc, vec arg_loc, switch (code & AARCH64_BUILTIN_CLASS) { case AARCH64_BUILTIN_GENERAL: - return true; + return aarch64_check_general_builtin_call (loc, subcode); case AARCH64_BUILTIN_SVE: return aarch64_sve::check_builtin_call (loc, arg_loc, subcode, diff --git a/gcc/config/aarch64/aarch64-protos.h b/gcc/config/aarch64/aarch64-protos.h index 30726140a6945dcb86b787f8f47952810d99379f..94022f77d7e7bab2533d78965bec241b4070c729 100644 --- a/gcc/config/aarch64/aarch64-protos.h +++ b/gcc/config/aarch64/aarch64-protos.h @@ -991,6 +991,8 @@ void handle_arm_neon_h (void); bool aarch64_check_required_extensions (location_t, tree, aarch64_feature_flags, bool = true); +bool aarch64_check_general_builtin_call (location_t, unsigned int); + namespace aarch64_sve { void init_builtins (); void handle_arm_sve_h (); diff --git a/gcc/config/aarch64/arm_acle.h b/gcc/config/aarch64/arm_acle.h index 7599a32301dadf80760d3cb40a8685d2e6a476fb..f4e35d1e12ac9bbcc4f1b75d8e5baad62f8634a0 100644 --- a/gcc/config/aarch64/arm_acle.h +++ b/gcc/config/aarch64/arm_acle.h @@ -222,10 +222,7 @@ __crc32d (uint32_t __a, uint64_t __b) #pragma GCC pop_options -#ifdef __ARM_FEATURE_TME -#pragma GCC push_options -#pragma GCC target ("+nothing+tme") - +/* Constants for TME failure reason. */ #define _TMFAILURE_REASON 0x00007fffu #define _TMFAILURE_RTRY 0x00008000u #define _TMFAILURE_CNCL 0x00010000u @@ -238,37 +235,6 @@ __crc32d (uint32_t __a, uint64_t __b) #define _TMFAILURE_INT 0x00800000u #define _TMFAILURE_TRIVIAL 0x01000000u -__extension__ extern __inline uint64_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__tstart (void) -{ - return __builtin_aarch64_tstart (); -} - -__extension__ extern __inline void -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__tcommit (void) -{ - __builtin_aarch64_tcommit (); -} - -__extension__ extern __inline void -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__tcancel (const uint64_t __reason) -{ - __builtin_aarch64_tcancel (__reason); -} - -__extension__ extern __inline uint64_t -__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) -__ttest (void) -{ - return __builtin_aarch64_ttest (); -} - -#pragma GCC pop_options -#endif - #ifdef __ARM_FEATURE_LS64 typedef __arm_data512_t data512_t; #endif diff --git a/gcc/testsuite/gcc.target/aarch64/acle/tme_guard-1.c b/gcc/testsuite/gcc.target/aarch64/acle/tme_guard-1.c new file mode 100644 index 0000000000000000000000000000000000000000..9894d3341f6bc352c22ad95d4d1e000207ca8d00 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/tme_guard-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8-a" } */ + +#include + +void foo (void) +{ + __tcommit (); /* { dg-error {ACLE function '__tcommit' requires ISA extension 'tme'} } */ +} diff --git a/gcc/testsuite/gcc.target/aarch64/acle/tme_guard-2.c b/gcc/testsuite/gcc.target/aarch64/acle/tme_guard-2.c new file mode 100644 index 0000000000000000000000000000000000000000..4e3d69712b14a8123f45a2ead02b5048883614d9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/tme_guard-2.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8-a" } */ + +#include + +#pragma GCC target("arch=armv8-a+tme") +void foo (void) +{ + __tcommit (); +} diff --git a/gcc/testsuite/gcc.target/aarch64/acle/tme_guard-3.c b/gcc/testsuite/gcc.target/aarch64/acle/tme_guard-3.c new file mode 100644 index 0000000000000000000000000000000000000000..5f480ebb8209fdaeb4baa77dbdf5467d16936644 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/tme_guard-3.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8-a+tme -mgeneral-regs-only" } */ + +#include + +void foo (void) +{ + __tcommit (); +} diff --git a/gcc/testsuite/gcc.target/aarch64/acle/tme_guard-4.c b/gcc/testsuite/gcc.target/aarch64/acle/tme_guard-4.c new file mode 100644 index 0000000000000000000000000000000000000000..bf4d368370c614ffe33035d9ec4f86988f3f1c30 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/tme_guard-4.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8-a+tme" } */ + +#include + +#pragma GCC target("arch=armv8-a") +void foo (void) +{ + __tcommit (); /* { dg-error {ACLE function '__tcommit' requires ISA extension 'tme'} } */ +} From patchwork Thu Nov 9 11:26:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Carlotti X-Patchwork-Id: 163351 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b129:0:b0:403:3b70:6f57 with SMTP id q9csp366144vqs; Thu, 9 Nov 2023 03:27:45 -0800 (PST) X-Google-Smtp-Source: AGHT+IEjnM6bVYE7xNxoKLBss49McXaC5NaVgY1+RQLfDfSvabZDZTcCWkurwUEgxuqC7Lq4SVO5 X-Received: by 2002:a05:620a:244b:b0:778:8ebc:129f with SMTP id h11-20020a05620a244b00b007788ebc129fmr12163551qkn.8.1699529265363; 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Thu, 9 Nov 2023 11:26:58 +0000 Date: Thu, 9 Nov 2023 11:26:55 +0000 From: Andrew Carlotti To: gcc-patches@gcc.gnu.org Cc: richard.earnshaw@arm.com, richard.sandiford@arm.com, kyrylo.tkachov@arm.com Subject: [3/4] aarch64: Fix memtag intrinsic availability Message-ID: <9e6ff577-22b0-a3fe-6dc0-384d8b426ef0@e124511.cambridge.arm.com> References: <6dccdd32-6c7b-5962-24e4-8acc7910a76d@e124511.cambridge.arm.com> Content-Disposition: inline In-Reply-To: <6dccdd32-6c7b-5962-24e4-8acc7910a76d@e124511.cambridge.arm.com> X-ClientProxiedBy: LO4P265CA0048.GBRP265.PROD.OUTLOOK.COM (2603:10a6:600:2ac::8) To AS8PR08MB6678.eurprd08.prod.outlook.com (2603:10a6:20b:398::8) MIME-Version: 1.0 X-MS-TrafficTypeDiagnostic: AS8PR08MB6678:EE_|AM7PR08MB5479:EE_|AM3PEPF00009B9D:EE_|AM9PR08MB6241:EE_ X-MS-Office365-Filtering-Correlation-Id: 0d6a2400-03bb-42e0-8aaa-08dbe116d1a2 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; 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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM3PEPF00009B9D.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM9PR08MB6241 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_LOTSOFHASH, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1782085599019157495 X-GMAIL-MSGID: 1782085599019157495 The availability of memtag intrinsics and data types were determined solely by the globally specified architecture features, which did not reflect any changes specified in target pragmas or attributes. This patch removes the initialisation-time guards for the intrinsics, and replaces them with checks at use time. It also removes the macro indirection from the header file - this simplifies the header, and allows the missing extension error reporting to find the user-facing intrinsic names. gcc/ChangeLog: PR target/112108 * config/aarch64/aarch64-builtins.cc (aarch64_init_memtag_builtins): Replace internal builtin names with intrinsic names. (aarch64_general_init_builtins): Remove feature check. (aarch64_check_general_builtin_call): Check memtag intrinsics. (aarch64_expand_builtin_memtag): Add feature check. * config/aarch64/arm_acle.h (__arm_mte_create_random_tag) (__arm_mte_exclude_tag, __arm_mte_ptrdiff) (__arm_mte_increment_tag, __arm_mte_set_tag, __arm_mte_get_tag): Remove. gcc/testsuite/ChangeLog: PR target/112108 * gcc.target/aarch64/acle/memtag_guard-1.c: New test. * gcc.target/aarch64/acle/memtag_guard-2.c: New test. * gcc.target/aarch64/acle/memtag_guard-3.c: New test. * gcc.target/aarch64/acle/memtag_guard-4.c: New test. diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc index ac0259a892e16adb5b241032ac3df1e7ab5370ef..503d8ad98d7de959d8c7c78cef575d29e2132f78 100644 --- a/gcc/config/aarch64/aarch64-builtins.cc +++ b/gcc/config/aarch64/aarch64-builtins.cc @@ -1813,7 +1813,7 @@ aarch64_init_memtag_builtins (void) #define AARCH64_INIT_MEMTAG_BUILTINS_DECL(F, N, I, T) \ aarch64_builtin_decls[AARCH64_MEMTAG_BUILTIN_##F] \ - = aarch64_general_add_builtin ("__builtin_aarch64_memtag_"#N, \ + = aarch64_general_add_builtin ("__arm_mte_"#N, \ T, AARCH64_MEMTAG_BUILTIN_##F); \ aarch64_memtag_builtin_data[AARCH64_MEMTAG_BUILTIN_##F - \ AARCH64_MEMTAG_BUILTIN_START - 1] = \ @@ -1821,19 +1821,19 @@ aarch64_init_memtag_builtins (void) fntype = build_function_type_list (ptr_type_node, ptr_type_node, uint64_type_node, NULL); - AARCH64_INIT_MEMTAG_BUILTINS_DECL (IRG, irg, irg, fntype); + AARCH64_INIT_MEMTAG_BUILTINS_DECL (IRG, create_random_tag, irg, fntype); fntype = build_function_type_list (uint64_type_node, ptr_type_node, uint64_type_node, NULL); - AARCH64_INIT_MEMTAG_BUILTINS_DECL (GMI, gmi, gmi, fntype); + AARCH64_INIT_MEMTAG_BUILTINS_DECL (GMI, exclude_tag, gmi, fntype); fntype = build_function_type_list (ptrdiff_type_node, ptr_type_node, ptr_type_node, NULL); - AARCH64_INIT_MEMTAG_BUILTINS_DECL (SUBP, subp, subp, fntype); + AARCH64_INIT_MEMTAG_BUILTINS_DECL (SUBP, ptrdiff, subp, fntype); fntype = build_function_type_list (ptr_type_node, ptr_type_node, unsigned_type_node, NULL); - AARCH64_INIT_MEMTAG_BUILTINS_DECL (INC_TAG, inc_tag, addg, fntype); + AARCH64_INIT_MEMTAG_BUILTINS_DECL (INC_TAG, increment_tag, addg, fntype); fntype = build_function_type_list (void_type_node, ptr_type_node, NULL); AARCH64_INIT_MEMTAG_BUILTINS_DECL (SET_TAG, set_tag, stg, fntype); @@ -2036,8 +2036,7 @@ aarch64_general_init_builtins (void) aarch64_init_tme_builtins (); - if (TARGET_MEMTAG) - aarch64_init_memtag_builtins (); + aarch64_init_memtag_builtins (); if (in_lto_p) handle_arm_acle_h (); @@ -2152,6 +2151,12 @@ bool aarch64_check_general_builtin_call (location_t location, default: break; } + + if (fcode >= AARCH64_MEMTAG_BUILTIN_START + && fcode <= AARCH64_MEMTAG_BUILTIN_END) + return aarch64_check_required_extensions (location, fndecl, + AARCH64_FL_MEMTAG, false); + return true; } @@ -2716,6 +2721,11 @@ aarch64_expand_builtin_memtag (int fcode, tree exp, rtx target) return const0_rtx; } + tree fndecl = aarch64_builtin_decls[fcode]; + if (!aarch64_check_required_extensions (EXPR_LOCATION (exp), fndecl, + AARCH64_FL_MEMTAG, false)) + return target; + rtx pat = NULL; enum insn_code icode = aarch64_memtag_builtin_data[fcode - AARCH64_MEMTAG_BUILTIN_START - 1].icode; diff --git a/gcc/config/aarch64/arm_acle.h b/gcc/config/aarch64/arm_acle.h index f4e35d1e12ac9bbcc4f1b75d8e5baad62f8634a0..57f16603d22cec81002b00b94afe1201c83b4b94 100644 --- a/gcc/config/aarch64/arm_acle.h +++ b/gcc/config/aarch64/arm_acle.h @@ -257,29 +257,6 @@ __rndrrs (uint64_t *__res) #pragma GCC pop_options -#pragma GCC push_options -#pragma GCC target ("+nothing+memtag") - -#define __arm_mte_create_random_tag(__ptr, __u64_mask) \ - __builtin_aarch64_memtag_irg(__ptr, __u64_mask) - -#define __arm_mte_exclude_tag(__ptr, __u64_excluded) \ - __builtin_aarch64_memtag_gmi(__ptr, __u64_excluded) - -#define __arm_mte_ptrdiff(__ptr_a, __ptr_b) \ - __builtin_aarch64_memtag_subp(__ptr_a, __ptr_b) - -#define __arm_mte_increment_tag(__ptr, __u_offset) \ - __builtin_aarch64_memtag_inc_tag(__ptr, __u_offset) - -#define __arm_mte_set_tag(__tagged_address) \ - __builtin_aarch64_memtag_set_tag(__tagged_address) - -#define __arm_mte_get_tag(__address) \ - __builtin_aarch64_memtag_get_tag(__address) - -#pragma GCC pop_options - #ifdef __cplusplus } #endif diff --git a/gcc/testsuite/gcc.target/aarch64/acle/memtag_guard-1.c b/gcc/testsuite/gcc.target/aarch64/acle/memtag_guard-1.c new file mode 100644 index 0000000000000000000000000000000000000000..4a34c37f44fae590d2a3f947dd1bf404fe8261fa --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/memtag_guard-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.5-a" } */ + +#include + +void foo (int * p) +{ + __arm_mte_set_tag (p); /* { dg-error {ACLE function '__arm_mte_set_tag' requires ISA extension 'memtag'} } */ +} diff --git a/gcc/testsuite/gcc.target/aarch64/acle/memtag_guard-2.c b/gcc/testsuite/gcc.target/aarch64/acle/memtag_guard-2.c new file mode 100644 index 0000000000000000000000000000000000000000..bf06b284dadd2082496cfc0a345f7cf5a783bd3b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/memtag_guard-2.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.5-a" } */ + +#include + +#pragma GCC target("arch=armv8.5-a+memtag") +void foo (int * p) +{ + __arm_mte_set_tag (p); +} diff --git a/gcc/testsuite/gcc.target/aarch64/acle/memtag_guard-3.c b/gcc/testsuite/gcc.target/aarch64/acle/memtag_guard-3.c new file mode 100644 index 0000000000000000000000000000000000000000..1f4ffa454a763e6b35bd84af6ef6c7d6474a518b --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/memtag_guard-3.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.5-a+memtag -mgeneral-regs-only" } */ + +#include + +void foo (int * p) +{ + __arm_mte_set_tag (p); +} diff --git a/gcc/testsuite/gcc.target/aarch64/acle/memtag_guard-4.c b/gcc/testsuite/gcc.target/aarch64/acle/memtag_guard-4.c new file mode 100644 index 0000000000000000000000000000000000000000..a1cd45ec79d242dcf710abdc375c29063866eb5a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/memtag_guard-4.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-march=armv8.5-a+memtag" } */ + +#include + +#pragma GCC target("arch=armv8.5-a") +void foo (int * p) +{ + __arm_mte_set_tag (p); /* { dg-error {ACLE function '__arm_mte_set_tag' requires ISA extension 'memtag'} } */ +}