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[23.128.96.35]) by mx.google.com with ESMTPS id o8-20020a656a48000000b005bd39be60b3si3002275pgu.390.2023.11.07.07.28.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Nov 2023 07:28:17 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) client-ip=23.128.96.35; Authentication-Results: mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=ktHQmlUv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by groat.vger.email (Postfix) with ESMTP id 4B43A80443A6; Tue, 7 Nov 2023 07:28:14 -0800 (PST) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.11 at groat.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343834AbjKGP1b (ORCPT + 32 others); Tue, 7 Nov 2023 10:27:31 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55814 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234099AbjKGP10 (ORCPT ); Tue, 7 Nov 2023 10:27:26 -0500 Received: from mail-pg1-x533.google.com (mail-pg1-x533.google.com [IPv6:2607:f8b0:4864:20::533]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B339A113 for ; Tue, 7 Nov 2023 07:27:24 -0800 (PST) Received: by mail-pg1-x533.google.com with SMTP id 41be03b00d2f7-5bd306f86a8so3523340a12.0 for ; Tue, 07 Nov 2023 07:27:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; t=1699370844; x=1699975644; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=PtKbq6gTZrURkQc/6QWUt4p94lELBM6ajnXaIsFT5Fk=; b=ktHQmlUvEGh07IudoE1GTRc0X95raVD2ulViS3JxZHCPViJrwKn1UxqWFxRLb9hPOz DDe+SBLtcTampfozU9+pM1EKIZUj8O4n5qCxujnfE9F5IYUS0RoEx2/FIBhvLgUUVCzV MJwZEFquJhjFBDcxsw5aoaXk2N9hvTOuzCdn4= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699370844; x=1699975644; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=PtKbq6gTZrURkQc/6QWUt4p94lELBM6ajnXaIsFT5Fk=; b=Txil+CLscrlTUpryj3V3jUMVKiplw0Q+MrAnfbI1VjR4TriTWHlmECU6ibjAC9+vu7 8PdBEMAclPYvoQR1q5Kn51b+tUkPFIuoJDm4QgeQ3mE91d1ItO5uLwgE4fvwVKGmajw5 Gv7QgvTk5mLz3/hwvwNbVFpvligJyjc2pFXXYw8sdiK5oOBCHweyY+tsM7GLB7e/gUHF YBnk5qEcm5w5p1uQjDXIgX+3zEoIxlrINfhOe7zdIf5lhOk5q9WgWeGclt4uxU2Oc1oJ XIc0eiYcTup9tai5bUKhWEhUatSjTYYB2d93XwKfhHESf7wSLBmjtVkkiIBu4VibtOfO SrRw== X-Gm-Message-State: AOJu0YwBBIiD05paPuI7bwBixxriP/+6e1SQ9r6bYMXmteFEADxqEzG6 TY0fSlurOmDnblMZpROiB5kzL6/TUei3EjtLG2j+rtmz X-Received: by 2002:a17:90b:4b11:b0:281:d55:6fe8 with SMTP id lx17-20020a17090b4b1100b002810d556fe8mr4416063pjb.24.1699370844108; Tue, 07 Nov 2023 07:27:24 -0800 (PST) Received: from tictac2.mtv.corp.google.com ([2620:15c:9d:2:16a7:2c01:9126:36a4]) by smtp.gmail.com with ESMTPSA id l7-20020a17090a49c700b002808c9e3095sm7066259pjm.26.2023.11.07.07.27.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 07 Nov 2023 07:27:23 -0800 (PST) From: Douglas Anderson To: Marc Zyngier , Mark Rutland , Catalin Marinas , Will Deacon , Chen-Yu Tsai Cc: Douglas Anderson , Amit Daniel Kachhap , AngeloGioacchino Del Regno , James Morse , Joey Gouly , Mark Brown , Matthias Brugger , Thomas Gleixner , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v2 1/2] arm64: Move Mediatek GIC quirk handling from irqchip to core Date: Tue, 7 Nov 2023 07:26:56 -0800 Message-ID: <20231107072651.v2.1.Ide945748593cffd8ff0feb9ae22b795935b944d6@changeid> X-Mailer: git-send-email 2.42.0.869.gea05f2083d-goog MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Tue, 07 Nov 2023 07:28:14 -0800 (PST) X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781919538545093391 X-GMAIL-MSGID: 1781919538545093391 In commit 44bd78dd2b88 ("irqchip/gic-v3: Disable pseudo NMIs on Mediatek devices w/ firmware issues") we added a method for detecting Mediatek devices with broken firmware and disabled pseudo-NMI. While that worked, it didn't address the problem at a deep enough level. The fundamental issue with this broken firmware is that it's not saving and restoring several important GICR registers. The current list is believed to be: * GICR_NUM_IPRIORITYR * GICR_CTLR * GICR_ISPENDR0 * GICR_ISACTIVER0 * GICR_NSACR Pseudo-NMI didn't work because it was the only thing (currently) in the kernel that relied on the broken registers, so forcing pseudo-NMI off was an effective fix. However, it could be observed that calling system_uses_irq_prio_masking() on these systems still returned "true". That caused confusion and led to the need for commit a07a59415217 ("arm64: smp: avoid NMI IPIs with broken MediaTek FW"). It's worried that the incorrect value returned by system_uses_irq_prio_masking() on these systems will continue to confuse future developers. Let's fix the issue a little more completely by disabling IRQ priorities at a deeper level in the kernel. Once we do this we can revert some of the other bits of code dealing with this quirk. This includes a partial revert of commit 44bd78dd2b88 ("irqchip/gic-v3: Disable pseudo NMIs on Mediatek devices w/ firmware issues"). This isn't a full revert because it leaves some of the changes to the "quirks" structure around in case future code needs it. Suggested-by: Mark Rutland Signed-off-by: Douglas Anderson Acked-by: Marc Zyngier Reviewed-by: AngeloGioacchino Del Regno Tested-by: AngeloGioacchino Del Regno Acked-by: Mark Rutland --- Changes in v2: - Just detect the quirk once at init time. - Fixed typo in subject: s/GiC/GIC. - Squash in ("Remove Mediatek pseudo-NMI firmware quirk handling"). arch/arm64/kernel/cpufeature.c | 46 ++++++++++++++++++++++++++++------ drivers/irqchip/irq-gic-v3.c | 22 +--------------- 2 files changed, 39 insertions(+), 29 deletions(-) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index f6b2e2906fc9..928124ea2e96 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -999,6 +999,37 @@ static void init_32bit_cpu_features(struct cpuinfo_32bit *info) init_cpu_ftr_reg(SYS_MVFR2_EL1, info->reg_mvfr2); } +#ifdef CONFIG_ARM64_PSEUDO_NMI +static bool enable_pseudo_nmi; + +static int __init early_enable_pseudo_nmi(char *p) +{ + return kstrtobool(p, &enable_pseudo_nmi); +} +early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); + +static __init void detect_system_supports_pseudo_nmi(void) +{ + struct device_node *np; + + if (!enable_pseudo_nmi) + return; + + /* + * Detect broken Mediatek firmware that doesn't properly save and + * restore GIC priorities. + */ + np = of_find_compatible_node(NULL, NULL, "arm,gic-v3"); + if (np && of_property_read_bool(np, "mediatek,broken-save-restore-fw")) { + pr_info("Pseudo-NMI disabled due to Mediatek Chromebook GICR save problem\n"); + enable_pseudo_nmi = false; + } + of_node_put(np); +} +#else /* CONFIG_ARM64_PSEUDO_NMI */ +static inline void detect_system_supports_pseudo_nmi(void) { } +#endif + void __init init_cpu_features(struct cpuinfo_arm64 *info) { /* Before we start using the tables, make sure it is sorted */ @@ -1057,6 +1088,13 @@ void __init init_cpu_features(struct cpuinfo_arm64 *info) */ init_cpucap_indirect_list(); + /* + * Detect broken pseudo-NMI. Must be called _before_ the call to + * setup_boot_cpu_capabilities() since it interacts with + * can_use_gic_priorities(). + */ + detect_system_supports_pseudo_nmi(); + /* * Detect and enable early CPU capabilities based on the boot CPU, * after we have initialised the CPU feature infrastructure. @@ -2085,14 +2123,6 @@ static void cpu_enable_e0pd(struct arm64_cpu_capabilities const *cap) #endif /* CONFIG_ARM64_E0PD */ #ifdef CONFIG_ARM64_PSEUDO_NMI -static bool enable_pseudo_nmi; - -static int __init early_enable_pseudo_nmi(char *p) -{ - return kstrtobool(p, &enable_pseudo_nmi); -} -early_param("irqchip.gicv3_pseudo_nmi", early_enable_pseudo_nmi); - static bool can_use_gic_priorities(const struct arm64_cpu_capabilities *entry, int scope) { diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 68d11ccee441..1ba674367ee3 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -39,8 +39,7 @@ #define FLAGS_WORKAROUND_GICR_WAKER_MSM8996 (1ULL << 0) #define FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539 (1ULL << 1) -#define FLAGS_WORKAROUND_MTK_GICR_SAVE (1ULL << 2) -#define FLAGS_WORKAROUND_ASR_ERRATUM_8601001 (1ULL << 3) +#define FLAGS_WORKAROUND_ASR_ERRATUM_8601001 (1ULL << 2) #define GIC_IRQ_TYPE_PARTITION (GIC_IRQ_TYPE_LPI + 1) @@ -1779,15 +1778,6 @@ static bool gic_enable_quirk_msm8996(void *data) return true; } -static bool gic_enable_quirk_mtk_gicr(void *data) -{ - struct gic_chip_data *d = data; - - d->flags |= FLAGS_WORKAROUND_MTK_GICR_SAVE; - - return true; -} - static bool gic_enable_quirk_cavium_38539(void *data) { struct gic_chip_data *d = data; @@ -1888,11 +1878,6 @@ static const struct gic_quirk gic_quirks[] = { .compatible = "asr,asr8601-gic-v3", .init = gic_enable_quirk_asr8601, }, - { - .desc = "GICv3: Mediatek Chromebook GICR save problem", - .property = "mediatek,broken-save-restore-fw", - .init = gic_enable_quirk_mtk_gicr, - }, { .desc = "GICv3: HIP06 erratum 161010803", .iidr = 0x0204043b, @@ -1959,11 +1944,6 @@ static void gic_enable_nmi_support(void) if (!gic_prio_masking_enabled()) return; - if (gic_data.flags & FLAGS_WORKAROUND_MTK_GICR_SAVE) { - pr_warn("Skipping NMI enable due to firmware issues\n"); - return; - } - rdist_nmi_refs = kcalloc(gic_data.ppi_nr + SGI_NR, sizeof(*rdist_nmi_refs), GFP_KERNEL); if (!rdist_nmi_refs) From patchwork Tue Nov 7 15:26:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Doug Anderson X-Patchwork-Id: 162640 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:aa0b:0:b0:403:3b70:6f57 with SMTP id k11csp310321vqo; Tue, 7 Nov 2023 07:28:14 -0800 (PST) X-Google-Smtp-Source: AGHT+IHy4vtsd3lex2obKZHIO7GTfDl+QWvu75gxeZ/9nbQvsGnPOXAKXfNSvP9VxqmSpLA+mgBd X-Received: by 2002:a05:6a21:3e02:b0:180:e3f1:4f60 with SMTP id bk2-20020a056a213e0200b00180e3f14f60mr18812675pzc.45.1699370893913; Tue, 07 Nov 2023 07:28:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699370893; cv=none; d=google.com; s=arc-20160816; b=H2n7WrCh8vHcSGsWtSdJGTauZ8787mF9XzsX8HZQMsIdD59wXZcQUv+qPyFcOTu3mJ tnY93zNrzvgcvVlKG6y8gL5o9A+tdCIlfz3DmNYHmZnsxPna8Gr+gOEMNn6UE752t0j1 QWSqZZA72GFRwwdUxIHLlVwi7NInv8VpKg/lclk/dSwHEaigfn+rgwP4A+ZDqcIUVET4 fS/5jP6JQ94FaPDUmB8tZ8zB5083ULlmNpTTenFNQBexq3CT79xMNc8Qi5xfAbTheu6E xgxyVkehtDGTPNpSRWTBDn3JvU+AO/lAD7ZV1YK+52wrLply7uOYk2YOsNTdaZZ9bNI3 XfMA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=U2SccpyfV2fl1KuQVt090nerznp46yA/P71X1kRc3n4=; fh=+kQqjh0bEhafAhfSk+f9BRTkY6zLDMI3dWtC3ZGNASU=; b=PSwmiGglkx9trhLAQ5h9GGFevo0gzSulVzCITaNwLQv4hkWtPdi8jNK7ONdHQCX7is NHreUIT7liaQU6WoecrsGWEi9KxdEMdTes10OA0Ur67M16nnYCbFhUxK95HoQCxJT8to 1jqHNf3z2nKR8zFjbZ4seDbltzmI0k78VtoVYuL27RR81hgwSAlbhRb1s9bbybXvwTVf nAOqxbvuaIx9MFCw0S5KpvGZibOnctseErljrKkNzq5lnaY3RK3ruRSj5iXkp62/ECek Z3/VlbR4NAkcLtbV1peSb/HOpcA9KNP+8mRxDIFhvTWDTmFFEaBrIdNC3OXmijcIrDpm R75A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@chromium.org header.s=google header.b=VRoCrDSG; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=chromium.org Received: from lipwig.vger.email (lipwig.vger.email. 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This is no longer needed after the patch ("arm64: Move Mediatek GIC quirk handling from irqchip to core). Signed-off-by: Douglas Anderson Acked-by: Marc Zyngier Acked-by: Mark Rutland --- Changes in v2: - Fixed typo in subject: s/GiC/GIC. arch/arm64/kernel/smp.c | 5 +---- drivers/irqchip/irq-gic-v3.c | 2 +- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/arch/arm64/kernel/smp.c b/arch/arm64/kernel/smp.c index be95b523c101..defbab84e9e5 100644 --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -965,10 +965,7 @@ static void smp_cross_call(const struct cpumask *target, unsigned int ipinr) static bool ipi_should_be_nmi(enum ipi_msg_type ipi) { - DECLARE_STATIC_KEY_FALSE(supports_pseudo_nmis); - - if (!system_uses_irq_prio_masking() || - !static_branch_likely(&supports_pseudo_nmis)) + if (!system_uses_irq_prio_masking()) return false; switch (ipi) { diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c index 1ba674367ee3..98b0329b7154 100644 --- a/drivers/irqchip/irq-gic-v3.c +++ b/drivers/irqchip/irq-gic-v3.c @@ -105,7 +105,7 @@ static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key); * - Figure 4-7 Secure read of the priority field for a Non-secure Group 1 * interrupt. */ -DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis); +static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis); DEFINE_STATIC_KEY_FALSE(gic_nonsecure_priorities); EXPORT_SYMBOL(gic_nonsecure_priorities);