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Tue, 07 Nov 2023 12:26:32 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3A7CQVrb016331 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 7 Nov 2023 12:26:31 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Tue, 7 Nov 2023 04:26:26 -0800 From: Krishna chaitanya chundru Date: Tue, 7 Nov 2023 17:56:13 +0530 Subject: [PATCH v2 1/3] dt-bindings: phy: qcom,qmp: Add PCIe qcom,refclk-always-on property MIME-Version: 1.0 Message-ID: <20231107-refclk_always_on-v2-1-de23962fc4b3@quicinc.com> References: <20231107-refclk_always_on-v2-0-de23962fc4b3@quicinc.com> In-Reply-To: <20231107-refclk_always_on-v2-0-de23962fc4b3@quicinc.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , , , , , , , "Krishna chaitanya chundru" X-Mailer: b4 0.13-dev-83828 X-Developer-Signature: v=1; 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Tue, 07 Nov 2023 04:40:07 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781909014313491970 X-GMAIL-MSGID: 1781909014313491970 Document qcom,refclk-always-on property which is needed in some platforms to supply refclk even in PCIe low power states. Signed-off-by: Krishna chaitanya chundru --- .../devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml index 2c3d6553a7ba..263291447a5b 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -93,6 +93,13 @@ properties: "#phy-cells": const: 0 + qcom,refclk-always-on: + type: boolean + description: If there is some issues in platform with clkreq signal + propagation to the host and due to that host will not send refclk, which + results in linkdown in L1.2 or L1.1 exit initiated by EP. This property + if set keeps refclk always on even in Low power states (optional). + required: - compatible - reg From patchwork Tue Nov 7 12:26:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krishna chaitanya chundru X-Patchwork-Id: 162443 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:aa0b:0:b0:403:3b70:6f57 with SMTP id k11csp204013vqo; Tue, 7 Nov 2023 04:40:49 -0800 (PST) X-Google-Smtp-Source: AGHT+IF6EIrahusOyfPw62Eg9HvvFf5IUHZgayH7tKe5jazvza4AMtQ94HnQUL5bojWDaC4U4QLE X-Received: by 2002:a05:6a00:10d4:b0:690:1857:3349 with SMTP id d20-20020a056a0010d400b0069018573349mr34998023pfu.25.1699360849607; Tue, 07 Nov 2023 04:40:49 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1699360849; cv=none; d=google.com; s=arc-20160816; b=yVB6oPojaEXVQKTFHonLhfjHCbnOKxzmd1Md09BrHvxK9ZytA8SmWcoV/YxgfXMcTZ jONzU0VYAwpmrQSG/eNjt5USZ38tYdoeieO61g0YAryPMSyjwop62fJQulId7hP1oEAg UwWhXIeAu2fPCM6f63JNFvAE6Muqc6Q3cOhGoEX8x4l4HZuN+8BXk6kedlFWOm6znxNC oNMsvn2iktmb69aTgJM3B8HM3m87JL6b1NjwE/KsRGXvtCJpNrSKnF3vQhPNOUjKkzCG 4g3Lk9UnZgcjy8vpGEJVum+Qxg+Bzo5fYmJ5hGk9xH8Op7nmlxTLBs92Qw/zOnJ0dgX6 Uyhg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=oMRemMIvwiE2zroFHp2/PLiNZr1IPmhJUQutzi9KI+Y=; fh=EFIAKKtQRIe9H8zeoA9xLqoI3gyQkUU8ZMs+AiKe2pw=; b=L9tMQySmHNzoY5XJSkAyuT87i/8UgLtqQyiD8Fb/OyCFkJ9vwAyKsQ0zN6w9A50ffA BVvqAZVlFINkZan0YcvavyHhw0L8DbY4ME6eYTgCW+Sgei2YmcoOQSP9JvhH0ousWPWO THvovLMUtESlAPQX+kF2FonwT9/Bm3iGOkM/FOPxNcE8fLsm8EAcXmlujZA1Ezd3iv2o 8+AaIZyZcbboI0LPUB4vrIM8Pb+dW91oB4eaQnEeyGORFSEFrRScB41MVL2kDDvxGBSw sFkV+N+5MCDPKsu19bRodz8P8A+7YSKN51SoicauCrS7daQKZw5m6BCrROxA8USdKdoW nbGQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=UqPr873p; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from lipwig.vger.email (lipwig.vger.email. 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Tue, 07 Nov 2023 12:26:37 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 3A7CQaM0016385 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 7 Nov 2023 12:26:36 GMT Received: from hu-krichai-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Tue, 7 Nov 2023 04:26:31 -0800 From: Krishna chaitanya chundru Date: Tue, 7 Nov 2023 17:56:14 +0530 Subject: [PATCH v2 2/3] phy: qcom-qmp-pcie: Add endpoint refclk control register offset MIME-Version: 1.0 Message-ID: <20231107-refclk_always_on-v2-2-de23962fc4b3@quicinc.com> References: <20231107-refclk_always_on-v2-0-de23962fc4b3@quicinc.com> In-Reply-To: <20231107-refclk_always_on-v2-0-de23962fc4b3@quicinc.com> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , , , , , , , , "Krishna chaitanya chundru" X-Mailer: b4 0.13-dev-83828 X-Developer-Signature: v=1; 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Tue, 07 Nov 2023 04:40:17 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781909002033028960 X-GMAIL-MSGID: 1781909002033028960 Some platforms needs to keep endpoint refclk always on, for this purpose add this offset for all the applicable phy versions. And also add reg layout for few controllers as we are adding endpoint refclk control register which changes based upon phy version. Signed-off-by: Krishna chaitanya chundru Reviewed-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 26 +++++++++++++++++++--- drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h | 1 + drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h | 1 + drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h | 1 + 4 files changed, 26 insertions(+), 3 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index a63ca7424974..74d03d217ff2 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -77,6 +77,7 @@ enum qphy_reg_layout { QPHY_START_CTRL, QPHY_PCS_STATUS, QPHY_PCS_POWER_DOWN_CONTROL, + QPHY_PCS_ENDPOINT_REFCLK_CNTRL, /* Keep last to ensure regs_layout arrays are properly initialized */ QPHY_LAYOUT_SIZE }; @@ -93,6 +94,7 @@ static const unsigned int pciephy_v3_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, + [QPHY_PCS_ENDPOINT_REFCLK_CNTRL] = QPHY_V3_PCS_ENDPOINT_REFCLK_CNTRL, }; static const unsigned int sdm845_qhp_pciephy_regs_layout[QPHY_LAYOUT_SIZE] = { @@ -107,6 +109,7 @@ static const unsigned int pciephy_v4_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL, [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1, [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL, + [QPHY_PCS_ENDPOINT_REFCLK_CNTRL] = QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_CNTRL, }; static const unsigned int pciephy_v5_regs_layout[QPHY_LAYOUT_SIZE] = { @@ -114,6 +117,23 @@ static const unsigned int pciephy_v5_regs_layout[QPHY_LAYOUT_SIZE] = { [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL, [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1, [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL, + [QPHY_PCS_ENDPOINT_REFCLK_CNTRL] = QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_CNTRL, +}; + +static const unsigned int pciephy_v5_20_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET, + [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL, + [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1, + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL, + [QPHY_PCS_ENDPOINT_REFCLK_CNTRL] = QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_CNTRL, +}; + +static const unsigned int pciephy_v6_20_regs_layout[QPHY_LAYOUT_SIZE] = { + [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET, + [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL, + [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1, + [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL, + [QPHY_PCS_ENDPOINT_REFCLK_CNTRL] = QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_CNTRL, }; static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = { @@ -2956,7 +2976,7 @@ static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = pciephy_v5_regs_layout, + .regs = pciephy_v5_20_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .phy_status = PHYSTATUS_4_20, @@ -3012,7 +3032,7 @@ static const struct qmp_phy_cfg sm8550_qmp_gen4x2_pciephy_cfg = { .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = sm8550_qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(sm8550_qmp_phy_vreg_l), - .regs = pciephy_v5_regs_layout, + .regs = pciephy_v6_20_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .phy_status = PHYSTATUS_4_20, @@ -3047,7 +3067,7 @@ static const struct qmp_phy_cfg sa8775p_qmp_gen4x2_pciephy_cfg = { .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), .vreg_list = qmp_phy_vreg_l, .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), - .regs = pciephy_v5_regs_layout, + .regs = pciephy_v5_20_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, .phy_status = PHYSTATUS_4_20, diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h index a469ae2a10a1..9b166286afda 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5.h @@ -11,6 +11,7 @@ #define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG2 0x0c #define QPHY_V5_PCS_PCIE_POWER_STATE_CONFIG4 0x14 #define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20 +#define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_CNTRL 0x24 #define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54 #define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94 #define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h index cdf8c04ea078..8b114e538a07 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v5_20.h @@ -9,6 +9,7 @@ /* Only for QMP V5_20 PHY - PCIe PCS registers */ #define QPHY_V5_20_PCS_PCIE_POWER_STATE_CONFIG2 0x00c #define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c +#define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_CNTRL 0x020 #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x084 #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090 #define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0 diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h index e3eb08776339..f7abe95c49ad 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h @@ -10,6 +10,7 @@ #define QPHY_PCIE_V6_20_PCS_POWER_STATE_CONFIG2 0x00c #define QPHY_PCIE_V6_20_PCS_TX_RX_CONFIG 0x018 #define QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_DRIVE 0x01c +#define QPHY_PCIE_V6_20_PCS_ENDPOINT_REFCLK_CNTRL 0x020 #define QPHY_PCIE_V6_20_PCS_OSC_DTCT_ATCIONS 0x090 #define QPHY_PCIE_V6_20_PCS_EQ_CONFIG1 0x0a0 #define QPHY_PCIE_V6_20_PCS_EQ_CONFIG5 0x108 From patchwork Tue Nov 7 12:26:15 2023 Content-Type: text/plain; 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Tue, 07 Nov 2023 04:40:57 -0800 (PST) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781909025567238231 X-GMAIL-MSGID: 1781909025567238231 In PCIe low power states like L1.1 or L1.2 the phy will stop supplying refclk to endpoint. If endpoint asserts clkreq to bring back link L0, then RC needs to provide refclk to endpoint. If there is some issues in platform with clkreq signal propagation to host and due to that host will not send refclk which results PCIe link down. For those platforms phy needs to provide refclk even in low power states. Add a flag to keep refclk always supplied to endpoint. Signed-off-by: Krishna chaitanya chundru Reviewed-by: Dmitry Baryshkov --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 74d03d217ff2..a8d6d69e3f74 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -43,6 +43,8 @@ /* QPHY_PCS_STATUS bit */ #define PHYSTATUS BIT(6) #define PHYSTATUS_4_20 BIT(7) +/* PCS_PCIE_ENDPOINT_REFCLK_CNTRL */ +#define EPCLK_ALWAYS_ON_EN BIT(6) #define PHY_INIT_COMPLETE_TIMEOUT 10000 @@ -2264,6 +2266,8 @@ struct qmp_pcie { struct phy *phy; int mode; + bool refclk_always_on; + struct clk_fixed_rate pipe_clk_fixed; }; @@ -3179,6 +3183,10 @@ static void qmp_pcie_init_registers(struct qmp_pcie *qmp, const struct qmp_phy_c qmp_pcie_configure(pcs, tbls->pcs, tbls->pcs_num); qmp_pcie_configure(pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num); + if (qmp->refclk_always_on && cfg->regs[QPHY_PCS_ENDPOINT_REFCLK_CNTRL]) + qphy_setbits(pcs_misc, cfg->regs[QPHY_PCS_ENDPOINT_REFCLK_CNTRL], + EPCLK_ALWAYS_ON_EN); + if (cfg->lanes >= 4 && qmp->tcsr_4ln_config) { qmp_pcie_configure(serdes, cfg->serdes_4ln_tbl, cfg->serdes_4ln_num); qmp_pcie_init_port_b(qmp, tbls); @@ -3701,6 +3709,12 @@ static int qmp_pcie_probe(struct platform_device *pdev) if (ret) goto err_node_put; + qmp->refclk_always_on = of_property_read_bool(dev->of_node, "qcom,refclk-always-on"); + if (qmp->refclk_always_on && !qmp->cfg->regs[QPHY_PCS_ENDPOINT_REFCLK_CNTRL]) { + dev_err(dev, "refclk is always on is present but refclk cntrl offset is not present\n"); + goto err_node_put; + } + ret = phy_pipe_clk_register(qmp, np); if (ret) goto err_node_put;