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[2620:137:e000::1:20]) by mx.google.com with ESMTP id p12-20020a17090ab90c00b00200acd39846si13242514pjr.63.2022.11.08.07.44.19; Tue, 08 Nov 2022 07:44:32 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xA55vWia; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234356AbiKHPlL (ORCPT + 99 others); Tue, 8 Nov 2022 10:41:11 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59176 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234256AbiKHPlH (ORCPT ); Tue, 8 Nov 2022 10:41:07 -0500 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DF173140E9 for ; Tue, 8 Nov 2022 07:41:06 -0800 (PST) Received: by mail-wm1-x32e.google.com with SMTP id t1so9065884wmi.4 for ; Tue, 08 Nov 2022 07:41:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=J2RysX7TiVCclv2UJBtgXviDFq2/T3mQypqGPEA1b7s=; b=xA55vWiaWt8+Fe2aBbuyjq3MufWdeda/bR3VkkuFVXy/V29Bn6ByY13oKRLcE0c0Ix twWWJ+pcSFTWqzaI1Dj0ByIFNnejv6NQfJCfDqXbdg1b2R7L5mBfV2QQ+JAmH3q2oEO8 1f5gJKr6qA9czzXKrUwjln7XBPP6fgTOGQBLXd49aMbQisAWxSnwHcn7LVXO+ARPvyJJ iKoOGCioiyMm6lLAmkMU9OLd+8kF6JhVCmEgX+0qpAbl89EEwXW5A1cNfbyfMU04bL3s CwZceFoA2ubcBjKOwMZI4Z+8BM1qVpQat7OGXfx0T2hTyc/07azuwLW+1lJ9ie84N19H 0wxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=J2RysX7TiVCclv2UJBtgXviDFq2/T3mQypqGPEA1b7s=; b=vHrywfz6+eqYWC6LHgQGPCD320vCRIs1BBiymKYgtyEih67eVZrscn9oAefzVnIOp/ PtCOnquCBMOrkO2cIBrjoDwQzg8osknt648n/cqIefGu6d3P0eKFOb5rRzOcC/WoH/A9 gGrkrwoEaKaekRpmKTkXqmANY+FLdV5E4lWn41qsrYUYW882LJ9TR8wVFl/Xlg0eu0fK b3NkIJ307Ylkxpo1xa1GV12YX3We+1UadIR1za56HzgNd1TTaTxCtUoqYWFCaFVOwp/G awpmsNUSxXMNgBtvJaDwL8LM7kLpwKfapTpbbffiOUL5P2Ao3tYVC776TvJcGNmOaepO cH8w== X-Gm-Message-State: ACrzQf04c0nP3FQyXyWF6AMZnJmnFk9+LbaiOma8dZ4lpsriF3cKvi7d EAJZ1c8lq4jVXzU12U2u7QhG X-Received: by 2002:a7b:c5d6:0:b0:3c6:f970:e755 with SMTP id n22-20020a7bc5d6000000b003c6f970e755mr37377706wmk.132.1667922066448; Tue, 08 Nov 2022 07:41:06 -0800 (PST) Received: from localhost.localdomain ([117.207.25.46]) by smtp.gmail.com with ESMTPSA id e4-20020adff344000000b002364c77bc96sm10906899wrp.33.2022.11.08.07.40.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Nov 2022 07:41:05 -0800 (PST) From: Manivannan Sadhasivam To: andersson@kernel.org, viresh.kumar@linaro.org, krzysztof.kozlowski+dt@linaro.org, rafael@kernel.org, robh+dt@kernel.org Cc: johan@kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Manivannan Sadhasivam , Rob Herring Subject: [PATCH v5 1/3] dt-bindings: cpufreq: cpufreq-qcom-hw: Add cpufreq clock provider Date: Tue, 8 Nov 2022 21:10:35 +0530 Message-Id: <20221108154037.111794-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221108154037.111794-1-manivannan.sadhasivam@linaro.org> References: <20221108154037.111794-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748943264848358061?= X-GMAIL-MSGID: =?utf-8?q?1748943264848358061?= Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks to the CPU cores. Document the same in the binding to reflect the actual implementation. CPUFreq HW will become the clock provider and CPU cores will become the clock consumers. The clock index for each CPU core is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Rob Herring --- .../devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml index e58c55f78aaa..676d369a6fdd 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml @@ -56,6 +56,9 @@ properties: '#freq-domain-cells': const: 1 + '#clock-cells': + const: 1 + required: - compatible - reg @@ -83,6 +86,7 @@ examples: enable-method = "psci"; next-level-cache = <&L2_0>; qcom,freq-domain = <&cpufreq_hw 0>; + clocks = <&cpufreq_hw 0>; L2_0: l2-cache { compatible = "cache"; cache-unified; @@ -103,6 +107,7 @@ examples: enable-method = "psci"; next-level-cache = <&L2_100>; qcom,freq-domain = <&cpufreq_hw 0>; + clocks = <&cpufreq_hw 0>; L2_100: l2-cache { compatible = "cache"; cache-unified; @@ -118,6 +123,7 @@ examples: enable-method = "psci"; next-level-cache = <&L2_200>; qcom,freq-domain = <&cpufreq_hw 0>; + clocks = <&cpufreq_hw 0>; L2_200: l2-cache { compatible = "cache"; cache-unified; @@ -133,6 +139,7 @@ examples: enable-method = "psci"; next-level-cache = <&L2_300>; qcom,freq-domain = <&cpufreq_hw 0>; + clocks = <&cpufreq_hw 0>; L2_300: l2-cache { compatible = "cache"; cache-unified; @@ -148,6 +155,7 @@ examples: enable-method = "psci"; next-level-cache = <&L2_400>; qcom,freq-domain = <&cpufreq_hw 1>; + clocks = <&cpufreq_hw 1>; L2_400: l2-cache { compatible = "cache"; cache-unified; @@ -163,6 +171,7 @@ examples: enable-method = "psci"; next-level-cache = <&L2_500>; qcom,freq-domain = <&cpufreq_hw 1>; + clocks = <&cpufreq_hw 1>; L2_500: l2-cache { compatible = "cache"; cache-unified; @@ -178,6 +187,7 @@ examples: enable-method = "psci"; next-level-cache = <&L2_600>; qcom,freq-domain = <&cpufreq_hw 1>; + clocks = <&cpufreq_hw 1>; L2_600: l2-cache { compatible = "cache"; cache-unified; @@ -193,6 +203,7 @@ examples: enable-method = "psci"; next-level-cache = <&L2_700>; qcom,freq-domain = <&cpufreq_hw 1>; + clocks = <&cpufreq_hw 1>; L2_700: l2-cache { compatible = "cache"; cache-unified; @@ -215,6 +226,7 @@ examples: clock-names = "xo", "alternate"; #freq-domain-cells = <1>; + #clock-cells = <1>; }; }; ... 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But this relationship is not represented in DTS so far. So let's make cpufreq node as the clock provider and CPU nodes as the consumers. The clock index for each CPU node is based on the frequency domain index. Signed-off-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sm8450.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index d32f08df743d..234d2722a4fa 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -51,6 +51,7 @@ CPU0: cpu@0 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; + clocks = <&cpufreq_hw 0>; L2_0: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -70,6 +71,7 @@ CPU1: cpu@100 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; + clocks = <&cpufreq_hw 0>; L2_100: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -86,6 +88,7 @@ CPU2: cpu@200 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; + clocks = <&cpufreq_hw 0>; L2_200: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -102,6 +105,7 @@ CPU3: cpu@300 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 0>; #cooling-cells = <2>; + clocks = <&cpufreq_hw 0>; L2_300: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -118,6 +122,7 @@ CPU4: cpu@400 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; + clocks = <&cpufreq_hw 1>; L2_400: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -134,6 +139,7 @@ CPU5: cpu@500 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; + clocks = <&cpufreq_hw 1>; L2_500: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -151,6 +157,7 @@ CPU6: cpu@600 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 1>; #cooling-cells = <2>; + clocks = <&cpufreq_hw 1>; L2_600: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -167,6 +174,7 @@ CPU7: cpu@700 { power-domain-names = "psci"; qcom,freq-domain = <&cpufreq_hw 2>; #cooling-cells = <2>; + clocks = <&cpufreq_hw 2>; L2_700: l2-cache { compatible = "cache"; next-level-cache = <&L3_0>; @@ -3075,6 +3083,7 @@ cpufreq_hw: cpufreq@17d91000 { ; interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2"; #freq-domain-cells = <1>; + #clock-cells = <1>; }; gem_noc: interconnect@19100000 { From patchwork Tue Nov 8 15:40:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 17107 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2787208wru; Tue, 8 Nov 2022 07:46:06 -0800 (PST) X-Google-Smtp-Source: AMsMyM4Gf8adz+C25Vpsl38YQsFv3opoXeIkA03IMPeHn8NiN5lrP7JxGIN31Q7/h7Sf7ULCMSj4 X-Received: by 2002:a17:903:1381:b0:186:8bdb:6865 with SMTP id jx1-20020a170903138100b001868bdb6865mr55998255plb.166.1667922366260; Tue, 08 Nov 2022 07:46:06 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1667922366; cv=none; d=google.com; s=arc-20160816; b=cEZWGzxdsjkxp+x1/vXgPct7RqNbUVtL6vtHmmmEmuokAyaRJtvC/Z0eZTreeSn4AZ MVoCFGrwxtjwecqcQyydr6GxH4wrRhQTrmcl9m0BxyKeg9zV3HiBxAAj83uEnzJeyAx0 F6gaOAZpB+ZcPKo7zP85oVRTupB8HC2IEU3CYh4ygqwr+RVe0Empo+vo7ol8kdnrpJRg JMarLfN8GT3VUyleQk/7slKu8r5hwZbHMjfamwoYTxN6UI4aQp+8R1tLxVxF4aJcktq6 OE84T6JfQrlE2vlHlTOH6q8vDWPBX8/IEKWARMJCmhyOaiIxA2Ta89MWwXGawf8Pz97J X0Tw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=yIl+Qt8RB0v0fumM9NIaZyrAwuRsmhqUeWJ9GHQ1hx0=; b=pnnbUJBFtY4GqmJZfM8OhHoZjsW8ENlBekehpj/Fkb0Y9QTEIVEUf7kBi/p7sw+uCZ PGMN5zBP6yw3+QpckT2438c4S6Wox1gYae6LPauDfsC4/Bi2VuH3sm9U0KqmZeSb9y6V v+MByHS3wLJysl8bsz8nEHOGFkAoSjH+x93gOQYb0DTLiDk4z7zm74MU2TOQI7o+3Fal Tas9iYfSGbB6rmTzFuxrj/24k2Epf2RjCh1kYVhLkkjY48vae/txijBGme7/BqgXEje3 4M1bRY8N3ogvx14Ntbv7V35aueBGj7BKzAmktbhShZLwUBVHD3b18W8BLMlZEzb2y+/I m+Wg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tCARyLvz; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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But this relationship is not represented with the clk framework so far. So, let's make the qcom-cpufreq-hw driver a clock provider. This makes the clock producer/consumer relationship cleaner and is also useful for CPU related frameworks like OPP to know the frequency at which the CPUs are running. The clock frequency provided by the driver is for each frequency domain. We cannot get the frequency of each CPU core because, not all platforms support per-core DCVS feature. Also the frequency supplied by the driver is the actual frequency that comes out of the EPSS/OSM block after the DCVS operation. This frequency is not same as what the CPUFreq framework has set but it is the one that gets supplied to the CPUs after throttling by LMh. Signed-off-by: Manivannan Sadhasivam --- drivers/cpufreq/qcom-cpufreq-hw.c | 43 +++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/drivers/cpufreq/qcom-cpufreq-hw.c b/drivers/cpufreq/qcom-cpufreq-hw.c index 5e0598730a04..86bb11de347f 100644 --- a/drivers/cpufreq/qcom-cpufreq-hw.c +++ b/drivers/cpufreq/qcom-cpufreq-hw.c @@ -4,6 +4,7 @@ */ #include +#include #include #include #include @@ -54,6 +55,7 @@ struct qcom_cpufreq_data { bool cancel_throttle; struct delayed_work throttle_work; struct cpufreq_policy *policy; + struct clk_hw cpu_clk; bool per_core_dcvs; @@ -615,8 +617,20 @@ static struct cpufreq_driver cpufreq_qcom_hw_driver = { .ready = qcom_cpufreq_ready, }; +static unsigned long qcom_cpufreq_hw_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) +{ + struct qcom_cpufreq_data *data = container_of(hw, struct qcom_cpufreq_data, cpu_clk); + + return qcom_lmh_get_throttle_freq(data); +} + +static const struct clk_ops qcom_cpufreq_hw_clk_ops = { + .recalc_rate = qcom_cpufreq_hw_recalc_rate, +}; + static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev) { + struct clk_hw_onecell_data *clk_data; struct device *dev = &pdev->dev; struct device *cpu_dev; struct clk *clk; @@ -659,8 +673,16 @@ static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev) qcom_cpufreq.soc_data = of_device_get_match_data(dev); + clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, num_domains), GFP_KERNEL); + if (!clk_data) + return -ENOMEM; + + clk_data->num = num_domains; + for (i = 0; i < num_domains; i++) { struct qcom_cpufreq_data *data = &qcom_cpufreq.data[i]; + struct clk_init_data init = {}; + const char *clk_name; struct resource *res; void __iomem *base; @@ -672,6 +694,27 @@ static int qcom_cpufreq_hw_driver_probe(struct platform_device *pdev) data->base = base; data->res = res; + + /* Register CPU clock for each frequency domain */ + clk_name = devm_kasprintf(dev, GFP_KERNEL, "qcom_cpufreq%d", i); + init.name = clk_name; + init.flags = CLK_GET_RATE_NOCACHE; + init.ops = &qcom_cpufreq_hw_clk_ops; + data->cpu_clk.init = &init; + + ret = devm_clk_hw_register(dev, &data->cpu_clk); + if (ret < 0) { + dev_err(dev, "Failed to register Qcom CPUFreq clock\n"); + return ret; + } + + clk_data->hws[i] = &data->cpu_clk; + } + + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clk_data); + if (ret < 0) { + dev_err(dev, "Failed to add Qcom CPUFreq clock provider\n"); + return ret; } ret = cpufreq_register_driver(&cpufreq_qcom_hw_driver);