From patchwork Tue Nov 8 14:23:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 17071 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2741611wru; Tue, 8 Nov 2022 06:29:30 -0800 (PST) X-Google-Smtp-Source: AMsMyM53ZNSvMYzXAGFdpp+MjwRNd+QT7cTQl/q45iWVa/GyN7W/ziOCCxNjKQPU8YKlkNWlfyvp X-Received: by 2002:a05:6402:754:b0:463:67da:3dc with SMTP id p20-20020a056402075400b0046367da03dcmr46735094edy.386.1667917770070; Tue, 08 Nov 2022 06:29:30 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1667917770; cv=none; d=google.com; s=arc-20160816; b=AOcHJU9h4rvlOBE7vKFCUahsbMZhSU4Ck/kHQgCy/kU1UlPl+zQY6J1Fjsdk1hkzAQ 4VR+8M7k8xpx1v29zJBv/1lS8Epg8f0MgqVgwfSft/HtYYkgiWBQaw/PsKC6E6a4QwTU rPFmemaoGJliy8IE9twd23f3JgQMKvZWjbReiN0QKkHnbixBypaLc8aUBeYqLqxel1zz gl9KmFF1ecHZ+cgGtrms8NF6it4VsUzDwETPiblMnFijv6HWeEwDXbhJ/y00xXtUDZhz deZGxQ/U83Eol8LUZV1M+NFDjwMdlyJ4vNE6FtOUHVIrnZJRGFaD1WqRQDMkQI2zAZWn dUsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=kzxTV0X+yQxXJgZlrlaClTgQHtvgc1ORzzoobFuqWL0=; b=b89+wf5DS8O0fFUWabY9A8ZFukmFfBQP5rZhmYeLDWUw7DWhWul6o2G6hfHTEyGyS7 jZuHmFraR/DnO6+ax3YW+/RYJCAvQHi9sOdmwHlIwXeZdYeysmLsOA1txnq3pGTOSBlc I3wUeVztjYLO2pG90BIgqlwzqoqB2Tu3LPnfBK9vbF9VfPZB5MGy/+twJ2wfDAvpHdjS 7eZH+FV5alHwqJA0srPMWRLvL4aTyP7seAV9z+YzLnO9gwu7n8VLYcToJnh8lgl/RX/X XqGSCG/EoEepiry3isSPyLSdXxdOFSwnVhYRkd+JktFzC4e/6O+Ywac7LqqOkaJT6KaU 5Wmw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NNWN8VT0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id r13-20020a05640251cd00b00462e5d768b3si15538616edd.612.2022.11.08.06.29.00; Tue, 08 Nov 2022 06:29:30 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NNWN8VT0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234310AbiKHOZv (ORCPT + 99 others); Tue, 8 Nov 2022 09:25:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57672 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234423AbiKHOZY (ORCPT ); Tue, 8 Nov 2022 09:25:24 -0500 Received: from mail-lj1-x22f.google.com (mail-lj1-x22f.google.com [IPv6:2a00:1450:4864:20::22f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 101E754B36 for ; Tue, 8 Nov 2022 06:24:03 -0800 (PST) Received: by mail-lj1-x22f.google.com with SMTP id z24so21345378ljn.4 for ; Tue, 08 Nov 2022 06:24:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=kzxTV0X+yQxXJgZlrlaClTgQHtvgc1ORzzoobFuqWL0=; b=NNWN8VT07DCC3zDfTVTAG14DrKNcDUhkMCeJG4wKqNPfOCeu3/+5fKWcgPUSBYBcao qSlVXfb7G/v2Qm0KlRhXYCe/GN218qFxST+DFzCGFpf8RId9qM2p2M/8/iW0KzuLozuH n9h/aw+vOM1VXBjZ4+qvUNG00ognxosf4wenhMjFdv2RUWay068kdc4SOEc3OiWdbyZq 3RlYxLBw4xiOPE+QzLkW4LAoJ0l1VAb7ZOgXFSFCzLbjYTZ7CuT7VEwlsf2LOgTr57I5 KqSBJpETWyw0QHz7UC/bT0WopfYD4gNZIfpOFvaLBv97Yhjw2o851rjLMDsf3ycUPTfU bCZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=kzxTV0X+yQxXJgZlrlaClTgQHtvgc1ORzzoobFuqWL0=; b=6JaH34oLadAI+l59d091x2emu0k5EWdZ21+0zhlu6cTmLi1jbnZgbAcwRq3l8Vah0j XmXSeqRmjjLMgDCQZpkM9RospJC9YJMCdxU2Pxjbq+xOD0nTMT9Zwv7AdSLsErIMutHz hfa04uD3cL7UjVuVRJ1+RrsXN12T24MrRGca2Z11TeeKkWjyZDlVLVRFSPWDea7WWlMc th+mLy+AvrdEjoaiyYEoArQqhztWIicZ79X34JEbEFTji2QKFABrFIkLLTW8rXNO8BHQ B65kMpJhcGmTBzUT9x32jBzz/SuAE3AchUlZ+DiIN/s5LctR2tIBSrhwgqP4lBjW1uxx suWg== X-Gm-Message-State: ACrzQf3IGpP5GeDaDfxgX0CwckBDyYlGuvfYfyUjHotqzc5t8YelCDJS kPIoMeghw+LQOLk0tZfEoXYFbg== X-Received: by 2002:a2e:8781:0:b0:26d:e758:ce84 with SMTP id n1-20020a2e8781000000b0026de758ce84mr18941581lji.178.1667917441301; Tue, 08 Nov 2022 06:24:01 -0800 (PST) Received: from krzk-bin.NAT.warszawa.vectranet.pl (088156142199.dynamic-2-waw-k-3-2-0.vectranet.pl. [88.156.142.199]) by smtp.gmail.com with ESMTPSA id k7-20020ac24f07000000b004a65780e4cfsm1815117lfr.106.2022.11.08.06.23.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Nov 2022 06:23:59 -0800 (PST) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 1/2] dt-bindings: pinctrl: qcom,ipq8074: convert to dtschema Date: Tue, 8 Nov 2022 15:23:56 +0100 Message-Id: <20221108142357.67202-1-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748938543740520229?= X-GMAIL-MSGID: =?utf-8?q?1748938543740520229?= Convert Qualcomm IPQ8074 pin controller bindings to DT schema. Keep the parsing of pin configuration subnodes consistent with other Qualcomm schemas (children named with '-state' suffix, their children with '-pins'). Signed-off-by: Krzysztof Kozlowski Reviewed-by: Linus Walleij Reviewed-by: Bjorn Andersson --- .../bindings/pinctrl/qcom,ipq8074-pinctrl.txt | 181 ------------------ .../pinctrl/qcom,ipq8074-pinctrl.yaml | 135 +++++++++++++ 2 files changed, 135 insertions(+), 181 deletions(-) delete mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt deleted file mode 100644 index 7b151894f5a0..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt +++ /dev/null @@ -1,181 +0,0 @@ -Qualcomm Technologies, Inc. IPQ8074 TLMM block - -This binding describes the Top Level Mode Multiplexer block found in the -IPQ8074 platform. - -- compatible: - Usage: required - Value type: - Definition: must be "qcom,ipq8074-pinctrl" - -- reg: - Usage: required - Value type: - Definition: the base address and size of the TLMM register space. - -- interrupts: - Usage: required - Value type: - Definition: should specify the TLMM summary IRQ. - -- interrupt-controller: - Usage: required - Value type: - Definition: identifies this node as an interrupt controller - -- #interrupt-cells: - Usage: required - Value type: - Definition: must be 2. Specifying the pin number and flags, as defined - in - -- gpio-controller: - Usage: required - Value type: - Definition: identifies this node as a gpio controller - -- #gpio-cells: - Usage: required - Value type: - Definition: must be 2. Specifying the pin number and flags, as defined - in - -- gpio-ranges: - Usage: required - Definition: see ../gpio/gpio.txt - -- gpio-reserved-ranges: - Usage: optional - Definition: see ../gpio/gpio.txt - -Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for -a general description of GPIO and interrupt bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -The pin configuration nodes act as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for a -pin, a group, or a list of pins or groups. This configuration can include the -mux function to select on those pin(s)/group(s), and various pin configuration -parameters, such as pull-up, drive strength, etc. - - -PIN CONFIGURATION NODES: - -The name of each subnode is not important; all subnodes should be enumerated -and processed purely based on their content. - -Each subnode only affects those parameters that are explicitly listed. In -other words, a subnode that lists a mux function but no pin configuration -parameters implies no information about any pin configuration parameters. -Similarly, a pin subnode that describes a pullup parameter implies no -information about e.g. the mux function. - - -The following generic properties as defined in pinctrl-bindings.txt are valid -to specify in a pin configuration subnode: - -- pins: - Usage: required - Value type: - Definition: List of gpio pins affected by the properties specified in - this subnode. Valid pins are: - gpio0-gpio69 - -- function: - Usage: required - Value type: - Definition: Specify the alternative function to be configured for the - specified pins. Functions are only valid for gpio pins. - Valid values are: - atest_char, atest_char0, atest_char1, atest_char2, - atest_char3, audio_rxbclk, audio_rxd, audio_rxfsync, - audio_rxmclk, audio_txbclk, audio_txd, audio_txfsync, - audio_txmclk, blsp0_i2c, blsp0_spi, blsp0_uart, blsp1_i2c, - blsp1_spi, blsp1_uart, blsp2_i2c, blsp2_spi, blsp2_uart, - blsp3_i2c, blsp3_spi, blsp3_spi0, blsp3_spi1, blsp3_spi2, - blsp3_spi3, blsp3_uart, blsp4_i2c0, blsp4_i2c1, blsp4_spi0, - blsp4_spi1, blsp4_uart0, blsp4_uart1, blsp5_i2c, blsp5_spi, - blsp5_uart, burn0, burn1, cri_trng, cri_trng0, cri_trng1, - cxc0, cxc1, dbg_out, gcc_plltest, gcc_tlmm, gpio, ldo_en, - ldo_update, led0, led1, led2, mac0_sa0, mac0_sa1, mac1_sa0, - mac1_sa1, mac1_sa2, mac1_sa3, mac2_sa0, mac2_sa1, mdc, - mdio, pcie0_clk, pcie0_rst, pcie0_wake, pcie1_clk, - pcie1_rst, pcie1_wake, pcm_drx, pcm_dtx, pcm_fsync, - pcm_pclk, pcm_zsi0, pcm_zsi1, prng_rosc, pta1_0, pta1_1, - pta1_2, pta2_0, pta2_1, pta2_2, pwm0, pwm1, pwm2, pwm3, - qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, - qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, - qdss_cti_trig_out_a0, qdss_cti_trig_out_a1, - qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, - qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a, - qdss_tracectl_b, qdss_tracedata_a, qdss_tracedata_b, - qpic, rx0, rx1, rx2, sd_card, sd_write, tsens_max, wci2a, - wci2b, wci2c, wci2d - -- bias-disable: - Usage: optional - Value type: - Definition: The specified pins should be configured as no pull. - -- bias-pull-down: - Usage: optional - Value type: - Definition: The specified pins should be configured as pull down. - -- bias-pull-up: - Usage: optional - Value type: - Definition: The specified pins should be configured as pull up. - -- output-high: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - high. - -- output-low: - Usage: optional - Value type: - Definition: The specified pins are configured in output mode, driven - low. - -- drive-strength: - Usage: optional - Value type: - Definition: Selects the drive strength for the specified pins, in mA. - Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16 - -Example: - - tlmm: pinctrl@1000000 { - compatible = "qcom,ipq8074-pinctrl"; - reg = <0x1000000 0x300000>; - interrupts = ; - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&tlmm 0 0 70>; - interrupt-controller; - #interrupt-cells = <2>; - - uart2: uart2-default { - mux { - pins = "gpio23", "gpio24"; - function = "blsp4_uart1"; - }; - - rx { - pins = "gpio23"; - drive-strength = <4>; - bias-disable; - }; - - tx { - pins = "gpio24"; - drive-strength = <2>; - bias-pull-up; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.yaml new file mode 100644 index 000000000000..c02dd2ad9b31 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.yaml @@ -0,0 +1,135 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,ipq8074-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ8074 TLMM pin controller + +maintainers: + - Bjorn Andersson + - Krzysztof Kozlowski + +description: + Top Level Mode Multiplexer pin controller in Qualcomm IPQ8074 SoC. + +properties: + compatible: + const: qcom,ipq8074-pinctrl + + reg: + maxItems: 1 + + interrupts: true + interrupt-controller: true + "#interrupt-cells": true + gpio-controller: true + "#gpio-cells": true + gpio-ranges: true + wakeup-parent: true + + gpio-reserved-ranges: + minItems: 1 + maxItems: 35 + + gpio-line-names: + maxItems: 70 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-ipq8074-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-ipq8074-tlmm-state" + additionalProperties: false + +$defs: + qcom-ipq8074-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|[1-6][0-9]|70)$" + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ gpio, atest_char, atest_char0, atest_char1, atest_char2, + atest_char3, audio_rxbclk, audio_rxd, audio_rxfsync, + audio_rxmclk, audio_txbclk, audio_txd, audio_txfsync, + audio_txmclk, blsp0_i2c, blsp0_spi, blsp0_uart, blsp1_i2c, + blsp1_spi, blsp1_uart, blsp2_i2c, blsp2_spi, blsp2_uart, + blsp3_i2c, blsp3_spi, blsp3_spi0, blsp3_spi1, blsp3_spi2, + blsp3_spi3, blsp3_uart, blsp4_i2c0, blsp4_i2c1, blsp4_spi0, + blsp4_spi1, blsp4_uart0, blsp4_uart1, blsp5_i2c, blsp5_spi, + blsp5_uart, burn0, burn1, cri_trng, cri_trng0, cri_trng1, cxc0, + cxc1, dbg_out, gcc_plltest, gcc_tlmm, ldo_en, ldo_update, led0, + led1, led2, mac0_sa0, mac0_sa1, mac1_sa0, mac1_sa1, mac1_sa2, + mac1_sa3, mac2_sa0, mac2_sa1, mdc, mdio, pcie0_clk, pcie0_rst, + pcie0_wake, pcie1_clk, pcie1_rst, pcie1_wake, pcm_drx, pcm_dtx, + pcm_fsync, pcm_pclk, pcm_zsi0, pcm_zsi1, prng_rosc, pta1_0, + pta1_1, pta1_2, pta2_0, pta2_1, pta2_2, pwm0, pwm1, pwm2, pwm3, + qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, qdss_cti_trig_in_b0, + qdss_cti_trig_in_b1, qdss_cti_trig_out_a0, + qdss_cti_trig_out_a1, qdss_cti_trig_out_b0, + qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_traceclk_b, + qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a, + qdss_tracedata_b, qpic, rx0, rx1, rx2, sd_card, sd_write, + tsens_max, wci2a, wci2b, wci2c, wci2d ] + + bias-pull-down: true + bias-pull-up: true + bias-disable: true + drive-strength: true + input-enable: true + output-high: true + output-low: true + + required: + - pins + + additionalProperties: false + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq8074-pinctrl"; + reg = <0x01000000 0x300000>; + interrupts = ; + gpio-controller; + gpio-ranges = <&tlmm 0 0 70>; + #gpio-cells = <0x2>; + interrupt-controller; + #interrupt-cells = <0x2>; + + serial4-state { + pins = "gpio23", "gpio24"; + function = "blsp4_uart1"; + drive-strength = <8>; + bias-disable; + }; + }; From patchwork Tue Nov 8 14:23:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Krzysztof Kozlowski X-Patchwork-Id: 17070 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2741597wru; Tue, 8 Nov 2022 06:29:28 -0800 (PST) X-Google-Smtp-Source: AMsMyM62IjZnAW0PYBX7OwMzZ9EGH0riohqMkamf3W++diI6iHxMeTNyafXYSKH5jwTPyUW6CJwv X-Received: by 2002:a17:907:1b1e:b0:783:8e33:2d1c with SMTP id mp30-20020a1709071b1e00b007838e332d1cmr52980752ejc.304.1667917768192; Tue, 08 Nov 2022 06:29:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1667917768; cv=none; d=google.com; s=arc-20160816; b=QuDDRGr6Nbihjdu0XBWmMMnscm/1Sh8mLf0xuTWgnBAfJP+teycx5OT7E6GyTEzrZo QOlndMboBSHFfyx2rhhAXhvztKfLjfL6TeezxTFDmsGEWFn29nb+NeISsOIRineLJ97r rq7NE0zm+3+JZG/r223GN/ZBRwGjIrYcZXx62YA6NhocIiXpCowK/jFLV3dar1U1NeTE UPrtOMs/LJ1vWHXDMl/D23WQ9HUayeZIAAyhN1DUiaD+dE3iITBPdfYELR+Yug0ddUfh IWpDV6NIDOHj3oIuBIse60GfcdMEn90+OR82lk54i75mfydd6vw+uHLmjsXyvijCh/aR sZwA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=dnA9bYpkTooTYFD8QmC/+zf1bx2KSFMylSXBFYcLmDE=; b=F2+iyKMLlb1ymT+sGFl2t2kNGEFfO3p/vHvKIjXkQyWIY8hok/id1ePvf58SdlodiR 0zuUZycsWikW3mGvMzijLrBy0WhKIDmUAFjnDm3PyI9Ee/UPDvezQNhmcr0RrPwhq4UC 80pSWqIbzCfGz4JIaJ8Wi7VGUcdk+KM37FKIHKn7niwggBRp54d6Me21nx5bnWZrQhA5 5xV2YYF+iwidfOHk7XRedtrE+IUNT6DjaXaQIVODf1WpSh9dBRZ4vdlNyxR2hHSJNaom CDA4HUtLcWL6QGDCPOEbpjSdIfe1+yMGJLF6YsieEMfq6b68O+NDbhSIqoa4hPwD3jVE EYwA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=w+jxQcrX; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id q24-20020a056402033800b0045878af0adbsi11442006edw.393.2022.11.08.06.29.02; Tue, 08 Nov 2022 06:29:28 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=w+jxQcrX; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233943AbiKHOZz (ORCPT + 99 others); Tue, 8 Nov 2022 09:25:55 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58782 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233638AbiKHOZ0 (ORCPT ); Tue, 8 Nov 2022 09:25:26 -0500 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0D1EE7054F for ; Tue, 8 Nov 2022 06:24:04 -0800 (PST) Received: by mail-lf1-x135.google.com with SMTP id d6so21451544lfs.10 for ; Tue, 08 Nov 2022 06:24:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dnA9bYpkTooTYFD8QmC/+zf1bx2KSFMylSXBFYcLmDE=; b=w+jxQcrXMmL3YJK2Yqlz9qJJAFSmW9RV0w4RDT8uZYaWLnavtdA9o9cOAPvlAz3Nzm ROxchebgsEtjz33rq0UOvaZYn10Q8fRNW79DAWcpzLxvTUUdyM8RBB38SjnOwU0XEvnn 4ez2AXTkfjZ2vnqovvqVfhPEwo8ePxqlV1+uPkURDejBDWjm9oqRZ+TMOASEm21GChGg EsJiOX9BvEb2CXqKbHpnV+PyNbhk2vhJG0f5ji3er96WIi5x7bhKxeLhd8Q71HvCRLTF tUZD7iJv1GIK5jXoKjXoMcK/aFdMZI3cGp4CLw57hOQ35WvKAJ3MoZlOo31jKOgwyWXO hsDw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dnA9bYpkTooTYFD8QmC/+zf1bx2KSFMylSXBFYcLmDE=; b=E8OyPXueTVHeX4OkxGz/GN8B2ZwNqQpp2wVxb7Z6Klxg0uO6v+DltdzpbcPXNK7O8A /FTSK9BwklhjZPLGFNUAdK63KGT0B0PQ2+g9M/HK9WJ1NH09XvCMcP2maB3ZHuY5JDoN czxBjGpHDTXr7EoZbN+mi11fyH+qbKVyrfabgqbmSDQyx5js9zVRYiRw3RXjZHrrpGF9 gXBCYBhHQg/y8fknLloUIGJKCQw0l0n9Fhr9XJahI0FpYV0ewzeljWssqPFVP0y4d/KP ftstaO5q77tBSCPBtWdoLCvG1sPpF8XK6WRitYPUoUV5UwCHp9wCmu8K7RcLb+J+G5Vr q68g== X-Gm-Message-State: ACrzQf1LFayxULbAnYZ6pWHvZmLc+6elHCfFdgjn42oqx2fJ3/YNIYea dynQrU1HGxHRjyIyaAlBt0lBSQ== X-Received: by 2002:ac2:447c:0:b0:4a2:4fc6:4cbb with SMTP id y28-20020ac2447c000000b004a24fc64cbbmr18747443lfl.99.1667917442449; Tue, 08 Nov 2022 06:24:02 -0800 (PST) Received: from krzk-bin.NAT.warszawa.vectranet.pl (088156142199.dynamic-2-waw-k-3-2-0.vectranet.pl. [88.156.142.199]) by smtp.gmail.com with ESMTPSA id k7-20020ac24f07000000b004a65780e4cfsm1815117lfr.106.2022.11.08.06.24.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 08 Nov 2022 06:24:01 -0800 (PST) From: Krzysztof Kozlowski To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Linus Walleij , Rob Herring , Krzysztof Kozlowski , linux-arm-msm@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [PATCH 2/2] arm64: dts: qcom: ipq8074: align TLMM pin configuration with DT schema Date: Tue, 8 Nov 2022 15:23:57 +0100 Message-Id: <20221108142357.67202-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221108142357.67202-1-krzysztof.kozlowski@linaro.org> References: <20221108142357.67202-1-krzysztof.kozlowski@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748938541481799887?= X-GMAIL-MSGID: =?utf-8?q?1748938541481799887?= DT schema expects TLMM pin configuration nodes to be named with '-state' suffix and their optional children with '-pins' suffix. Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index d3d9e7eb5837..363ccc272cf1 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -317,35 +317,35 @@ tlmm: pinctrl@1000000 { interrupt-controller; #interrupt-cells = <0x2>; - serial_4_pins: serial4-pinmux { + serial_4_pins: serial4-state { pins = "gpio23", "gpio24"; function = "blsp4_uart1"; drive-strength = <8>; bias-disable; }; - i2c_0_pins: i2c-0-pinmux { + i2c_0_pins: i2c-0-state { pins = "gpio42", "gpio43"; function = "blsp1_i2c"; drive-strength = <8>; bias-disable; }; - spi_0_pins: spi-0-pins { + spi_0_pins: spi-0-state { pins = "gpio38", "gpio39", "gpio40", "gpio41"; function = "blsp0_spi"; drive-strength = <8>; bias-disable; }; - hsuart_pins: hsuart-pins { + hsuart_pins: hsuart-state { pins = "gpio46", "gpio47", "gpio48", "gpio49"; function = "blsp2_uart"; drive-strength = <8>; bias-disable; }; - qpic_pins: qpic-pins { + qpic_pins: qpic-state { pins = "gpio1", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7", "gpio8", "gpio10", "gpio11",