From patchwork Thu Nov 2 03:06:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 160764 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:8f47:0:b0:403:3b70:6f57 with SMTP id j7csp95712vqu; Wed, 1 Nov 2023 20:06:58 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGg7L1ohmC9xSTGg50GQjgRwIWboalTsOki6g2qBiL36vz1nWAz3J9TLpJ8qTJ1ZnFXobGP X-Received: by 2002:a25:4201:0:b0:d9a:4d90:feda with SMTP id p1-20020a254201000000b00d9a4d90fedamr15741050yba.62.1698894417477; Wed, 01 Nov 2023 20:06:57 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1698894417; cv=pass; d=google.com; s=arc-20160816; b=Iei7ipbJFFlWDj/Wbsc0Q3vJOIZGqC5jkq3aANSEUPXwbV/Tje6yf4ujbVLCTfVmQ7 312WWbgtRd9p3YnvgYWWjlJVWuOzFRU7RolYDpGMVvgyi5nmI19NNRyvYhhk3SjdadMx sU/HNnq/PJBeUu1h/hcjtmc37MSPaISM7Ylf7hZhvVtJ/3VKSJHfuT2dxrksErbEgTIv Wk6ajZNrogXxQ6/JC02yeYfHs10MadUSx0jrRVlNr5zGHtk2ythmrDEKPaPJVp6sCHal 8IYNokq2Aw9txYiWAOEUeLEePGh/ZprbciwnehBCPF1y0VH/cpoaLJPx/g3h9j82drnj vGJA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:feedback-id :content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:arc-filter:dmarc-filter:delivered-to; bh=ZbZF8ugnwYzXIXnDS/caAJxrMesWEuZW7XvJLihnH/E=; fh=12MRPJmZ1mgDpHqWoogMKqnaGRGM2b7lcuJroqfjJiw=; b=BGRjIxTgHqqoWRpfTqmlD3LNYR3FjIf0JriM1LQdXF4uA7ZWNdg8ZjXc74/3uw3mph 4a4XkezQfO9nVOzfgm7K8FhjViHQK8DnBCwyl/3BJnn9cMox55iK8S2zuzuVJoKMv8O3 +rmg9CKMo+vbBscFFkCoGW2fcOPg6lraZIVVMgar3QXgSJI5MvylD2crInQUuItKFrKH 6fzpBqGqr5zPNPcg/nUU5cQvHXxTELTqMoPoUCYL9iVOQwscy0qLhPuw5B56v2Z525BX oCddJ2hoBtAfzgpx96UW8I10i0xctAOd/2PklPw4ITodBPKT8VuzuxOGGofoKkh0gVlf FDfQ== ARC-Authentication-Results: i=2; mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id v17-20020a05622a189100b0041cc3fd51a3si3742376qtc.13.2023.11.01.20.06.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 01 Nov 2023 20:06:57 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 3B5AA3858436 for ; Thu, 2 Nov 2023 03:06:57 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgsg1.qq.com (smtpbgsg1.qq.com [54.254.200.92]) by sourceware.org (Postfix) with ESMTPS id D36003858D35 for ; Thu, 2 Nov 2023 03:06:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org D36003858D35 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org D36003858D35 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=54.254.200.92 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698894391; cv=none; b=DuViXkczH2ghxs5QZz4LXzpMuhjDLT0XVksB4KSc919VncYH2zNA0snHjb2k2pKNaB+b2qryRm2Y9kt1MVWVi7JrApX5xElJCLMo2eXdwUAXG7zsTJYHbPXrGMS/J/gbIuuA1NAXIhovj/1Bs07InlSMyUkBcH8IpGP9yLOf5ks= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698894391; c=relaxed/simple; bh=DCcJbIuL9lrjQlLgXGduUgHVBl8tMGzUnXywSNIH9AY=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=nKwHWWF7a25Wwxh3tER/rmY01eGGMu/ucbzrXQc9nPaNrm9ZsEmZai9llDW4O5lQmmm6feCZWjfmZTijtLf/5sqy5fx+UW1LVGciN+9CxfOsbF2jTyhNL4J8SIF6Rp5n5OcnSOsltRf4fWzFoZ7ZyrUMHtHZvlkACEVqXuGbc2A= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp88t1698894373tcaav5mu Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Thu, 02 Nov 2023 11:06:12 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: +ujAKkuGAaU5owk494c4VYJay5pR4nILbZdBrD8oqhyyIj+olYRTIvdEV8toQ 32cSUN9Z2K5UT4jwzZK+6aJdn3osZ5Hx7ephnasTe1m+yOR6N8WtsGoWSqS2V613aHVh+Gk MVDb1LwNum9p6+tgMyBLL7O+9EaDveqeORy79hF+pZ0qe7rMGmmjNZMGNYZiqyKrIdds/Qe Q1Xh+oTVClxvusmb+w33mu280dWCatI8EoSILTDlP91GGcR+VxM5Xxc+cCQKQwvHQVBfD4B kYSz9oKw7KOjtxMybeh/UzHwibbC+wdURB1wKrkIFXHJfLK+dhDSQ6FXmcZEZgUhYCLOhMj PxI/5z4BqGfKMfn/IAJelUipCHqdcWFACfnYJv8/7TNunHPgRqMKSEB1l1WYlCQzPQDr9FD qdueDJ1keXRQESIH8H1CdQ== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 9836652447374621094 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Fix redundant vsetvl in fixed-vlmax vectorized codes[PR112326] Date: Thu, 2 Nov 2023 11:06:11 +0800 Message-Id: <20231102030611.2653544-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781419912892507132 X-GMAIL-MSGID: 1781419912892507132 With compile option --param=riscv-autovec-preference=fixed-vlmax, we have redundant AVL/VL toggling: vsetvli a5,a3,e8,mf4,ta,ma -> should be changed into e32m1 vle32.v v1,0(a1) vle32.v v2,0(a0) vsetivli zero,4,e32,m1,ta,ma -> redundant slli a2,a5,2 vadd.vv v1,v1,v2 sub a3,a3,a5 vsetvli zero,a5,e32,m1,ta,ma -> redundant vse32.v v1,0(a4) add a0,a0,a2 add a1,a1,a2 add a4,a4,a2 bne a3,zero,.L3 The root cause is because we simplify AVL into immediate AVL too early in FIXED-VLMAX situation. The later avlprop PASS failed to propagate AVL generated by (SELECT_VL/vsetvl VL, AVL) into the normal RVV instruction. So we need to remove immedate AVL simplification in 'expand' stage. After this patch: vsetvli a5,a3,e32,m1,ta,ma slli a2,a5,2 vle32.v v1,0(a1) vle32.v v2,0(a0) sub a3,a3,a5 vadd.vv v1,v1,v2 vse32.v v1,0(a4) add a0,a0,a2 add a1,a1,a2 add a4,a4,a2 bne a3,zero,.L3 After the removed simplification, the following situation should be fixed: typedef int8_t vnx2qi __attribute__ ((vector_size (2))); __attribute__ ((noipa)) void f_vnx2qi (int8_t a, int8_t b, int8_t *out) { vnx2qi v = {a, b}; *(vnx2qi *) out = v; } We should use vsetvili zero, 2 instead of vsetvl a5,zero. Such simplification is done in avlprop PASS which is also included in this patch to fix regression of these situation. PR target/112326 gcc/ChangeLog: * config/riscv/riscv-avlprop.cc (get_insn_vtype_mode): New function. (simplify_replace_vlmax_avl): Ditto. (pass_avlprop::execute): Add immediate AVL simplification. * config/riscv/riscv-protos.h (imm_avl_p): Rename. * config/riscv/riscv-v.cc (const_vlmax_p): Ditto. (imm_avl_p): Ditto. (emit_vlmax_insn): Adapt for new interface name. * config/riscv/vector.md (mode_idx): New attribute. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/pr112326.c: New test. --- gcc/config/riscv/riscv-avlprop.cc | 76 +++++++++++++++---- gcc/config/riscv/riscv-protos.h | 1 + gcc/config/riscv/riscv-v.cc | 24 ++---- gcc/config/riscv/vector.md | 29 ++++++- .../gcc.target/riscv/rvv/autovec/pr112326.c | 16 ++++ 5 files changed, 113 insertions(+), 33 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112326.c diff --git a/gcc/config/riscv/riscv-avlprop.cc b/gcc/config/riscv/riscv-avlprop.cc index c59eb7f6fa3..e4d14a89a91 100644 --- a/gcc/config/riscv/riscv-avlprop.cc +++ b/gcc/config/riscv/riscv-avlprop.cc @@ -109,6 +109,36 @@ vlmax_ta_p (rtx_insn *rinsn) return vlmax_avl_type_p (rinsn) && tail_agnostic_p (rinsn); } +static machine_mode +get_insn_vtype_mode (rtx_insn *rinsn) +{ + extract_insn_cached (rinsn); + int mode_idx = get_attr_mode_idx (rinsn); + gcc_assert (mode_idx != INVALID_ATTRIBUTE); + return GET_MODE (recog_data.operand[mode_idx]); +} + +static void +simplify_replace_vlmax_avl (rtx_insn *rinsn, rtx new_avl) +{ + /* Replace AVL operand. */ + extract_insn_cached (rinsn); + rtx avl = recog_data.operand[get_attr_vl_op_idx (rinsn)]; + int count = count_regno_occurrences (rinsn, REGNO (avl)); + gcc_assert (count == 1); + rtx new_pat = simplify_replace_rtx (PATTERN (rinsn), avl, new_avl); + validate_change_or_fail (rinsn, &PATTERN (rinsn), new_pat, false); + + /* Change AVL TYPE into NONVLMAX if it is VLMAX. */ + if (vlmax_avl_type_p (rinsn)) + { + int index = get_attr_avl_type_idx (rinsn); + gcc_assert (index != INVALID_ATTRIBUTE); + validate_change_or_fail (rinsn, recog_data.operand_loc[index], + get_avl_type_rtx (avl_type::NONVLMAX), false); + } +} + const pass_data pass_data_avlprop = { RTL_PASS, /* type */ "avlprop", /* name */ @@ -385,22 +415,7 @@ pass_avlprop::execute (function *fn) print_rtl_single (dump_file, rinsn); } /* Replace AVL operand. */ - extract_insn_cached (rinsn); - rtx avl = recog_data.operand[get_attr_vl_op_idx (rinsn)]; - int count = count_regno_occurrences (rinsn, REGNO (avl)); - gcc_assert (count == 1); - rtx new_pat = simplify_replace_rtx (PATTERN (rinsn), avl, prop.second); - validate_change_or_fail (rinsn, &PATTERN (rinsn), new_pat, false); - - /* Change AVL TYPE into NONVLMAX if it is VLMAX. */ - if (vlmax_avl_type_p (rinsn)) - { - int index = get_attr_avl_type_idx (rinsn); - gcc_assert (index != INVALID_ATTRIBUTE); - validate_change_or_fail (rinsn, recog_data.operand_loc[index], - get_avl_type_rtx (avl_type::NONVLMAX), - false); - } + simplify_replace_vlmax_avl (rinsn, prop.second); if (dump_file && (dump_flags & TDF_DETAILS)) { fprintf (dump_file, "Successfully to match this instruction: "); @@ -408,6 +423,35 @@ pass_avlprop::execute (function *fn) } } + if (riscv_autovec_preference == RVV_FIXED_VLMAX) + { + /* Simplify VLMAX AVL into immediate AVL. + E.g. Simplify this following case: + + vsetvl a5, zero, e32, m1 + vadd.vv + + into: + + vsetvl zero, 4, e32, m1 + vadd.vv + if GET_MODE_NUNITS (RVVM1SImode) == 4. */ + if (dump_file && (dump_flags & TDF_DETAILS)) + fprintf (dump_file, "\nSimplifying VLMAX AVL into IMM AVL\n\n"); + for (auto &candidate : m_candidates) + { + rtx_insn *rinsn = candidate.second->rtl (); + machine_mode vtype_mode = get_insn_vtype_mode (rinsn); + if (candidate.first == AVLPROP_VLMAX_TA + && !m_avl_propagations->get (candidate.second) + && imm_avl_p (vtype_mode)) + { + rtx new_avl = gen_int_mode (GET_MODE_NUNITS (vtype_mode), Pmode); + simplify_replace_vlmax_avl (rinsn, new_avl); + } + } + } + avlprop_done (); return 0; } diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h index 02056591ec6..6a0c59bd63f 100644 --- a/gcc/config/riscv/riscv-protos.h +++ b/gcc/config/riscv/riscv-protos.h @@ -593,6 +593,7 @@ bool vlmax_avl_p (rtx); uint8_t get_sew (rtx_insn *); enum vlmul_type get_vlmul (rtx_insn *); int count_regno_occurrences (rtx_insn *, unsigned int); +bool imm_avl_p (machine_mode); } /* We classify builtin types into two classes: diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index 668f3cd706b..679f922bc20 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -55,17 +55,17 @@ using namespace riscv_vector; namespace riscv_vector { -/* Return true if vlmax is constant value and can be used in vsetivl. */ -static bool -const_vlmax_p (machine_mode mode) +/* Return true if NUNTIS <=31 so that we can use immediate AVL in vsetivli. */ +bool +imm_avl_p (machine_mode mode) { poly_uint64 nuints = GET_MODE_NUNITS (mode); return nuints.is_constant () - /* The vsetivli can only hold register 0~31. */ - ? (IN_RANGE (nuints.to_constant (), 0, 31)) - /* Only allowed in VLS-VLMAX mode. */ - : false; + /* The vsetivli can only hold register 0~31. */ + ? (IN_RANGE (nuints.to_constant (), 0, 31)) + /* Only allowed in VLS-VLMAX mode. */ + : false; } /* Helper functions for insn_flags && insn_types */ @@ -298,14 +298,6 @@ public: len = force_reg (Pmode, len); vls_p = true; } - else if (const_vlmax_p (vtype_mode)) - { - /* Optimize VLS-VLMAX code gen, we can use vsetivli instead of - the vsetvli to obtain the value of vlmax. */ - poly_uint64 nunits = GET_MODE_NUNITS (vtype_mode); - len = gen_int_mode (nunits, Pmode); - vls_p = true; - } else if (can_create_pseudo_p ()) { len = gen_reg_rtx (Pmode); @@ -370,7 +362,7 @@ void emit_vlmax_insn (unsigned icode, unsigned insn_flags, rtx *ops) { insn_expander e (insn_flags, true); - gcc_assert (can_create_pseudo_p () || const_vlmax_p (e.get_vtype_mode (ops))); + gcc_assert (can_create_pseudo_p () || imm_avl_p (e.get_vtype_mode (ops))); e.emit_insn ((enum insn_code) icode, ops); } diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index a1a78120525..28baee59a9b 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -708,6 +708,32 @@ (const_int 5)] (const_int INVALID_ATTRIBUTE))) +;; The index of operand[] represents the machine mode of the instruction. +(define_attr "mode_idx" "" + (cond [(eq_attr "type" "vlde,vste,vldm,vstm,vlds,vsts,vldux,vldox,vldff,vldr,vstr,\ + vlsegde,vlsegds,vlsegdux,vlsegdox,vlsegdff,vialu,vext,vicalu,\ + vshift,vicmp,viminmax,vimul,vidiv,vimuladd,vimerge,vimov,\ + vsalu,vaalu,vsmul,vsshift,vfalu,vfmul,vfdiv,vfmuladd,vfsqrt,vfrecp,\ + vfcmp,vfminmax,vfsgnj,vfclass,vfmerge,vfmov,\ + vfcvtitof,vfncvtitof,vfncvtftoi,vfncvtftof,vmalu,vmiota,vmidx,\ + vimovxv,vfmovfv,vslideup,vslidedown,vislide1up,vislide1down,vfslide1up,vfslide1down,\ + vgather,vcompress,vmov") + (const_int 0) + + (eq_attr "type" "vimovvx,vfmovvf") + (const_int 1) + + (eq_attr "type" "vssegte,vnshift,vmpop,vmffs") + (const_int 2) + + (eq_attr "type" "vstux,vstox,vssegts,vssegtux,vssegtox,vfcvtftoi,vfwcvtitof,vfwcvtftoi, + vfwcvtftof,vmsfs,vired,viwred,vfredu,vfredo,vfwredu,vfwredo") + (const_int 3) + + (eq_attr "type" "viwalu,viwmul,viwmuladd,vnclip,vfwalu,vfwmul,vfwmuladd") + (const_int 4)] + (const_int INVALID_ATTRIBUTE))) + ;; The index of operand[] to get the avl op. (define_attr "vl_op_idx" "" (cond [(eq_attr "type" "vlde,vste,vimov,vfmov,vldm,vstm,vmalu,vsts,vstux,\ @@ -1207,7 +1233,8 @@ } [(set_attr "type" "vmov,vlde,vste") (set_attr "mode" "") - (set (attr "avl_type_idx") (const_int INVALID_ATTRIBUTE))]) + (set (attr "avl_type_idx") (const_int INVALID_ATTRIBUTE)) + (set (attr "mode_idx") (const_int INVALID_ATTRIBUTE))]) ;; ----------------------------------------------------------------- ;; ---- VLS Moves Operations diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112326.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112326.c new file mode 100644 index 00000000000..2ad50139cb2 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr112326.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3 -fno-vect-cost-model --param=riscv-autovec-preference=fixed-vlmax" } */ + +void +f (int *__restrict y, int *__restrict x, int *__restrict z, int n) +{ + for (int i = 0; i < n; ++i) + x[i] = y[i] + x[i]; +} + +/* { dg-final { scan-assembler-times {vsetvli} 1 } } */ +/* { dg-final { scan-assembler-not {vsetivli} } } */ +/* { dg-final { scan-assembler-times {vsetvli\s*[a-x0-9]+,\s*[a-x0-9]+} 1 } } */ +/* { dg-final { scan-assembler-not {vsetvli\s*[a-x0-9]+,\s*zero} } } */ +/* { dg-final { scan-assembler-not {vsetvli\s*zero} } } */ +/* { dg-final { scan-assembler-not {vsetivli\s*zero} } } */