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Wed, 01 Nov 2023 19:49:09 -0700 (PDT) From: Drew Fustini Date: Wed, 01 Nov 2023 19:48:52 -0700 Subject: [PATCH v4 1/7] dt-bindings: mmc: sdhci-of-dwcmhsc: Add T-Head TH1520 support MIME-Version: 1.0 Message-Id: <20231101-th1520-mmc-v4-1-86e0216b5994@baylibre.com> References: <20231101-th1520-mmc-v4-0-86e0216b5994@baylibre.com> In-Reply-To: <20231101-th1520-mmc-v4-0-86e0216b5994@baylibre.com> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jisheng Zhang , Adrian Hunter , Guo Ren , Fu Wei , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley Cc: Robert Nelson , Jason Kridner , Xi Ruoyao , Han Gao , Icenowy Zheng , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Drew Fustini , Krzysztof Kozlowski X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1698893345; l=855; i=dfustini@baylibre.com; s=20230430; h=from:subject:message-id; bh=sdi2GBRazAXQCmzsLeFCtwwLCyPq9k+jdkf3IoMSdfo=; b=H4G0SP7skk6Qkcbi+uapfpuNbAmQTW/dR3ZoBNmECYpgjatiRsb97dClg0sTNqpZ4Jlitliv7 IQ3UFs6gNtTCBp7USBUipzcGlL3y+nqr907S94xunPmACrwIsm57q05 X-Developer-Key: i=dfustini@baylibre.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 01 Nov 2023 19:49:26 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781418811768343150 X-GMAIL-MSGID: 1781418811768343150 Add compatible value for the T-Head TH1520 dwcmshc controller. Acked-by: Guo Ren Acked-by: Krzysztof Kozlowski Signed-off-by: Drew Fustini --- Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml index a43eb837f8da..42804d955293 100644 --- a/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/snps,dwcmshc-sdhci.yaml @@ -19,6 +19,7 @@ properties: - rockchip,rk3568-dwcmshc - rockchip,rk3588-dwcmshc - snps,dwcmshc-sdhci + - thead,th1520-dwcmshc reg: maxItems: 1 From patchwork Thu Nov 2 02:48:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Drew Fustini X-Patchwork-Id: 160754 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:8f47:0:b0:403:3b70:6f57 with SMTP id j7csp90271vqu; Wed, 1 Nov 2023 19:49:29 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFblWHN3bRjF4F2kQnoG0XVf6ZO1B92Ey8wCsOW7ULTcVTPcSdX3pYyGLSo37YfoUWc+zWF X-Received: by 2002:a17:902:f9ce:b0:1ca:a07b:36d with SMTP id kz14-20020a170902f9ce00b001caa07b036dmr14916356plb.48.1698893369058; Wed, 01 Nov 2023 19:49:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698893369; cv=none; d=google.com; s=arc-20160816; b=z+yWG4bBJawZIqN1DK3+5BGWTzLrhUmMeWZz9sml4t0AEmHkJ+TnTiknJ/p00iyWOd ksj8ch42YTde5PngBrqTm/3iXehcIzPhVFdxTnbwju8Ng4bWFfBl7oeXvt1u3mAlFSx6 EaQIgayk3S2nr2kcQQyiC39qf4uU/BOGfl7y924BrBjRg8P6JMZ53wiTcLboHwd84v6W s3i+/51K/3z0rP8H2vYoART1dwqViMQlWoyHcIehoiAv0KD+ZNZAVdiiIpYzejok5sc6 us8Hb4WYQvvgArHstw/RfAOYq5YozxBWV2EMAdL/OQFnt7qogYbbNPWEoa6s/Tll9grS JdVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=l++Rbeq1YJ0LFMw4HKx/yirX8siQghzI93qQn3u3z5E=; fh=vHR8U309XOCZR8G4JUyhb/0ihb0aVduZkDFEUxYc3iE=; b=FfDTSh++ZTDbw15YCcQhlLwrzaanDLwlBiDrLtZCzaCG1mreScQquigQTNr7fJ/kPD h07rhlK3r4l7l3c7iEtTNrz5wvhhTNRcmcdLLS8TumFpgdqTaBN3t6Tw5KTdKZHPLWXV HI9UaqDD991s7cJzvjPBARQgbZbSmSzUPOAfLfTBjg4FrfZOkg+i4Sg1E8YOSUtUWvu/ C1+0H250YYFvZRtld0yE2hvYT6FCwMopNGjiAcuItDTRiE7Pf+uvCuizsm1Q6qWMZ//2 TRKULo8TLybsSjH+ItE86lUIZgXt074s9IIatC9xufbO611/G38F5jJgr2uv1EA+ClYW 8+jw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20230601.gappssmtp.com header.s=20230601 header.b=2tGNWYet; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from snail.vger.email (snail.vger.email. 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Wed, 01 Nov 2023 19:49:11 -0700 (PDT) From: Drew Fustini Date: Wed, 01 Nov 2023 19:48:53 -0700 Subject: [PATCH v4 2/7] mmc: sdhci: add __sdhci_execute_tuning() to header MIME-Version: 1.0 Message-Id: <20231101-th1520-mmc-v4-2-86e0216b5994@baylibre.com> References: <20231101-th1520-mmc-v4-0-86e0216b5994@baylibre.com> In-Reply-To: <20231101-th1520-mmc-v4-0-86e0216b5994@baylibre.com> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jisheng Zhang , Adrian Hunter , Guo Ren , Fu Wei , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley Cc: Robert Nelson , Jason Kridner , Xi Ruoyao , Han Gao , Icenowy Zheng , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Drew Fustini X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1698893345; l=2057; i=dfustini@baylibre.com; s=20230430; h=from:subject:message-id; bh=O0pl7kPWnknxTc+1ciCix3vi2PmSyK8UTzQqhv8rZP0=; b=5GZXJKYUX2PFkk79fptSj56AIJweFxSSLNmoeJAhqhhT1nEb/6DFj2Ax/BGJa/TaoghgrIX10 cU1vL2QBWy9BYkEYSEo48YklZTTrxD2hSaGn6Vgf6Is+H9lAI4Fza/e X-Developer-Key: i=dfustini@baylibre.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 01 Nov 2023 19:49:28 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781418813184978587 X-GMAIL-MSGID: 1781418813184978587 Expose __sdhci_execute_tuning() so that it can be called from the mmc host controller drivers. In the sdhci-of-dwcmshc driver, sdhci_dwcmshc_th1520_ops sets platform_execute_tuning to th1520_execute_tuning(). That function has to manipulate phy registers before tuning can be performed. To avoid copying the code verbatim from __sdhci_execute_tuning() into th1520_execute_tuning(), make it possible for __sdhci_execute_tuning() to be called from sdhci-of-dwcmshc. Signed-off-by: Drew Fustini Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci.c | 3 ++- drivers/mmc/host/sdhci.h | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index ff41aa56564e..c79f73459915 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -2841,7 +2841,7 @@ void sdhci_send_tuning(struct sdhci_host *host, u32 opcode) } EXPORT_SYMBOL_GPL(sdhci_send_tuning); -static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) +int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) { int i; @@ -2879,6 +2879,7 @@ static int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) sdhci_reset_tuning(host); return -EAGAIN; } +EXPORT_SYMBOL_GPL(__sdhci_execute_tuning); int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) { diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index f219bdea8f28..a20864fc0641 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -793,6 +793,7 @@ void sdhci_set_bus_width(struct sdhci_host *host, int width); void sdhci_reset(struct sdhci_host *host, u8 mask); void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing); int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode); +int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode); void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios); int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios); From patchwork Thu Nov 2 02:48:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Drew Fustini X-Patchwork-Id: 160755 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:8f47:0:b0:403:3b70:6f57 with SMTP id j7csp90281vqu; Wed, 1 Nov 2023 19:49:33 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFGy/Ng0pxyehaP4wcwBukfB1oUF8A+rA0j6EWqHYTvlRFnow6nPPTdh641CbcOR9Twt0At X-Received: by 2002:a17:902:d4cf:b0:1cc:1686:37ac with SMTP id o15-20020a170902d4cf00b001cc168637acmr22812763plg.55.1698893372810; Wed, 01 Nov 2023 19:49:32 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698893372; cv=none; d=google.com; s=arc-20160816; b=RR5UXy4I5LLw++46mwp4bZUZH/TAOdB7fjrtFEkhfvKiIZYf7gZ5h7/HT79dkthTHn lRkujR5Jr7ZShWBMph8TA+yHZbXyTmnPy0UtMq0+NLwUrLP6egJ/8/jMaut5jIeQZtNE LmPWGidB6r36mhiz99Bk7m0+r9uXox46DMKzxU0Eya4LqxuV6LrHkh4HMI1elXP7XDMA VQ4zLLfsAVHvxCEoM/IGWzus98R6mrxo7lchZLkWHQZa+me8LHzWA2aozkWyd9haGxk1 cVo2iErqTzZTdGuSOzonLajMFZP78W/XA+vB2iSu0lpx8PyTrMUF4P0d2tnfUOcWEyAL +0Ng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=JHk1CgnLLTewJ8o3tN4/S0YEjB9r+T1MH+waxZAekc4=; fh=vHR8U309XOCZR8G4JUyhb/0ihb0aVduZkDFEUxYc3iE=; b=Y6wVY1LTsPPwLqfajPYMg9F3Uc1NnnbgkRX0G/ZRnjS4U/faL5OYFM0QOgK5LDqebB ddF+7FbDGhUP2lrYPJdQRi+XzSUfCHMueaCD2cOsh3E52BtTnCDerd/WkhX724gk4GEl x8UrijU/k78oKgO+Mtc1QfUfjoovH35HZxDbWh1hnoJqlrD/1E0a0Lw+bT3V3p+slkdm +SzGrqxW9gXUNT1yO7MMqF/+DNgoIickz23OU+QlsZZrwe31iIpuuzYAfS6UG0Xak4wB 1/ysvtkcrawkFqSpc3UeFoeEOZSQuYgYlg6I2vY7Dijw8R71RzYPtCQyZJTdsKvwY4hr N5qg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20230601.gappssmtp.com header.s=20230601 header.b=mxRgWKZB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from snail.vger.email (snail.vger.email. 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Wed, 01 Nov 2023 19:49:13 -0700 (PDT) From: Drew Fustini Date: Wed, 01 Nov 2023 19:48:54 -0700 Subject: [PATCH v4 3/7] mmc: sdhci-of-dwcmshc: Add support for T-Head TH1520 MIME-Version: 1.0 Message-Id: <20231101-th1520-mmc-v4-3-86e0216b5994@baylibre.com> References: <20231101-th1520-mmc-v4-0-86e0216b5994@baylibre.com> In-Reply-To: <20231101-th1520-mmc-v4-0-86e0216b5994@baylibre.com> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jisheng Zhang , Adrian Hunter , Guo Ren , Fu Wei , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley Cc: Robert Nelson , Jason Kridner , Xi Ruoyao , Han Gao , Icenowy Zheng , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Drew Fustini X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1698893345; l=16879; i=dfustini@baylibre.com; s=20230430; h=from:subject:message-id; bh=uzJNxAqlHPC1mKPXh8Lt4rwNZSxKbrUUvZ0eAWDPuT8=; b=eBWPJFy1hdLcz/UOc5sQy7r+DZYUkyGzXjW9zZqJ8VGORP9vhUIu/RXZtBMmSyFBFSEtp3J2h GfIiShuL4bJAdTYUmtqgWGLzYXUZGG4MZA7lzRgw4eP1RZnJzoN81Q6 X-Developer-Key: i=dfustini@baylibre.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 01 Nov 2023 19:49:32 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781418816908427563 X-GMAIL-MSGID: 1781418816908427563 Add support for the mmc controller in the T-Head TH1520 with the new compatible "thead,th1520-dwcmshc". Implement custom sdhci_ops for set_uhs_signaling, reset, voltage_switch, and platform_execute_tuning. Signed-off-by: Drew Fustini Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-of-dwcmshc.c | 348 ++++++++++++++++++++++++++++++++++++ 1 file changed, 348 insertions(+) diff --git a/drivers/mmc/host/sdhci-of-dwcmshc.c b/drivers/mmc/host/sdhci-of-dwcmshc.c index 3a3bae6948a8..1a1386b742c1 100644 --- a/drivers/mmc/host/sdhci-of-dwcmshc.c +++ b/drivers/mmc/host/sdhci-of-dwcmshc.c @@ -8,6 +8,7 @@ */ #include +#include #include #include #include @@ -35,6 +36,21 @@ #define DWCMSHC_CARD_IS_EMMC BIT(0) #define DWCMSHC_ENHANCED_STROBE BIT(8) #define DWCMSHC_EMMC_ATCTRL 0x40 +/* Tuning and auto-tuning fields in AT_CTRL_R control register */ +#define AT_CTRL_AT_EN BIT(0) /* autotuning is enabled */ +#define AT_CTRL_CI_SEL BIT(1) /* interval to drive center phase select */ +#define AT_CTRL_SWIN_TH_EN BIT(2) /* sampling window threshold enable */ +#define AT_CTRL_RPT_TUNE_ERR BIT(3) /* enable reporting framing errors */ +#define AT_CTRL_SW_TUNE_EN BIT(4) /* enable software managed tuning */ +#define AT_CTRL_WIN_EDGE_SEL_MASK GENMASK(11, 8) /* bits [11:8] */ +#define AT_CTRL_WIN_EDGE_SEL 0xf /* sampling window edge select */ +#define AT_CTRL_TUNE_CLK_STOP_EN BIT(16) /* clocks stopped during phase code change */ +#define AT_CTRL_PRE_CHANGE_DLY_MASK GENMASK(18, 17) /* bits [18:17] */ +#define AT_CTRL_PRE_CHANGE_DLY 0x1 /* 2-cycle latency */ +#define AT_CTRL_POST_CHANGE_DLY_MASK GENMASK(20, 19) /* bits [20:19] */ +#define AT_CTRL_POST_CHANGE_DLY 0x3 /* 4-cycle latency */ +#define AT_CTRL_SWIN_TH_VAL_MASK GENMASK(31, 24) /* bits [31:24] */ +#define AT_CTRL_SWIN_TH_VAL 0x9 /* sampling window threshold */ /* Rockchip specific Registers */ #define DWCMSHC_EMMC_DLL_CTRL 0x800 @@ -72,6 +88,82 @@ (((x) & DWCMSHC_EMMC_DLL_TIMEOUT) == 0)) #define RK35xx_MAX_CLKS 3 +/* PHY register area pointer */ +#define DWC_MSHC_PTR_PHY_R 0x300 + +/* PHY general configuration */ +#define PHY_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x00) +#define PHY_CNFG_RSTN_DEASSERT 0x1 /* Deassert PHY reset */ +#define PHY_CNFG_PAD_SP_MASK GENMASK(19, 16) /* bits [19:16] */ +#define PHY_CNFG_PAD_SP 0x0c /* PMOS TX drive strength */ +#define PHY_CNFG_PAD_SN_MASK GENMASK(23, 20) /* bits [23:20] */ +#define PHY_CNFG_PAD_SN 0x0c /* NMOS TX drive strength */ + +/* PHY command/response pad settings */ +#define PHY_CMDPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x04) + +/* PHY data pad settings */ +#define PHY_DATAPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x06) + +/* PHY clock pad settings */ +#define PHY_CLKPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x08) + +/* PHY strobe pad settings */ +#define PHY_STBPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x0a) + +/* PHY reset pad settings */ +#define PHY_RSTNPAD_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x0c) + +/* Bitfields are common for all pad settings */ +#define PHY_PAD_RXSEL_1V8 0x1 /* Receiver type select for 1.8V */ +#define PHY_PAD_RXSEL_3V3 0x2 /* Receiver type select for 3.3V */ + +#define PHY_PAD_WEAKPULL_MASK GENMASK(4, 3) /* bits [4:3] */ +#define PHY_PAD_WEAKPULL_PULLUP 0x1 /* Weak pull up enabled */ +#define PHY_PAD_WEAKPULL_PULLDOWN 0x2 /* Weak pull down enabled */ + +#define PHY_PAD_TXSLEW_CTRL_P_MASK GENMASK(8, 5) /* bits [8:5] */ +#define PHY_PAD_TXSLEW_CTRL_P 0x3 /* Slew control for P-Type pad TX */ +#define PHY_PAD_TXSLEW_CTRL_N_MASK GENMASK(12, 9) /* bits [12:9] */ +#define PHY_PAD_TXSLEW_CTRL_N 0x3 /* Slew control for N-Type pad TX */ + +/* PHY CLK delay line settings */ +#define PHY_SDCLKDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x1d) +#define PHY_SDCLKDL_CNFG_UPDATE BIT(4) /* set before writing to SDCLKDL_DC */ + +/* PHY CLK delay line delay code */ +#define PHY_SDCLKDL_DC_R (DWC_MSHC_PTR_PHY_R + 0x1e) +#define PHY_SDCLKDL_DC_INITIAL 0x40 /* initial delay code */ +#define PHY_SDCLKDL_DC_DEFAULT 0x32 /* default delay code */ +#define PHY_SDCLKDL_DC_HS400 0x18 /* delay code for HS400 mode */ + +/* PHY drift_cclk_rx delay line configuration setting */ +#define PHY_ATDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x21) +#define PHY_ATDL_CNFG_INPSEL_MASK GENMASK(3, 2) /* bits [3:2] */ +#define PHY_ATDL_CNFG_INPSEL 0x3 /* delay line input source */ + +/* PHY DLL control settings */ +#define PHY_DLL_CTRL_R (DWC_MSHC_PTR_PHY_R + 0x24) +#define PHY_DLL_CTRL_DISABLE 0x0 /* PHY DLL is enabled */ +#define PHY_DLL_CTRL_ENABLE 0x1 /* PHY DLL is disabled */ + +/* PHY DLL configuration register 1 */ +#define PHY_DLL_CNFG1_R (DWC_MSHC_PTR_PHY_R + 0x25) +#define PHY_DLL_CNFG1_SLVDLY_MASK GENMASK(5, 4) /* bits [5:4] */ +#define PHY_DLL_CNFG1_SLVDLY 0x2 /* DLL slave update delay input */ +#define PHY_DLL_CNFG1_WAITCYCLE 0x5 /* DLL wait cycle input */ + +/* PHY DLL configuration register 2 */ +#define PHY_DLL_CNFG2_R (DWC_MSHC_PTR_PHY_R + 0x26) +#define PHY_DLL_CNFG2_JUMPSTEP 0xa /* DLL jump step input */ + +/* PHY DLL master and slave delay line configuration settings */ +#define PHY_DLLDL_CNFG_R (DWC_MSHC_PTR_PHY_R + 0x28) +#define PHY_DLLDL_CNFG_SLV_INPSEL_MASK GENMASK(6, 5) /* bits [6:5] */ +#define PHY_DLLDL_CNFG_SLV_INPSEL 0x3 /* clock source select for slave DL */ + +#define FLAG_IO_FIXED_1V8 BIT(0) + #define BOUNDARY_OK(addr, len) \ ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1))) @@ -92,6 +184,8 @@ struct dwcmshc_priv { struct clk *bus_clk; int vendor_specific_area1; /* P_VENDOR_SPECIFIC_AREA reg */ void *priv; /* pointer to SoC private stuff */ + u16 delay_line; + u16 flags; }; /* @@ -157,6 +251,126 @@ static void dwcmshc_request(struct mmc_host *mmc, struct mmc_request *mrq) sdhci_request(mmc, mrq); } +static void dwcmshc_phy_1_8v_init(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); + u32 val; + + /* deassert phy reset & set tx drive strength */ + val = PHY_CNFG_RSTN_DEASSERT; + val |= FIELD_PREP(PHY_CNFG_PAD_SP_MASK, PHY_CNFG_PAD_SP); + val |= FIELD_PREP(PHY_CNFG_PAD_SN_MASK, PHY_CNFG_PAD_SN); + sdhci_writel(host, val, PHY_CNFG_R); + + /* disable delay line */ + sdhci_writeb(host, PHY_SDCLKDL_CNFG_UPDATE, PHY_SDCLKDL_CNFG_R); + + /* set delay line */ + sdhci_writeb(host, priv->delay_line, PHY_SDCLKDL_DC_R); + sdhci_writeb(host, PHY_DLL_CNFG2_JUMPSTEP, PHY_DLL_CNFG2_R); + + /* enable delay lane */ + val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R); + val &= ~(PHY_SDCLKDL_CNFG_UPDATE); + sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R); + + /* configure phy pads */ + val = PHY_PAD_RXSEL_1V8; + val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLUP); + val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); + val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); + sdhci_writew(host, val, PHY_CMDPAD_CNFG_R); + sdhci_writew(host, val, PHY_DATAPAD_CNFG_R); + sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R); + + val = FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); + val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); + sdhci_writew(host, val, PHY_CLKPAD_CNFG_R); + + val = PHY_PAD_RXSEL_1V8; + val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLDOWN); + val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); + val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); + sdhci_writew(host, val, PHY_STBPAD_CNFG_R); + + /* enable data strobe mode */ + sdhci_writeb(host, FIELD_PREP(PHY_DLLDL_CNFG_SLV_INPSEL_MASK, PHY_DLLDL_CNFG_SLV_INPSEL), + PHY_DLLDL_CNFG_R); + + /* enable phy dll */ + sdhci_writeb(host, PHY_DLL_CTRL_ENABLE, PHY_DLL_CTRL_R); +} + +static void dwcmshc_phy_3_3v_init(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); + u32 val; + + /* deassert phy reset & set tx drive strength */ + val = PHY_CNFG_RSTN_DEASSERT; + val |= FIELD_PREP(PHY_CNFG_PAD_SP_MASK, PHY_CNFG_PAD_SP); + val |= FIELD_PREP(PHY_CNFG_PAD_SN_MASK, PHY_CNFG_PAD_SN); + sdhci_writel(host, val, PHY_CNFG_R); + + /* disable delay line */ + sdhci_writeb(host, PHY_SDCLKDL_CNFG_UPDATE, PHY_SDCLKDL_CNFG_R); + + /* set delay line */ + sdhci_writeb(host, priv->delay_line, PHY_SDCLKDL_DC_R); + sdhci_writeb(host, PHY_DLL_CNFG2_JUMPSTEP, PHY_DLL_CNFG2_R); + + /* enable delay lane */ + val = sdhci_readb(host, PHY_SDCLKDL_CNFG_R); + val &= ~(PHY_SDCLKDL_CNFG_UPDATE); + sdhci_writeb(host, val, PHY_SDCLKDL_CNFG_R); + + /* configure phy pads */ + val = PHY_PAD_RXSEL_3V3; + val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLUP); + val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); + val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); + sdhci_writew(host, val, PHY_CMDPAD_CNFG_R); + sdhci_writew(host, val, PHY_DATAPAD_CNFG_R); + sdhci_writew(host, val, PHY_RSTNPAD_CNFG_R); + + val = FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); + val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); + sdhci_writew(host, val, PHY_CLKPAD_CNFG_R); + + val = PHY_PAD_RXSEL_3V3; + val |= FIELD_PREP(PHY_PAD_WEAKPULL_MASK, PHY_PAD_WEAKPULL_PULLDOWN); + val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_P_MASK, PHY_PAD_TXSLEW_CTRL_P); + val |= FIELD_PREP(PHY_PAD_TXSLEW_CTRL_N_MASK, PHY_PAD_TXSLEW_CTRL_N); + sdhci_writew(host, val, PHY_STBPAD_CNFG_R); + + /* enable phy dll */ + sdhci_writeb(host, PHY_DLL_CTRL_ENABLE, PHY_DLL_CTRL_R); +} + +static void th1520_sdhci_set_phy(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); + u16 emmc_ctrl; + + /* Before power on, set PHY configs */ + if (priv->flags & FLAG_IO_FIXED_1V8) + dwcmshc_phy_1_8v_init(host); + else + dwcmshc_phy_3_3v_init(host); + + if (host->mmc->caps2 & (MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO)) { + emmc_ctrl = sdhci_readw(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL); + emmc_ctrl |= DWCMSHC_CARD_IS_EMMC; + sdhci_writew(host, emmc_ctrl, priv->vendor_specific_area1 + DWCMSHC_EMMC_CONTROL); + } + + sdhci_writeb(host, FIELD_PREP(PHY_DLL_CNFG1_SLVDLY_MASK, PHY_DLL_CNFG1_SLVDLY) | + PHY_DLL_CNFG1_WAITCYCLE, PHY_DLL_CNFG1_R); +} + static void dwcmshc_set_uhs_signaling(struct sdhci_host *host, unsigned int timing) { @@ -189,9 +403,25 @@ static void dwcmshc_set_uhs_signaling(struct sdhci_host *host, ctrl_2 |= DWCMSHC_CTRL_HS400; } + if (priv->flags & FLAG_IO_FIXED_1V8) + ctrl_2 |= SDHCI_CTRL_VDD_180; sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); } +static void th1520_set_uhs_signaling(struct sdhci_host *host, + unsigned int timing) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); + + dwcmshc_set_uhs_signaling(host, timing); + if (timing == MMC_TIMING_MMC_HS400) + priv->delay_line = PHY_SDCLKDL_DC_HS400; + else + sdhci_writeb(host, 0, PHY_DLLDL_CNFG_R); + th1520_sdhci_set_phy(host); +} + static void dwcmshc_hs400_enhanced_strobe(struct mmc_host *mmc, struct mmc_ios *ios) { @@ -338,6 +568,79 @@ static void rk35xx_sdhci_reset(struct sdhci_host *host, u8 mask) sdhci_reset(host, mask); } +static int th1520_execute_tuning(struct sdhci_host *host, u32 opcode) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); + u32 val = 0; + + if (host->flags & SDHCI_HS400_TUNING) + return 0; + + sdhci_writeb(host, FIELD_PREP(PHY_ATDL_CNFG_INPSEL_MASK, PHY_ATDL_CNFG_INPSEL), + PHY_ATDL_CNFG_R); + val = sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); + + /* + * configure tuning settings: + * - center phase select code driven in block gap interval + * - disable reporting of framing errors + * - disable software managed tuning + * - disable user selection of sampling window edges, + * instead tuning calculated edges are used + */ + val &= ~(AT_CTRL_CI_SEL | AT_CTRL_RPT_TUNE_ERR | AT_CTRL_SW_TUNE_EN | + FIELD_PREP(AT_CTRL_WIN_EDGE_SEL_MASK, AT_CTRL_WIN_EDGE_SEL)); + + /* + * configure tuning settings: + * - enable auto-tuning + * - enable sampling window threshold + * - stop clocks during phase code change + * - set max latency in cycles between tx and rx clocks + * - set max latency in cycles to switch output phase + * - set max sampling window threshold value + */ + val |= AT_CTRL_AT_EN | AT_CTRL_SWIN_TH_EN | AT_CTRL_TUNE_CLK_STOP_EN; + val |= FIELD_PREP(AT_CTRL_PRE_CHANGE_DLY_MASK, AT_CTRL_PRE_CHANGE_DLY); + val |= FIELD_PREP(AT_CTRL_POST_CHANGE_DLY_MASK, AT_CTRL_POST_CHANGE_DLY); + val |= FIELD_PREP(AT_CTRL_SWIN_TH_VAL_MASK, AT_CTRL_SWIN_TH_VAL); + + sdhci_writel(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); + val = sdhci_readl(host, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); + + /* perform tuning */ + sdhci_start_tuning(host); + host->tuning_err = __sdhci_execute_tuning(host, opcode); + if (host->tuning_err) { + /* disable auto-tuning upon tuning error */ + val &= ~AT_CTRL_AT_EN; + sdhci_writel(host, val, priv->vendor_specific_area1 + DWCMSHC_EMMC_ATCTRL); + dev_err(mmc_dev(host->mmc), "tuning failed: %d\n", host->tuning_err); + return -EIO; + } + sdhci_end_tuning(host); + + return 0; +} + +static void th1520_sdhci_reset(struct sdhci_host *host, u8 mask) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct dwcmshc_priv *priv = sdhci_pltfm_priv(pltfm_host); + u16 ctrl_2; + + sdhci_reset(host, mask); + + if (priv->flags & FLAG_IO_FIXED_1V8) { + ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + if (!(ctrl_2 & SDHCI_CTRL_VDD_180)) { + ctrl_2 |= SDHCI_CTRL_VDD_180; + sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); + } + } +} + static const struct sdhci_ops sdhci_dwcmshc_ops = { .set_clock = sdhci_set_clock, .set_bus_width = sdhci_set_bus_width, @@ -356,6 +659,17 @@ static const struct sdhci_ops sdhci_dwcmshc_rk35xx_ops = { .adma_write_desc = dwcmshc_adma_write_desc, }; +static const struct sdhci_ops sdhci_dwcmshc_th1520_ops = { + .set_clock = sdhci_set_clock, + .set_bus_width = sdhci_set_bus_width, + .set_uhs_signaling = th1520_set_uhs_signaling, + .get_max_clock = dwcmshc_get_max_clock, + .reset = th1520_sdhci_reset, + .adma_write_desc = dwcmshc_adma_write_desc, + .voltage_switch = dwcmshc_phy_1_8v_init, + .platform_execute_tuning = &th1520_execute_tuning, +}; + static const struct sdhci_pltfm_data sdhci_dwcmshc_pdata = { .ops = &sdhci_dwcmshc_ops, .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, @@ -379,6 +693,12 @@ static const struct sdhci_pltfm_data sdhci_dwcmshc_rk35xx_pdata = { SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN, }; +static const struct sdhci_pltfm_data sdhci_dwcmshc_th1520_pdata = { + .ops = &sdhci_dwcmshc_th1520_ops, + .quirks = SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, +}; + static int dwcmshc_rk35xx_init(struct sdhci_host *host, struct dwcmshc_priv *dwc_priv) { int err; @@ -447,6 +767,10 @@ static const struct of_device_id sdhci_dwcmshc_dt_ids[] = { .compatible = "snps,dwcmshc-sdhci", .data = &sdhci_dwcmshc_pdata, }, + { + .compatible = "thead,th1520-dwcmshc", + .data = &sdhci_dwcmshc_th1520_pdata, + }, {}, }; MODULE_DEVICE_TABLE(of, sdhci_dwcmshc_dt_ids); @@ -542,6 +866,30 @@ static int dwcmshc_probe(struct platform_device *pdev) goto err_clk; } + if (pltfm_data == &sdhci_dwcmshc_th1520_pdata) { + priv->delay_line = PHY_SDCLKDL_DC_DEFAULT; + + if ((device_property_read_bool(dev, "mmc-ddr-1_8v")) | + (device_property_read_bool(dev, "mmc-hs200-1_8v")) | + (device_property_read_bool(dev, "mmc-hs400-1_8v"))) + priv->flags |= FLAG_IO_FIXED_1V8; + else + priv->flags &= ~FLAG_IO_FIXED_1V8; + + /* + * start_signal_voltage_switch() will try 3.3V first + * then 1.8V. Use SDHCI_SIGNALING_180 rather than + * SDHCI_SIGNALING_330 to avoid setting voltage to 3.3V + * in sdhci_start_signal_voltage_switch(). + */ + if (priv->flags & FLAG_IO_FIXED_1V8) { + host->flags &= ~SDHCI_SIGNALING_330; + host->flags |= SDHCI_SIGNALING_180; + } + + sdhci_enable_v4_mode(host); + } + #ifdef CONFIG_ACPI if (pltfm_data == &sdhci_dwcmshc_bf3_pdata) sdhci_enable_v4_mode(host); From patchwork Thu Nov 2 02:48:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Drew Fustini X-Patchwork-Id: 160756 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:8f47:0:b0:403:3b70:6f57 with SMTP id j7csp90317vqu; Wed, 1 Nov 2023 19:49:39 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGBqx8VYBS9lDpt240djjM9y6p4at5Hyud6rFFaW1/Wok204paloquz+rJ2vblhJKrOl9W4 X-Received: by 2002:a81:9a96:0:b0:5a7:b723:8fa3 with SMTP id r144-20020a819a96000000b005a7b7238fa3mr15358064ywg.26.1698893378862; Wed, 01 Nov 2023 19:49:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698893378; cv=none; d=google.com; s=arc-20160816; b=Ol13sIiQ9WdFIBebk6yEiQOX0HJqECjGrEGyf3SpUX8gHwNvKr6k7X6+rna662GHEC 20k22fkWAZdX5XXtg45N73zYnReg3pj0yF9cSTvt4opiisu+bvkkf7HHi0PAqwISTrA/ MUCxS/VGkM32aXp6sgVw0a9SFg+gWjxadEuBUbgm/55lwAKlmOufic7debkbuPaqWnjt maBoSW8lwg6pRaU7K2i+unjNt/VW2GcVFytpffdLwEljMkhJQdpChsy23q/JKX1axWqn nwc7a+DP+YXpQifl+JkwI+a0QZPzP1n0jUVDKSQPGn2uyWtDXvkgE6P1AoPGusxigO/D o1Fw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=xY9e61NSBd34WKgwLiextVdIl1pEHWCBao7kYEHaYbc=; fh=vHR8U309XOCZR8G4JUyhb/0ihb0aVduZkDFEUxYc3iE=; b=W9DLS5srjDdY7ox/6OmTDnJcWdANKlg2LJCXHHAZHFPI9Or+8if4zZ1ugXKEqqeq3g NsT3A/RGbl0MFp9NpnVYfTrfWseR4U4JPftT7jLR5So+P/wdXWUb6/g8yoXEleOQupBn NswV4n+COM5oVKoLf1NJDsSmh1VpCph5QEv9WEOfZWvwu9KhWF/ps+vRXkCqIDt8ftUk 1R8jkGZ6DciCaTPZV40vhg09IQZoe/Sn2Bb4IsTYiqVXs7mM8XKHK7UqIpAbSE+9lSMk 7e9NjicLibqMYDGUsRvquAPDZNQEJR3PAnCpMs3FTdEz8Mw29XRG8kgMEtAvqNlC1hbD lLXQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20230601.gappssmtp.com header.s=20230601 header.b=yFqza9ow; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from snail.vger.email (snail.vger.email. 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Wed, 01 Nov 2023 19:49:16 -0700 (PDT) From: Drew Fustini Date: Wed, 01 Nov 2023 19:48:55 -0700 Subject: [PATCH v4 4/7] riscv: defconfig: Enable mmc and dma drivers for T-Head TH1520 MIME-Version: 1.0 Message-Id: <20231101-th1520-mmc-v4-4-86e0216b5994@baylibre.com> References: <20231101-th1520-mmc-v4-0-86e0216b5994@baylibre.com> In-Reply-To: <20231101-th1520-mmc-v4-0-86e0216b5994@baylibre.com> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jisheng Zhang , Adrian Hunter , Guo Ren , Fu Wei , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley Cc: Robert Nelson , Jason Kridner , Xi Ruoyao , Han Gao , Icenowy Zheng , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Drew Fustini X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1698893345; l=915; i=dfustini@baylibre.com; s=20230430; h=from:subject:message-id; bh=ht5Rt9iMCRM1t5yThjxoCTbuOVz3OXmRTAYLzzfd3/s=; b=FZMIpbOF3eXJOg41M+jpGkm0JMPaPS1i+Fh/DURCDFJ6QTIV6xnD4KSvnKvDKTZm/Q5C4u02O XJ40YVrYjkqDC8JNiTK4WMQXC8RJvH5O3/cEe7X9+tCNDrDxEPQ8ITa X-Developer-Key: i=dfustini@baylibre.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 01 Nov 2023 19:49:37 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781418823649864944 X-GMAIL-MSGID: 1781418823649864944 Enable the mmc controller driver and dma controller driver needed for T-Head TH1520 based boards, like the LicheePi 4A and BeagleV-Ahead, to boot from eMMC storage. Reviewed-by: Guo Ren Signed-off-by: Drew Fustini --- arch/riscv/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index ab86ec3b9eab..c5a8583236d0 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -168,12 +168,14 @@ CONFIG_MMC=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_PLTFM=y CONFIG_MMC_SDHCI_CADENCE=y +CONFIG_MMC_SDHCI_OF_DWCMSHC=y CONFIG_MMC_SPI=y CONFIG_MMC_SUNXI=y CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_SUN6I=y CONFIG_DMADEVICES=y CONFIG_DMA_SUN6I=m +CONFIG_DW_AXI_DMAC=y CONFIG_VIRTIO_PCI=y CONFIG_VIRTIO_BALLOON=y CONFIG_VIRTIO_INPUT=y From patchwork Thu Nov 2 02:48:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Drew Fustini X-Patchwork-Id: 160757 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:8f47:0:b0:403:3b70:6f57 with SMTP id j7csp90316vqu; Wed, 1 Nov 2023 19:49:38 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH+JPW4rJ+5N/6nzp+HuVp2L21tfnNnD7ZIBPcsF8W/jXU2ftlys3ONN+JdS45mOkEcUXcK X-Received: by 2002:a05:6a00:93a5:b0:6b2:69c:3471 with SMTP id ka37-20020a056a0093a500b006b2069c3471mr15537637pfb.26.1698893378668; Wed, 01 Nov 2023 19:49:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698893378; cv=none; d=google.com; s=arc-20160816; b=DH+T4LhHU5oDTQhbsyDrUDkE7QSGubNRo2184rslQL6jlL1gOmo+6eWTOPS8PuRcSE hCIVitmbxz0ndaI0dniow9eT+t5yuthxCSSxmA0oteBruIIZr2wlshuXLNZTzgM8qw7/ UxBblX8BciWxou/So4HfHy6xB1N2pGrwDgGf6FNpNDZM56UG9NAczNcwJMOfQziCv1zf sZcAHPtP3n1E1Bxnu2vQBH0PHEwwHL9waROS2Fb3956ndCKNx1fJ3J2aDrVxD40A/OkO RTnNXBcdkYDCmMYT0wOt9W9S2BYY0lahycplcQDIZ79who4qcqqq0POqyLKcO6PkOF8v GA4w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=frioRiPhaekRnCE/0ENvI5wkvdspg2jE1Z81EEiVDoc=; fh=vHR8U309XOCZR8G4JUyhb/0ihb0aVduZkDFEUxYc3iE=; b=bXgKl/m2QLeTyhdJ2/WWqKKG7NBB3PvzJeLYlj73LWAI0SenivQoAsjgST+e5JxD+W 29mtRgAP6NW+d2VFRuGoNElscx2y2crfXNm043JfLcKMcf5QW+xK3bQyMw9kwFVF6cWD U8D47bc/lYaTov8mQoBs7nveitKP0sa7NkNEkXogtc6UGc+0c21ZC0aRHobJeNa34SKH 2/LbLCOInJ4/OnZ646rh+cqhfWaetuqaGbztH3RLtVqHdosq1WEMIClAEDEZbAkDm4Y7 /YgNXqBjLW9RCcFWD+hE+trbY4nbTiH9AnAILzJ85jisdtqUAI/1CCQk53j1ImqTctOv VdLA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20230601.gappssmtp.com header.s=20230601 header.b=mBRLAmU3; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from snail.vger.email (snail.vger.email. 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Wed, 01 Nov 2023 19:49:18 -0700 (PDT) From: Drew Fustini Date: Wed, 01 Nov 2023 19:48:56 -0700 Subject: [PATCH v4 5/7] riscv: dts: thead: Add TH1520 mmc controllers and sdhci clock MIME-Version: 1.0 Message-Id: <20231101-th1520-mmc-v4-5-86e0216b5994@baylibre.com> References: <20231101-th1520-mmc-v4-0-86e0216b5994@baylibre.com> In-Reply-To: <20231101-th1520-mmc-v4-0-86e0216b5994@baylibre.com> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jisheng Zhang , Adrian Hunter , Guo Ren , Fu Wei , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley Cc: Robert Nelson , Jason Kridner , Xi Ruoyao , Han Gao , Icenowy Zheng , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Drew Fustini X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1698893345; l=1608; i=dfustini@baylibre.com; s=20230430; h=from:subject:message-id; bh=118IOeI3EDHQnRGvuv5ewuNsGEAnYvxtIZdzQTMEyXk=; b=eyKHDo5yqtNJ502x7Fih43LJiwPFfx23Zy+xbTqFt5fKit9A49CnrPno3Mm3ut0CzYLTtYrbA /vn+hYssfSJB6Sw6E+5blOk1/IPFdDAfudZiDruEEXAfuKyEA9hPRw1 X-Developer-Key: i=dfustini@baylibre.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 01 Nov 2023 19:49:37 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781418823517326530 X-GMAIL-MSGID: 1781418823517326530 Add node for the SDHCI fixed clock. Add mmc0 node for the first mmc controller instance which is typically connected to the eMMC device. Add mmc1 node for the second mmc controller instance which is typically connected to microSD slot. Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi index ff364709a6df..f5ec9326c4b8 100644 --- a/arch/riscv/boot/dts/thead/th1520.dtsi +++ b/arch/riscv/boot/dts/thead/th1520.dtsi @@ -134,6 +134,13 @@ uart_sclk: uart-sclk-clock { #clock-cells = <0>; }; + sdhci_clk: sdhci-clock { + compatible = "fixed-clock"; + clock-frequency = <198000000>; + clock-output-names = "sdhci_clk"; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&plic>; @@ -292,6 +299,22 @@ dmac0: dma-controller@ffefc00000 { status = "disabled"; }; + mmc0: mmc@ffe7080000 { + compatible = "thead,th1520-dwcmshc"; + reg = <0xff 0xe7080000 0x0 0x10000>; + interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sdhci_clk>; + clock-names = "core"; + }; + + mmc1: mmc@ffe7090000 { + compatible = "thead,th1520-dwcmshc"; + reg = <0xff 0xe7090000 0x0 0x10000>; + interrupts = <64 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sdhci_clk>; + clock-names = "core"; + }; + timer0: timer@ffefc32000 { compatible = "snps,dw-apb-timer"; reg = <0xff 0xefc32000 0x0 0x14>; From patchwork Thu Nov 2 02:48:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Drew Fustini X-Patchwork-Id: 160759 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:8f47:0:b0:403:3b70:6f57 with SMTP id j7csp90805vqu; Wed, 1 Nov 2023 19:51:17 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFzRGYEpriugrQoGPlQDQFqXTVbrCWFveHSiyxxt4IPuuIacN+Dl579XXRRGeLBxjY8f2QI X-Received: by 2002:a05:6830:124e:b0:6b7:1d93:72e0 with SMTP id s14-20020a056830124e00b006b71d9372e0mr16504837otp.32.1698893477129; Wed, 01 Nov 2023 19:51:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698893477; cv=none; d=google.com; s=arc-20160816; b=rKg7dWik2Zz/T6LsqSUNyUNOChxmsPneiBse77jlinQ/PS/2W528ETkkbq+IjD5GX9 IJtAH18BM0NqBuuh6XKdIxZ1ZK8sfmNvXYDZW0l2ZCrqSDQ0ymL/Ia0qjAcbFkgJMofD 3nmIdEyA+6Z8TSH+8zSQMInN2WP8ZwIeM1gjMk2Qz/YkPLaRjM0Pkxir+hx2azUSI1Ut zAvs6+vY6c3X/7Z5w0cSbG3KswWSuAWwbbaEE712Gs1bXNcg66HDrjoWxNt9zwrBk71j g2amrQJjvjAU7RzCviEAYssG0NMTSuUIFkD2ksuck1qP4kLBZs8Sj1wyTiJT5b6qO2Mg VNQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=uSa6NAVY2VMgd1nmwOwphCO64qKVXCiZUmGbVj1XUeM=; fh=vHR8U309XOCZR8G4JUyhb/0ihb0aVduZkDFEUxYc3iE=; b=QThnVJ6LgBJIZNGqE2DtWuqHnzruz7dJkWuogbSws8C8MKGDLWZ5PG2c6veeiVztqy felLYtP0EthC/cCDwyw1WGxPq93xsK862fUNbz9vRLMgwVnKxfab4Ogi3JYLN6xxFlPT nenA0BwIHkQ8NwqWZG0w1qLXPwVCp3kTKI0BVkwLSYwqPSixn4eaZXVNQIRHcqmiE1Mk jNzR96M5txUCifxcMfKC0uTUFrJb25rvXRnaw8evqZwczYDqBzq/I8me2DfVbcReZGU9 3KyTgmFOEBhKPdBFt3uG+GSK6HabQIBMzuqLX9vPoSBcGGRlaso4JGY4qCpMnWeZGR9g Wi0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20230601.gappssmtp.com header.s=20230601 header.b=LprtyhiG; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from fry.vger.email (fry.vger.email. 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Wed, 01 Nov 2023 19:49:23 -0700 (PDT) From: Drew Fustini Date: Wed, 01 Nov 2023 19:48:57 -0700 Subject: [PATCH v4 6/7] riscv: dts: thead: Enable BeagleV Ahead eMMC and microSD MIME-Version: 1.0 Message-Id: <20231101-th1520-mmc-v4-6-86e0216b5994@baylibre.com> References: <20231101-th1520-mmc-v4-0-86e0216b5994@baylibre.com> In-Reply-To: <20231101-th1520-mmc-v4-0-86e0216b5994@baylibre.com> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jisheng Zhang , Adrian Hunter , Guo Ren , Fu Wei , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley Cc: Robert Nelson , Jason Kridner , Xi Ruoyao , Han Gao , Icenowy Zheng , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Drew Fustini X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1698893345; l=1108; i=dfustini@baylibre.com; s=20230430; h=from:subject:message-id; bh=4bgo3aK3cuR26cRWBbMVA6MrvhUqOJ8As8gzvmDCzhs=; b=aA13H2waFkFK8rdICEfWcJcPhFaGSH0ZRd4ROe0tmGrxSg7hrWq8+i/vrM2/4uVwYFqUm7YA2 XG5qUI7lWhuBylW5Vf6NOpK9BxdJC/LQDXKQpfLDXXSAcE3QiPgjyL3 X-Developer-Key: i=dfustini@baylibre.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Wed, 01 Nov 2023 19:50:36 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781418926747338032 X-GMAIL-MSGID: 1781418926747338032 Add mmc0 properties for the eMMC device and add mmc1 properties for the microSD slot. Set the frequency for the sdhci clock. Signed-off-by: Drew Fustini --- arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts index 70e8042c8304..f91d94f95510 100644 --- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts +++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts @@ -48,6 +48,10 @@ &apb_clk { clock-frequency = <62500000>; }; +&sdhci_clk { + clock-frequency = <198000000>; +}; + &uart_sclk { clock-frequency = <100000000>; }; @@ -56,6 +60,22 @@ &dmac0 { status = "okay"; }; +&mmc0 { + bus-width = <8>; + max-frequency = <198000000>; + mmc-hs400-1_8v; + non-removable; + no-sdio; + no-sd; + status = "okay"; +}; + +&mmc1 { + max-frequency = <198000000>; + bus-width = <4>; + status = "okay"; +}; + &uart0 { status = "okay"; }; From patchwork Thu Nov 2 02:48:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Drew Fustini X-Patchwork-Id: 160758 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:8f47:0:b0:403:3b70:6f57 with SMTP id j7csp90623vqu; Wed, 1 Nov 2023 19:50:42 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEVYlLq8SUZ3hcGewluPjDH/25mNb3OMhByaL4imAL6Dl7vERQt8fvFgjYQi1M0IAbJO9c8 X-Received: by 2002:a17:902:e881:b0:1cc:5549:aab8 with SMTP id w1-20020a170902e88100b001cc5549aab8mr12927181plg.5.1698893442006; Wed, 01 Nov 2023 19:50:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698893441; cv=none; d=google.com; s=arc-20160816; b=NBnNfOerhV9zTpnY2CWFkXxvW+IOgk5W8Of2C6hPyy0/e3iwDnwJp2YtkDyHTR3FZ7 6SQLilx0udusk/VkPfS7Ta9J77JotO5SyonMV24n/DVBfQxS3s9afCygIH/A7IIyUoyH vU+PMi7p4EeXWPb261aTiQv+Cxj6IXxazz6Ak8Kbo7We++INU16ZmzT0W9eM78HzcBcO E+z4l05NiJlNdYNqPOgQeYHLbFLGTG3naZmagK4Inbk1yMv5mOHjKvns97OhWiNE8F4V OG4cshxRmpx0uDO+gU0yF3/Vbi1blv9qyPS5I1rpJNLBMzj+r8P8On0ENqE+fiW+/FrN w4dw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=DnDZGk512Fn6FcfRLVRqtgZTjSOOBJwTCzWACAW0uhY=; fh=vHR8U309XOCZR8G4JUyhb/0ihb0aVduZkDFEUxYc3iE=; b=VFbqd0caXUFIYC/yj7sO/i3KiDFxdAEI8zlm9Z1g9kkaW8yvgBD4jYNYM0RknKIMw1 cvtYQJH7QZ2L6wPOd3tFSwuU+NnVG8kGiNLvtMH4koj1MH+/kpjgi6GXda/5/3oEuczH FQMD6FJBnJpM2sSjF8Z6mcvDUBoe9vN4dGfQEXclld2wIQNO5C65YhqUZpYIptsWrGOn nUQxGeE4hCKlOn1sVbXjcLhR3sTFZD1RQkHOayXMf2hKCjq5WO636ABjI3R+KFr2Qks6 5SaTSbSWstzPhrAXf8SM0CRJ+Vke8E2JRWqZ4XSVTWbdAAuGqX203o6TLkm0Sm8WiLdp GCWw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20230601.gappssmtp.com header.s=20230601 header.b=MVBwdtE2; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from lipwig.vger.email (lipwig.vger.email. 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Wed, 01 Nov 2023 19:49:25 -0700 (PDT) From: Drew Fustini Date: Wed, 01 Nov 2023 19:48:58 -0700 Subject: [PATCH v4 7/7] riscv: dts: thead: Enable LicheePi 4A eMMC and microSD MIME-Version: 1.0 Message-Id: <20231101-th1520-mmc-v4-7-86e0216b5994@baylibre.com> References: <20231101-th1520-mmc-v4-0-86e0216b5994@baylibre.com> In-Reply-To: <20231101-th1520-mmc-v4-0-86e0216b5994@baylibre.com> To: Ulf Hansson , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Jisheng Zhang , Adrian Hunter , Guo Ren , Fu Wei , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley Cc: Robert Nelson , Jason Kridner , Xi Ruoyao , Han Gao , Icenowy Zheng , linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Drew Fustini X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1698893345; l=1102; i=dfustini@baylibre.com; s=20230430; h=from:subject:message-id; bh=vZkA/Rp2zWEJvsAGA/badfpHmHgx6/3DqqLzYe2IxQc=; b=8GSfHaYjbAvdqR5aNak0qxCYTox6ynEJYklYiqEqs75Ahp961sktUsZMwhbfP69H8eDCKd2iX Qb0BX3cam5JBwzRquUhN8ceX4V+t4liKW0/NNfG/NOH4PRVtvHtorW+ X-Developer-Key: i=dfustini@baylibre.com; a=ed25519; pk=p3GKE9XFmjhwAayAHG4U108yag7V8xQVd4zJLdW0g7g= X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,T_SCC_BODY_TEXT_LINE autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Wed, 01 Nov 2023 19:50:39 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781418889885920063 X-GMAIL-MSGID: 1781418889885920063 Add mmc0 properties for the eMMC device and add mmc1 properties for the microSD slot. Set the frequency for the sdhci clock. Signed-off-by: Drew Fustini --- .../boot/dts/thead/th1520-lichee-module-4a.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi index a802ab110429..94f1741435a5 100644 --- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi @@ -29,6 +29,10 @@ &apb_clk { clock-frequency = <62500000>; }; +&sdhci_clk { + clock-frequency = <198000000>; +}; + &uart_sclk { clock-frequency = <100000000>; }; @@ -36,3 +40,19 @@ &uart_sclk { &dmac0 { status = "okay"; }; + +&mmc0 { + bus-width = <8>; + max-frequency = <198000000>; + mmc-hs400-1_8v; + non-removable; + no-sdio; + no-sd; + status = "okay"; +}; + +&mmc1 { + max-frequency = <198000000>; + bus-width = <4>; + status = "okay"; +};