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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id z6-20020a0ce986000000b0065d49825cc6si2307666qvn.79.2023.10.31.23.57.27 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 31 Oct 2023 23:57:27 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 64AF03858423 for ; Wed, 1 Nov 2023 06:57:27 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgeu2.qq.com (smtpbgeu2.qq.com [18.194.254.142]) by sourceware.org (Postfix) with ESMTPS id F37BA3858D39 for ; Wed, 1 Nov 2023 06:56:47 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org F37BA3858D39 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org F37BA3858D39 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=18.194.254.142 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698821818; cv=none; b=gmK+OvX+DoSdxQH80WsXUDNI9/GzsP3NZBqoB4heEJEQK1y7/wMf469dQMXoR9yJaDcNBxouafWVVPjQXFLS2EDCNSd3ykDq2+RMbwiZ8DTj9AAqCk/LWisv8odlsxW5F0ZQQjSsHxaHBRCqOLiVwD52+SAVdv0MaI8FPPWtmiw= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698821818; c=relaxed/simple; bh=pUvMmzYkPBU/VmLZV12xEThDmsjUumsTiHc/MDV3OXk=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=ZbNp8mrLkhhAWEEIe9jgq9zK1f+0X2d6A0O/ZqwZ8D0tcJCuJGEaoBAtwZHz57UaC2lSm00ieEKNdlDJGnr4p3JraWMrBaHUk2SX3VrJ8et2tMBj5o2vS7aE7LiyI7I9WxRU42meHFSAAMhlj+E4tjij10GKCeHM/khsYpPNKeU= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp82t1698821801ts8nfynu Received: from rios-cad121.hadoop.rioslab.org ( [58.60.1.9]) by bizesmtp.qq.com (ESMTP) with id ; Wed, 01 Nov 2023 14:56:40 +0800 (CST) X-QQ-SSF: 01400000000000G0V000000A0000000 X-QQ-FEAT: 3M0okmaRx3ilISsB6gd+V6PKQiNgX16L3qF/gFM0+/95H2kptm7zEJK0oET9f cjvF2UDct0nj2NzlqjLZShe5uVkOCljoQxUv5VoquIjBsN4pn3ZCf1zL+XIDJHhiTpVbBDH bIizVfkepzwja56+l4GJJz1PkNDNNgjckb7EsNoKXwniI1dG3xFRx/MIZifdT3ic8FfeMRX d/LejUCWE0RiUP9+MaIAIiDkDI6yAIMLOS3iJubN1dDkZov2t4ywPCGvRcMW+CK1OQ3f6Em 3Mk553dEiu48ArLuCVYVZFYZXfJZgy8+UJRxCCNU/fiEqShkHL3+c/EVlecNBN+dpyHTy4I tMaB22rEKVHvWhU73d+i45b0w1RJxm0G6VNezhbS/frYupGvw8cgMn0EiLJ1XpPn10ctBYr NUQarmrVSkLOl5komorwzQ== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 7447383634194206059 From: Juzhe-Zhong To: gcc-patches@gcc.gnu.org Cc: kito.cheng@gmail.com, kito.cheng@sifive.com, jeffreyalaw@gmail.com, rdapp.gcc@gmail.com, Juzhe-Zhong Subject: [PATCH] RISC-V: Allow dest operand and accumulator operand overlap of widen reduction instruction[PR112327] Date: Wed, 1 Nov 2023 14:56:39 +0800 Message-Id: <20231101065639.158911-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz7a-one-0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, T_SPF_HELO_TEMPERROR autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781343818032401750 X-GMAIL-MSGID: 1781343818032401750 Consider this following intrinsic code: void rvv_dot_prod(int16_t *pSrcA, int16_t *pSrcB, uint32_t n, int64_t *result) { size_t vl; vint16m4_t vSrcA, vSrcB; vint64m1_t vSum = __riscv_vmv_s_x_i64m1(0, 1); while (n > 0) { vl = __riscv_vsetvl_e16m4(n); vSrcA = __riscv_vle16_v_i16m4(pSrcA, vl); vSrcB = __riscv_vle16_v_i16m4(pSrcB, vl); vSum = __riscv_vwredsum_vs_i32m8_i64m1(__riscv_vwmul_vv_i32m8(vSrcA, vSrcB, vl), vSum, vl); pSrcA += vl; pSrcB += vl; n -= vl; } *result = __riscv_vmv_x_s_i64m1_i64(vSum); } https://godbolt.org/z/vWd35W7G6 Before this patch: ... Loop: ... vmv1r.v v2,v1 ... vwredsum.vs v1,v8,v2 ... After this patch: ... Loop: ... vwredsum.vs v1,v8,v1 ... PR target/112327 gcc/ChangeLog: * config/riscv/vector.md: Add '0'. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/base/pr112327-1.c: New test. * gcc.target/riscv/rvv/base/pr112327-2.c: New test. --- gcc/config/riscv/vector.md | 4 +-- .../gcc.target/riscv/rvv/base/pr112327-1.c | 27 +++++++++++++++++++ .../gcc.target/riscv/rvv/base/pr112327-2.c | 27 +++++++++++++++++++ 3 files changed, 56 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112327-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/pr112327-2.c diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index 0297e4f0227..3577971fa33 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -7765,7 +7765,7 @@ (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (unspec: [ (match_operand:VI_QHS 3 "register_operand" " vr, vr") - (match_operand: 4 "register_operand" " vr, vr") + (match_operand: 4 "register_operand" " vr0, vr0") ] ANY_WREDUC) (match_operand: 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))] "TARGET_VECTOR" @@ -7834,7 +7834,7 @@ (reg:SI FRM_REGNUM)] UNSPEC_VPREDICATE) (unspec: [ (match_operand:VF_HS 3 "register_operand" " vr, vr") - (match_operand: 4 "register_operand" " vr, vr") + (match_operand: 4 "register_operand" " vr0, vr0") ] ANY_FWREDUC_SUM) (match_operand: 2 "vector_merge_operand" " vu, 0")] UNSPEC_REDUC))] "TARGET_VECTOR" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112327-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112327-1.c new file mode 100644 index 00000000000..20da23976f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112327-1.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +void +foo (int16_t *pSrcA, int16_t *pSrcB, uint32_t n, int64_t *result) +{ + size_t vl; + vint16m4_t vSrcA, vSrcB; + vint64m1_t vSum = __riscv_vmv_s_x_i64m1 (0, 1); + while (n > 0) + { + vl = __riscv_vsetvl_e16m4 (n); + vSrcA = __riscv_vle16_v_i16m4 (pSrcA, vl); + vSrcB = __riscv_vle16_v_i16m4 (pSrcB, vl); + vSum = __riscv_vwredsum_vs_i32m8_i64m1 ( + __riscv_vwmul_vv_i32m8 (vSrcA, vSrcB, vl), vSum, vl); + pSrcA += vl; + pSrcB += vl; + n -= vl; + } + *result = __riscv_vmv_x_s_i64m1_i64 (vSum); +} + +/* { dg-final { scan-assembler-not {vmv1r} } } */ +/* { dg-final { scan-assembler-not {vmv\.v\.v} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/pr112327-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112327-2.c new file mode 100644 index 00000000000..5ffde000fbd --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/pr112327-2.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gcv_zvfh_zfh -mabi=lp64d -O3" } */ + +#include "riscv_vector.h" + +void +foo (_Float16 *pSrcA, _Float16 *pSrcB, uint32_t n, double *result) +{ + size_t vl; + vfloat16m4_t vSrcA, vSrcB; + vfloat64m1_t vSum = __riscv_vfmv_s_f_f64m1 (0, 1); + while (n > 0) + { + vl = __riscv_vsetvl_e16m4 (n); + vSrcA = __riscv_vle16_v_f16m4 (pSrcA, vl); + vSrcB = __riscv_vle16_v_f16m4 (pSrcB, vl); + vSum = __riscv_vfwredusum_vs_f32m8_f64m1 ( + __riscv_vfwmul_vv_f32m8 (vSrcA, vSrcB, vl), vSum, vl); + pSrcA += vl; + pSrcB += vl; + n -= vl; + } + *result = __riscv_vfmv_f_s_f64m1_f64 (vSum); +} + +/* { dg-final { scan-assembler-not {vmv1r} } } */ +/* { dg-final { scan-assembler-not {vmv\.v\.v} } } */