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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5PEPF00014B94.eurprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB9431 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_LOTSOFHASH, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781294244297133997 X-GMAIL-MSGID: 1781294244297133997 Hi, This patch adds for Guarded Control Stack Extension (GCS) extension. GCS feature is optional from Armv9.4-A architecture and enabled by passing +gcs option to -march (eg: -march=armv9.4-a+gcs) or using ".arch_extension gcs" directive in the assembly file. Also this patch adds support for GCS instructions gcspushx, gcspopcx, gcspopx, gcsss1, gcsss2, gcspushm, gcspopm, gcsstr and gcssttr. For this feature in gas/doc/c-aarch64.texi: column 2 is marked N/A, as this column "minimum architecture" is not relevant any more and will be removed in the later patches. Regression tested for aarch64-none-elf target and found no regressions. Ok for binutils-master? Regards, Srinath. diff --git a/gas/NEWS b/gas/NEWS index 896ea2d7eb24cd7295f953ce0c619b0a778024f0..60f616c10735b929980f7181e95b6d1159ab967b 100644 --- a/gas/NEWS +++ b/gas/NEWS @@ -1,5 +1,7 @@ -*- text -*- +* Add support for Guarded Control Stack (GCS) for AArch64. + * Add support for AArch64 Check Feature Status Extension (CHK). * Add support for 'armv8.9-a' and 'armv9.4-a' for -march in AArch64 GAS. diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index f5b7b427dd6b5a0bc899cc3c79f05c02005b6c5b..6d2040037c3ff2c4c5d1ff967ad3c7222d878c93 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -10325,6 +10325,7 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = { {"hbc", AARCH64_FEATURE (HBC), AARCH64_NO_FEATURES}, {"cssc", AARCH64_FEATURE (CSSC), AARCH64_NO_FEATURES}, {"chk", AARCH64_FEATURE (CHK), AARCH64_NO_FEATURES}, + {"gcs", AARCH64_FEATURE (GCS), AARCH64_NO_FEATURES}, {NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES}, }; diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi index f10a44eae9347d5432ad6f7d5a07da4946e53ae2..7e053185d30b378ca3a6da74dd4b925dba9b5422 100644 --- a/gas/doc/c-aarch64.texi +++ b/gas/doc/c-aarch64.texi @@ -261,6 +261,8 @@ automatically cause those extensions to be disabled. @tab Enable Transactional Memory Extensions. @item @code{chk} @tab ARMv8-A @tab No @tab Enable Check Feature Status Extension. +@item @code{gcs} @tab N/A @tab No + @tab Enable Guarded Control Stack Extension. @end multitable @node AArch64 Syntax diff --git a/gas/testsuite/gas/aarch64/gcs-1-bad.d b/gas/testsuite/gas/aarch64/gcs-1-bad.d new file mode 100644 index 0000000000000000000000000000000000000000..7c3a7ae50a8dc7bf411a6deb419f723d50ff3812 --- /dev/null +++ b/gas/testsuite/gas/aarch64/gcs-1-bad.d @@ -0,0 +1,3 @@ +#as: -march=armv9.2-a +#source: gcs-1.s +#error_output: gcs-1-bad.l diff --git a/gas/testsuite/gas/aarch64/gcs-1-bad.l b/gas/testsuite/gas/aarch64/gcs-1-bad.l new file mode 100644 index 0000000000000000000000000000000000000000..ca8d17ab8fc5123f2444a6c54193ab2354be1e6e --- /dev/null +++ b/gas/testsuite/gas/aarch64/gcs-1-bad.l @@ -0,0 +1,45 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: selected processor does not support `gcspushx' +[^ :]+:[0-9]+: Error: selected processor does not support `gcspopcx' +[^ :]+:[0-9]+: Error: selected processor does not support `gcspopx' +[^ :]+:[0-9]+: Error: selected processor does not support `gcspopm' +[^ :]+:[0-9]+: Error: selected processor does not support `gcspushm x0' +[^ :]+:[0-9]+: Error: selected processor does not support `gcspushm x15' +[^ :]+:[0-9]+: Error: selected processor does not support `gcspushm x30' +[^ :]+:[0-9]+: Error: selected processor does not support `gcspushm xzr' +[^ :]+:[0-9]+: Error: selected processor does not support `gcsss1 x0' +[^ :]+:[0-9]+: Error: selected processor does not support `gcsss1 x15' +[^ :]+:[0-9]+: Error: selected processor does not support `gcsss1 x30' +[^ :]+:[0-9]+: Error: selected processor does not support `gcsss1 xzr' +[^ :]+:[0-9]+: Error: selected processor does not support `gcsss2 x0' +[^ :]+:[0-9]+: Error: selected processor does not support `gcsss2 x15' +[^ :]+:[0-9]+: Error: selected processor does not support `gcsss2 x30' +[^ :]+:[0-9]+: Error: selected processor does not support `gcsss2 xzr' +[^ :]+:[0-9]+: Error: selected processor does not support `gcspopm x0' +[^ :]+:[0-9]+: Error: selected processor does not support `gcspopm x15' +[^ :]+:[0-9]+: Error: selected processor does not support `gcspopm x30' +[^ :]+:[0-9]+: Error: selected processor does not support `gcspopm xzr' +[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x0,x1' +[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x0,x16' +[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x0,sp' +[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x15,x1' +[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x15,x16' +[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x15,sp' +[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x30,x1' +[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x30,x16' +[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr x30,sp' +[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr xzr,x1' +[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr xzr,x16' +[^ :]+:[0-9]+: Error: selected processor does not support `gcsstr xzr,sp' +[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x0,x1' +[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x0,x16' +[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x0,sp' +[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x15,x1' +[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x15,x16' +[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x15,sp' +[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x30,x1' +[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x30,x16' +[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr x30,sp' +[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr xzr,x1' +[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr xzr,x16' +[^ :]+:[0-9]+: Error: selected processor does not support `gcssttr xzr,sp' diff --git a/gas/testsuite/gas/aarch64/gcs-1.d b/gas/testsuite/gas/aarch64/gcs-1.d new file mode 100644 index 0000000000000000000000000000000000000000..51f9dd6afc5cca1e69ad408849d71a6c7e3f09cf --- /dev/null +++ b/gas/testsuite/gas/aarch64/gcs-1.d @@ -0,0 +1,54 @@ +#name: Test of Guarded Control Stack Instructions. +#as: -march=armv9.3-a+gcs +#objdump: -dr + +[^:]+: file format .* + + +[^:]+: + +[^:]+: +.*: d508779f gcspushx +.*: d50877bf gcspopcx +.*: d50877df gcspopx +.*: d52b773f gcspopm +.*: d50b7700 gcspushm x0 +.*: d50b770f gcspushm x15 +.*: d50b771e gcspushm x30 +.*: d50b771f gcspushm xzr +.*: d50b7740 gcsss1 x0 +.*: d50b774f gcsss1 x15 +.*: d50b775e gcsss1 x30 +.*: d50b775f gcsss1 xzr +.*: d52b7760 gcsss2 x0 +.*: d52b776f gcsss2 x15 +.*: d52b777e gcsss2 x30 +.*: d52b777f gcsss2 xzr +.*: d52b7720 gcspopm x0 +.*: d52b772f gcspopm x15 +.*: d52b773e gcspopm x30 +.*: d52b773f gcspopm +.*: d91f0c20 gcsstr x0, x1 +.*: d91f0e00 gcsstr x0, x16 +.*: d91f0fe0 gcsstr x0, sp +.*: d91f0c2f gcsstr x15, x1 +.*: d91f0e0f gcsstr x15, x16 +.*: d91f0fef gcsstr x15, sp +.*: d91f0c3e gcsstr x30, x1 +.*: d91f0e1e gcsstr x30, x16 +.*: d91f0ffe gcsstr x30, sp +.*: d91f0c3f gcsstr xzr, x1 +.*: d91f0e1f gcsstr xzr, x16 +.*: d91f0fff gcsstr xzr, sp +.*: d91f1c20 gcssttr x0, x1 +.*: d91f1e00 gcssttr x0, x16 +.*: d91f1fe0 gcssttr x0, sp +.*: d91f1c2f gcssttr x15, x1 +.*: d91f1e0f gcssttr x15, x16 +.*: d91f1fef gcssttr x15, sp +.*: d91f1c3e gcssttr x30, x1 +.*: d91f1e1e gcssttr x30, x16 +.*: d91f1ffe gcssttr x30, sp +.*: d91f1c3f gcssttr xzr, x1 +.*: d91f1e1f gcssttr xzr, x16 +.*: d91f1fff gcssttr xzr, sp diff --git a/gas/testsuite/gas/aarch64/gcs-1.s b/gas/testsuite/gas/aarch64/gcs-1.s new file mode 100644 index 0000000000000000000000000000000000000000..9706587878d51d0c9874fdf1325d1052dd55ff57 --- /dev/null +++ b/gas/testsuite/gas/aarch64/gcs-1.s @@ -0,0 +1,19 @@ + .text + gcspushx + gcspopcx + gcspopx + gcspopm + + .irp op gcspushm, gcsss1, gcsss2, gcspopm + .irp reg1 x0, x15, x30, xzr + \op \reg1 + .endr + .endr + + .irp op gcsstr, gcssttr + .irp reg1 x0, x15, x30, xzr + .irp reg2 x1, x16, sp + \op \reg1, \reg2 + .endr + .endr + .endr diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index 004df9ec1eb59bb60c821a96ce8f2960b76a9a7c..fc6a01aefd6f957ceb4f1578d09977321ff270b6 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -161,6 +161,8 @@ enum aarch64_feature_bit { AARCH64_FEATURE_V8_9A, /* Check Feature Status Extension. */ AARCH64_FEATURE_CHK, + /* Guarded Control Stack. */ + AARCH64_FEATURE_GCS, /* SME2. */ AARCH64_FEATURE_SME2, DUMMY1, @@ -897,6 +899,7 @@ enum aarch64_insn_class dotproduct, bfloat16, cssc, + gcs, }; /* Opcode enumerators. */ diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 8f4bfc3f2d8a2cc64a72320cb4882d35c66b208e..f281fd55070da59f3ce598115b9ab701fd754deb 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -2574,6 +2574,8 @@ static const aarch64_feature_set aarch64_feature_cssc = AARCH64_FEATURE (CSSC); static const aarch64_feature_set aarch64_feature_chk = AARCH64_FEATURE (CHK); +static const aarch64_feature_set aarch64_feature_gcs = + AARCH64_FEATURE (GCS); #define CORE &aarch64_feature_v8 #define FP &aarch64_feature_fp @@ -2633,6 +2635,7 @@ static const aarch64_feature_set aarch64_feature_chk = #define HBC &aarch64_feature_hbc #define CSSC &aarch64_feature_cssc #define CHK &aarch64_feature_chk +#define GCS &aarch64_feature_gcs #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \ { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS, 0, 0, NULL } @@ -2782,6 +2785,8 @@ static const aarch64_feature_set aarch64_feature_chk = { NAME, OPCODE, MASK, cssc, 0, CSSC, OPS, QUALS, FLAGS, 0, 0, NULL } #define CHK_INSN(NAME, OPCODE, MASK, OPS, QUALS, FLAGS) \ { NAME, OPCODE, MASK, ic_system, 0, CHK, OPS, QUALS, FLAGS, 0, 0, NULL } +#define GCS_INSN(NAME, OPCODE, MASK, OPS, QUALS, FLAGS) \ + { NAME, OPCODE, MASK, gcs, 0, GCS, OPS, QUALS, FLAGS, 0, 0, NULL } #define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \ MOPS_INSN (NAME, OPCODE, MASK, 0, \ @@ -4141,6 +4146,16 @@ const struct aarch64_opcode aarch64_opcode_table[] = CORE_INSN ("dmb", 0xd50330bf, 0xfffff0ff, ic_system, 0, OP1 (BARRIER), {}, 0), CORE_INSN ("isb", 0xd50330df, 0xfffff0ff, ic_system, 0, OP1 (BARRIER_ISB), {}, F_OPD0_OPT | F_DEFAULT (0xF)), SB_INSN ("sb", 0xd50330ff, 0xffffffff, ic_system, OP0 (), {}, 0), + GCS_INSN ("gcspushx", 0xd508779f, 0xffffffff, OP0 (), {}, 0), + GCS_INSN ("gcspopx", 0xd50877df, 0xffffffff, OP0 (), {}, 0), + GCS_INSN ("gcspopcx", 0xd50877bf, 0xffffffff, OP0 (), {}, 0), + GCS_INSN ("gcsss1", 0xd50b7740, 0xffffffe0, OP1 (Rt), QL_I1X, 0), + GCS_INSN ("gcspushm", 0xd50b7700, 0xffffffe0, OP1 (Rt), QL_I1X, 0), + GCS_INSN ("gcsss2", 0xd52b7760, 0xffffffe0, OP1 (Rt), QL_I1X, 0), + GCS_INSN ("gcspopm", 0xd52b773f, 0xffffffff, OP0 (), {}, 0), + GCS_INSN ("gcspopm", 0xd52b7720, 0xffffffe0, OP1 (Rt), QL_I1X, 0), + GCS_INSN ("gcsstr", 0xd91f0c00, 0xfffffc00, OP2 (Rt, Rn_SP), QL_I2SAMEX, 0), + GCS_INSN ("gcssttr", 0xd91f1c00, 0xfffffc00, OP2 (Rt, Rn_SP), QL_I2SAMEX, 0), CORE_INSN ("sys", 0xd5080000, 0xfff80000, ic_system, 0, OP5 (UIMM3_OP1, CRn, CRm, UIMM3_OP2, Rt), QL_SYS, F_HAS_ALIAS | F_OPD4_OPT | F_DEFAULT (0x1F)), CORE_INSN ("at", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_AT, Rt), QL_SRC_X, F_ALIAS), CORE_INSN ("dc", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_DC, Rt), QL_SRC_X, F_ALIAS), From patchwork Tue Oct 31 17:51:19 2023 Content-Type: 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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM4PEPF00027A69.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB4PR08MB8005 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_LOTSOFHASH, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781294387462797896 X-GMAIL-MSGID: 1781294387462797896 Hi, This patch adds support for Guarded control stack data synchronization instruction (GCSB DSYNC). This instruction is allocated to existing HINT space and uses the HINT number 19 and to match this an entry is added to the aarch64_hint_options array. Regression tested for aarch64-none-elf target and found no regressions. Ok for binutils-master? Regards, Srinath. diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c index 6d2040037c3ff2c4c5d1ff967ad3c7222d878c93..1f687fe1ca07d5436602860bbdbc58e1e02f6cc2 100644 --- a/gas/config/tc-aarch64.c +++ b/gas/config/tc-aarch64.c @@ -4417,12 +4417,13 @@ parse_barrier (char **str) return o->value; } -/* Parse an operand for a PSB barrier. Set *HINT_OPT to the hint-option record - return 0 if successful. Otherwise return PARSE_FAIL. */ +/* Parse an option for barrier, bti and guarded control stack data + synchronization instructions. Return true on matching the target + options else return false. */ -static int -parse_barrier_psb (char **str, - const struct aarch64_name_value_pair ** hint_opt) +static bool +parse_hint_opt (const char *name, char **str, + const struct aarch64_name_value_pair ** hint_opt) { char *p, *q; const struct aarch64_name_value_pair *o; @@ -4433,64 +4434,19 @@ parse_barrier_psb (char **str, o = str_hash_find_n (aarch64_hint_opt_hsh, p, q - p); if (!o) - { - set_fatal_syntax_error - ( _("unknown or missing option to PSB/TSB")); - return PARSE_FAIL; - } + return false; - if (o->value != 0x11) - { - /* PSB only accepts option name 'CSYNC'. */ - set_syntax_error - (_("the specified option is not accepted for PSB/TSB")); - return PARSE_FAIL; - } + if ((strcmp ("gcsb", name) == 0 && o->value != HINT_OPD_DSYNC) + || ((strcmp ("psb", name) == 0 || strcmp ("tsb", name) == 0) + && o->value != HINT_OPD_CSYNC) + || ((strcmp ("bti", name) == 0) + && (o->value != HINT_OPD_C && o->value != HINT_OPD_J + && o->value != HINT_OPD_JC))) + return false; *str = q; *hint_opt = o; - return 0; -} - -/* Parse an operand for BTI. Set *HINT_OPT to the hint-option record - return 0 if successful. Otherwise return PARSE_FAIL. */ - -static int -parse_bti_operand (char **str, - const struct aarch64_name_value_pair ** hint_opt) -{ - char *p, *q; - const struct aarch64_name_value_pair *o; - - p = q = *str; - while (ISALPHA (*q)) - q++; - - o = str_hash_find_n (aarch64_hint_opt_hsh, p, q - p); - if (!o) - { - set_fatal_syntax_error - ( _("unknown option to BTI")); - return PARSE_FAIL; - } - - switch (o->value) - { - /* Valid BTI operands. */ - case HINT_OPD_C: - case HINT_OPD_J: - case HINT_OPD_JC: - break; - - default: - set_syntax_error - (_("unknown option to BTI")); - return PARSE_FAIL; - } - - *str = q; - *hint_opt = o; - return 0; + return true; } /* Parse STR for reg of REG_TYPE and following '.' and QUALIFIER. @@ -7777,8 +7733,7 @@ parse_operands (char *str, const aarch64_opcode *opcode) break; case AARCH64_OPND_BARRIER_PSB: - val = parse_barrier_psb (&str, &(info->hint_option)); - if (val == PARSE_FAIL) + if (!parse_hint_opt (opcode->name, &str, &(info->hint_option))) goto failure; break; @@ -7833,9 +7788,13 @@ parse_operands (char *str, const aarch64_opcode *opcode) info->qualifier = vectype_to_qualifier (&vectype); break; + case AARCH64_OPND_BARRIER_GCSB: + if (!parse_hint_opt (opcode->name, &str, &(info->hint_option))) + goto failure; + break; + case AARCH64_OPND_BTI_TARGET: - val = parse_bti_operand (&str, &(info->hint_option)); - if (val == PARSE_FAIL) + if (!parse_hint_opt (opcode->name, &str, &(info->hint_option))) goto failure; break; diff --git a/gas/testsuite/gas/aarch64/gcs-1.d b/gas/testsuite/gas/aarch64/gcs-1.d index 51f9dd6afc5cca1e69ad408849d71a6c7e3f09cf..09fa418e5eab6f27004dcdfa43486ecaa92afec5 100644 --- a/gas/testsuite/gas/aarch64/gcs-1.d +++ b/gas/testsuite/gas/aarch64/gcs-1.d @@ -12,6 +12,7 @@ .*: d50877bf gcspopcx .*: d50877df gcspopx .*: d52b773f gcspopm +.*: d503227f gcsb dsync .*: d50b7700 gcspushm x0 .*: d50b770f gcspushm x15 .*: d50b771e gcspushm x30 diff --git a/gas/testsuite/gas/aarch64/gcs-1.s b/gas/testsuite/gas/aarch64/gcs-1.s index 9706587878d51d0c9874fdf1325d1052dd55ff57..35584a8810ea3b5e704dce6ee794664d14014e8c 100644 --- a/gas/testsuite/gas/aarch64/gcs-1.s +++ b/gas/testsuite/gas/aarch64/gcs-1.s @@ -3,6 +3,7 @@ gcspopcx gcspopx gcspopm + gcsb dsync .irp op gcspushm, gcsss1, gcsss2, gcspopm .irp reg1 x0, x15, x30, xzr diff --git a/gas/testsuite/gas/aarch64/hint-bad.d b/gas/testsuite/gas/aarch64/hint-bad.d new file mode 100644 index 0000000000000000000000000000000000000000..e881fc9b386809123da9f956b0f1f12794490dee --- /dev/null +++ b/gas/testsuite/gas/aarch64/hint-bad.d @@ -0,0 +1,4 @@ +#name: Barrier and BTI instructions with wrong targets. +#as: -march=armv8-a +#source: hint-bad.s +#error_output: hint-bad.l diff --git a/gas/testsuite/gas/aarch64/hint-bad.l b/gas/testsuite/gas/aarch64/hint-bad.l new file mode 100644 index 0000000000000000000000000000000000000000..57caed10e9a16de8415bc1a19bf9799898b5755e --- /dev/null +++ b/gas/testsuite/gas/aarch64/hint-bad.l @@ -0,0 +1,8 @@ +[^ :]+: Assembler messages: +[^ :]+:[0-9]+: Error: operand 1 must be the GCSB option name DSYNC -- `gcsb' +[^ :]+:[0-9]+: Error: operand 1 must be the GCSB option name DSYNC -- `gcsb csync' +[^ :]+:[0-9]+: Error: operand 1 must be the PSB/TSB option name CSYNC -- `psb' +[^ :]+:[0-9]+: Error: operand 1 must be the PSB/TSB option name CSYNC -- `psb dsync' +[^ :]+:[0-9]+: Error: operand 1 must be the PSB/TSB option name CSYNC -- `tsb' +[^ :]+:[0-9]+: Error: operand 1 must be the PSB/TSB option name CSYNC -- `tsb dsync' +[^ :]+:[0-9]+: Error: operand 1 must be BTI targets j/c/jc -- `bti jj' diff --git a/gas/testsuite/gas/aarch64/hint-bad.s b/gas/testsuite/gas/aarch64/hint-bad.s new file mode 100644 index 0000000000000000000000000000000000000000..319b859f845ef37ad440eb300eac823456c470b0 --- /dev/null +++ b/gas/testsuite/gas/aarch64/hint-bad.s @@ -0,0 +1,8 @@ + .text + gcsb + gcsb csync + psb + psb dsync + tsb + tsb dsync + bti jj diff --git a/gas/testsuite/gas/aarch64/system.d b/gas/testsuite/gas/aarch64/system.d index 8ad274655049dd8b7ab5253f2d8b45537e50528f..bb1a94cb0204b953ba204365c075493622d24c16 100644 --- a/gas/testsuite/gas/aarch64/system.d +++ b/gas/testsuite/gas/aarch64/system.d @@ -34,7 +34,7 @@ Disassembly of section \.text: .*: d503221f (hint #0x10|esb) .*: d503223f (hint #0x11|psb csync) .*: d503225f (hint #0x12|tsb csync) -.*: d503227f hint #0x13 +.*: d503227f (hint #0x13|gcsb dsync) .*: d503229f (hint #0x14|csdb) .*: d50322bf hint #0x15 .*: d50322df (hint #0x16|clearbhb) diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h index fc6a01aefd6f957ceb4f1578d09977321ff270b6..8410a69ee24a692d340d3a5b3e82fe97dca8c7a2 100644 --- a/include/opcode/aarch64.h +++ b/include/opcode/aarch64.h @@ -520,6 +520,7 @@ enum aarch64_opnd AARCH64_OPND_PRFOP, /* Prefetch operation. */ AARCH64_OPND_RPRFMOP, /* Range prefetch operation. */ AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */ + AARCH64_OPND_BARRIER_GCSB, /* Barrier operand for GCSB. */ AARCH64_OPND_BTI_TARGET, /* BTI {}. */ AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [, #*16]. */ AARCH64_OPND_SVE_ADDR_RI_S4x32, /* SVE [, #*32]. */ @@ -1480,6 +1481,7 @@ struct aarch64_inst /* Defining the HINT #imm values for the aarch64_hint_options. */ #define HINT_OPD_CSYNC 0x11 +#define HINT_OPD_DSYNC 0x13 #define HINT_OPD_C 0x22 #define HINT_OPD_J 0x24 #define HINT_OPD_JC 0x26 diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 599bb6365374257189c3247ae0dbf0881ab6c079..6d9f3a06def7e696ffd6cd74fa8e1ffc7eeecbb7 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -554,6 +554,7 @@ const struct aarch64_name_value_pair aarch64_hint_options[] = /* BTI. This is also the F_DEFAULT entry for AARCH64_OPND_BTI_TARGET. */ { " ", HINT_ENCODE (HINT_OPD_F_NOPRINT, 0x20) }, { "csync", HINT_OPD_CSYNC }, /* PSB CSYNC. */ + { "dsync", HINT_OPD_DSYNC }, /* GCSB DSYNC. */ { "c", HINT_OPD_C }, /* BTI C. */ { "j", HINT_OPD_J }, /* BTI J. */ { "jc", HINT_OPD_JC }, /* BTI JC. */ @@ -4629,6 +4630,10 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc, snprintf (buf, size, "{%s}", style_reg (styler, "zt0")); break; + case AARCH64_OPND_BARRIER_GCSB: + snprintf (buf, size, "%s", style_sub_mnem (styler, "dsync")); + break; + case AARCH64_OPND_BTI_TARGET: if ((HINT_FLAG (opnd->hint_option->value) & HINT_OPD_F_NOPRINT) == 0) snprintf (buf, size, "%s", diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index f281fd55070da59f3ce598115b9ab701fd754deb..463939d24ca1db8ad59c3f8e7a4f27f007f4137a 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -4156,6 +4156,7 @@ const struct aarch64_opcode aarch64_opcode_table[] = GCS_INSN ("gcspopm", 0xd52b7720, 0xffffffe0, OP1 (Rt), QL_I1X, 0), GCS_INSN ("gcsstr", 0xd91f0c00, 0xfffffc00, OP2 (Rt, Rn_SP), QL_I2SAMEX, 0), GCS_INSN ("gcssttr", 0xd91f1c00, 0xfffffc00, OP2 (Rt, Rn_SP), QL_I2SAMEX, 0), + CORE_INSN ("gcsb", 0xd503227f, 0xffffffff, ic_system, 0, OP1 (BARRIER_GCSB), {}, F_ALIAS), CORE_INSN ("sys", 0xd5080000, 0xfff80000, ic_system, 0, OP5 (UIMM3_OP1, CRn, CRm, UIMM3_OP2, Rt), QL_SYS, F_HAS_ALIAS | F_OPD4_OPT | F_DEFAULT (0x1F)), CORE_INSN ("at", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_AT, Rt), QL_SRC_X, F_ALIAS), CORE_INSN ("dc", 0xd5080000, 0xfff80000, ic_system, 0, OP2 (SYSREG_DC, Rt), QL_SRC_X, F_ALIAS), @@ -6300,7 +6301,9 @@ const struct aarch64_opcode aarch64_opcode_table[] = "a range prefetch operation specifier") \ Y(SYSTEM, none, "BARRIER_PSB", 0, F (), \ "the PSB/TSB option name CSYNC") \ - Y(SYSTEM, hint, "BTI", 0, F (), \ + Y(SYSTEM, none, "BARRIER_GCSB", 0, F (), \ + "the GCSB option name DSYNC") \ + Y(SYSTEM, hint, "BTI_TARGET", 0, F (), \ "BTI targets j/c/jc") \ Y(ADDRESS, sve_addr_ri_s4, "SVE_ADDR_RI_S4x16", \ 4 << OPD_F_OD_LSB, F(FLD_Rn), \ From patchwork Tue Oct 31 17:52:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinath Parvathaneni X-Patchwork-Id: 160300 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b90f:0:b0:403:3b70:6f57 with SMTP id t15csp412325vqg; Tue, 31 Oct 2023 10:53:16 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHkl/wzRm2N8sOgZAW0dCNngEcMJrjNPWG9PHijaoJPZvFpV3zOMJCIuWxjYvgB+Gz/AEtw X-Received: by 2002:a05:622a:1914:b0:408:392e:2aa5 with SMTP id w20-20020a05622a191400b00408392e2aa5mr572279qtc.20.1698774796638; Tue, 31 Oct 2023 10:53:16 -0700 (PDT) Received: from server2.sourceware.org (server2.sourceware.org. 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Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM2PEPF0001C70E.eurprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PAWPR08MB9493 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_LOTSOFHASH, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781294481313035368 X-GMAIL-MSGID: 1781294481313035368 Hi, This patch adds support for 10 new AArch64 system registers (gcscre0_el1, gcscr_el1, gcscr_el12, gcscr_el2, gcscr_el3, gcspr_el0, gcspr_el1 ,gcspr_el12, gcspr_el2 and gcspr_el3), which are enabled on using Guarded Control Stack (+gcs flag) feature. Regression tested for aarch64-none-elf target and found no regressions. Ok for binutils-master? Regards, Srinath. diff --git a/gas/testsuite/gas/aarch64/gcs-sysregs-bad.d b/gas/testsuite/gas/aarch64/gcs-sysregs-bad.d new file mode 100644 index 0000000000000000000000000000000000000000..439c1bdbabaeb05ed23f998c76a409864b3d844e --- /dev/null +++ b/gas/testsuite/gas/aarch64/gcs-sysregs-bad.d @@ -0,0 +1,3 @@ +#as: -march=armv8-a +#source: gcs-sysregs.s +#error_output: gcs-sysregs-bad.l diff --git a/gas/testsuite/gas/aarch64/gcs-sysregs-bad.l b/gas/testsuite/gas/aarch64/gcs-sysregs-bad.l new file mode 100644 index 0000000000000000000000000000000000000000..9ebfd8cfde8bdd2109fc45eb21c466124ec0a5fb --- /dev/null +++ b/gas/testsuite/gas/aarch64/gcs-sysregs-bad.l @@ -0,0 +1,21 @@ +[^:]*: Assembler messages: +.*: Error: selected processor does not support system register name 'gcscr_el1' +.*: Error: selected processor does not support system register name 'gcscr_el1' +.*: Error: selected processor does not support system register name 'gcspr_el1' +.*: Error: selected processor does not support system register name 'gcspr_el1' +.*: Error: selected processor does not support system register name 'gcscr_el2' +.*: Error: selected processor does not support system register name 'gcscr_el2' +.*: Error: selected processor does not support system register name 'gcspr_el2' +.*: Error: selected processor does not support system register name 'gcspr_el2' +.*: Error: selected processor does not support system register name 'gcscr_el3' +.*: Error: selected processor does not support system register name 'gcscr_el3' +.*: Error: selected processor does not support system register name 'gcspr_el3' +.*: Error: selected processor does not support system register name 'gcspr_el3' +.*: Error: selected processor does not support system register name 'gcspr_el0' +.*: Error: selected processor does not support system register name 'gcspr_el0' +.*: Error: selected processor does not support system register name 'gcspr_el12' +.*: Error: selected processor does not support system register name 'gcspr_el12' +.*: Error: selected processor does not support system register name 'gcscr_el12' +.*: Error: selected processor does not support system register name 'gcscr_el12' +.*: Error: selected processor does not support system register name 'gcscre0_el1' +.*: Error: selected processor does not support system register name 'gcscre0_el1' diff --git a/gas/testsuite/gas/aarch64/gcs-sysregs.d b/gas/testsuite/gas/aarch64/gcs-sysregs.d new file mode 100644 index 0000000000000000000000000000000000000000..f75c2708a14be2555c14d0e043486da88c9b50ad --- /dev/null +++ b/gas/testsuite/gas/aarch64/gcs-sysregs.d @@ -0,0 +1,29 @@ +#name: Test of Guarded Control Stack system registers +#as: -march=armv8.8-a+gcs +#objdump: -dr + +.*: file format .* + +Disassembly of section \.text: + +0+ <.*>: +.*: d5182500 msr gcscr_el1, x0 +.*: d538251e mrs x30, gcscr_el1 +.*: d5182520 msr gcspr_el1, x0 +.*: d538253e mrs x30, gcspr_el1 +.*: d51c2500 msr gcscr_el2, x0 +.*: d53c251e mrs x30, gcscr_el2 +.*: d51c2520 msr gcspr_el2, x0 +.*: d53c253e mrs x30, gcspr_el2 +.*: d51e2500 msr gcscr_el3, x0 +.*: d53e251e mrs x30, gcscr_el3 +.*: d51e2520 msr gcspr_el3, x0 +.*: d53e253e mrs x30, gcspr_el3 +.*: d51b2520 msr gcspr_el0, x0 +.*: d53b253e mrs x30, gcspr_el0 +.*: d51d2520 msr gcspr_el12, x0 +.*: d53d253e mrs x30, gcspr_el12 +.*: d51d2500 msr gcscr_el12, x0 +.*: d53d251e mrs x30, gcscr_el12 +.*: d5182540 msr gcscre0_el1, x0 +.*: d538255e mrs x30, gcscre0_el1 diff --git a/gas/testsuite/gas/aarch64/gcs-sysregs.s b/gas/testsuite/gas/aarch64/gcs-sysregs.s new file mode 100644 index 0000000000000000000000000000000000000000..0f5de0153880166abac2c7f74b2c98210011e228 --- /dev/null +++ b/gas/testsuite/gas/aarch64/gcs-sysregs.s @@ -0,0 +1,20 @@ + msr gcscr_el1, x0 + mrs x30, gcscr_el1 + msr gcspr_el1, x0 + mrs x30, gcspr_el1 + msr gcscr_el2, x0 + mrs x30, gcscr_el2 + msr gcspr_el2, x0 + mrs x30, gcspr_el2 + msr gcscr_el3, x0 + mrs x30, gcscr_el3 + msr gcspr_el3, x0 + mrs x30, gcspr_el3 + msr gcspr_el0, x0 + mrs x30, gcspr_el0 + msr gcspr_el12, x0 + mrs x30, gcspr_el12 + msr gcscr_el12, x0 + mrs x30, gcscr_el12 + msr gcscre0_el1, x0 + mrs x30, gcscre0_el1 diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def index 9adabea5cd41939dcde94c94579389b897ac7346..2f5780a21d49b9c2bf6b9e2c61aad82a7a5069b9 100644 --- a/opcodes/aarch64-sys-regs.def +++ b/opcodes/aarch64-sys-regs.def @@ -419,6 +419,16 @@ SYSREG ("fpcr", CPENC (3,3,4,4,0), 0, AARCH64_NO_FEATURES) SYSREG ("fpexc32_el2", CPENC (3,4,5,3,0), 0, AARCH64_NO_FEATURES) SYSREG ("fpsr", CPENC (3,3,4,4,1), 0, AARCH64_NO_FEATURES) + SYSREG ("gcspr_el0", CPENC (3,3,2,5,1), F_ARCHEXT, AARCH64_FEATURE (GCS)) + SYSREG ("gcspr_el1", CPENC (3,0,2,5,1), F_ARCHEXT, AARCH64_FEATURE (GCS)) + SYSREG ("gcspr_el2", CPENC (3,4,2,5,1), F_ARCHEXT, AARCH64_FEATURE (GCS)) + SYSREG ("gcspr_el12", CPENC (3,5,2,5,1), F_ARCHEXT, AARCH64_FEATURE (GCS)) + SYSREG ("gcspr_el3", CPENC (3,6,2,5,1), F_ARCHEXT, AARCH64_FEATURE (GCS)) + SYSREG ("gcscre0_el1", CPENC (3,0,2,5,2), F_ARCHEXT, AARCH64_FEATURE (GCS)) + SYSREG ("gcscr_el1", CPENC (3,0,2,5,0), F_ARCHEXT, AARCH64_FEATURE (GCS)) + SYSREG ("gcscr_el2", CPENC (3,4,2,5,0), F_ARCHEXT, AARCH64_FEATURE (GCS)) + SYSREG ("gcscr_el12", CPENC (3,5,2,5,0), F_ARCHEXT, AARCH64_FEATURE (GCS)) + SYSREG ("gcscr_el3", CPENC (3,6,2,5,0), F_ARCHEXT, AARCH64_FEATURE (GCS)) SYSREG ("gcr_el1", CPENC (3,0,1,0,6), F_ARCHEXT, AARCH64_FEATURE (MEMTAG)) SYSREG ("gmid_el1", CPENC (3,1,0,0,4), F_REG_READ|F_ARCHEXT, AARCH64_FEATURE (MEMTAG)) SYSREG ("gpccr_el3", CPENC (3,6,2,1,6), 0, AARCH64_NO_FEATURES)