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Tue, 31 Oct 2023 05:11:56 +0000 Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 39V5BrbU009999; Tue, 31 Oct 2023 05:11:53 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 3u0ucktx93-1; Tue, 31 Oct 2023 05:11:53 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 39V5Brhl009994; Tue, 31 Oct 2023 05:11:53 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-msarkar-hyd.qualcomm.com [10.213.111.194]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 39V5BqD2009989; Tue, 31 Oct 2023 05:11:53 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3891782) id 3AAE0450D; Tue, 31 Oct 2023 10:41:52 +0530 (+0530) From: Mrinmay Sarkar To: agross@kernel.org, andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, konrad.dybcio@linaro.org, mani@kernel.org Cc: quic_shazhuss@quicinc.com, quic_nitegupt@quicinc.com, quic_ramkri@quicinc.com, quic_nayiluri@quicinc.com, dmitry.baryshkov@linaro.org, robh@kernel.org, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com, quic_parass@quicinc.com, quic_schintav@quicinc.com, quic_shijose@quicinc.com, Mrinmay Sarkar , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Kishon Vijay Abraham I , linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mhi@lists.linux.dev Subject: [PATCH v6 1/4] dt-bindings: PCI: qcom-ep: Add support for SA8775P SoC Date: Tue, 31 Oct 2023 10:41:45 +0530 Message-Id: <1698729108-27356-2-git-send-email-quic_msarkar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1698729108-27356-1-git-send-email-quic_msarkar@quicinc.com> References: <1698729108-27356-1-git-send-email-quic_msarkar@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: xnMg34H0l242FmngQuC8yBgndgL6IOIM X-Proofpoint-ORIG-GUID: xnMg34H0l242FmngQuC8yBgndgL6IOIM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-30_13,2023-10-31_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 impostorscore=0 spamscore=0 suspectscore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 mlxlogscore=967 mlxscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2310240000 definitions=main-2310310039 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Mon, 30 Oct 2023 22:12:38 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781246631210380152 X-GMAIL-MSGID: 1781246631210380152 Add devicetree bindings support for SA8775P SoC. It has DMA register space and dma interrupt to support HDMA. Signed-off-by: Mrinmay Sarkar Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/pci/qcom,pcie-ep.yaml | 64 +++++++++++++++++++++- 1 file changed, 62 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml index a223ce0..46802f7 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml @@ -13,6 +13,7 @@ properties: compatible: oneOf: - enum: + - qcom,sa8775p-pcie-ep - qcom,sdx55-pcie-ep - qcom,sm8450-pcie-ep - items: @@ -20,6 +21,7 @@ properties: - const: qcom,sdx55-pcie-ep reg: + minItems: 6 items: - description: Qualcomm-specific PARF configuration registers - description: DesignWare PCIe registers @@ -27,8 +29,10 @@ properties: - description: Address Translation Unit (ATU) registers - description: Memory region used to map remote RC address space - description: BAR memory region + - description: DMA register space reg-names: + minItems: 6 items: - const: parf - const: dbi @@ -36,13 +40,14 @@ properties: - const: atu - const: addr_space - const: mmio + - const: dma clocks: - minItems: 7 + minItems: 5 maxItems: 8 clock-names: - minItems: 7 + minItems: 5 maxItems: 8 qcom,perst-regs: @@ -57,14 +62,18 @@ properties: - description: Perst separation enable offset interrupts: + minItems: 2 items: - description: PCIe Global interrupt - description: PCIe Doorbell interrupt + - description: DMA interrupt interrupt-names: + minItems: 2 items: - const: global - const: doorbell + - const: dma reset-gpios: description: GPIO used as PERST# input signal @@ -125,6 +134,10 @@ allOf: - qcom,sdx55-pcie-ep then: properties: + reg: + maxItems: 6 + reg-names: + maxItems: 6 clocks: items: - description: PCIe Auxiliary clock @@ -143,6 +156,10 @@ allOf: - const: slave_q2a - const: sleep - const: ref + interrupts: + maxItems: 2 + interrupt-names: + maxItems: 2 - if: properties: @@ -152,6 +169,10 @@ allOf: - qcom,sm8450-pcie-ep then: properties: + reg: + maxItems: 6 + reg-names: + maxItems: 6 clocks: items: - description: PCIe Auxiliary clock @@ -172,6 +193,45 @@ allOf: - const: ref - const: ddrss_sf_tbu - const: aggre_noc_axi + interrupts: + maxItems: 2 + interrupt-names: + maxItems: 2 + + - if: + properties: + compatible: + contains: + enum: + - qcom,sa8775p-pcie-ep + then: + properties: + reg: + minItems: 7 + maxItems: 7 + reg-names: + minItems: 7 + maxItems: 7 + clocks: + items: + - description: PCIe Auxiliary clock + - description: PCIe CFG AHB clock + - description: PCIe Master AXI clock + - description: PCIe Slave AXI clock + - description: PCIe Slave Q2A AXI clock + clock-names: + items: + - const: aux + - const: cfg + - const: bus_master + - const: bus_slave + - const: slave_q2a + interrupts: + minItems: 3 + maxItems: 3 + interrupt-names: + minItems: 3 + maxItems: 3 unevaluatedProperties: false From patchwork Tue Oct 31 05:11:46 2023 Content-Type: text/plain; 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Tue, 31 Oct 2023 05:12:00 +0000 Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 39V5BvhU010024; Tue, 31 Oct 2023 05:11:57 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 3u0ucktx9f-1; Tue, 31 Oct 2023 05:11:57 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 39V5BvkF010016; Tue, 31 Oct 2023 05:11:57 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-msarkar-hyd.qualcomm.com [10.213.111.194]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 39V5Bue9010012; Tue, 31 Oct 2023 05:11:57 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3891782) id 3A603450D; Tue, 31 Oct 2023 10:41:56 +0530 (+0530) From: Mrinmay Sarkar To: agross@kernel.org, andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, konrad.dybcio@linaro.org, mani@kernel.org Cc: quic_shazhuss@quicinc.com, quic_nitegupt@quicinc.com, quic_ramkri@quicinc.com, quic_nayiluri@quicinc.com, dmitry.baryshkov@linaro.org, robh@kernel.org, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com, quic_parass@quicinc.com, quic_schintav@quicinc.com, quic_shijose@quicinc.com, Mrinmay Sarkar , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Bjorn Helgaas , Kishon Vijay Abraham I , linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mhi@lists.linux.dev Subject: [PATCH v6 2/4] PCI: qcom-ep: Add support for SA8775P SOC Date: Tue, 31 Oct 2023 10:41:46 +0530 Message-Id: <1698729108-27356-3-git-send-email-quic_msarkar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1698729108-27356-1-git-send-email-quic_msarkar@quicinc.com> References: <1698729108-27356-1-git-send-email-quic_msarkar@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: axQ4gRnFOkxn54ZLfVVEgFvf21v2ADCr X-Proofpoint-GUID: axQ4gRnFOkxn54ZLfVVEgFvf21v2ADCr X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-30_13,2023-10-31_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 adultscore=0 mlxlogscore=984 bulkscore=0 mlxscore=0 phishscore=0 impostorscore=0 spamscore=0 malwarescore=0 clxscore=1015 suspectscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2310240000 definitions=main-2310310039 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Mon, 30 Oct 2023 22:12:36 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781246627497116828 X-GMAIL-MSGID: 1781246627497116828 Add support for SA8775P SoC to the Qualcomm PCIe Endpoint Controller driver. Adding new compatible string as it has different set of clocks compare to other SOCs. Signed-off-by: Mrinmay Sarkar Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 9e58f05..3a53d97 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -875,6 +875,7 @@ static void qcom_pcie_ep_remove(struct platform_device *pdev) } static const struct of_device_id qcom_pcie_ep_match[] = { + { .compatible = "qcom,sa8775p-pcie-ep", }, { .compatible = "qcom,sdx55-pcie-ep", }, { .compatible = "qcom,sm8450-pcie-ep", }, { } From patchwork Tue Oct 31 05:11:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mrinmay Sarkar X-Patchwork-Id: 159955 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b90f:0:b0:403:3b70:6f57 with SMTP id t15csp21006vqg; Mon, 30 Oct 2023 22:12:57 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFDkEbaHJe+fjiU1DsRz/JBBU6IBe/ih5zHEFT1LjRiZyqpgtSb/F2IC1gdVDSpIpEw+vO2 X-Received: by 2002:a05:6a00:1881:b0:68a:6d34:474b with SMTP id x1-20020a056a00188100b0068a6d34474bmr2676814pfh.15.1698729177407; Mon, 30 Oct 2023 22:12:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698729177; cv=none; d=google.com; s=arc-20160816; b=bkAGuhoAipEodZhnhNU6JuTn+yW/QsoH7Q9CAW8GqA4sBSDqbLuXuewm+6JHxRYq+n oxY1Zz9oBaK0vjbL5b/GGSi8Ft7+388i8GROtAXjJoMleuUmKjt+JhuHcT1CjNW6MT8X i1paTzyVeZ5lC3/qdwrIANnMqAybSSSE8A/ur0DVkt3OTU6sPGGppb0N9GTtivYvkjZu 8yn6mBcDSaWkq3sElLRjPm5GYyJkNvVUZmXmAwZDiyE3sdcPNEbM7wBtbC4XGBWVF94F OPTiSXse3IT3kTSao0e+lnM40PwiDYnKhtJSU4maqFo4SdI4h73akcOZDLflBRGGIxDB 95Rw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=YZxv9NCfA0KoehyT/p5DCELEr7QA33wTbAEWtL2k5fo=; fh=lBmHJ3Y4lTFTz8EdZvdYgZDSva4naO2W/ycnjVOB2p0=; b=T+NKufSIuAIqwBswTjQ+uOohYlR19IEvoILtcd8CAXHLhqnE9MZvu/AtncAU7rSGsP sMZGBBNZTs777mHxzYivkyB8Msi/dfHaVwN9bvExvvAlvT6fdwyFvRSVpVTXv5cl6QtB OhVkKCk3scn4U7AZq8eXTpw5ymlDT5uu5jhLTk/PjFa49XQNNZkYNahjgiRnrNRNct1q P67SEAiD2gtY6Cq96E7te0e2tvXDF9BUZeYrqJfQVnkbpIK0WVB3asVD4xtL/mvZd4Ht iqkbbtytXUoanFz8LNTBakJQWMXob5LseMU44tXSKM05oWlGjqYPdtl6+5KpJVvk/FYE 5FOQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=TKCOKNPx; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from pete.vger.email (pete.vger.email. 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Tue, 31 Oct 2023 05:12:04 +0000 Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 39V5Bv2j010023; Tue, 31 Oct 2023 05:12:01 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 3u0ucktx9y-1; Tue, 31 Oct 2023 05:12:01 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 39V5C1aF010043; Tue, 31 Oct 2023 05:12:01 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-msarkar-hyd.qualcomm.com [10.213.111.194]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 39V5C1bn010041; Tue, 31 Oct 2023 05:12:01 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3891782) id 65465450D; Tue, 31 Oct 2023 10:42:00 +0530 (+0530) From: Mrinmay Sarkar To: agross@kernel.org, andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, konrad.dybcio@linaro.org, mani@kernel.org Cc: quic_shazhuss@quicinc.com, quic_nitegupt@quicinc.com, quic_ramkri@quicinc.com, quic_nayiluri@quicinc.com, dmitry.baryshkov@linaro.org, robh@kernel.org, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com, quic_parass@quicinc.com, quic_schintav@quicinc.com, quic_shijose@quicinc.com, Mrinmay Sarkar , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Bjorn Helgaas , Kishon Vijay Abraham I , linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mhi@lists.linux.dev Subject: [PATCH v6 3/4] PCI: epf-mhi: Add support for SA8775P Date: Tue, 31 Oct 2023 10:41:47 +0530 Message-Id: <1698729108-27356-4-git-send-email-quic_msarkar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1698729108-27356-1-git-send-email-quic_msarkar@quicinc.com> References: <1698729108-27356-1-git-send-email-quic_msarkar@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Q1xJZGI9LKMsFjbK0Z3yIwoKzBW03tU6 X-Proofpoint-ORIG-GUID: Q1xJZGI9LKMsFjbK0Z3yIwoKzBW03tU6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-30_13,2023-10-31_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 phishscore=0 impostorscore=0 spamscore=0 suspectscore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 mlxlogscore=653 mlxscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2310240000 definitions=main-2310310039 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Mon, 30 Oct 2023 22:12:51 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781246646099809898 X-GMAIL-MSGID: 1781246646099809898 Add support for Qualcomm Snapdragon SA8775P SoC to the EPF driver. Reusing DID (0x0306) for SA8775P and it supports HDMA. Currently, it has no fixed PCI class, so it is being advertised as "PCI_CLASS_OTHERS". Signed-off-by: Mrinmay Sarkar Reviewed-by: Manivannan Sadhasivam --- drivers/pci/endpoint/functions/pci-epf-mhi.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/drivers/pci/endpoint/functions/pci-epf-mhi.c b/drivers/pci/endpoint/functions/pci-epf-mhi.c index b7b9d3e..23ea94e 100644 --- a/drivers/pci/endpoint/functions/pci-epf-mhi.c +++ b/drivers/pci/endpoint/functions/pci-epf-mhi.c @@ -114,6 +114,22 @@ static const struct pci_epf_mhi_ep_info sm8450_info = { .flags = MHI_EPF_USE_DMA, }; +static struct pci_epf_header sa8775p_header = { + .vendorid = PCI_VENDOR_ID_QCOM, + .deviceid = 0x0306, /* FIXME: Update deviceid for sa8775p EP */ + .baseclass_code = PCI_CLASS_OTHERS, + .interrupt_pin = PCI_INTERRUPT_INTA, +}; + +static const struct pci_epf_mhi_ep_info sa8775p_info = { + .config = &mhi_v1_config, + .epf_header = &sa8775p_header, + .bar_num = BAR_0, + .epf_flags = PCI_BASE_ADDRESS_MEM_TYPE_32, + .msi_count = 32, + .mru = 0x8000, +}; + struct pci_epf_mhi { const struct pci_epc_features *epc_features; const struct pci_epf_mhi_ep_info *info; @@ -677,6 +693,7 @@ static int pci_epf_mhi_probe(struct pci_epf *epf, } static const struct pci_epf_device_id pci_epf_mhi_ids[] = { + { .name = "sa8775p", .driver_data = (kernel_ulong_t)&sa8775p_info }, { .name = "sdx55", .driver_data = (kernel_ulong_t)&sdx55_info }, { .name = "sm8450", .driver_data = (kernel_ulong_t)&sm8450_info }, {}, From patchwork Tue Oct 31 05:11:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mrinmay Sarkar X-Patchwork-Id: 159954 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:b90f:0:b0:403:3b70:6f57 with SMTP id t15csp20964vqg; Mon, 30 Oct 2023 22:12:51 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFssoEgCI0sfwuHGwFO4CWQYkLGFWKsXjHNojWKyGmHxgSZaIUxC5n8C1DiIbmaDTUQuEct X-Received: by 2002:a05:6a00:1a4a:b0:68a:582b:6b62 with SMTP id h10-20020a056a001a4a00b0068a582b6b62mr2147272pfv.7.1698729171516; Mon, 30 Oct 2023 22:12:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698729171; cv=none; d=google.com; s=arc-20160816; b=rhk7eBcDnachkqfbFmguyq5ppTMl7POyvjo75sJFVhilyH1jIUazX3nkSH5lQcL+dC yfd8MosWk4EBDQC/iK90X6I5N78Z1iclJoNZDvRH2954Uy4FFnCYFnTAsu6lODrfRQ7V 5w9NJMM2oC7E31V9S37xDxQoB7kt2pUUE4JYy31sdRct0DKc/WvgPlV90CrOFoIspDyi qvEGK0v0m+eHtj1UFtDC3QY0ff7NWOh95N5jZN+lDMmTl2HH8PYOT0YVf4scemclGQ3s Wx8R31H4aWrRZXyEKWQrncnWIV5WIXKqHnkZE6RUt1CWt3wx9uG1ud6FZcoESJHBcgj2 5K0Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:references:in-reply-to:message-id:date:subject :cc:to:from:dkim-signature; bh=RsQx3p3Jdt45deKD8q2naBRmwFH/7pLMEOjfr52W8xs=; fh=yFr7qhcdQvImWR8Zc0n9HlheDCAdICrmTTRHFLnxeio=; b=ABN+xBWSWVByjG0ddJMI+UKp9REGT1uKxi85QlVxod/o7PskpqEnVJx8lxGN3mFXZv FRSd0Kd0TzeWz6IiJ07fQRry6w3rmONiu/GP6Kxo4sECqiNrGiFIhRnJVM4+N3urMz17 VMDRv4Ozc0D5KmzwNEkf0kTExax00BxSf3JGh9+TZHR4j53rp4gYqxfLsSeifpvni7X5 tjaGtwwLVS/sO4faOKcAnuB0cUlso3Glt5L8jxgFM7ER7TVf6lVg9obiPpGud33IOuMR 1Cs5epowivfS4BjrY/R9B/wiNd+YZu6ZKU9AI+1fElPXASJ23UgXvdiO2160wu35NRZy LVlQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=eMtccMgJ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from lipwig.vger.email (lipwig.vger.email. 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Tue, 31 Oct 2023 05:12:07 +0000 Received: from pps.filterd (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTP id 39V5C3p3010087; Tue, 31 Oct 2023 05:12:04 GMT Received: from pps.reinject (localhost [127.0.0.1]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 3u0ucktxaj-1; Tue, 31 Oct 2023 05:12:03 +0000 Received: from APBLRPPMTA02.qualcomm.com (APBLRPPMTA02.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 39V5C3Ne010081; Tue, 31 Oct 2023 05:12:03 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-msarkar-hyd.qualcomm.com [10.213.111.194]) by APBLRPPMTA02.qualcomm.com (PPS) with ESMTP id 39V5C3mJ010079; Tue, 31 Oct 2023 05:12:03 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3891782) id F237C450D; Tue, 31 Oct 2023 10:42:01 +0530 (+0530) From: Mrinmay Sarkar To: agross@kernel.org, andersson@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, konrad.dybcio@linaro.org, mani@kernel.org Cc: quic_shazhuss@quicinc.com, quic_nitegupt@quicinc.com, quic_ramkri@quicinc.com, quic_nayiluri@quicinc.com, dmitry.baryshkov@linaro.org, robh@kernel.org, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com, quic_parass@quicinc.com, quic_schintav@quicinc.com, quic_shijose@quicinc.com, Mrinmay Sarkar , Bjorn Helgaas , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Kishon Vijay Abraham I , linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mhi@lists.linux.dev Subject: [PATCH v6 4/4] arm64: dts: qcom: sa8775p: Add ep pcie0 controller node Date: Tue, 31 Oct 2023 10:41:48 +0530 Message-Id: <1698729108-27356-5-git-send-email-quic_msarkar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1698729108-27356-1-git-send-email-quic_msarkar@quicinc.com> References: <1698729108-27356-1-git-send-email-quic_msarkar@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: nJT0Zd_xpoxTGLx4nMS-Vzwk7I6Pjsrc X-Proofpoint-GUID: nJT0Zd_xpoxTGLx4nMS-Vzwk7I6Pjsrc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-30_13,2023-10-31_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 phishscore=0 mlxlogscore=999 adultscore=0 mlxscore=0 malwarescore=0 lowpriorityscore=0 impostorscore=0 priorityscore=1501 spamscore=0 suspectscore=0 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2310240000 definitions=main-2310310039 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Mon, 30 Oct 2023 22:12:46 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781246640003601366 X-GMAIL-MSGID: 1781246640003601366 Add ep pcie dtsi node for pcie0 controller found on sa8775p platform. It supports gen4 and x2 link width. Limiting the speed to Gen3 due to stability issues. Signed-off-by: Mrinmay Sarkar Reviewed-by: Manivannan Sadhasivam --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 46 +++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 13dd44d..7eab458 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -3586,6 +3586,52 @@ status = "disabled"; }; + pcie0_ep: pcie-ep@1c00000 { + compatible = "qcom,sa8775p-pcie-ep"; + reg = <0x0 0x01c00000 0x0 0x3000>, + <0x0 0x40000000 0x0 0xf20>, + <0x0 0x40000f20 0x0 0xa8>, + <0x0 0x40001000 0x0 0x4000>, + <0x0 0x40200000 0x0 0x100000>, + <0x0 0x01c03000 0x0 0x1000>, + <0x0 0x40005000 0x0 0x2000>; + reg-names = "parf", "dbi", "elbi", "atu", "addr_space", + "mmio", "dma"; + + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, + <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_AXI_CLK>, + <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>; + + clock-names = "aux", + "cfg", + "bus_master", + "bus_slave", + "slave_q2a"; + + interrupts = , + , + ; + + interrupt-names = "global", "doorbell", "dma"; + + interconnects = <&pcie_anoc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_PCIE_0 0>; + interconnect-names = "pcie-mem", "cpu-pcie"; + + iommus = <&pcie_smmu 0x0000 0x7f>; + resets = <&gcc GCC_PCIE_0_BCR>; + reset-names = "core"; + power-domains = <&gcc PCIE_0_GDSC>; + phys = <&pcie0_phy>; + phy-names = "pciephy"; + max-link-speed = <3>; /* FIXME: Limiting the Gen speed due to stability issues */ + num-lanes = <2>; + + status = "disabled"; + }; + pcie0_phy: phy@1c04000 { compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy"; reg = <0x0 0x1c04000 0x0 0x2000>;