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[8.43.85.97]) by mx.google.com with ESMTPS id l9-20020a05622a050900b004198ce7ce69si364784qtx.534.2023.10.30.20.40.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Oct 2023 20:40:16 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 52CC43858C00 for ; Tue, 31 Oct 2023 03:40:16 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgau1.qq.com (smtpbgau1.qq.com [54.206.16.166]) by sourceware.org (Postfix) with ESMTPS id 7DB9E3858D1E for ; Tue, 31 Oct 2023 03:39:51 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7DB9E3858D1E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 7DB9E3858D1E Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=54.206.16.166 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698723594; cv=none; b=aGkFtQ1CghxXi2ZAkA67I4rwncZ1Wh8zoAHaXmYyPqBJFcgjXcNa2ZOwEr82tg5OdwDeD84Ra5+ejRMkCuBmJON1qi5gYmx8M5CCkXVYLHux6gzWy071csYksJIWkQWJq/uF87L9PMMJs9EKt8j9t3jnHAwP0/SjyroZ25P5VO0= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698723594; c=relaxed/simple; bh=kIlTeOhsEvIHToB4rX9IQjpfFAVNcWuRhCfoGIPb6TA=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=sF+Zo/1OX6v3B7u96iXU5jz9JMNvYH9v33rCf/0UGNT41fMBtA/jfsrEyM+zRLuKO3JEtSYz9eOht1UxF2wbmrY1eftNvw//lDKzzwAOF2TvGoi1sEYEpp896vRoVwpzSgc0tCowos3Q5IhQqWehjFUW1+UuMyT9oB58hCDDsK8= ARC-Authentication-Results: i=1; server2.sourceware.org X-QQ-mid: bizesmtp83t1698723585teh8mxmg Received: from rios-cad122.hadoop.rioslab.org ( [58.60.1.26]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 31 Oct 2023 11:39:44 +0800 (CST) X-QQ-SSF: 01400000000000C0F000000A0000000 X-QQ-FEAT: C46Rb8GPIEfbjvwUujmc5+2wyHXzvyPaHl70EaMcNbz8Om5cvy27XoVnxjuKF 3VcVpqn+2668RFfU1lD3F8BwNC+gseBtwF6waiHoRp5Q/xfZ7jzVC3MOjGgGogNMbkzDpda /G11xVqGOsa1MfaM8Lg6KOXn73U0HPybCs7LZ3S7qRbF4uNNXBpm7ggswic5LpPYMDspy2h VNcfO3PJ3GalKF+Pjncg+lebbArAf3Naj/gMxUJelrKdII91+CVaAbwZ++7GM4wNV+fUFUn A7mP6dYgKv/86q4UEuq7wxakBOeeVbnoBOgc1vK6uGacEFWbt/Oa2EsHoYRH9ypqbc9EaGN 8Wq/KYNYnSBZzbzsQIHpesUWDtA1dLcoU0EwHWzIYmQayKVESBzTbSbYrovGg== X-QQ-GoodBg: 2 X-BIZMAIL-ID: 13946869491345288866 From: Lehua Ding To: gcc-patches@gcc.gnu.org Cc: juzhe.zhong@rivai.ai, kito.cheng@gmail.com, rdapp.gcc@gmail.com, palmer@rivosinc.com, jeffreyalaw@gmail.com, lehua.ding@rivai.ai Subject: [PATCH] RISC-V: Add the missed combine of [u]int64 -> _Float16 and vcond Date: Tue, 31 Oct 2023 11:39:43 +0800 Message-Id: <20231031033943.3550543-1-lehua.ding@rivai.ai> X-Mailer: git-send-email 2.36.3 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvrgz:qybglogicsvrgz6a-0 X-Spam-Status: No, score=-9.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781240815152455351 X-GMAIL-MSGID: 1781240815152455351 Hi, This patch let the INT64 to FP16 convert split to two small converts (INT64 -> FP32 and FP32 -> FP16) when expanding instead of dealy the split to split1 pass. This change could make it possible to combine the FP32 to FP16 and vcond patterns and so we don't need to add an combine pattern for INT64 to FP16 and vcond patterns. Consider this code: void foo (_Float16 *__restrict r, int64_t *__restrict a, _FLoat16 *__restrict b, int64_t *__restrict pred, int n) { for (int i = 0; i < n; i += 1) { r[i] = pred[i] ? (_Float16) a[i] : b[i]; } } Before this patch: ... vfncvt.f.f.w v2,v2 vmerge.vvm v1,v1,v2,v0 vse16.v v1,0(a0) ... After this patch: ... vfncvt.f.f.w v1,v2,v0.t vse16.v v1,0(a0) ... gcc/ChangeLog: * config/riscv/autovec.md (2): Change to define_expand. gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c: Add vfncvt.f.f.w assert. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c: Ditto. * gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c: Ditto. --- gcc/config/riscv/autovec.md | 5 +---- .../riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c | 2 ++ .../riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c | 2 ++ .../riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c | 2 ++ .../riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c | 2 ++ 5 files changed, 9 insertions(+), 4 deletions(-) diff --git a/gcc/config/riscv/autovec.md b/gcc/config/riscv/autovec.md index 5f49d73be44..bfd45dd76ff 100644 --- a/gcc/config/riscv/autovec.md +++ b/gcc/config/riscv/autovec.md @@ -977,14 +977,11 @@ ;; This operation can be performed in the loop vectorizer but unfortunately ;; not applicable for now. We can remove this pattern after loop vectorizer ;; is able to take care of INT64 to FP16 conversion. -(define_insn_and_split "2" +(define_expand "2" [(set (match_operand: 0 "register_operand") (any_float: (match_operand:VWWCONVERTI 1 "register_operand")))] "TARGET_VECTOR && TARGET_ZVFH && can_create_pseudo_p () && !flag_trapping_math" - "#" - "&& 1" - [(const_int 0)] { rtx single = gen_reg_rtx (mode); /* Get vector SF mode. */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c index f5d3bb4c789..030c8fe33ce 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-1.c @@ -12,4 +12,6 @@ /* { dg-final { scan-assembler-times {\tvfncvt\.f\.xu\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ /* { dg-final { scan-assembler-times {\tvfncvt\.f\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.f\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ + /* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c index f5d3bb4c789..030c8fe33ce 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv32-2.c @@ -12,4 +12,6 @@ /* { dg-final { scan-assembler-times {\tvfncvt\.f\.xu\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ /* { dg-final { scan-assembler-times {\tvfncvt\.f\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.f\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ + /* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c index 5ebed2f7fdc..d6298f5351a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-1.c @@ -12,4 +12,6 @@ /* { dg-final { scan-assembler-times {\tvfncvt\.f\.xu\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ /* { dg-final { scan-assembler-times {\tvfncvt\.f\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.f\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ + /* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c index 097e377f107..23ad5f2b579 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/cond/cond_convert_int2float-rv64-2.c @@ -12,4 +12,6 @@ /* { dg-final { scan-assembler-times {\tvfncvt\.f\.xu\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ /* { dg-final { scan-assembler-times {\tvfncvt\.f\.x\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ +/* { dg-final { scan-assembler-times {\tvfncvt\.f\.f\.w\tv[0-9]+,v[0-9]+,v0\.t} 2 } } */ + /* { dg-final { scan-assembler {\tvsetvli\t[a-z0-9]+,[a-z0-9]+,e[0-9]+,m[f0-9]+,t[au],mu} } } */