From patchwork Mon Oct 30 21:31:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elliot Berman X-Patchwork-Id: 159879 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp2517231vqb; Mon, 30 Oct 2023 14:32:52 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGqpO32YtkB7crnUxAT2Wbkbf5zIPXXrzdUsDNsaVMTbsFGx3ZxADhIoDuMex5KSj0cddRz X-Received: by 2002:a05:6a00:98f:b0:6be:3c44:c18b with SMTP id u15-20020a056a00098f00b006be3c44c18bmr10202082pfg.25.1698701572281; Mon, 30 Oct 2023 14:32:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698701572; cv=none; d=google.com; s=arc-20160816; b=cQp9IiOewQtnLsWdYRscgvLgBgaY7DG1z+5gAdoNOyPURUDj4lwMtjfwMBKtqHfPNd nDsxom7BuXJW8PT1p+R8gIevhUjtAsEP/OvQZ3vxTK+W4J2HoEbhkuycEJqriReccznz Dg8i2bOL1Kvc7JgitJZPSMqrTevsca91A/2/VrZscX7o6z4GGikbxGiWICQAnUluQofn h8VFFgZfcWYSxvnYm/fGIT35zseP3Mxe+bJgfhbBFNHUHbL4M2feLyB5W9OzuJqmuxdm 53sZ4y5v9wbS9+SvZKILuGZhwkZLe373sRz1ECM+mu/I9Rph+FEvRdxuo9KZ9YPN7iJm eGlw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=XVmHylPLC71quZBcFwO83oe5ZnMrVX7JUjoNKkPYCNU=; fh=hSqztiRBLPxJl4bBUOWDgSdeKGW5GNzk3N7GGirJHIY=; b=Pcnisn1PJSBzpFayWUPVwsuAQrF+JuU0tPRn88TsOjA2lJwRpwxfIr4pc3SLWeKxMp s+uffUEmIDzmopSdOCxsXGhKbS80caBBGLPFfJgMvvV+zCjQfSex7DCr7c3ATIg5iZAm XWZhcvBm1+rWI2njNtLPlfWiOFeWJZRhO9CkEDMWyjwTetkNv2vsIJac3wG9ktbF861j LzZgNgB43mFnJ4NRNN8FQpLNCoNDNb5T+NvK2dwmfTL8yZLATgHSpAaMCoqC8zzOqW80 QQbyepZw8HCMNS8Wuwd0oNCDRQwo7A1PE7tSXkd4mUPIoiJZH4CJeHX82Si0nz+wDbIR I3dw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=S1mqshgY; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from lipwig.vger.email (lipwig.vger.email. [2620:137:e000::3:3]) by mx.google.com with ESMTPS id s7-20020a056a00178700b006b7d62ed178si5506717pfg.5.2023.10.30.14.32.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Oct 2023 14:32:52 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) client-ip=2620:137:e000::3:3; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=S1mqshgY; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id BB6318047D65; Mon, 30 Oct 2023 14:32:49 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232022AbjJ3Vc1 (ORCPT + 32 others); Mon, 30 Oct 2023 17:32:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44950 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231985AbjJ3VcV (ORCPT ); Mon, 30 Oct 2023 17:32:21 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5C7F911A; Mon, 30 Oct 2023 14:32:12 -0700 (PDT) Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 39UKrCE5004694; Mon, 30 Oct 2023 21:31:56 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : date : subject : mime-version : content-type : content-transfer-encoding : message-id : references : in-reply-to : to : cc; s=qcppdkim1; bh=XVmHylPLC71quZBcFwO83oe5ZnMrVX7JUjoNKkPYCNU=; b=S1mqshgYFz2C+r+D9yy9TooMsDjbI9iwBwdHQgnDmHTitZTQo5gfUmD+7ApEauDruPt9 zwynO6RMfebiYBdCoTs9ogvd11LweZPLslrVs8e0mAGHxYf/j0cwC04Nam8RqFTr2F4s DbCMd+e6+jmqoMOKvhUde0XO7AYEooSC7Y/9Xq8q1vwZdXIXKqgJPExR+EWfWZoMkDgl WYLcOsXR+PtORCG893OnCRgLYXmGt1abJLZ/9BSrqLkUhHpWpY5yyYKOKGYR/kZFERli RMzTSmS7osd9ohNNZYVO34PkfvegJ99H2o+V4FSatn8B22O8RFygna2CY5/gygdXV8C7 KQ== Received: from nasanppmta04.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3u2c4rs9ef-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 30 Oct 2023 21:31:56 +0000 Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 39ULVtdd021818 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 30 Oct 2023 21:31:55 GMT Received: from hu-eberman-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Mon, 30 Oct 2023 14:31:55 -0700 From: Elliot Berman Date: Mon, 30 Oct 2023 14:31:33 -0700 Subject: [PATCH RFC 1/2] dt-bindings: arm: Document reboot mode magic MIME-Version: 1.0 Message-ID: <20231030-arm-psci-system_reset2-vendor-reboots-v1-1-dcdd63352ad1@quicinc.com> References: <20231030-arm-psci-system_reset2-vendor-reboots-v1-0-dcdd63352ad1@quicinc.com> In-Reply-To: <20231030-arm-psci-system_reset2-vendor-reboots-v1-0-dcdd63352ad1@quicinc.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , Mark Rutland CC: Satya Durga Srinivasu Prabhala , Melody Olvera , , , , Florian Fainelli , Elliot Berman X-Mailer: b4 0.13-dev X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: TC6wt5PFYEhWzV6GB5g3yj8in9UvKaWc X-Proofpoint-GUID: TC6wt5PFYEhWzV6GB5g3yj8in9UvKaWc X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-30_13,2023-10-27_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1011 bulkscore=0 phishscore=0 adultscore=0 spamscore=0 priorityscore=1501 mlxlogscore=952 malwarescore=0 mlxscore=0 suspectscore=0 impostorscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2310240000 definitions=main-2310300168 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Mon, 30 Oct 2023 14:32:49 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781217700142019353 X-GMAIL-MSGID: 1781217700142019353 Add bindings to describe vendor-specific reboot modes. Values here correspond to valid parameters to vendor-specific reset types in PSCI SYSTEM_RESET2 call. Signed-off-by: Elliot Berman --- Documentation/devicetree/bindings/arm/psci.yaml | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/psci.yaml b/Documentation/devicetree/bindings/arm/psci.yaml index 0c5381e081bd..dc23e901bd0a 100644 --- a/Documentation/devicetree/bindings/arm/psci.yaml +++ b/Documentation/devicetree/bindings/arm/psci.yaml @@ -122,6 +122,19 @@ patternProperties: [3] Documentation/devicetree/bindings/power/power-domain.yaml [4] Documentation/devicetree/bindings/power/domain-idle-state.yaml + "^reboot-mode-.*$": + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 2 + description: | + Describes a vendor-specific reset type. The string after "reboot-mode-" + maps a reboot mode to the parameters in the PSCI SYSTEM_RESET2 call. + + Parameters are named reboot-mode-xxx = , where xxx + is the name of the magic reboot mode, type is the lower 31 bits + of the reset_type, and, optionally, the cookie value. If the cookie + is not provided, it is defaulted to zero. + required: - compatible - method From patchwork Mon Oct 30 21:31:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elliot Berman X-Patchwork-Id: 159880 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp2517257vqb; Mon, 30 Oct 2023 14:32:56 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH4XPIvaZSlc42tcQLddUW41IKF+QMMiWCjGikjEuhtF7UDFKcYnG95ezerjM/dieNXMgg+ X-Received: by 2002:a05:6a20:7da4:b0:154:4246:d63b with SMTP id v36-20020a056a207da400b001544246d63bmr10830008pzj.25.1698701575732; Mon, 30 Oct 2023 14:32:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698701575; cv=none; d=google.com; s=arc-20160816; b=s1ZnYh/ZwRFUBmjQ4CQ9gcu/eS7YitpgTP184FKsjw4zWSehyffNWAx45pJ+i3ei/o A3JJcmVr7Ol32HVySbJPZCsBTbCfPDAalh/Tyy0YymN32zWFBXW48kt0sCuzP0kc0SPz Ma1wVOKoSUx2022i8nUsBO4UpOUBKVvdcxmvMwXNj5eBTZVUrbCtigEOlp1711g4ms9G oTv6SQBMH+1I24CINEZpOx+fN33ZbWOKSzo9hn9ekWh8LEWGASaxmH0T210ZZSsPyKe5 HPGBvaP2/sumzjyB515kWsjHZ4jJP8KO+IFDZ/mB5txJEIlFxC0IVBkBaTQgGkmRDaMp 4UTg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=JLBYQvouHm+ivITtAnS//CALxj6F/tmmVd/NsTeTqyE=; fh=hSqztiRBLPxJl4bBUOWDgSdeKGW5GNzk3N7GGirJHIY=; b=CrbqLUN408mEJ4e/mJ40e0ZIwWrRGtpJxQLeLdH2xBKUvp1xQy9IMULzN42SMwNJOI M2r5qKcjUjQNtOT/BrMUjpT3mthCGoxd99bZf+WMGFP2VIRi2Oyshc1ljGiFUWeMnLXa 9pMJAKwwMRVKoUqqm7uy4seYmgNnnUyntsf6KS+Ywf+6Huqa0VsQ+/stq/7/bGp+QWZC 0JSSdz3RWwzbSRQhAWujoowEg3XaIsfgdTV4b7yY13avRuGfZUiPDlzAc4QLxBes2udc N62u/06NICwLG7jY9aeV7HqNxbS8TFgVtIHCCfwr8Q1nLY/nc9uj37t8n8F5xZ/CrlJl O1/g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=mVQM5zRR; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from groat.vger.email (groat.vger.email. [2620:137:e000::3:5]) by mx.google.com with ESMTPS id h5-20020a056a001a4500b006be25c80c8fsi5525323pfv.267.2023.10.30.14.32.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Oct 2023 14:32:55 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) client-ip=2620:137:e000::3:5; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=mVQM5zRR; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by groat.vger.email (Postfix) with ESMTP id 42C3280A2223; Mon, 30 Oct 2023 14:32:53 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at groat.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231995AbjJ3VcY (ORCPT + 32 others); Mon, 30 Oct 2023 17:32:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44954 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231928AbjJ3VcW (ORCPT ); Mon, 30 Oct 2023 17:32:22 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 79CD611B; Mon, 30 Oct 2023 14:32:12 -0700 (PDT) Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 39ULVuEv016684; Mon, 30 Oct 2023 21:31:56 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : date : subject : mime-version : content-type : content-transfer-encoding : message-id : references : in-reply-to : to : cc; s=qcppdkim1; bh=JLBYQvouHm+ivITtAnS//CALxj6F/tmmVd/NsTeTqyE=; b=mVQM5zRRDwJHiF79Hfq3oWk9idm/OLvnuVYDkVPlTWw6y+PfNvgPgWXm6XsffpYJaOK6 j1XeQb2lu5agLaQkNcbTx0yQTJM3HsfIybqzGDpXcacTdUpbaPoPYsq86y+l8JTuh/Y5 JCeLQE/Vo7cpgVeNo3nf1WdvbrXIGOhyIRLj55S0cL6JWv6dfvQz7EnY57c/SGb4MVFW z9yS3yyX6enaRdoonfI938zpFTtyorkVZKZSVcv5r11x6qYKYfOnxqSJXg14cVVCfPt7 YOdvsBKxbRCuZ5EoIN9IsD1nST2eJt1IEbss98TU9IgwLA+C/TURfqUoeJAcpzgGhCrj Gg== Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3u2chyh7rf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 30 Oct 2023 21:31:56 +0000 Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 39ULVubm011305 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 30 Oct 2023 21:31:56 GMT Received: from hu-eberman-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Mon, 30 Oct 2023 14:31:55 -0700 From: Elliot Berman Date: Mon, 30 Oct 2023 14:31:34 -0700 Subject: [PATCH RFC 2/2] firmware: psci: Read and use vendor reset types MIME-Version: 1.0 Message-ID: <20231030-arm-psci-system_reset2-vendor-reboots-v1-2-dcdd63352ad1@quicinc.com> References: <20231030-arm-psci-system_reset2-vendor-reboots-v1-0-dcdd63352ad1@quicinc.com> In-Reply-To: <20231030-arm-psci-system_reset2-vendor-reboots-v1-0-dcdd63352ad1@quicinc.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Lorenzo Pieralisi , Mark Rutland CC: Satya Durga Srinivasu Prabhala , Melody Olvera , , , , Florian Fainelli , Elliot Berman X-Mailer: b4 0.13-dev X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01b.na.qualcomm.com (10.47.209.197) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: nPoM-AxfQC_BuKVQzcAwanO9tqVyCc2T X-Proofpoint-GUID: nPoM-AxfQC_BuKVQzcAwanO9tqVyCc2T X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-30_13,2023-10-27_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 mlxscore=0 adultscore=0 mlxlogscore=999 spamscore=0 phishscore=0 clxscore=1015 suspectscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2310240000 definitions=main-2310300168 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Mon, 30 Oct 2023 14:32:53 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781217703722437170 X-GMAIL-MSGID: 1781217703722437170 SoC vendors have different types of resets and are controlled through various registers. For instance, Qualcomm chipsets can reboot to a "download mode" that allows a RAM dump to be collected. Another example is they also support writing a cookie that can be read by bootloader during next boot. PSCI offers a mechanism, SYSTEM_RESET2, for these vendor reset types to be implemented without requiring drivers for every register/cookie. Add support in PSCI to statically map reboot mode commands from userspace to a vendor reset and cookie value using the device tree. Reboot mode framework is close but doesn't quite fit with the design and requirements for PSCI SYSTEM_RESET2. Some of these issues can be solved but doesn't seem reasonable in sum: 1. reboot mode registers against the reboot_notifier_list, which is too early to call SYSTEM_RESET2. PSCI would need to remember the reset type from the reboot-mode framework callback and use it psci_sys_reset. 2. reboot mode assumes only one cookie/parameter is described in the device tree. SYSTEM_RESET2 uses 2: one for the type and one for cookie. 3. psci cpuidle driver already registers a driver against the arm,psci-1.0 compatible. Refactoring would be needed to have both a cpuidle and reboot-mode driver. Signed-off-by: Elliot Berman --- drivers/firmware/psci/psci.c | 87 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 86 insertions(+), 1 deletion(-) diff --git a/drivers/firmware/psci/psci.c b/drivers/firmware/psci/psci.c index d9629ff87861..93914b48a950 100644 --- a/drivers/firmware/psci/psci.c +++ b/drivers/firmware/psci/psci.c @@ -29,6 +29,8 @@ #include #include +#define REBOOT_PREFIX "reboot-mode-" + /* * While a 64-bit OS can make calls with SMC32 calling conventions, for some * calls it is necessary to use SMC64 to pass or return 64-bit values. @@ -79,6 +81,14 @@ struct psci_0_1_function_ids get_psci_0_1_function_ids(void) static u32 psci_cpu_suspend_feature; static bool psci_system_reset2_supported; +struct psci_reset_param { + const char *mode; + u32 reset_type; + u32 cookie; +}; +static struct psci_reset_param *psci_reset_params; +static size_t num_psci_reset_params; + static inline bool psci_has_ext_power_state(void) { return psci_cpu_suspend_feature & @@ -305,11 +315,29 @@ static int get_set_conduit_method(const struct device_node *np) return 0; } +static void psci_vendor_sys_reset2(unsigned long action, void *data) +{ + const char *cmd = data; + size_t i; + + for (i = 0; i < num_psci_reset_params; i++) { + if (!strcmp(psci_reset_params[i].mode, cmd)) { + invoke_psci_fn(PSCI_FN_NATIVE(1_1, SYSTEM_RESET2), + psci_reset_params[i].reset_type, + psci_reset_params[i].cookie, 0); + break; + } + } +} + static int psci_sys_reset(struct notifier_block *nb, unsigned long action, void *data) { + if (psci_system_reset2_supported && num_psci_reset_params) + psci_vendor_sys_reset2(action, data); + if ((reboot_mode == REBOOT_WARM || reboot_mode == REBOOT_SOFT) && - psci_system_reset2_supported) { + psci_system_reset2_supported) { /* * reset_type[31] = 0 (architectural) * reset_type[30:0] = 0 (SYSTEM_WARM_RESET) @@ -748,6 +776,63 @@ static const struct of_device_id psci_of_match[] __initconst = { {}, }; +static int __init psci_init_system_reset2_modes(void) +{ + const size_t len = strlen(REBOOT_PREFIX); + struct psci_reset_param *param; + struct device_node *np; + struct property *prop; + size_t count = 0; + u32 magic[2]; + int ret; + + if (!psci_system_reset2_supported) + return 0; + + np = of_find_matching_node(NULL, psci_of_match); + if (!np) + return 0; + + for_each_property_of_node(np, prop) { + if (strncmp(prop->name, REBOOT_PREFIX, len)) + continue; + ret = of_property_count_elems_of_size(np, prop->name, sizeof(magic[0])); + if (ret != 1 && ret != 2) + continue; + + count++; + } + + param = psci_reset_params = kcalloc(count, sizeof(*psci_reset_params), GFP_KERNEL); + if (!psci_reset_params) + return -ENOMEM; + + for_each_property_of_node(np, prop) { + if (strncmp(prop->name, REBOOT_PREFIX, len)) + continue; + + param->mode = kstrdup_const(prop->name + len, GFP_KERNEL); + if (!param->mode) + continue; + + ret = of_property_read_variable_u32_array(np, prop->name, magic, 1, 2); + if (ret < 0) { + pr_warn("Failed to parse vendor reboot mode %s\n", param->mode); + kfree(param->mode); + continue; + } + + /* Force reset type to be in vendor space */ + param->reset_type = PSCI_1_1_RESET_TYPE_VENDOR_START | magic[0]; + param->cookie = ret == 2 ? magic[1] : 0; + param++; + num_psci_reset_params++; + } + + return 0; +} +arch_initcall(psci_init_system_reset2_modes); + int __init psci_dt_init(void) { struct device_node *np;