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Mon, 30 Oct 2023 18:00:25 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 30 Oct 2023 18:00:23 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 30 Oct 2023 18:00:23 +0800 From: Moudy Ho To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Mauro Carvalho Chehab , "Matthias Brugger" , AngeloGioacchino Del Regno , Hans Verkuil CC: , , , , , , "Moudy Ho" Subject: [PATCH v8 01/16] dt-bindings: media: mediatek: mdp3: correct RDMA and WROT node with generic names Date: Mon, 30 Oct 2023 18:00:07 +0800 Message-ID: <20231030100022.9262-2-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231030100022.9262-1-moudy.ho@mediatek.com> References: <20231030100022.9262-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--4.069300-8.000000 X-TMASE-MatchedRID: fqobMUxwriteJRw5hj8/hCZm6wdY+F8KvtVce6w5+K8QHQ+7AkbTsXGp r8/fPJWivQEW+BqnrVrnftxNodBrx8RBLZ5x+SkXH5YQyOg71ZYW40XiUkbrG9zOQo7mTgA+gT4 HLsARG1siA7lT3EYqXMCl/H6TvsoyfyoI97TEvxDdQFsmvD2aF30tCKdnhB589yM15V5aWpj6C0 ePs7A07bPc2SM55IWTEuWIMizKVcgj3xHkfYyBbghfjsft4ylftTANX/L85TsBgnXS2r9efsAvE +5Ll8kwkOhGKBYh93YBIkWfxN2ph2T5Bq5czqY4dmtRsRmKkASJZPT2ZDPuzPD2QfzMDLjhIh26 TkmSN3fAvpLE+mvX8g== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--4.069300-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 8AA03BBF88E85500B2DB7F87D11529387D99DA604E5062EEA756EF876044B37C2000:8 X-MTK: N X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Mon, 30 Oct 2023 03:02:31 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781174277640559428 X-GMAIL-MSGID: 1781174277640559428 The DMA-related nodes RDMA/WROT in MDP3 should be changed to generic names. In addition, fix improper space indent in example. Fixes: 4ad7b39623ab ("media: dt-binding: mediatek: add bindings for MediaTek MDP3 components") Signed-off-by: Moudy Ho Acked-by: Rob Herring Reviewed-by: AngeloGioacchino Del Regno --- .../bindings/media/mediatek,mdp3-rdma.yaml | 29 +++++++++++-------- .../bindings/media/mediatek,mdp3-wrot.yaml | 23 +++++++++------ 2 files changed, 31 insertions(+), 21 deletions(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml index 7032c7e15039..3e128733ef53 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml @@ -61,6 +61,9 @@ properties: - description: used for 1st data pipe from RDMA - description: used for 2nd data pipe from RDMA + '#dma-cells': + const: 1 + required: - compatible - reg @@ -70,6 +73,7 @@ required: - clocks - iommus - mboxes + - '#dma-cells' additionalProperties: false @@ -80,16 +84,17 @@ examples: #include #include - mdp3_rdma0: mdp3-rdma0@14001000 { - compatible = "mediatek,mt8183-mdp3-rdma"; - reg = <0x14001000 0x1000>; - mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>; - mediatek,gce-events = , - ; - power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; - clocks = <&mmsys CLK_MM_MDP_RDMA0>, - <&mmsys CLK_MM_MDP_RSZ1>; - iommus = <&iommu>; - mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>, - <&gce 21 CMDQ_THR_PRIO_LOWEST>; + dma-controller@14001000 { + compatible = "mediatek,mt8183-mdp3-rdma"; + reg = <0x14001000 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>; + mediatek,gce-events = , + ; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_MDP_RDMA0>, + <&mmsys CLK_MM_MDP_RSZ1>; + iommus = <&iommu>; + mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>, + <&gce 21 CMDQ_THR_PRIO_LOWEST>; + #dma-cells = <1>; }; diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml index 0baa77198fa2..64ea98aa0592 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml @@ -50,6 +50,9 @@ properties: iommus: maxItems: 1 + '#dma-cells': + const: 1 + required: - compatible - reg @@ -58,6 +61,7 @@ required: - power-domains - clocks - iommus + - '#dma-cells' additionalProperties: false @@ -68,13 +72,14 @@ examples: #include #include - mdp3_wrot0: mdp3-wrot0@14005000 { - compatible = "mediatek,mt8183-mdp3-wrot"; - reg = <0x14005000 0x1000>; - mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; - mediatek,gce-events = , - ; - power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; - clocks = <&mmsys CLK_MM_MDP_WROT0>; - iommus = <&iommu>; + dma-controller@14005000 { + compatible = "mediatek,mt8183-mdp3-wrot"; + reg = <0x14005000 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; + mediatek,gce-events = , + ; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_MDP_WROT0>; + iommus = <&iommu>; + #dma-cells = <1>; }; From patchwork Mon Oct 30 10:00:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TW91ZHkgSG8gKOS9leWul+WOnyk=?= X-Patchwork-Id: 159632 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp2094570vqb; Mon, 30 Oct 2023 03:03:28 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGWivzZSy6gCFX0UNK7WYpAp6wqamKO+I/OZTqTMxDaJT7CQbw1fb7oM1bIgu7FRUElrx9M X-Received: by 2002:a05:6871:4984:b0:1ea:2e2c:e9e7 with SMTP id tx4-20020a056871498400b001ea2e2ce9e7mr8908241oab.59.1698660208394; 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[23.128.96.37]) by mx.google.com with ESMTPS id v185-20020a6389c2000000b005b8fb1da631si4752495pgd.897.2023.10.30.03.03.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Oct 2023 03:03:28 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=YUGoBe6y; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 152878031E0A; Mon, 30 Oct 2023 03:03:14 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233259AbjJ3KDD (ORCPT + 31 others); Mon, 30 Oct 2023 06:03:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54002 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232940AbjJ3KBD (ORCPT ); Mon, 30 Oct 2023 06:01:03 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D7CF010E7; Mon, 30 Oct 2023 03:00:35 -0700 (PDT) X-UUID: 2518fa28770b11eea33bb35ae8d461a2-20231030 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=/67Rsh2cMjY+iuLSaYmi+i827Jcv2dBO1fcRVc0zxyY=; b=YUGoBe6y4h81A4DbWe7WVW29F8xBTbRb4mMVB0itGkkCNtSb9pTlNKjS9Qr2t7yfT+YtRN15jsNeR/nfJWv1ZI9OF64liVxBEudg9kk9ZBbWbgs1sl8NIquCu7nJyQsA8HcJRrxBZ3JxQlhLvx+R/lVlAugwB0FYP5w+2Eh3esQ=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.32,REQID:841b2658-de72-444d-9b50-eedbe9b9ef07,IP:0,U RL:25,TC:0,Content:-25,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTI ON:release,TS:0 X-CID-META: VersionHash:5f78ec9,CLOUDID:91c3cb94-10ce-4e4b-85c2-c9b5229ff92b,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: 2518fa28770b11eea33bb35ae8d461a2-20231030 Received: from mtkmbs13n2.mediatek.inc [(172.21.101.108)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 631750122; Mon, 30 Oct 2023 18:00:24 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 30 Oct 2023 18:00:23 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 30 Oct 2023 18:00:23 +0800 From: Moudy Ho To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mauro Carvalho Chehab , Matthias Brugger , AngeloGioacchino Del Regno , Hans Verkuil CC: , , , , , , Moudy Ho Subject: [PATCH v8 02/16] dt-bindings: media: mediatek: mdp3: merge the indentical RDMA under display Date: Mon, 30 Oct 2023 18:00:08 +0800 Message-ID: <20231030100022.9262-3-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231030100022.9262-1-moudy.ho@mediatek.com> References: <20231030100022.9262-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_PASS, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Mon, 30 Oct 2023 03:03:14 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781174326556778831 X-GMAIL-MSGID: 1781174326556778831 To simplify maintenance and avoid branches, the identical component should be merged and placed in the path belonging to the MDP (from display/* to media/*). In addition, currently only MDP utilizes RDMA through CMDQ, and the necessary properties for "mediatek,gce-events", and "mboxes" have been set up for this purpose. Within DISP, it directly receives component interrupt signals. Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno --- .../display/mediatek/mediatek,mdp-rdma.yaml | 88 ------------------- .../bindings/media/mediatek,mdp3-rdma.yaml | 55 +++++++++--- 2 files changed, 45 insertions(+), 98 deletions(-) delete mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml deleted file mode 100644 index dd12e2ff685c..000000000000 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,mdp-rdma.yaml +++ /dev/null @@ -1,88 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/display/mediatek/mediatek,mdp-rdma.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: MediaTek MDP RDMA - -maintainers: - - Chun-Kuang Hu - - Philipp Zabel - -description: - The MediaTek MDP RDMA stands for Read Direct Memory Access. - It provides real time data to the back-end panel driver, such as DSI, - DPI and DP_INTF. - It contains one line buffer to store the sufficient pixel data. - RDMA device node must be siblings to the central MMSYS_CONFIG node. - For a description of the MMSYS_CONFIG binding, see - Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml for details. - -properties: - compatible: - const: mediatek,mt8195-vdo1-rdma - - reg: - maxItems: 1 - - interrupts: - maxItems: 1 - - power-domains: - maxItems: 1 - - clocks: - items: - - description: RDMA Clock - - iommus: - maxItems: 1 - - mediatek,gce-client-reg: - description: - The register of display function block to be set by gce. There are 4 arguments, - such as gce node, subsys id, offset and register size. The subsys id that is - mapping to the register of display function blocks is defined in the gce header - include/dt-bindings/gce/-gce.h of each chips. - $ref: /schemas/types.yaml#/definitions/phandle-array - items: - items: - - description: phandle of GCE - - description: GCE subsys id - - description: register offset - - description: register size - maxItems: 1 - -required: - - compatible - - reg - - power-domains - - clocks - - iommus - - mediatek,gce-client-reg - -additionalProperties: false - -examples: - - | - #include - #include - #include - #include - #include - - soc { - #address-cells = <2>; - #size-cells = <2>; - - rdma@1c104000 { - compatible = "mediatek,mt8195-vdo1-rdma"; - reg = <0 0x1c104000 0 0x1000>; - interrupts = ; - clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>; - power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; - iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>; - mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>; - }; - }; diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml index 3e128733ef53..c043204cf210 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml @@ -20,8 +20,9 @@ description: | properties: compatible: - items: - - const: mediatek,mt8183-mdp3-rdma + enum: + - mediatek,mt8183-mdp3-rdma + - mediatek,mt8195-vdo1-rdma reg: maxItems: 1 @@ -49,17 +50,18 @@ properties: maxItems: 1 clocks: - items: - - description: RDMA clock - - description: RSZ clock + minItems: 1 + maxItems: 2 iommus: maxItems: 1 mboxes: - items: - - description: used for 1st data pipe from RDMA - - description: used for 2nd data pipe from RDMA + minItems: 1 + maxItems: 2 + + interrupts: + maxItems: 1 '#dma-cells': const: 1 @@ -68,13 +70,46 @@ required: - compatible - reg - mediatek,gce-client-reg - - mediatek,gce-events - power-domains - clocks - iommus - - mboxes - '#dma-cells' +allOf: + - if: + properties: + compatible: + contains: + const: mediatek,mt8183-mdp3-rdma + + then: + properties: + clocks: + items: + - description: RDMA clock + - description: RSZ clock (shared SRAM with RDMA) + + mboxes: + items: + - description: used for 1st data pipe from RDMA + - description: used for 2nd data pipe from RDMA + + required: + - mboxes + - mediatek,gce-events + + - if: + properties: + compatible: + contains: + const: mediatek,mt8195-vdo1-rdma + + then: + properties: + clocks: + items: + - description: RDMA clock + additionalProperties: false examples: From patchwork Mon Oct 30 10:00:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TW91ZHkgSG8gKOS9leWul+WOnyk=?= X-Patchwork-Id: 159642 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp2096072vqb; Mon, 30 Oct 2023 03:06:12 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEvoVBLHcjkdk6tEIpU82BMgKOMeWu6Omg/SDzw1vunnVGjXTaLJB/H9AT9iY2AxWxsAXlY X-Received: by 2002:a17:902:ea0d:b0:1cc:4f55:db72 with SMTP id s13-20020a170902ea0d00b001cc4f55db72mr2362013plg.0.1698660372403; Mon, 30 Oct 2023 03:06:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698660372; cv=none; d=google.com; s=arc-20160816; b=CBWfppOJbcrejswsP0oB8HyGcznIsSauKyx/DKrIvmI7S2NJzbY5bz/447MzJkVQpS G9taC35wcauyZCBDFPsrtxaAVrgZ/GIbBLu+vSCl92zK5pYiKeCswX9pSyunQ0zqB54f N6j/Fc+V+Nvz6Ts4cY+5F7r2sip/5ar52U6OwxEahKDdoNGVR9gGBbbey8oTQMGztO2f XY27jUeVSWxsMgj0l29pIPpzu3cuDQ2k5pB1T8EhBBNS0XSXyHbbFeVClc8XfFBbfJjb sf5EMHGv0Ji21/CXkU9lhPDJilDIReW8ia86O48nZSJsRURbLJP2llNQxy67KFSWS6k+ 1Vgw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=ToxDj4Jh9UEI1Nb/YtvDgd8K3/Q8XFBBACqcPBFHRYc=; fh=N25l34UKybvwssildkJfWZzd7U86IAOGhJYPnp0TxMk=; b=jQG5ROl56+ZBLDQ8lirjpoKKpWJF+v56ehETzeefaPaT/BBzmnUIcQQ45fx/hg6+/C J0pviypmTD3PkAHVAqfP2yqKxR/jzID2sKZylPTYbR5ldS+MJ+AS353eAmTUPpmbzMUV fyYz89Xcggtg5W8W1/YJQUuAI6XG3pL1Gw3T5CaTK+2qN0TNJmM468dfdlYQLHOKatXK lYaUr7ZhGJpmoWeAmFvwY7/IzNde5eS1xGZfHJ+g4xKczPCeOQlaO+7Kotnh4BJOk9S7 xhK+brsi0585eLkQH3gh1xj2Rh3+IUiFervboiLANsCVSLL7q+dtOuNwu5+jpbLzh2K7 TFnw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=utcSVT0w; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from pete.vger.email (pete.vger.email. [23.128.96.36]) by mx.google.com with ESMTPS id i13-20020a17090332cd00b001cc5d28bb2csi114633plr.151.2023.10.30.03.06.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Oct 2023 03:06:12 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) client-ip=23.128.96.36; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=utcSVT0w; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by pete.vger.email (Postfix) with ESMTP id 322B580765DD; Mon, 30 Oct 2023 03:05:13 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at pete.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232493AbjJ3KDH (ORCPT + 31 others); Mon, 30 Oct 2023 06:03:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55904 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232911AbjJ3KBD (ORCPT ); Mon, 30 Oct 2023 06:01:03 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 33E131700; Mon, 30 Oct 2023 03:00:33 -0700 (PDT) X-UUID: 25411c7e770b11ee8051498923ad61e6-20231030 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=ToxDj4Jh9UEI1Nb/YtvDgd8K3/Q8XFBBACqcPBFHRYc=; b=utcSVT0wKvhKehYCl/VuBY3FO/YIJFAK03+xdvnTbLCqRSltWbKMvq/erSZiLpuOGa6fS2yvFIsLV/m36PTsWqXOcmmzS2CJFihvLvR+3XGF7IFJXyhANNJroyC86tRIX3NbLl3HSE8vsl5pmMOgUYhLwTNtbZySELS7U3Z9bO4=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.32,REQID:f7b3f16b-dcb5-4aeb-9a65-d333931879dd,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5f78ec9,CLOUDID:78c3cb94-10ce-4e4b-85c2-c9b5229ff92b,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 25411c7e770b11ee8051498923ad61e6-20231030 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1356428682; Mon, 30 Oct 2023 18:00:24 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 30 Oct 2023 18:00:23 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 30 Oct 2023 18:00:23 +0800 From: Moudy Ho To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mauro Carvalho Chehab , Matthias Brugger , AngeloGioacchino Del Regno , Hans Verkuil CC: , , , , , , Moudy Ho Subject: [PATCH v8 03/16] dt-bindings: media: mediatek: mdp3: add config for MT8195 RDMA Date: Mon, 30 Oct 2023 18:00:09 +0800 Message-ID: <20231030100022.9262-4-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231030100022.9262-1-moudy.ho@mediatek.com> References: <20231030100022.9262-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Mon, 30 Oct 2023 03:05:13 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781174498452014910 X-GMAIL-MSGID: 1781174498452014910 Added the configuration for MT8195 RDMA. In comparison to MT8183, it no longer shares SRAM with RSZ, and there are now preconfigured 5 mbox. Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno --- .../bindings/media/mediatek,mdp3-rdma.yaml | 26 ++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml index c043204cf210..504334a76fb3 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml @@ -22,6 +22,7 @@ properties: compatible: enum: - mediatek,mt8183-mdp3-rdma + - mediatek,mt8195-mdp3-rdma - mediatek,mt8195-vdo1-rdma reg: @@ -58,7 +59,7 @@ properties: mboxes: minItems: 1 - maxItems: 2 + maxItems: 5 interrupts: maxItems: 1 @@ -98,6 +99,29 @@ allOf: - mboxes - mediatek,gce-events + - if: + properties: + compatible: + contains: + const: mediatek,mt8195-mdp3-rdma + + then: + properties: + clocks: + items: + - description: RDMA clock + + mboxes: + items: + - description: used for 1st data pipe from RDMA + - description: used for 2nd data pipe from RDMA + - description: used for 3rd data pipe from RDMA + - description: used for 4th data pipe from RDMA + - description: used for the data pipe from SPLIT + + required: + - mediatek,gce-events + - if: properties: compatible: From patchwork Mon Oct 30 10:00:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TW91ZHkgSG8gKOS9leWul+WOnyk=?= X-Patchwork-Id: 159630 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp2094481vqb; Mon, 30 Oct 2023 03:03:20 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEghvnUVf70uxiDxeJ0ICPGfK+ZtnQ9EVz10LJ9Xd80pldSsVFBSLpzkf1lTASFiZs0v0JF X-Received: by 2002:a17:903:c4:b0:1cc:3b86:cfc5 with SMTP id x4-20020a17090300c400b001cc3b86cfc5mr4218373plc.4.1698660200504; Mon, 30 Oct 2023 03:03:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698660200; cv=none; d=google.com; s=arc-20160816; b=zHhlCDFiQBuU3gopDot+vmES2vNch0AADuuJSMiWd2VlRhrtR6ocoyzIinoemtVd5s x2XoB+VVJNS/QZZuQtYdE9s6lxjo3iDgMhcyFs7cp7dyfwrDQkXrR4eYwErhLhWhxMcP MyVDsSjKXVEDIzPPbxMnBpLmKxXixquI5DX2USkpeHCNw8UKkxQUV31hOQCsDrzs+Pn4 pqxlyuIYP59RMXPxugkqjmz86f/Y2/GefZeTMuOgRTtZ4ULpoqO2ei5WU7WLlLqMvd3/ AbdbYoVWNGaFjD7Y5IoGArLUKFQcFEcmIiQOlMqRmAcJQ/raGA1q0+CIcZ+rscEVl/53 fb+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=GuaatKpJJKQ8P3UzwE+5PZkOWfDZVusyH/8yORVTn1k=; fh=e0RlLHzlztEJgFr1G5iUAfmLhro7zrN0SmKLmnTwLIM=; b=XV7Wu5TV+Xuv3ggKkZH7AvQFE0hFBKDXGXp6absI3xY5lj2XxVHYCjF2K4Df9z2THV nq4foV85DtOUwYh2Ic06Q9ecGXQCH89waSFZ+K5XOttri5c3hT1N/97IgFor8LKhUewm JZES+8R9Au+73OUpDfy7ldnWJCz5gBhSy0n7+yvKoLZ0eNzdxhnebcu3h7gbCX6OJVxa x8vNzc6ErMLy8VuzIzep0RuhDyJ0nca1Ce47Xx6S53GWOKhybvXzFphEvHS2UkK0bDDi sxozzr+ui/O9OPC8iEvY5HyOCKY15PJdVmIu5/sn7UejAdQgTCS7EcqZbhX31eXlObw2 vPlw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=o99wEYct; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from lipwig.vger.email (lipwig.vger.email. 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Mon, 30 Oct 2023 18:00:25 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 30 Oct 2023 18:00:23 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 30 Oct 2023 18:00:23 +0800 From: Moudy Ho To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Mauro Carvalho Chehab , "Matthias Brugger" , AngeloGioacchino Del Regno , Hans Verkuil CC: , , , , , , "Moudy Ho" Subject: [PATCH v8 04/16] dt-bindings: media: mediatek: mdp3: add compatible for MT8195 RSZ Date: Mon, 30 Oct 2023 18:00:10 +0800 Message-ID: <20231030100022.9262-5-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231030100022.9262-1-moudy.ho@mediatek.com> References: <20231030100022.9262-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--0.551500-8.000000 X-TMASE-MatchedRID: cAwOsowI+VIDh1tb/sWFHED6z8N1m1ALTJDl9FKHbrmYBF1C0J2QPjQz 47GqDWjpxMujmXyGahWAMuqetGVetnyef22ep6XYro1URZJFbJug7sWlw3XsXlfh9ESKeQDv1jG 8ZsDHeH7T/jdn/4Yuc/XEBV7HQugfrX6tM/OsbihyZ2HQxNrrszHJQPTfIuUfBclF7ltO/aCOh+ wyNBrFXDJiNuKohDcKzKSG3JdyKAPqtV2AGMNPavWdclq8lU1q X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--0.551500-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 89B58F40B8515AC7F6E265B9370A53FFD517E53B14BE8E28A0F207A9A3F15CD02000:8 X-MTK: N X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Mon, 30 Oct 2023 03:03:18 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781174318820991836 X-GMAIL-MSGID: 1781174318820991836 MT8195 RSZ inherited from MT8183, add the corresponding compatible name to it. Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/media/mediatek,mdp3-rsz.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml index 78f9de6192ef..f5676bec4326 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml @@ -15,9 +15,13 @@ description: | properties: compatible: - items: + oneOf: - enum: - mediatek,mt8183-mdp3-rsz + - items: + - enum: + - mediatek,mt8195-mdp3-rsz + - const: mediatek,mt8183-mdp3-rsz reg: maxItems: 1 From patchwork Mon Oct 30 10:00:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TW91ZHkgSG8gKOS9leWul+WOnyk=?= X-Patchwork-Id: 159633 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp2094638vqb; Mon, 30 Oct 2023 03:03:35 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFY6/0Ri78PVG89ofnOakk3v58OYLF+wcKbz7x1F0aNyDsmZyTQrl1jFmiN/I6K1b+ubFtE X-Received: by 2002:a05:6a21:66c7:b0:17f:cf8e:2415 with SMTP id ze7-20020a056a2166c700b0017fcf8e2415mr4683576pzb.54.1698660214791; Mon, 30 Oct 2023 03:03:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698660214; cv=none; d=google.com; s=arc-20160816; b=gx8D44/bcf2uzwm652tvVCJY2baFsnJLq4F4yc/UHmbzvot2TWvzZP0GPlFg1tREpW HNl7w8HVlFZ5uHall9AyXIrv1hNeFnZQ5mpH+8kto7DB8vUtoW60FcaTpThPgbNvwDM9 vPN+jOnhl1XmXwG6DGwj1LjxG/VJs87PAxdHcuyFsdmNNCk84rblJ78U72igYo8pLM5f VotljInzMoQTR7G8dBsHVm7YIspb2ojikcYe72jP23XdHjbRLGLqrfhYjHqIOWLmAkyG lq8Pe4QD7HQGGSOwLNZ4LuvvMDWUhsOXy8iWCP74aypJKS6N+uXxYpb8hl5N2zNxkeJE SS4A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=Vb24kkSmzFqLkYt275IGRO8kfWGasUiCdUh0M9mkibA=; fh=e0RlLHzlztEJgFr1G5iUAfmLhro7zrN0SmKLmnTwLIM=; b=NmcmlXda0h95j66As50f4AiewYKg+XRgjdZO8avo9U+uAem0hYLtGUTaDEK8NGxkOb hnwSpgKBiePtSc9Vs4FD7Zy0CdZhc5wqZhkX334b+KdocqD65oeFu11+4r3op1T3Us/p VEP5BVKCCY2uHOXmvOa4P4SDjdWxRaSzI4IFXIZCM2twU/b6CxkcA2ZfZPPs1pONS31Y n7U0gQHHO7NIfJrGPip2GtErHO0+hwOlZTWLlKtJsn68YBJLT43pfsWWzligy7onjrAa WHuOnLgoMvtM7PdJ1/TbiVA06tmPvB/EPIk1MjZ0t03yDrDbMp/7I50wgrA9rRymZwYn y/Ew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=cz8KbRmE; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from snail.vger.email (snail.vger.email. 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Mon, 30 Oct 2023 18:00:25 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 30 Oct 2023 18:00:23 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 30 Oct 2023 18:00:23 +0800 From: Moudy Ho To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Mauro Carvalho Chehab , "Matthias Brugger" , AngeloGioacchino Del Regno , Hans Verkuil CC: , , , , , , "Moudy Ho" Subject: [PATCH v8 05/16] dt-bindings: media: mediatek: mdp3: add compatible for MT8195 WROT Date: Mon, 30 Oct 2023 18:00:11 +0800 Message-ID: <20231030100022.9262-6-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231030100022.9262-1-moudy.ho@mediatek.com> References: <20231030100022.9262-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--0.551500-8.000000 X-TMASE-MatchedRID: cAwOsowI+VIDh1tb/sWFHED6z8N1m1ALTJDl9FKHbrmYBF1C0J2QPjQz 47GqDWjpxMujmXyGahWAMuqetGVetnyef22ep6XYro1URZJFbJug7sWlw3XsXlfh9ESKeQDv1jG 8ZsDHeH7T/jdn/4Yucx21lASq3oFNV576su74nzHxfCoIocRdvUEyMtVsBYOoljIESwJjC1eOh+ wyNBrFXDJiNuKohDcKzKSG3JdyKAPqtV2AGMNPavWdclq8lU1q X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--0.551500-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: DAAA71397983D472F97DB71C9C2BBF27E7EAD127AA1673109FCD3EF250F2D3152000:8 X-MTK: N X-Spam-Status: No, score=-1.3 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED,RDNS_NONE, SPF_HELO_PASS,SPF_PASS,UNPARSEABLE_RELAY autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); 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Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/media/mediatek,mdp3-wrot.yaml | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml index 64ea98aa0592..53a679338402 100644 --- a/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml @@ -15,9 +15,13 @@ description: | properties: compatible: - items: + oneOf: - enum: - mediatek,mt8183-mdp3-wrot + - items: + - enum: + - mediatek,mt8195-mdp3-wrot + - const: mediatek,mt8183-mdp3-wrot reg: maxItems: 1 From patchwork Mon Oct 30 10:00:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TW91ZHkgSG8gKOS9leWul+WOnyk=?= X-Patchwork-Id: 159634 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp2094672vqb; Mon, 30 Oct 2023 03:03:37 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGBwKepT4sK0i5hv5GY1BJwKzmg3TyHWnzIf6hqfkVc7oGC6yLV1hTBA/Arq95u6JaDUv2L X-Received: by 2002:a17:90a:d497:b0:27f:ecd9:6d0e with SMTP id s23-20020a17090ad49700b0027fecd96d0emr8069663pju.34.1698660217497; Mon, 30 Oct 2023 03:03:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698660217; cv=none; d=google.com; s=arc-20160816; b=oRutZGZYHwHrEkkdBvxFeHPPngSb6PTLIqvvS9aQLamPjzskNB6bXOSWHPtAhBpKDr p13CQsUGPvn7f/ITcxOeEaRCDAJjbbWXvR3V1gLsNzNvjWpYE5a/egwMa6Fa6XPBquq8 Io46MeBIGXVn69z3QxqJyljAcrfverJAqyVgvzl0KLlVlzsM2zFLhjwvVIQLF3OINQwt /4DfiZ7qNnclpWPR0kJX59AMAB/jlsxPCE1mjot3ikZWdcKK3CIUS4aaH62fJZP5XNew fl9qQc2ho5Ubx6PTXS3ZLnLSYO0PUQW7RyuWg5/t9p+/IjpduKacCLM8D7TpEyUVgxuo 2wEA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=ZbKsTEXQ06nZKi8eEHm/YLTPz1FZJoAUmXN9IUI475U=; fh=N25l34UKybvwssildkJfWZzd7U86IAOGhJYPnp0TxMk=; b=Wsx/HrhZy9De4Bi0tM1ynHSvOy8ns3fLbEArHiVrcgooTm5l/OSOh29PWDKtEsR3se wRvs3QBDGnl1iUpINc1GnybzPXjy5c8mfc1dveUIGvkAYVhprInxUWSizSOw7tCknW5l 1BCv2rT46D3I3xzDA8odeM1I1i/aJL/fCWNfLulSK9kDpSUyJXkEtS3c7ITcc1e9sRSo W38ozL6fBOayWsvHq9Mo7CiVYJXpSWFtnM3x69NAlmUZOy1cRMocdL3aPoDuTR27fzeO E1VRBxnJtWEVyVSX9DtFCiaT6ZoWlH1f9BaQa7AbHmnZAFM4CU/JTdbkaJ3LR8MGxtP/ lYPg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=H0UJ1vyC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from snail.vger.email (snail.vger.email. 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Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski --- .../bindings/media/mediatek,mdp3-fg.yaml | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml new file mode 100644 index 000000000000..03f31b009085 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-fg.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mdp3-fg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Media Data Path 3 Film Grain + +maintainers: + - Matthias Brugger + - Moudy Ho + +description: + Film Grain (FG) is a Media Data Path 3 (MDP3) component used to add + the film grain according to the AOMedia Video 1 (AV1) standard. + +properties: + compatible: + enum: + - mediatek,mt8195-mdp3-fg + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + description: + The register of display function block to be set by gce. There are 4 arguments, + such as gce node, subsys id, offset and register size. The subsys id that is + mapping to the register of display function blocks is defined in the gce header + include/dt-bindings/gce/-gce.h of each chips. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle of GCE + - description: GCE subsys id + - description: register offset + - description: register size + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - mediatek,gce-client-reg + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + + display@14002000 { + compatible = "mediatek,mt8195-mdp3-fg"; + reg = <0x14002000 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x2000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_FG>; + }; From patchwork Mon Oct 30 10:00:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TW91ZHkgSG8gKOS9leWul+WOnyk=?= X-Patchwork-Id: 159628 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp2094406vqb; Mon, 30 Oct 2023 03:03:15 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFhLNJfQW9o86RVT/XVQmlzJnqP7vKkaF27Oe/aAsTzkUGFW+o6Ze049Dlujbq7GnIAW287 X-Received: by 2002:a05:6a21:a108:b0:16c:1340:c621 with SMTP id aq8-20020a056a21a10800b0016c1340c621mr9659416pzc.31.1698660195146; Mon, 30 Oct 2023 03:03:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698660195; cv=none; d=google.com; s=arc-20160816; b=0RWZ7P1zrgX9J+yhAeBVvaJbLFIGQskGRLx2Ji8r/hRO30XIXWT+02+FCTDCOWK1xA 474HNPjoZ/9r6fjildel079NukAoJlr+otqbdjG1vOPETmXPJ42B+0Uct8pWlaUccLvd sV2Qrxa5klP/YdvSNiAOEXNPko/EWZioxZZSbPk366G7CfFd8ixkndZiIQLRpBS3BNBE g+GzHD0/JlMZ5aITDyFsvMtjIGS8+cl4EzwCgx7EzVoWsOAPDAA6eszLokPb4dG8tbyq Wf7X3c3M3j+ah01cOTVDQteEHVuNKxd53FXnBTg5LjhLSstzK7T4zMF8YMrFtEzciowC TJ5A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=8l5B9d28IzVrTNFOgQusSXRsLqIIUpnduD1x+ROUPPw=; fh=N25l34UKybvwssildkJfWZzd7U86IAOGhJYPnp0TxMk=; b=LRngugybaCQbQgd+4NbJLadTLQUaFC9Z/zsp2TX95x1aLeJyh2c11qpmq+JmZA93Zw 6j8nVEqv+DHZK+cjabre5GxU1U25SJfd0R0BzI1gKn8X92hhYriSXkjydYakKk5legik IVvVw9QvQE/JUscq/aa3Yp6B/Y6FuOr9rFwwWJpLGgJPMrIzZPsX+2QIeuSdTLXeiXmw FFruBZitFtMXXXxYy7me53nj5FarCwnYxGIeXu2NT43QjUjXqDHDYYnMZdONSdII41kz Otfn4/ePktuR+bc62naZSMd1LaICP+v76gwpceRIR1HkurN8p7L5ZA9mLpg1+agrzbbE BwFw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=YUF9qWrb; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from snail.vger.email (snail.vger.email. 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Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski --- .../bindings/media/mediatek,mdp3-hdr.yaml | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml new file mode 100644 index 000000000000..d4609bba6578 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-hdr.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mdp3-hdr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Media Data Path 3 HDR + +maintainers: + - Matthias Brugger + - Moudy Ho + +description: + A Media Data Path 3 (MDP3) component used to perform conversion from + High Dynamic Range (HDR) to Standard Dynamic Range (SDR). + +properties: + compatible: + enum: + - mediatek,mt8195-mdp3-hdr + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + description: + The register of display function block to be set by gce. There are 4 arguments, + such as gce node, subsys id, offset and register size. The subsys id that is + mapping to the register of display function blocks is defined in the gce header + include/dt-bindings/gce/-gce.h of each chips. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle of GCE + - description: GCE subsys id + - description: register offset + - description: register size + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - mediatek,gce-client-reg + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + + display@14004000 { + compatible = "mediatek,mt8195-mdp3-hdr"; + reg = <0x14004000 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x4000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_HDR>; + }; From patchwork Mon Oct 30 10:00:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TW91ZHkgSG8gKOS9leWul+WOnyk=?= X-Patchwork-Id: 159627 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp2094374vqb; Mon, 30 Oct 2023 03:03:12 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFSg7ZkiLgM5knfKn8jjCpBIDwM7VsHiP4cd3x/V//YAuovNH4SZoRLnS0BcPQGGp8ngVEg X-Received: by 2002:a17:90a:31ca:b0:27d:c36:e12c with SMTP id j10-20020a17090a31ca00b0027d0c36e12cmr6404385pjf.9.1698660192429; Mon, 30 Oct 2023 03:03:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698660192; cv=none; d=google.com; s=arc-20160816; b=aFPFhhQQNFEZ9ogTthhJ5MOPyHU0444ecXSOhd72SI0OQSBQEclWPobHT31uIzSSmZ QdfIliw/JPQSZ5FXNaEAWv+K1hYbiA9miKSOg0sdGGu5x1g5hkpGNbP0VFYCaQ36OTLz xmu8EC5bSpk/Cnzd23eKXr8HiLjp0ldbu0Jj56dDscV23WpRClQvMoWgSR0jtU7aCNJF gHc0f9xr4rqinb6X/yOssPQZmIW4dw+ooS9T3f7XbqaiBtwz2EYjhjdiWiZjsyWoRfVc Q7gmnYLaMky4YhbghzeljLIsE5HaZkMQL1BhQidx55r4I4dsdccVhfgKrFBhNnRhjKqu AZEg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=ANuFUsFoyoEqWIC9YUSMwJ/ZYm1GzfjVh08nIzoTWGU=; fh=N25l34UKybvwssildkJfWZzd7U86IAOGhJYPnp0TxMk=; b=TuGSpqu0T6mIZTKaASdNhAyAaPca5n9gcAb6A2PE+OaqxhfnIz8p/YjLZFV5SnipmE JLLF2qXqtClZIhDvSzOMj81HRaNmym49lf6cXkVKez0QPL/xTTHjJaPP5DtkST1xPPpg aEpNbQLOOkw0c5G+oB34r05pY4wWAuoFiVtyUYtL7WZCB2ke5fgwuObGACtTFctHCer/ uTbS5QFTBBbp+iRkUYiF5iZZ5gKs6XuHznpljs0GWmKbTIrBy/KrRpmZn8yXNLfk2NGw O8M7S/Tetgp6+ec+T0KHQlipwK6SOjVMtSdWB62MRp7xrOFazxeKVOu5kII5D0NnGSQt ZZ9Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b="lWYa/HPY"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from pete.vger.email (pete.vger.email. [23.128.96.36]) by mx.google.com with ESMTPS id my15-20020a17090b4c8f00b002802838d551si3276980pjb.157.2023.10.30.03.03.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Oct 2023 03:03:12 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) client-ip=23.128.96.36; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b="lWYa/HPY"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by pete.vger.email (Postfix) with ESMTP id 2F86780A9985; Mon, 30 Oct 2023 03:02:58 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at pete.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233215AbjJ3KCN (ORCPT + 31 others); Mon, 30 Oct 2023 06:02:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55780 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232855AbjJ3KA7 (ORCPT ); Mon, 30 Oct 2023 06:00:59 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 37A6F1FF3; Mon, 30 Oct 2023 03:00:31 -0700 (PDT) X-UUID: 2542e630770b11ee8051498923ad61e6-20231030 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=ANuFUsFoyoEqWIC9YUSMwJ/ZYm1GzfjVh08nIzoTWGU=; b=lWYa/HPYB59Xtefn93eamz/uH2DUtte9sjV+Uo7RPZg9Jk863RLoKfNKzL94B11lcExQVwQlw7Tm7E328lR2ifh8oHQqSPjEwhc19KhXq7mFIgws7pPr6mbbcMB9ItAOf1Cti8shZ/hzs1frU3U7YnQWzhRgOYQJSzHFHWL8xb0=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.32,REQID:329b680d-8160-4bb5-b3d1-96985f79fe98,IP:0,U RL:25,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:25 X-CID-META: VersionHash:5f78ec9,CLOUDID:c2390e72-1bd3-4f48-b671-ada88705968c,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR,TF_CID_SPAM_ULN X-UUID: 2542e630770b11ee8051498923ad61e6-20231030 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 710847364; Mon, 30 Oct 2023 18:00:24 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 30 Oct 2023 18:00:24 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 30 Oct 2023 18:00:24 +0800 From: Moudy Ho To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mauro Carvalho Chehab , Matthias Brugger , AngeloGioacchino Del Regno , Hans Verkuil CC: , , , , , , Moudy Ho Subject: [PATCH v8 08/16] dt-bindings: media: mediatek: mdp3: add component STITCH for MT8195 Date: Mon, 30 Oct 2023 18:00:14 +0800 Message-ID: <20231030100022.9262-9-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231030100022.9262-1-moudy.ho@mediatek.com> References: <20231030100022.9262-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Mon, 30 Oct 2023 03:02:58 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781174310106920844 X-GMAIL-MSGID: 1781174310106920844 Add the fundamental hardware configuration of component STITCH, which is controlled by MDP3 on MT8195. Signed-off-by: Moudy Ho Reviewed-by: Krzysztof Kozlowski --- .../bindings/media/mediatek,mdp3-stitch.yaml | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml new file mode 100644 index 000000000000..d815bea29154 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-stitch.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mdp3-stitch.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Media Data Path 3 STITCH + +maintainers: + - Matthias Brugger + - Moudy Ho + +description: + One of Media Data Path 3 (MDP3) components used to combine multiple video frame + with overlapping fields of view to produce a segmented panorame. + +properties: + compatible: + enum: + - mediatek,mt8195-mdp3-stitch + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + description: + The register of display function block to be set by gce. There are 4 arguments, + such as gce node, subsys id, offset and register size. The subsys id that is + mapping to the register of display function blocks is defined in the gce header + include/dt-bindings/gce/-gce.h of each chips. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle of GCE + - description: GCE subsys id + - description: register offset + - description: register size + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - mediatek,gce-client-reg + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + + display@14003000 { + compatible = "mediatek,mt8195-mdp3-stitch"; + reg = <0x14003000 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x3000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_STITCH>; + }; From patchwork Mon Oct 30 10:00:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TW91ZHkgSG8gKOS9leWul+WOnyk=?= X-Patchwork-Id: 159631 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp2094526vqb; Mon, 30 Oct 2023 03:03:23 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEx+GBw8j0K66GvM/p6xFK3iYAXHseCCOuEo8riLs9dd80QlQxYVhU9ouduV1oskg45iU+N X-Received: by 2002:a05:6a20:918d:b0:13f:1622:29de with SMTP id v13-20020a056a20918d00b0013f162229demr8069551pzd.7.1698660203507; Mon, 30 Oct 2023 03:03:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698660203; cv=none; d=google.com; s=arc-20160816; b=yQ0uwVrMUN7u5E323pCa0GGO2GlwBlzX0Ze8hcUamKZWFmih9+KS9yfw1DcMFbuarj lbl76M3PBKuUPPMuq1tUuqoHzZWGroGB/SOCOcCfQZSFtaCAa+AKQ859TQyzXuI04iUy o/UF/HS4l0XldQMOEJXA97+FyUjzNjlp6SqpJhIJ7nLOSBmCbf6LrLKFxQK0+gEqAIFv Xws5/b42y0IjmYtHBcM03NS76xB02KjLYh/nNtEHCGRcj/9h0uxjQXbgQFL0rK3lSmuO MINHxyFyOcbG+wr7sr9oTdpVAUJWWxyG1KK39+M3MGLOLpk9w1ji9B5ezORdYqJkamSO bYjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=5QjcwvzrebWfLqJww9KhwNbe3Z1/pLAvIef2nvvVTbQ=; fh=N25l34UKybvwssildkJfWZzd7U86IAOGhJYPnp0TxMk=; b=kO/onSjF9tMts+IAG5bKLcPCV9dBPPOQWBdQMrR66bucDun2COFUmEQtYTbNm7+xMA t4k6E1oXq0yk1q+89N8WvmNaxI4mo/+/O64O5rjGTSRzPxW2CmW1D8PfJ3LSdn4TYnyK 9KiNI1wrsdXsdUpqEl2RXzITXo7g8PUc8x9oED/vQQ4ady8kl6GoK49bhkYIjn27LDHA 6hVMcI7Ui9+OWln7S0mAvz9+QAx10yI9IpPyac5Mc4Rp/5ZHwti+O8cjH/UXDElGZV3M Y32751jNTvYZiV5xUS3biIW/XuHqEMJw22A7mFlTZN0cbOob1OlakenoporbzktGF6aj Jb6A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=PebvUAjV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from snail.vger.email (snail.vger.email. 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Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski --- .../bindings/media/mediatek,mdp3-tcc.yaml | 62 +++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml new file mode 100644 index 000000000000..14ea556d4f82 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-tcc.yaml @@ -0,0 +1,62 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mdp3-tcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Media Data Path 3 Tone Curve Conversion + +maintainers: + - Matthias Brugger + +description: + Tone Curve Conversion (TCC) is one of Media Profile Path 3 (MDP3) components. + It is used to handle the tone mapping of various gamma curves in order to + achieve HDR10 effects. This helps adapt the content to the color and + brightness range that standard display devices typically support. + +properties: + compatible: + enum: + - mediatek,mt8195-mdp3-tcc + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + description: + The register of display function block to be set by gce. There are 4 arguments, + such as gce node, subsys id, offset and register size. The subsys id that is + mapping to the register of display function blocks is defined in the gce header + include/dt-bindings/gce/-gce.h of each chips. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle of GCE + - description: GCE subsys id + - description: register offset + - description: register size + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - mediatek,gce-client-reg + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + + display@1400b000 { + compatible = "mediatek,mt8195-mdp3-tcc"; + reg = <0x1400b000 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xb000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_TCC>; + }; From patchwork Mon Oct 30 10:00:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TW91ZHkgSG8gKOS9leWul+WOnyk=?= X-Patchwork-Id: 159641 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp2096065vqb; Mon, 30 Oct 2023 03:06:12 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHHtH0HHx3uBvaHK1DKbQgRDU14R/ax4mNpuHOMbMD8P+JSDUvBS2+RZAr4X3Bwn1xlfSoL X-Received: by 2002:a17:902:dcc5:b0:1cc:b3f:dd81 with SMTP id t5-20020a170902dcc500b001cc0b3fdd81mr6072670pll.67.1698660371892; Mon, 30 Oct 2023 03:06:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698660371; cv=none; d=google.com; s=arc-20160816; b=WUhX1JNWjeQPeT6wYpcoxXkxHa45ZBcNQvgBZXo8EdW1KbnBvdrmq52KcpTW+HPIqk Y9OJIVaYjIkQGC2xQ4pRM2PJ2f3UyoKu0ZKX47CMMmKpH6drw0yXAr2rkZVXlLNeLiLR EK6DMsCmrp0YU06fqbfy4HTl+7HiCXo8y0cn23SkMnP0czyWbHYmILdODLB90YeUcJAM vK0Sej0/XeG3gkJ1fMQTvhTM1ZMZKn6cmBpU96PqnRsOjlnU0igVaV5i5QaP5O/kmPp9 h5xttZC/6BdxyoeRRbDH8ZLJXsUKpIecgAYopXwxaUetkuju3iCYwnRVYTElyQWZcBtk RtHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=LXiaxvzc+VKk9AXDACkXrguSN5q7SHGlOT4sgve/e1E=; fh=N25l34UKybvwssildkJfWZzd7U86IAOGhJYPnp0TxMk=; b=hoqrpLZY2vtA7bW0t/ihxqa9dY91/7Ag7fzmY1ajsH1aaFFwHp5SsubZQRO2u4mdOO Eu+BZZlr4rEY3/giFL9bdMDh7I0dQ/6WUfXJmTY610cx9/Bodjm+4jnDFQi9bEf55jBC f+z23galHV1dGSVYZtPk5A6OdC0kqH0fNN7ROHlyxcr6NOZfA1YCNYFD7N+cw5QOfzRg qUgSx7ZHpJLjoQqjNKqRjv5Z4i8QLCu4DqwDuPJk+kGuLbTXH8Gtb3a9wXZ2A6uQBecz 6NAUDrBm063h/SdkLl1smyncbHdOZ1W+I8kOQpDqLrjjWd068vEczVgv+r+fWq/mL2Sf EU3A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=ct6pyF3B; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from pete.vger.email (pete.vger.email. [23.128.96.36]) by mx.google.com with ESMTPS id o2-20020a17090323c200b001bf0e15c0a9si4678535plh.269.2023.10.30.03.06.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Oct 2023 03:06:11 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) client-ip=23.128.96.36; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=ct6pyF3B; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by pete.vger.email (Postfix) with ESMTP id 6AFF580AC458; Mon, 30 Oct 2023 03:05:02 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at pete.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232860AbjJ3KCx (ORCPT + 31 others); Mon, 30 Oct 2023 06:02:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54072 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232956AbjJ3KBF (ORCPT ); Mon, 30 Oct 2023 06:01:05 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 47A5110EB; Mon, 30 Oct 2023 03:00:35 -0700 (PDT) X-UUID: 25dc54fa770b11ee8051498923ad61e6-20231030 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=LXiaxvzc+VKk9AXDACkXrguSN5q7SHGlOT4sgve/e1E=; b=ct6pyF3BVEcca0veyEXb3db7FiPsPfK64uRSf2cn/smo6KFRosmoKoFjjsVAUzSLs6zsrLyT8hwmlGAx2BPS+514iPrN4Ix/096YLSvJgUWjRcZmRPJq8jpm1QielYo87s/RE1B9Hpf/X60Km9UgLU0OgXU1+CGUzM73YQIFEU4=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.32,REQID:85d41ff6-40e7-4852-81da-7199835ba609,IP:0,U RL:25,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:25 X-CID-META: VersionHash:5f78ec9,CLOUDID:56167bd7-04a0-4e50-8742-3543eab8cb8e,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:11|1,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR: NO,DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_ULN,TF_CID_SPAM_SNR X-UUID: 25dc54fa770b11ee8051498923ad61e6-20231030 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 231608169; Mon, 30 Oct 2023 18:00:25 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs13n1.mediatek.inc (172.21.101.193) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 30 Oct 2023 18:00:24 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 30 Oct 2023 18:00:24 +0800 From: Moudy Ho To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mauro Carvalho Chehab , Matthias Brugger , AngeloGioacchino Del Regno , Hans Verkuil CC: , , , , , , Moudy Ho Subject: [PATCH v8 10/16] dt-bindings: media: mediatek: mdp3: add component TDSHP for MT8195 Date: Mon, 30 Oct 2023 18:00:16 +0800 Message-ID: <20231030100022.9262-11-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231030100022.9262-1-moudy.ho@mediatek.com> References: <20231030100022.9262-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Mon, 30 Oct 2023 03:05:02 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781174498180024037 X-GMAIL-MSGID: 1781174498180024037 Add the fundamental hardware configuration of component TDSHP, which is controlled by MDP3 on MT8195. Signed-off-by: Moudy Ho Reviewed-by: Krzysztof Kozlowski --- .../bindings/media/mediatek,mdp3-tdshp.yaml | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml diff --git a/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml b/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml new file mode 100644 index 000000000000..8ab7f2d8e148 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mdp3-tdshp.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mdp3-tdshp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Media Data Path 3 Two-Dimensional Sharpness + +maintainers: + - Matthias Brugger + - Moudy Ho + +description: + Two-Dimensional Sharpness (TDSHP) is a Media Profile Path 3 (MDP3) component + used to perform image edge sharpening and enhance vividness and contrast. + +properties: + compatible: + enum: + - mediatek,mt8195-mdp3-tdshp + + reg: + maxItems: 1 + + mediatek,gce-client-reg: + description: + The register of display function block to be set by gce. There are 4 arguments, + such as gce node, subsys id, offset and register size. The subsys id that is + mapping to the register of display function blocks is defined in the gce header + include/dt-bindings/gce/-gce.h of each chips. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle of GCE + - description: GCE subsys id + - description: register offset + - description: register size + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - mediatek,gce-client-reg + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + + display@14007000 { + compatible = "mediatek,mt8195-mdp3-tdshp"; + reg = <0x14007000 0x1000>; + mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0x7000 0x1000>; + clocks = <&vppsys0 CLK_VPP0_MDP_TDSHP>; + }; From patchwork Mon Oct 30 10:00:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TW91ZHkgSG8gKOS9leWul+WOnyk=?= X-Patchwork-Id: 159635 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp2094717vqb; Mon, 30 Oct 2023 03:03:43 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFnWDD9YNo7VcG8XNIrofxCwStGTPFhCbVQG+c8dVyETJcd7EcgJr4ixiyAVRCvydHhUX/8 X-Received: by 2002:a05:6a00:1414:b0:6b4:231b:a45c with SMTP id l20-20020a056a00141400b006b4231ba45cmr10278601pfu.26.1698660223075; Mon, 30 Oct 2023 03:03:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698660223; cv=none; d=google.com; s=arc-20160816; b=R3D6/k66uYLOxgmWdsIsnR9y3SU1mfeaIjxDWdxcrlq/iR6XDIVUy5bPygJT4w3tSV KLcK8IaQ8t4k+L7eK+ObcUZOA5Yx/8LROvMI3JyjeRHq1YOOcjotKDYy0KxLZnS/5TrK xxw0OLq9BaE6BQM+Vzo66gfvd+DGxhV75J5GSZDnjW/du/0QN+6Ppw/CJvc5LPp+rvHN LB9UlZWf7zKi8WzgBfkAqVHdYgdc2cWdAVLK1iEhQkbT5rBTc0jmBYrYnSv5qQ/kVMwo Tw4hNJhnrYbz70RoJUIGwpGWcMkI6b+CRNZ4b67qEZacCV53km9Yp1eu9k9mb6riOoiL nUfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=uBjiNYTO2WSmvyy9DZRC1WiD40IMo3yDRg/HtSKYR6I=; fh=N25l34UKybvwssildkJfWZzd7U86IAOGhJYPnp0TxMk=; b=Gw0tBos6LahmwwNtBNdl7BEQsCCWfDBwAs65Err/1RuuaKa70Ub6sQ7D1ik0Lx8xB+ zHIvtkAjXy3Od4THiprpkj+x3vmMJFZmcm8mG66OQqTiaYzY2GipxQml6u2SWZG/X0Rv WgQgQVAl5Nmom0xLqkNqqjMmIH8UncHqp7VtwhS18uDI2oBDuEGRZS6bB8AubTEXqPNT 7JVzjERHqQeGM+479DFwre/DopCj9mLpGkaJAlAjIx1H6ucgu9gVPD2AgEewQQW+FQMd JD9pTPOIM3xL+UcDpHYoP/bsYcxhJNZK1YjFRFNbCrWk41aFcmvZPFOv+1Vz1NiMSKZR tFmw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=ZCrP6n7y; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from agentk.vger.email (agentk.vger.email. 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Signed-off-by: Moudy Ho Acked-by: Conor Dooley Reviewed-by: AngeloGioacchino Del Regno --- .../devicetree/bindings/display/mediatek/mediatek,aal.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml index 7fd42c8fdc32..b4c28e96dd55 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,aal.yaml @@ -24,6 +24,7 @@ properties: - enum: - mediatek,mt8173-disp-aal - mediatek,mt8183-disp-aal + - mediatek,mt8195-mdp3-aal - items: - enum: - mediatek,mt2712-disp-aal From patchwork Mon Oct 30 10:00:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TW91ZHkgSG8gKOS9leWul+WOnyk=?= X-Patchwork-Id: 159625 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp2094326vqb; Mon, 30 Oct 2023 03:03:07 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGo1SPfRH/3cBrF3oDwx6QxybgqdNujDdt0UaY+2kNF2xQjMrjvPFiZDwU/7jO7/Qe0TAx9 X-Received: by 2002:a05:6a00:1143:b0:6b2:69c:346a with SMTP id b3-20020a056a00114300b006b2069c346amr10369952pfm.19.1698660187212; Mon, 30 Oct 2023 03:03:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698660187; cv=none; d=google.com; s=arc-20160816; b=pXCP7w1Kxsj6tYW0W0HbfrKvxEu3FyQTCj2xAdMawcMS5ksORs796aH7v/Dul8jBM9 SMeHxJd+T+WtUgDvdNlFiPVtD6WtPDmEogVI98UfpzaodjtDzQLtbL/MxdPg0SyDqqTm kRyw4CVfndamrI3sNMfw+qLvxqtO2A3A6SNn/+OGftHdro4WrkwqcPSlD7c/l9rwaCZc tyrnSn1w69+AOO6tOUhqE/PHj+pXBDgDHRW+Q4R6Zqk3RqCOl1VX2+1ZCJ/G5R9shMJf LDTeDjWCtQtS/eSquWnbtXsF1Yb7gcx87lhfj0tIlSQh8n8habCBkNwP2Fml1y4ne8yn 0Ocg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=S+BFsscpOYXgIjZ4vvUEbFaZKileuAcJkmvyZC22tyQ=; fh=N25l34UKybvwssildkJfWZzd7U86IAOGhJYPnp0TxMk=; b=NNkW+y22czWR2di5WZRuH75DuB++y0KRzEBwAtbJX/ApgsQcgSPb3quzlkaqxW2Uaf KeaR54WiDKRcaY8foxYnaiAodyhRR6sXe+wQiRCblQ5b+0XyR7MrJ2BZ82LEXWIvPtRn 00fPTpZSoHBnjDGhfOQYtBlNk6Qrg6RaCEVaOkcDNq3KtY7ECqAVKVEEaSs5omPfKIgF s8EIi7HhMtMue683EYIWK4yER8ZlHmBJbNB30EnZ1wLSEiiE8Nl40lNn2iH3Futrw2Rb ELtLniIMMqALrZmX3YMGa7I68+8N9XsDsSJI1+HdfMEJZL0lmvw8JoOava3p1I8Wp8a6 TlVg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=E6s3b+vp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from lipwig.vger.email (lipwig.vger.email. [23.128.96.33]) by mx.google.com with ESMTPS id e27-20020aa798db000000b00690c953e024si4629681pfm.119.2023.10.30.03.03.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Oct 2023 03:03:07 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) client-ip=23.128.96.33; Authentication-Results: mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=E6s3b+vp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id D7790804C6D8; Mon, 30 Oct 2023 03:03:04 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233260AbjJ3KCq (ORCPT + 31 others); Mon, 30 Oct 2023 06:02:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54042 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232912AbjJ3KBD (ORCPT ); Mon, 30 Oct 2023 06:01:03 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D901F10CF; Mon, 30 Oct 2023 03:00:34 -0700 (PDT) X-UUID: 26059752770b11eea33bb35ae8d461a2-20231030 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=S+BFsscpOYXgIjZ4vvUEbFaZKileuAcJkmvyZC22tyQ=; b=E6s3b+vpYiJaTAyWiOaEt/QRMZK6LaFomRufwAm0DzSkMY5Nc+04XrHxARQ8cXdE/oHW2qj+hj/AVQW1PdPpcR3d+l6WkE3R9198noM5zlOf+Ei0c69v86+rK06HJdwgKP/Z3i8o8WoYs5C78/u5+v0CG2Pvc/MJCYHqvHmwUYc=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.32,REQID:f6d73db9-c3b7-4783-bf2f-1e6a88e11cee,IP:0,U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:5f78ec9,CLOUDID:e0390e72-1bd3-4f48-b671-ada88705968c,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:102,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV:0,LES:1,SPR:NO, DKR:0,DKP:0,BRR:0,BRE:0 X-CID-BVR: 0 X-CID-BAS: 0,_,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 26059752770b11eea33bb35ae8d461a2-20231030 Received: from mtkmbs10n1.mediatek.inc [(172.21.101.34)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 773433683; Mon, 30 Oct 2023 18:00:26 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 30 Oct 2023 18:00:25 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 30 Oct 2023 18:00:25 +0800 From: Moudy Ho To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mauro Carvalho Chehab , Matthias Brugger , AngeloGioacchino Del Regno , Hans Verkuil CC: , , , , , , Moudy Ho Subject: [PATCH v8 12/16] dt-bindings: display: mediatek: color: add compatible for MT8195 Date: Mon, 30 Oct 2023 18:00:18 +0800 Message-ID: <20231030100022.9262-13-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231030100022.9262-1-moudy.ho@mediatek.com> References: <20231030100022.9262-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Mon, 30 Oct 2023 03:03:04 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781174304657545049 X-GMAIL-MSGID: 1781174304657545049 Add a compatible string for the COLOR block in MediaTek MT8195 that is controlled by MDP3. Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/display/mediatek/mediatek,color.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml index f21e44092043..b886ca0d89ea 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,color.yaml @@ -26,6 +26,7 @@ properties: - mediatek,mt2701-disp-color - mediatek,mt8167-disp-color - mediatek,mt8173-disp-color + - mediatek,mt8195-mdp3-color - items: - enum: - mediatek,mt7623-disp-color From patchwork Mon Oct 30 10:00:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TW91ZHkgSG8gKOS9leWul+WOnyk=?= X-Patchwork-Id: 159640 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp2095911vqb; Mon, 30 Oct 2023 03:05:57 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF0h6LpkCcigXOt4sgoPr1V7G6SzMsu8AJcRb/8f7Ge6SydWthWFmQUVxUFi2AobDZfIo5b X-Received: by 2002:a05:6a00:1a86:b0:6b8:2ef3:331d with SMTP id e6-20020a056a001a8600b006b82ef3331dmr7823110pfv.10.1698660356726; Mon, 30 Oct 2023 03:05:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698660356; cv=none; d=google.com; s=arc-20160816; b=OzayX6H576ovZ13GWxJ+iZqtd/UJQzeGg+01rsTt9AEyWe7Km7MsZc897mFM6MfMM0 cqpkasBOlZ7PYgO/Y03udmvdvyjdzosIACqmRAqeSTtUS4VJCNBvEpnByQHdcFPjpTT4 M74K3JNGihSoJOENIimtvLQsSPMdrF8OdgjApUjJmHo8shp7Yr4h2Z8DUrwj7+rDCA/O 67s+BdYpz+5n9GhjT2tLKIlbD9qTRLDgqIKWSZzvX5q46kcH69hpa9Nfof689WdM2rjw 63ENV7U8tGr6DDhNpvnMjUFAonEps6NG/J8VkbTPKAo02eyklYjIQpMfGaJAGE0jRG89 bz1Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=FTZqwD/20ghPILDsRmA6p9FFef8yR//zyhkrO7qqtPo=; fh=e0RlLHzlztEJgFr1G5iUAfmLhro7zrN0SmKLmnTwLIM=; b=jRMPNHnzf5aoRp59UsZLVGPIMtQgP2Ybjd2QSBZjCHI55IRSucH0Q58YIaIGdoAZcq RMtpd3xvPI8EyOT9/u9u/lOBUP4iblPXhLSZD2myYcmASW73E34EWttHC4YcK7Ux0v6E 8IlrC+T9Mj8GV8un9PQojok/zIP6X4ceKuizXb9c+JiHg7cTbpfWzy6jd+QQQSPtYKsU iWpPoU1B7oadACJV3Oudtj/MQHW0u6kXIf5sGR9sWjObWzYGZHZGqy4Iu40v53xdox79 Y99t5Bc4+F82dR7M6wYHHXBCFlbyPob1dTt+uVGiAxlJr9c0Mwrsd2gwXumf4pQa1W9K zIaA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=qZcELl7I; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from howler.vger.email (howler.vger.email. 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Mon, 30 Oct 2023 18:00:25 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by MTKMBS14N1.mediatek.inc (172.21.101.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 30 Oct 2023 18:00:25 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 30 Oct 2023 18:00:25 +0800 From: Moudy Ho To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Mauro Carvalho Chehab , "Matthias Brugger" , AngeloGioacchino Del Regno , Hans Verkuil CC: , , , , , , "Moudy Ho" Subject: [PATCH v8 13/16] dt-bindings: display: mediatek: merge: add compatible for MT8195 Date: Mon, 30 Oct 2023 18:00:19 +0800 Message-ID: <20231030100022.9262-14-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231030100022.9262-1-moudy.ho@mediatek.com> References: <20231030100022.9262-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--1.516100-8.000000 X-TMASE-MatchedRID: jhJi18RLqAImeoNhEXvE7GNW0DAjL5p++OI6XsK3BWHfUZT83lbkEA0F DzFL1GEo4vM1YF6AJbbCCfuIMF6xLSdET58jp62StOboac408wrTZLRnjJe5lyLduB+YTr2F4Ls gnyEXJ/7GKlgywFgEgrWewVTTuN2MaMbTUW726amDmxjMOlD4FRbCe0yH6xqWgITnGkK0NFNRsk XKHhdfKpij9M86UwHhsKHfMTjCprwNQJGvyiKf6Q== X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--1.516100-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 3E0EDB0E25AFA84E5638703EB97B25B6C3DBCFE617571E71083A4CAC617E35922000:8 X-MTK: N X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on howler.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Mon, 30 Oct 2023 03:04:59 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781174482600056893 X-GMAIL-MSGID: 1781174482600056893 Add a compatible string for the MERGE block in MediaTek MT8195 that is controlled by MDP3. Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/display/mediatek/mediatek,merge.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml index eead5cb8636e..401498523404 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,merge.yaml @@ -24,6 +24,7 @@ properties: - enum: - mediatek,mt8173-disp-merge - mediatek,mt8195-disp-merge + - mediatek,mt8195-mdp3-merge - items: - const: mediatek,mt6795-disp-merge - const: mediatek,mt8173-disp-merge From patchwork Mon Oct 30 10:00:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TW91ZHkgSG8gKOS9leWul+WOnyk=?= X-Patchwork-Id: 159626 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp2094372vqb; Mon, 30 Oct 2023 03:03:12 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH4jAe1s4miZYYU8jB7CdKWgZl5t45aZ1KjoAuhwFrOETqfmYDRhbK0S5vUbKWVzkYE545D X-Received: by 2002:a17:902:f214:b0:1cc:32df:427a with SMTP id m20-20020a170902f21400b001cc32df427amr5420861plc.27.1698660192422; Mon, 30 Oct 2023 03:03:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698660192; cv=none; d=google.com; s=arc-20160816; b=yD5YBHF9FCDDC8WBWvK/QUvsa7Z92xnORTY8td7LUNcQtHKOu2OYbF5VSH8N1v6SkO xBs+JWFe7Q3y8BEovaK1T+iZzmm1by5gygs4UNhIJ9jMAVfxVEFVrj7vqJquWkvY/8eB B4UaON7dzjlF18gx3QZuikcSCDEJIoFQIX6Ce67Oj+j4UuSq/Z1WcAbxFKEq+QoTgyT4 VVmnYph/XD7BaI2/rh42gXZVn7JPe5THdBvjAvt+iPk+yztpzSgg6t2Oo61kwil3SgLG 7ewm+gQX/NQE0aLrlLAP0LqSUSWttXgP2ncFxlorQUOIkeHxxhH5F/F/d5mmCE/C4C9K Yv1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=CZfwX/wsWCkwVK0PMNBkW/bjKkWMLaDfZFL2RraVoKE=; fh=e0RlLHzlztEJgFr1G5iUAfmLhro7zrN0SmKLmnTwLIM=; b=kKqiUe+Ko+BtTI0M8Rv9Bg2Utye4nID5eZ1mMTKvqcQ7Ykxj7wx9BkhTcvfIRS/7lX DwlrjCoYTLOZaQlYMAE9VhFxFbCEVFCp0dwXX+lmgRe6HIlPgSI+kfk2oTwXmr9ojun2 7GkSviGeL4FObiiQBS0xOfY8v2anTktuHPB+jjhOEUpdCiBUOsqzt8JwgahAqXEdX7JU tjVcni7HhHYJ8g4j0+57LYeOGTr6ryDNyhGtyH+v8nwI4jmTIb0seEdHwH55/aMCgNbt G4KAO3n8kQBdxO3JTvxaiIzi+eju0pRz5KF114MFbF/zBMO0kwt3I6WQJEuNtKVN8S9w 2Etw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=fIQaJzK8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from snail.vger.email (snail.vger.email. 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Mon, 30 Oct 2023 03:02:48 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781174310052446195 X-GMAIL-MSGID: 1781174310052446195 Add a compatible string for the OVL block in MediaTek MT8195 that is controlled by MDP3. Signed-off-by: Moudy Ho Reviewed-by: AngeloGioacchino Del Regno Acked-by: Krzysztof Kozlowski --- .../devicetree/bindings/display/mediatek/mediatek,ovl.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml index 3e1069b00b56..c471a181d125 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml @@ -26,6 +26,7 @@ properties: - mediatek,mt8173-disp-ovl - mediatek,mt8183-disp-ovl - mediatek,mt8192-disp-ovl + - mediatek,mt8195-mdp3-ovl - items: - enum: - mediatek,mt7623-disp-ovl From patchwork Mon Oct 30 10:00:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TW91ZHkgSG8gKOS9leWul+WOnyk=?= X-Patchwork-Id: 159636 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp2094858vqb; Mon, 30 Oct 2023 03:03:57 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEoK3IJJGJe+XxWpKlXio6iaWCjfqn5AEpIqnFU28O+2UBy+DIS4pSV1EFJq7Ca1aeRdieP X-Received: by 2002:a17:90a:800b:b0:27d:492e:137a with SMTP id b11-20020a17090a800b00b0027d492e137amr6385475pjn.45.1698660236703; Mon, 30 Oct 2023 03:03:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698660236; cv=none; d=google.com; s=arc-20160816; b=ge7UdUgzLiiRMeHXrY7kp37dK2D97wv2Yirw6Vl2n/hfF2e9iheqLCpCthbmSGIC2g pXfTjguZvY5xh6wNyuAY4IckWDBIws8W8BbD1CEKVDySOnamFg8e2ygfQ3zfHHZtO56/ StCKYG4ukarZvAQnF8enSHWw8qRRiBMxZ+terAWt9WTuLR4nJ4m7lok3ZTgCaFEdEvb7 xnOuh3f8NW0qaHJrUAmYuzjNaTa97nSG7d5UF+rZVpHdrKrQvYx8ELq+B/QF1iVfgkST y29I6pK41ZVI5T0GlGPpOcoGeL9rYovrjRajMlicXQFuM32m7gXiyPGhqEg+5mcKBgih RsKA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=tJf5yBrmP9+h3QbyKaZHSTjQbagz9H0rJQiO4PcgBeM=; fh=N25l34UKybvwssildkJfWZzd7U86IAOGhJYPnp0TxMk=; b=PK5LjFmhI7g8U0rbpASya6jFCArr3Il0b9u28+vu/gVNz2d+qIEQzhuvxq+1l4CYoT YLr5BDebHUQDNz+sRU3AVhzCLC6JgDELgwBoeXSZeZgJ7yQAxWDJB6DItX3JiSuKjYfU hDmJYlT1lwRK77lLeQ2CHHI1rqhsG0OTJCQ0yR15JGRFTZozz4V/G2Bz5hS9vcybJ0pp F0cE9JjSQsBb3E0ciLCZsluXtHyBLpzrrwC3h3F8uk9IHArtjtpqgyjKcA55jf3aaqmT 8qFGOm63qnBN/aCknOM3iRs/olUt7ML4sIKZ5ab+cj14cq6a2fJnnJHStBXOt3WeH2iB r+Aw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=hPKuNV7+; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from pete.vger.email (pete.vger.email. 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Signed-off-by: Moudy Ho Reviewed-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno --- .../display/mediatek/mediatek,split.yaml | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml index a8a5c9608598..e4affc854f3d 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,split.yaml @@ -23,6 +23,7 @@ properties: oneOf: - enum: - mediatek,mt8173-disp-split + - mediatek,mt8195-mdp3-split - items: - const: mediatek,mt6795-disp-split - const: mediatek,mt8173-disp-split @@ -38,6 +39,21 @@ properties: the power controller specified by phandle. See Documentation/devicetree/bindings/power/power-domain.yaml for details. + mediatek,gce-client-reg: + description: + The register of display function block to be set by gce. There are 4 arguments, + such as gce node, subsys id, offset and register size. The subsys id that is + mapping to the register of display function blocks is defined in the gce header + include/dt-bindings/gce/-gce.h of each chips. + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + items: + - description: phandle of GCE + - description: GCE subsys id + - description: register offset + - description: register size + maxItems: 1 + clocks: items: - description: SPLIT Clock @@ -48,6 +64,17 @@ required: - power-domains - clocks +allOf: + - if: + properties: + compatible: + contains: + const: mediatek,mt8195-mdp3-split + + then: + required: + - mediatek,gce-client-reg + additionalProperties: false examples: From patchwork Mon Oct 30 10:00:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?TW91ZHkgSG8gKOS9leWul+WOnyk=?= X-Patchwork-Id: 159621 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp2094026vqb; Mon, 30 Oct 2023 03:02:39 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGVpSi4WsCgYOQ+j1Im76eZrRrlCwSFd63PL3PM74GPapY21BX59IkmGyZ1fFU0eGV4onbC X-Received: by 2002:a05:6871:5a87:b0:1e9:dd69:2fc1 with SMTP id oo7-20020a0568715a8700b001e9dd692fc1mr13813721oac.7.1698660159627; Mon, 30 Oct 2023 03:02:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698660159; cv=none; d=google.com; s=arc-20160816; b=TVVh+Mava4SJl6dGfnZnSGXhA+sFMourkUXTLI9L74v5jqZBYOX0Bgv6sprNBNrcnV sefBSiCLXQLGgYSBE4ms+gW1jPV0LI0lyNjGoUB12zZaW24cpY1yIBwbci2D8gEbEawA AXdkiJ2xEWbcad3+fe83M3d4KsK85nUQL6A38/aHJjTiocXM2XronsraJ8QIl12zC1Dd oNkuncWqp/PVOvDrSkFd97qEvPmLgbpl4rnUZNIM3Ga15Bz+tHofWWJrf5DviVEvj0wD Enbbh5Vi1yRXYdOPfW7Mj6KhTkno1COausFlgnhx8NhsTlBW346guNi6lPh5w8EB9wCJ V5OQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=sTdqgndZioahB36TamwdXkWsk/lwWHQXh9oJU7H/fNE=; fh=e0RlLHzlztEJgFr1G5iUAfmLhro7zrN0SmKLmnTwLIM=; b=luCNV/2VajiKxJMorjhhstGCNmckH+W4oYoTFLwWuUv15iPgDndtl+ZUBGhukT9CIQ 2EdTuCgb8YSAhf6T4GM9gOxnYNWiP5SNF07+ciTjJWdOlQpCjO2AGO0H9AR5mAKky+K0 2Q9uxxgVoLdiX9R55U+pyKFS0p6uNHDdj6Q6sGpfIH7Nqu0B0wL5xVak9whqmkgcb9sv uNl3bamqn9iWgHcNU6oxQ4rRT0RU6pdeGBvIRna4Z9QN3gncoY9dVv6he7FsnZ1CDfGG nyUoJhY3lijY3MuOjPBpxj8J3KrxoXQxrYAO97xW0FaHFa4TFadwIJ051eo2sOZDz2UI mixw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@mediatek.com header.s=dk header.b=RNb6Wbon; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=mediatek.com Received: from snail.vger.email (snail.vger.email. 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Mon, 30 Oct 2023 18:00:26 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.26; Mon, 30 Oct 2023 18:00:25 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1118.26 via Frontend Transport; Mon, 30 Oct 2023 18:00:25 +0800 From: Moudy Ho To: Chun-Kuang Hu , Philipp Zabel , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Rob Herring , "Krzysztof Kozlowski" , Conor Dooley , Mauro Carvalho Chehab , "Matthias Brugger" , AngeloGioacchino Del Regno , Hans Verkuil CC: , , , , , , "Moudy Ho" Subject: [PATCH v8 16/16] dt-bindings: display: mediatek: padding: add compatible for MT8195 Date: Mon, 30 Oct 2023 18:00:22 +0800 Message-ID: <20231030100022.9262-17-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20231030100022.9262-1-moudy.ho@mediatek.com> References: <20231030100022.9262-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-TM-AS-Product-Ver: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-AS-Result: No-10--1.396600-8.000000 X-TMASE-MatchedRID: tiRXYRqWr+smeoNhEXvE7APZZctd3P4Bw8djaG0FrZsCsxyhR8y7CcWF IdIOy0D44vM1YF6AJbZhyT3WNjppUtAtbEEX0MxBxEHRux+uk8ifEzJ5hPndGUWfnWTctzBf+OB ug60jVLXJBEI9NAtDYW2HFo0yIP2iw8b/NMMrngvXDpEFsZAfSZZpMVRjqqOQsSC3YENW09G2mp J7z7tekHmVKZusLp922v9OjYWA2uMMswg45VMfPadst5iAforfVlxr1FJij9s= X-TM-AS-User-Approved-Sender: No X-TM-AS-User-Blocked-Sender: No X-TMASE-Result: 10--1.396600-8.000000 X-TMASE-Version: SMEX-14.0.0.3152-9.1.1006-23728.005 X-TM-SNTS-SMTP: 97323CFA7FE59B36D41D87ED604BB08D57D30C3A2D2979CFDBFAA5FDCD476C4E2000:8 X-MTK: N X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_PASS, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Mon, 30 Oct 2023 03:01:43 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781174275824087744 X-GMAIL-MSGID: 1781174275824087744 Add a compatible string for the PADDING block in MediaTek MT8195 that is controlled by MDP3. Signed-off-by: Moudy Ho Acked-by: Rob Herring --- .../bindings/display/mediatek/mediatek,padding.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml index db24801ebc48..19858d826808 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,padding.yaml @@ -20,7 +20,9 @@ description: properties: compatible: - const: mediatek,mt8188-padding + enum: + - mediatek,mt8188-padding + - mediatek,mt8195-mdp3-padding reg: maxItems: 1