From patchwork Mon Oct 30 09:47:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 159583 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp2088363vqb; Mon, 30 Oct 2023 02:48:46 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHxWu9ez6hNWfI/tm8rzfgFmE+ZyC+FNyo0E48HQ22jb68rW8witmo1amjwxPP4wisnbjM8 X-Received: by 2002:a54:448b:0:b0:3af:d750:16b0 with SMTP id v11-20020a54448b000000b003afd75016b0mr10024475oiv.25.1698659326438; Mon, 30 Oct 2023 02:48:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698659326; cv=none; d=google.com; s=arc-20160816; b=Hl3jBKOVq7FD+yzPFdthvlYF7BcKU2RDqRYaNkvVofAtlN2QNzb0oIOjvV7XewegYH IXXRLxQl2dzZy7NayjR4lXsdv7Fw8gITHc2rL8IRCnlnCAwRhZwjEA/uOjhjLQvr9+sA jRRNA0CsYk1r+Izqz5JOTtFxF263nNoGEIu8unJwMr4yrNpd8hyeG1MfdTicZh481Mik mk4Jnvjr+XfnkJq5Fku6fvS6KH1zhvHBNFZOeNFNiy2ETcDoTp6hSUDceca0WletUSES HctcRORbK8xdC6+6svgxb11PmrQr69pXkQ7qaN8S/YHpl5CN5EForxG1vsOJXBcif4vZ EVUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=C7DYLGiKV5lE/9t/qTidkZ8vlSjIyxJ0rFmwZMM0b78=; fh=gfCwzJd/1auOn37TCxo+G+sybAUeroi1DxMWExaAZgc=; b=SyFqDz4dsbjvuBcHPnl9O4B4OWM1aXuVh6tBPsY3UOKE7sxWE7YF2TdvUrKPQKHyeu M8REYyU5l5JT2lnVA9al3iRtFBbphm5kqa918Oxwpj0W7nso/6Q2jH4C0bHcVf+q/sWL MWYBzSYpMH/lDqtdakIIr1jaz6P5rTGwNh1C/3ba3QxaG8ERTf41DOMs693jYKhPgq3R iqXGoSvZ9pYD6rkK4Z51YL/k8I6cV7+9IvJvFymuWrsOqK9VIFWb+6/6LC+wHONe1+60 u4kW1uetkEMZxJ/VpKBYnJO0uxb5/4weWyVKs9l0hqfpOVJd07ADEu1/9JG8sHLkNrva MYUw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=W9yejQX9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from groat.vger.email (groat.vger.email. [23.128.96.35]) by mx.google.com with ESMTPS id l5-20020a633e05000000b005b8f61fcba4si4565759pga.35.2023.10.30.02.48.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Oct 2023 02:48:46 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) client-ip=23.128.96.35; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=W9yejQX9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by groat.vger.email (Postfix) with ESMTP id F31C980990E1; Mon, 30 Oct 2023 02:48:43 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at groat.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232504AbjJ3Jrt (ORCPT + 31 others); Mon, 30 Oct 2023 05:47:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33582 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232432AbjJ3Jrr (ORCPT ); Mon, 30 Oct 2023 05:47:47 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E4CB6B6; Mon, 30 Oct 2023 02:47:44 -0700 (PDT) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 39U8OTEK000830; Mon, 30 Oct 2023 09:47:36 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : date : subject : mime-version : content-type : content-transfer-encoding : message-id : references : in-reply-to : to : cc; s=qcppdkim1; bh=C7DYLGiKV5lE/9t/qTidkZ8vlSjIyxJ0rFmwZMM0b78=; b=W9yejQX9h7a2VyLaB9ONcTVvR8ntckQN/qgieTiU4t63Tt7ZTNC0ImNcPnTFY9BzZfqF wEVYWGne21qa+7/UwrcKreqPsbUMc16Dp7TcScfBY47PBv7JPjnul4WUaaCMyMBrl9a7 I5Z2Jo2vOmJRoscwiKa239F1jHliXPmecIozjpz2GXWaR8LLgrPZbzqG3oXGhOjn6Vy3 2LBitj4QuQw7dFK92yb7FAnZFOc2ruNYnEZAOidCBbx99LHb/m99GCIkxO39ElqL/5q0 UubG9FrXtlbdjLIYgxRB1/Nb77PbDrFUBhhEgXykwq5Gqdlp5+YMc+XvHxkYibscllNK MA== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3u280jr9xa-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 30 Oct 2023 09:47:36 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 39U9lZB2030817 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 30 Oct 2023 09:47:35 GMT Received: from hu-kathirav-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Mon, 30 Oct 2023 02:47:29 -0700 From: Kathiravan Thirumoorthy Date: Mon, 30 Oct 2023 15:17:16 +0530 Subject: [PATCH 1/8] clk: qcom: ipq5332: drop the few nssnoc clocks MIME-Version: 1.0 Message-ID: <20231030-ipq5332-nsscc-v1-1-6162a2c65f0a@quicinc.com> References: <20231030-ipq5332-nsscc-v1-0-6162a2c65f0a@quicinc.com> In-Reply-To: <20231030-ipq5332-nsscc-v1-0-6162a2c65f0a@quicinc.com> To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Catalin Marinas , Will Deacon CC: , , , , , , "Kathiravan Thirumoorthy" X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1698659244; l=3486; i=quic_kathirav@quicinc.com; s=20230906; h=from:subject:message-id; bh=oVXi/0aUJi/5j62/P9dVUg1qaWfJBSnzkOdAng8wz00=; b=YV3QNxwuR6BcsLyU2vlvKyR9LiL9ZPWLst2yoXkjsSWUgWNV2t+YABaWJROo6/TTeAp3D74K5 //VCcxGISVgDekMQFbfXAjnuvlNezjoNoGocHENvKljAaRKvZH5IDlS X-Developer-Key: i=quic_kathirav@quicinc.com; a=ed25519; pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: rtvgygZ8iZFI4OowwggOsRtvolOJGNMa X-Proofpoint-ORIG-GUID: rtvgygZ8iZFI4OowwggOsRtvolOJGNMa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-30_08,2023-10-27_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 mlxlogscore=708 adultscore=0 spamscore=0 bulkscore=0 impostorscore=0 clxscore=1015 mlxscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2310240000 definitions=main-2310300074 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Mon, 30 Oct 2023 02:48:44 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781173401629131934 X-GMAIL-MSGID: 1781173401629131934 gcc_snoc_nssnoc_clk, gcc_snoc_nssnoc_1_clk, gcc_nssnoc_nsscc_clk are enabled by default and it's RCG is properly configured by bootloader. Some of the NSS clocks needs these clocks to be enabled. To avoid these clocks being disabled by clock framework, drop these entries. Signed-off-by: Kathiravan Thirumoorthy --- drivers/clk/qcom/gcc-ipq5332.c | 57 ------------------------------------------ 1 file changed, 57 deletions(-) diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c index f98591148a97..235849876a9a 100644 --- a/drivers/clk/qcom/gcc-ipq5332.c +++ b/drivers/clk/qcom/gcc-ipq5332.c @@ -1672,24 +1672,6 @@ static struct clk_branch gcc_nssnoc_atb_clk = { }, }; -static struct clk_branch gcc_nssnoc_nsscc_clk = { - .halt_reg = 0x17030, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x17030, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_nssnoc_nsscc_clk", - .parent_hws = (const struct clk_hw*[]) { - &gcc_pcnoc_bfdcd_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_nssnoc_qosgen_ref_clk = { .halt_reg = 0x1701c, .halt_check = BRANCH_HALT, @@ -2585,42 +2567,6 @@ static struct clk_branch gcc_snoc_lpass_cfg_clk = { }, }; -static struct clk_branch gcc_snoc_nssnoc_1_clk = { - .halt_reg = 0x17090, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x17090, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_snoc_nssnoc_1_clk", - .parent_hws = (const struct clk_hw*[]) { - &gcc_system_noc_bfdcd_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - -static struct clk_branch gcc_snoc_nssnoc_clk = { - .halt_reg = 0x17084, - .halt_check = BRANCH_HALT, - .clkr = { - .enable_reg = 0x17084, - .enable_mask = BIT(0), - .hw.init = &(const struct clk_init_data) { - .name = "gcc_snoc_nssnoc_clk", - .parent_hws = (const struct clk_hw*[]) { - &gcc_system_noc_bfdcd_clk_src.clkr.hw, - }, - .num_parents = 1, - .flags = CLK_SET_RATE_PARENT, - .ops = &clk_branch2_ops, - }, - }, -}; - static struct clk_branch gcc_snoc_pcie3_1lane_1_m_clk = { .halt_reg = 0x2e050, .halt_check = BRANCH_HALT, @@ -3330,7 +3276,6 @@ static struct clk_regmap *gcc_ipq5332_clocks[] = { [GCC_NSSCC_CLK] = &gcc_nsscc_clk.clkr, [GCC_NSSCFG_CLK] = &gcc_nsscfg_clk.clkr, [GCC_NSSNOC_ATB_CLK] = &gcc_nssnoc_atb_clk.clkr, - [GCC_NSSNOC_NSSCC_CLK] = &gcc_nssnoc_nsscc_clk.clkr, [GCC_NSSNOC_QOSGEN_REF_CLK] = &gcc_nssnoc_qosgen_ref_clk.clkr, [GCC_NSSNOC_SNOC_1_CLK] = &gcc_nssnoc_snoc_1_clk.clkr, [GCC_NSSNOC_SNOC_CLK] = &gcc_nssnoc_snoc_clk.clkr, @@ -3398,8 +3343,6 @@ static struct clk_regmap *gcc_ipq5332_clocks[] = { [GCC_SDCC1_APPS_CLK_SRC] = &gcc_sdcc1_apps_clk_src.clkr, [GCC_SLEEP_CLK_SRC] = &gcc_sleep_clk_src.clkr, [GCC_SNOC_LPASS_CFG_CLK] = &gcc_snoc_lpass_cfg_clk.clkr, - [GCC_SNOC_NSSNOC_1_CLK] = &gcc_snoc_nssnoc_1_clk.clkr, - [GCC_SNOC_NSSNOC_CLK] = &gcc_snoc_nssnoc_clk.clkr, [GCC_SNOC_PCIE3_1LANE_1_M_CLK] = &gcc_snoc_pcie3_1lane_1_m_clk.clkr, [GCC_SNOC_PCIE3_1LANE_1_S_CLK] = &gcc_snoc_pcie3_1lane_1_s_clk.clkr, [GCC_SNOC_PCIE3_1LANE_M_CLK] = &gcc_snoc_pcie3_1lane_m_clk.clkr, From patchwork Mon Oct 30 09:47:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 159582 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp2088275vqb; Mon, 30 Oct 2023 02:48:34 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF2/LMHZ3zCDkV+ys5wPRPJ3VzqtHR3KnVuAL/02BLxX7MXHri3hCiRQHrDKf+DuOvi7WJC X-Received: by 2002:a17:902:e806:b0:1bf:d92e:c5a7 with SMTP id u6-20020a170902e80600b001bfd92ec5a7mr8563053plg.28.1698659314007; Mon, 30 Oct 2023 02:48:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698659313; cv=none; d=google.com; s=arc-20160816; b=hQluR9elmM+Lzs5bvqLP20e5vrJ8AKicyfQ9OaQrA+3PFFDmemf7Dlb1oaGxiCOTnq hNdIgmGqQbRABCKCFlxL+OG29pEPdfaZq1/OnDM6bVyZbvMNtQwB1NnsHwAAb0KhzEZu EQVOS/h8P2UWEdNN5e37zIFrarKubi/PXkjwDdv7540sJ0qMWTsLiriPO2LgeNFs3UW8 Hs3o/DTaZFcnUn3c/K4oPlWccC/Lb+y66G35nGCca0SMLtzVA26+SX4eJS9smzVNqJ8y P/aWoITGuxokEsf8qKPXegfQklfD/s40Dl45Z/M0NBFqww+smH78A7vzs2fuY5lfE9js WCbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=6Uy1lHvNkZbFXTw54nBi6xD71h6W0UhVX/V3hiEankg=; fh=gfCwzJd/1auOn37TCxo+G+sybAUeroi1DxMWExaAZgc=; b=fZ2nZ5XJOssDT8dBCqoRraV7XkCY3e9XMDR7ROkrWG/lEW1KgFyK1NCFX/ZdBwpQFQ u8B/oslu9MRJdkSXrsUtbpqhzOlqZS16RR+eFL7rbPdf4Tx14RF+Ry1Gj/LeCRRXaFiD oaD5kUiIQ0+c9z6Bcjga1b+NXaqkiZYx+JlgLHqzwz03js+ZbkB0TpDwxAqhHMp+SJDI ygVoL/a47ept8riQmbjVulfbtfqDiDIP51I7rmW+8O/uq+38zhtFOpjRJjFH6mrSwAU7 m/UjEznj6i1rN5knCAXqkDEpdGvyLoM1Xc143EJksLtEj6vj9EBE/lp5kqa5DXULRBhW yo6g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=lRovHzCI; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from groat.vger.email (groat.vger.email. [23.128.96.35]) by mx.google.com with ESMTPS id a18-20020a170902ecd200b001c9c9514db7si4901617plh.604.2023.10.30.02.48.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Oct 2023 02:48:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) client-ip=23.128.96.35; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=lRovHzCI; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by groat.vger.email (Postfix) with ESMTP id C03FF80990D7; Mon, 30 Oct 2023 02:48:31 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at groat.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232609AbjJ3JsI (ORCPT + 31 others); Mon, 30 Oct 2023 05:48:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34514 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232596AbjJ3JsC (ORCPT ); Mon, 30 Oct 2023 05:48:02 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9344B103; Mon, 30 Oct 2023 02:47:54 -0700 (PDT) Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 39U70hNN026890; Mon, 30 Oct 2023 09:47:42 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : date : subject : mime-version : content-type : content-transfer-encoding : message-id : references : in-reply-to : to : cc; s=qcppdkim1; bh=6Uy1lHvNkZbFXTw54nBi6xD71h6W0UhVX/V3hiEankg=; b=lRovHzCI6gIUNv+GjVUoTBQegV9IhNs3ZNDK941nW+TopDjZ5V6A79rzUyTm+LavxJoQ ejz8JsC6yKx0EsvGw78/Zkv7SQ+AeqR53GekKFdlFUzI7W2Zeh/NR7bm4PTZVgyZPdmp BpxTVVjNQyp//wffdPkL9Z5MtveH1JANzype0ZbySPz19aurSv3+boSHqDzXu/bnkeVp vnCvsKwKrA+01sFU2Iph8zXF2HYsv2RaX6yDvRQtKOQQcOvbnWv1cPcK9821rFzZJM42 6oYg37eD2P7DdFoD4Olz3AxQUTsKWBzJXPPGIxwOJcDuRFQg7dsv50G1jDAh5m472/bO 1A== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3u0tphue0p-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 30 Oct 2023 09:47:42 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 39U9leNC031294 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 30 Oct 2023 09:47:41 GMT Received: from hu-kathirav-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Mon, 30 Oct 2023 02:47:35 -0700 From: Kathiravan Thirumoorthy Date: Mon, 30 Oct 2023 15:17:17 +0530 Subject: [PATCH 2/8] dt-bindings: clock: ipq5332: drop the few nss clocks definition MIME-Version: 1.0 Message-ID: <20231030-ipq5332-nsscc-v1-2-6162a2c65f0a@quicinc.com> References: <20231030-ipq5332-nsscc-v1-0-6162a2c65f0a@quicinc.com> In-Reply-To: <20231030-ipq5332-nsscc-v1-0-6162a2c65f0a@quicinc.com> To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Catalin Marinas , Will Deacon CC: , , , , , , "Kathiravan Thirumoorthy" X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1698659244; l=1324; i=quic_kathirav@quicinc.com; s=20230906; h=from:subject:message-id; bh=5t1crxdnVdF/q1ZP8avNT9Pk+9XUyieoSwwl5zLjqhY=; b=y6+m37yrQZAmeu84hHC9nSBmPpLl2tjh+iHq6kVChz1yQbr04XPntyMPFufyc/CaUB5scs0BX iRPqH1NCCeOAYsGB+zvZQxokNrbJ1rGOwuh0LswAOzJwXOb8nevVadx X-Developer-Key: i=quic_kathirav@quicinc.com; a=ed25519; pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Ec0Ovi4UWC_cZBJjT0P-pDkOxxIu8AK5 X-Proofpoint-GUID: Ec0Ovi4UWC_cZBJjT0P-pDkOxxIu8AK5 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-30_08,2023-10-27_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 mlxlogscore=764 spamscore=0 lowpriorityscore=0 malwarescore=0 phishscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 impostorscore=0 adultscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2310240000 definitions=main-2310300074 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Mon, 30 Oct 2023 02:48:31 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781173388681261443 X-GMAIL-MSGID: 1781173388681261443 gcc_snoc_nssnoc_clk, gcc_snoc_nssnoc_1_clk, gcc_nssnoc_nsscc_clk are enabled by default and it's RCG is properly configured by bootloader. Some of the NSS clocks needs these clocks to be enabled. To avoid these clocks being disabled by clock framework, drop these entries. Signed-off-by: Kathiravan Thirumoorthy --- include/dt-bindings/clock/qcom,ipq5332-gcc.h | 3 --- 1 file changed, 3 deletions(-) diff --git a/include/dt-bindings/clock/qcom,ipq5332-gcc.h b/include/dt-bindings/clock/qcom,ipq5332-gcc.h index 8a405a0a96d0..4649026da332 100644 --- a/include/dt-bindings/clock/qcom,ipq5332-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq5332-gcc.h @@ -55,7 +55,6 @@ #define GCC_NSSCC_CLK 46 #define GCC_NSSCFG_CLK 47 #define GCC_NSSNOC_ATB_CLK 48 -#define GCC_NSSNOC_NSSCC_CLK 49 #define GCC_NSSNOC_QOSGEN_REF_CLK 50 #define GCC_NSSNOC_SNOC_1_CLK 51 #define GCC_NSSNOC_SNOC_CLK 52 @@ -124,8 +123,6 @@ #define GCC_SDCC1_APPS_CLK_SRC 115 #define GCC_SLEEP_CLK_SRC 116 #define GCC_SNOC_LPASS_CFG_CLK 117 -#define GCC_SNOC_NSSNOC_1_CLK 118 -#define GCC_SNOC_NSSNOC_CLK 119 #define GCC_SNOC_PCIE3_1LANE_1_M_CLK 120 #define GCC_SNOC_PCIE3_1LANE_1_S_CLK 121 #define GCC_SNOC_PCIE3_1LANE_M_CLK 122 From patchwork Mon Oct 30 09:47:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 159584 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp2088383vqb; Mon, 30 Oct 2023 02:48:48 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEWiMIleJMbMzYbTCT4E1vAVDoYUR73oyIpT/NiE5FeaxSCg4eqJieqlgvC23KlCZL/xpTm X-Received: by 2002:a05:6a00:134c:b0:6ba:2ba7:b9cb with SMTP id k12-20020a056a00134c00b006ba2ba7b9cbmr11486217pfu.12.1698659328726; Mon, 30 Oct 2023 02:48:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698659328; cv=none; d=google.com; s=arc-20160816; b=lYQDVYsREESvmQynbm9jim/Cq9jIHOknX0pWHrPmwbMd9LtbYeTW9eKWkbRcZ9SUai vV3NWLm86EQW589qiYWOtUhELqod+uviUPcXm2H6jgdJBXOnp1l1mq9IpAgC2o6F3JLD apADKTjJWCUyx8nkco0sQY1Wk4839Ip1u4D9tLsDnhNraiZsBYSJiqJ0OQuETRo+HG29 d3txKKs7B47LfZWhPQgtXexNxMNBCQOenc7o8ugSXt4q16nX+5Onp23qkbRyjwfeLWDY rIFz/CN9RXs61H6Ieoves1HW/Aje0xkJ06TzJZUcRy78nRYH/k0Se/5TdChnxj6QvbtE JU4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=47a8Kd/di4nYBiraczXJIoewiBNTXFH+cVUpLiKQv/g=; fh=gfCwzJd/1auOn37TCxo+G+sybAUeroi1DxMWExaAZgc=; b=tC/d7v+vCG1yPPhdK8wxO1s5HWx3wJjFePntzQmbJz4Tqi+dYwp9YE3cb/GZ2TSRLq jvYh0MjMhRpNQxYIbLOZV6tzQIFL29/T8r+yOo5oiCfnZJNJjA0iio+dopFaNIxVk6KI gY7XJL+rstIFeZdhC8kDrAdhgHWgxoOst2yacVKqU8ghy2wGTkXV4lq2ouMpMidbqh6A b5Z6DXVtN8b8m9CdEGEdRalodr4Vm/4sfDGcVdyl7E52+SPPKzED56IYR4guDun1eei2 sugIjDbABX6duLSRfkDYbogefbPcSLP2kdPmAsQD+4AbQ6LXZD5phj3cFvcKGfo0CQDO JLFA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=GUPPtWOo; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from pete.vger.email (pete.vger.email. [2620:137:e000::3:6]) by mx.google.com with ESMTPS id l10-20020a056a0016ca00b00690d25b1991si4758801pfc.41.2023.10.30.02.48.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Oct 2023 02:48:48 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) client-ip=2620:137:e000::3:6; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=GUPPtWOo; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by pete.vger.email (Postfix) with ESMTP id 9EA6E80A998E; Mon, 30 Oct 2023 02:48:44 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at pete.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232491AbjJ3JsO (ORCPT + 31 others); Mon, 30 Oct 2023 05:48:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34446 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232624AbjJ3JsE (ORCPT ); Mon, 30 Oct 2023 05:48:04 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1F68A122; Mon, 30 Oct 2023 02:47:55 -0700 (PDT) Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 39U8JFDq005590; Mon, 30 Oct 2023 09:47:48 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : date : subject : mime-version : content-type : content-transfer-encoding : message-id : references : in-reply-to : to : cc; s=qcppdkim1; bh=47a8Kd/di4nYBiraczXJIoewiBNTXFH+cVUpLiKQv/g=; b=GUPPtWOoFOhxg7/5aka6hFC+4hB9NhOBPI8FAZNYuGr80DygEbGv69bc3Q0m6PVLYtZS +spg9w9pTNqb1b4NtrnwrTBv/vr4CXVR+Ykxv+WnyB47IC9u6b1UKtA2SdwGFi/nnChF M+JQd8s7/2tdECbIPd3qsyO1rQZ2w/dXJgbU3piJedV5gLXiZMHZd+ZpcQ6v0hxFV1/m FbUFl6xr2zr9LFFBBotLLopntc2lcB8XpS1wArk1CQTFzBjpBX8/6BGsmjDlntSIR2a5 AW5KwewhrUR8QTbTlsHvrx25a/aPl9TG0QTKSmHKs1CIPQE1LEFx7pvPD13MhKlhjHsa JQ== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3u0sw7ufpf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 30 Oct 2023 09:47:47 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 39U9lkTH027633 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 30 Oct 2023 09:47:46 GMT Received: from hu-kathirav-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Mon, 30 Oct 2023 02:47:40 -0700 From: Kathiravan Thirumoorthy Date: Mon, 30 Oct 2023 15:17:18 +0530 Subject: [PATCH 3/8] dt-bindings: clock: ipq5332: add definition for GPLL0_OUT_AUX clock MIME-Version: 1.0 Message-ID: <20231030-ipq5332-nsscc-v1-3-6162a2c65f0a@quicinc.com> References: <20231030-ipq5332-nsscc-v1-0-6162a2c65f0a@quicinc.com> In-Reply-To: <20231030-ipq5332-nsscc-v1-0-6162a2c65f0a@quicinc.com> To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Catalin Marinas , Will Deacon CC: , , , , , , "Kathiravan Thirumoorthy" X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1698659244; l=721; i=quic_kathirav@quicinc.com; s=20230906; h=from:subject:message-id; bh=7DHRVV4reBPtWLZAXBh6odJKBZeQj5TFKZRfh5Ysgj4=; b=EqqzTpiqeHfD9K83QVzTIkiN7DZZsPJBmUakXztMM2PE4S5CCmcvK3vi12fYPoG8TAQ6ohwSj 4PVmcel0zdiCqjkRge88icdvIj9IF9S9bGSP7s9nfgpoPQOhLI9Ex5A X-Developer-Key: i=quic_kathirav@quicinc.com; a=ed25519; pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: W3hrVZiwO44iw2X8e9IsJqPIq4TpabnS X-Proofpoint-GUID: W3hrVZiwO44iw2X8e9IsJqPIq4TpabnS X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-30_08,2023-10-27_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=985 clxscore=1015 phishscore=0 lowpriorityscore=0 spamscore=0 malwarescore=0 priorityscore=1501 adultscore=0 bulkscore=0 impostorscore=0 suspectscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2310240000 definitions=main-2310300074 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Mon, 30 Oct 2023 02:48:44 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781173404330396612 X-GMAIL-MSGID: 1781173404330396612 Add the definition for GPLL0_OUT_AUX clock. Signed-off-by: Kathiravan Thirumoorthy Acked-by: Krzysztof Kozlowski --- include/dt-bindings/clock/qcom,ipq5332-gcc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/dt-bindings/clock/qcom,ipq5332-gcc.h b/include/dt-bindings/clock/qcom,ipq5332-gcc.h index 4649026da332..486b6cf2e916 100644 --- a/include/dt-bindings/clock/qcom,ipq5332-gcc.h +++ b/include/dt-bindings/clock/qcom,ipq5332-gcc.h @@ -176,6 +176,7 @@ #define GCC_PCIE3X1_0_PIPE_CLK_SRC 170 #define GCC_PCIE3X1_1_PIPE_CLK_SRC 171 #define GCC_USB0_PIPE_CLK_SRC 172 +#define GPLL0_OUT_AUX 173 #define GCC_ADSS_BCR 0 #define GCC_ADSS_PWM_CLK_ARES 1 From patchwork Mon Oct 30 09:47:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 159585 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp2088450vqb; Mon, 30 Oct 2023 02:49:03 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH7tnOQWnw0XhBBPgEcJztj1IQjUj9QY1LR74APRk+InAh5CztY0sc35lVhjD7re5MKFMVI X-Received: by 2002:a05:6808:2394:b0:3a6:fb16:c782 with SMTP id bp20-20020a056808239400b003a6fb16c782mr13519645oib.30.1698659343547; Mon, 30 Oct 2023 02:49:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698659343; cv=none; d=google.com; s=arc-20160816; b=gqDggmASaBUr56pRIDduKkplZ1ekgUinLVdF1uOsrWSjL8daj9key8qyDCKGxs+eRa R/nsLnFJY8lnV/3coyy75IZDvTKENROLwGIEXWBbwyCbd5b+ud9swjN6k0lCeb/5cOzL ECkKvoaLk+SmS5P5YUMb7XIFQrWHwLRzhYUZHzRNT92uu6uYH8yIo0MJwLyLRjLHSTfn UZJRN3uUd/JiL1CVf5GvIGqxi9SAKq8UAJI5dkk1XhNrjopgydWaYsAjLH6QL08aobGh z8ropyQqPI8Lqz06OnOUYKJfW4ZhfHXI5VmvDIfrSa2p+lqU9GUrvQ6sCzQwMsve/I4K gv8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=kT3ioBmRWCOTcK8bn7Du1m7PCwGBwI/GHElbSnTpe7U=; fh=gfCwzJd/1auOn37TCxo+G+sybAUeroi1DxMWExaAZgc=; b=W3iqrJchJbaGW4cSKh+pNEOW3KZutzUrxXFvMfL4T7UqqdPWWyRuF7Ji0ZiH8uMB/m 2ZKRvphiEomu5YLYiRqzJq+sBM5w+V9m9ifaDAPTz+YjJjvyira4Kq8JeMcF53IdLTBB 2PKoVnKd24IeWCdkuwUmW9KY9JLx0Whm+Wc7h3QASgeNa4aW1Pon8g8Xf0cIj/pHPDbV BvvhIUrkv8Ykk93kdZOL5B79B+8oVQ98TrmZ74WmtjrrZ7T8RwfCMAZZeudFw9Et8izr i8SHaH3+99j92GJfu2wcqm8Wbc/xqRT8QQACPwBKEG6LbKhMa95L9C8M9c0CZ1fwM5mz kVtw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b="HV8P/K1/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from groat.vger.email (groat.vger.email. [2620:137:e000::3:5]) by mx.google.com with ESMTPS id l4-20020a056a00140400b006bca1246564si4676805pfu.271.2023.10.30.02.49.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Oct 2023 02:49:03 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) client-ip=2620:137:e000::3:5; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b="HV8P/K1/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by groat.vger.email (Postfix) with ESMTP id 09CD680990DC; Mon, 30 Oct 2023 02:49:01 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at groat.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232700AbjJ3Jsf (ORCPT + 31 others); Mon, 30 Oct 2023 05:48:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59858 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232698AbjJ3JsP (ORCPT ); Mon, 30 Oct 2023 05:48:15 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A4FD7D44; Mon, 30 Oct 2023 02:48:01 -0700 (PDT) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 39U7KEmP025179; Mon, 30 Oct 2023 09:47:52 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : date : subject : mime-version : content-type : content-transfer-encoding : message-id : references : in-reply-to : to : cc; s=qcppdkim1; bh=kT3ioBmRWCOTcK8bn7Du1m7PCwGBwI/GHElbSnTpe7U=; b=HV8P/K1/6xsE27E53t4w6YWkkA7r0MvUoDjdTzR3sxK8SYnoQPuls5nP8mBe03cwVLSP sxTZynAPt5/3xlGN5ihmfYz2TY+C2oTYsQtVi/A63xrFeww+P7IFAg0ikEsVHspk8Rl3 +T3NqMegWT6TkRFtjfZqxH9Nc7WK1KFynVEdWLdi1lNzQ0+7qiJF4cjPrILT7RxbxWoD rt3pGeBmJzZwAtZTeA1ITKonjbcJ5q5PuWSP/QfZDQth8geHi4j66UkLnRIjDGNVKUkq zzUculzACxjquHpM8rev2rFvLLk4Mkv1jO+Qkz2YKDVQfmp1R+8qK+CONVjSYr0AYGxh +A== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3u280jr9xw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 30 Oct 2023 09:47:52 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 39U9lqth031375 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 30 Oct 2023 09:47:52 GMT Received: from hu-kathirav-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Mon, 30 Oct 2023 02:47:46 -0700 From: Kathiravan Thirumoorthy Date: Mon, 30 Oct 2023 15:17:19 +0530 Subject: [PATCH 4/8] clk: qcom: ipq5332: add gpll0_out_aux clock MIME-Version: 1.0 Message-ID: <20231030-ipq5332-nsscc-v1-4-6162a2c65f0a@quicinc.com> References: <20231030-ipq5332-nsscc-v1-0-6162a2c65f0a@quicinc.com> In-Reply-To: <20231030-ipq5332-nsscc-v1-0-6162a2c65f0a@quicinc.com> To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Catalin Marinas , Will Deacon CC: , , , , , , "Kathiravan Thirumoorthy" X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1698659244; l=1460; i=quic_kathirav@quicinc.com; s=20230906; h=from:subject:message-id; bh=AMEeKniRFTiKycBkLXrAU9OUuKWH7z1VWO4bz7GJqok=; b=IE91GTSuRAnjGTi7zrKCc1axwVaHDJYCRByBpSDNJ3CMMrjEIzRD7XDnZf1GPd4a9nDg+XPhk fobq8qr/5jVBHgMwmBiPBewQX+e8aK8MOLxyqOro6mC5NzMoFYEICQW X-Developer-Key: i=quic_kathirav@quicinc.com; a=ed25519; pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: abVPL1GMMoazH5cfxe3-p4mOWFC_wi7M X-Proofpoint-ORIG-GUID: abVPL1GMMoazH5cfxe3-p4mOWFC_wi7M X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-30_08,2023-10-27_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 lowpriorityscore=0 priorityscore=1501 phishscore=0 mlxlogscore=999 adultscore=0 spamscore=0 bulkscore=0 impostorscore=0 clxscore=1015 mlxscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2310240000 definitions=main-2310300074 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Mon, 30 Oct 2023 02:49:01 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781173420084880914 X-GMAIL-MSGID: 1781173420084880914 Add support for gpll0_out_aux clock which acts as the parent for certain networking subsystem (NSS) clocks. Signed-off-by: Kathiravan Thirumoorthy --- drivers/clk/qcom/gcc-ipq5332.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/clk/qcom/gcc-ipq5332.c b/drivers/clk/qcom/gcc-ipq5332.c index 235849876a9a..966bb7ca8854 100644 --- a/drivers/clk/qcom/gcc-ipq5332.c +++ b/drivers/clk/qcom/gcc-ipq5332.c @@ -87,6 +87,19 @@ static struct clk_alpha_pll_postdiv gpll0 = { }, }; +static struct clk_alpha_pll_postdiv gpll0_out_aux = { + .offset = 0x20000, + .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS], + .width = 4, + .clkr.hw.init = &(struct clk_init_data) { + .name = "gpll0_out_aux", + .parent_hws = (const struct clk_hw *[]) { + &gpll0_main.clkr.hw }, + .num_parents = 1, + .ops = &clk_alpha_pll_postdiv_ro_ops, + }, +}; + static struct clk_alpha_pll gpll2_main = { .offset = 0x21000, .regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_STROMER_PLUS], @@ -3393,6 +3406,7 @@ static struct clk_regmap *gcc_ipq5332_clocks[] = { [GCC_PCIE3X1_0_PIPE_CLK_SRC] = &gcc_pcie3x1_0_pipe_clk_src.clkr, [GCC_PCIE3X1_1_PIPE_CLK_SRC] = &gcc_pcie3x1_1_pipe_clk_src.clkr, [GCC_USB0_PIPE_CLK_SRC] = &gcc_usb0_pipe_clk_src.clkr, + [GPLL0_OUT_AUX] = &gpll0_out_aux.clkr, }; static const struct qcom_reset_map gcc_ipq5332_resets[] = { From patchwork Mon Oct 30 09:47:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 159586 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp2088491vqb; Mon, 30 Oct 2023 02:49:11 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEIINylbAscUMd/hXH6L5CMzIJ9ru+v/YvouRP09HeQzXNEfSsWVj0AXLc5G+SmPKAgFIUa X-Received: by 2002:a17:903:228b:b0:1cc:474a:ddc9 with SMTP id b11-20020a170903228b00b001cc474addc9mr1805939plh.28.1698659351090; Mon, 30 Oct 2023 02:49:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698659351; cv=none; d=google.com; s=arc-20160816; b=iD/6r8LLAyQbEC+AGxmPofA5pGzK/1Mx8WBSfmjbEpHTEKNdsvTKpsQBc41BkzqzSX ORKiU9gdkE164tpTt3sYRy2gwfx6DPrCVSioC0LFnCOgWtCBn/dSk/pRFNLFfGJtreKG t/7/+dZIb17bmh1UtQV45doO7FYVNtqmTaiN7Xpd6aiot541Nvnqg0o/KWsr+gy3cHC9 IauNNyvMhxAq7Gv/OJu7kMDMQ9qrj8WwEwPccMGhj0WbByEuykW3j6r/c8Wks6K8nXfJ uWyOqYlHJ6BTUVrdVRVgFmR5hcUeGLPJwkryyX1/EaWp/mFvbwLKutkVYLtMeuURvK5T hLVQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=nBUwvv1TU5njiVfmxmIc5DjWqcQHCwam9AG/snVJj/E=; fh=gfCwzJd/1auOn37TCxo+G+sybAUeroi1DxMWExaAZgc=; b=UO8UMXRa5Lv3s9JxLw4Q4pJwr6S2w5qprDRkEWQ6ZP2WrcNZHUar6rLm61c5PI6yT2 SO5GJxajG9qO+2d8A/CplJiT3wPkMtarU3q39u7VZ3TEKfINHyMmSVMh13rlDYZSTBIp GFzV7hUGDOx788+l22cykgH20fIoksv6wfc5biOIJKaJAd0uNhyjPLpAMzBLVRKV06hJ UC+EgB/Jod7h+DYEwek10r2drHZMic4feUSpV3Mf+jt/ULf/TODy8g8nAp2+WhczFWoa x0EYJA8Kdnslkwf+WChNIM+Bzt0Br7wD2U1LNlMCHd4SGsPWAr7ExZkL0H0GjEyoDT6J w0qA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=cbRLRpx0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from groat.vger.email (groat.vger.email. [2620:137:e000::3:5]) by mx.google.com with ESMTPS id i16-20020a17090332d000b001c9db56c09asi96349plr.144.2023.10.30.02.49.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Oct 2023 02:49:11 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) client-ip=2620:137:e000::3:5; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=cbRLRpx0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by groat.vger.email (Postfix) with ESMTP id 26B1A80990E1; Mon, 30 Oct 2023 02:49:08 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at groat.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232648AbjJ3Jst (ORCPT + 31 others); Mon, 30 Oct 2023 05:48:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47994 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232607AbjJ3Js0 (ORCPT ); Mon, 30 Oct 2023 05:48:26 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4BC99119; Mon, 30 Oct 2023 02:48:08 -0700 (PDT) Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 39U7LHWj021956; Mon, 30 Oct 2023 09:47:59 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : date : subject : mime-version : content-type : content-transfer-encoding : message-id : references : in-reply-to : to : cc; s=qcppdkim1; bh=nBUwvv1TU5njiVfmxmIc5DjWqcQHCwam9AG/snVJj/E=; b=cbRLRpx0FJ3Doa+0JuZYb2JNKM7Zgy/bpWJFx5umKGmGFB/4NJfM0tatbObHy3DmSMX4 WNN1ITe48vPK3v4DVBBSrmPZM5lmHV4822By9Fd95jNaSJy6mWfIUN0p4VM0/fCd53s4 oZt2b+0DZ4GGpM+UPpga61yvLVnPqwqvikZHa9NWkO8wv6f3qaW5u1EWywmyl+47gkyI MMFqOqa+4wYwd3hPh6kH4Dex6UcK9COU22w6TFdmzn2MhtNX9ixZDzXHtq2Tx4lyveBP cEEezjonrWUYPdLWgDAInYIBT6qgbK8ldnfIfawrf13WOwL+FxxS103adSxjkIHr4oxM Iw== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3u0sw7ufpr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 30 Oct 2023 09:47:58 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 39U9lv7t027699 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 30 Oct 2023 09:47:57 GMT Received: from hu-kathirav-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Mon, 30 Oct 2023 02:47:52 -0700 From: Kathiravan Thirumoorthy Date: Mon, 30 Oct 2023 15:17:20 +0530 Subject: [PATCH 5/8] dt-bindings: clock: add IPQ5332 NSSCC clock and reset definitions MIME-Version: 1.0 Message-ID: <20231030-ipq5332-nsscc-v1-5-6162a2c65f0a@quicinc.com> References: <20231030-ipq5332-nsscc-v1-0-6162a2c65f0a@quicinc.com> In-Reply-To: <20231030-ipq5332-nsscc-v1-0-6162a2c65f0a@quicinc.com> To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Catalin Marinas , Will Deacon CC: , , , , , , "Kathiravan Thirumoorthy" X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1698659244; l=5960; i=quic_kathirav@quicinc.com; s=20230906; h=from:subject:message-id; bh=gnTxTHVemRJjz6NLYE10vtmDzXAuRzOl7oJEOK+mBb8=; b=aZC8ISsbqgPDG8R4L8ATxcqR77ddz7AUklVXbQmx7UVpC/tJXsriUAX+SChjC7wW5Bv91SC0U 6LMHNWNLJHtAtboKuYOoSYPXBRtLWylLLMMRzcqEV6vpa53gaM8mgmP X-Developer-Key: i=quic_kathirav@quicinc.com; a=ed25519; pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Sn3n1aFA8pWlhSJg12HD0iFM_DO8hVe8 X-Proofpoint-GUID: Sn3n1aFA8pWlhSJg12HD0iFM_DO8hVe8 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-30_08,2023-10-27_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 clxscore=1015 phishscore=0 lowpriorityscore=0 spamscore=0 malwarescore=0 priorityscore=1501 adultscore=0 bulkscore=0 impostorscore=0 suspectscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2310240000 definitions=main-2310300074 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Mon, 30 Oct 2023 02:49:08 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781173428026645072 X-GMAIL-MSGID: 1781173428026645072 Add NSSCC clock and reset definitions for IPQ5332. Signed-off-by: Kathiravan Thirumoorthy Reviewed-by: Krzysztof Kozlowski --- .../bindings/clock/qcom,ipq5332-nsscc.yaml | 60 +++++++++++++++ include/dt-bindings/clock/qcom,ipq5332-nsscc.h | 86 ++++++++++++++++++++++ 2 files changed, 146 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5332-nsscc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5332-nsscc.yaml new file mode 100644 index 000000000000..59f8d1e99229 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5332-nsscc.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,ipq5332-nsscc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Networking Sub System Clock & Reset Controller on IPQ5332 + +maintainers: + - Bjorn Andersson + +description: | + Qualcomm networking sub system clock control module provides the clocks, + resets and power domains on IPQ5332 + + See also:: + include/dt-bindings/clock/qcom,ipq5332-nsscc.h + +allOf: + - $ref: qcom,gcc.yaml# + +properties: + compatible: + const: qcom,ipq5332-nsscc + + clocks: + items: + - description: Common PLL nss clock 200M source + - description: Common PLL nss clock 300M source + - description: GCC GPLL0 out aux clock source + - description: Uniphy0 NSS Rx clock source + - description: Uniphy0 NSS Tx clock source + - description: Uniphy1 NSS Rx clock source + - description: Uniphy1 NSS Tx clock source + - description: Board XO source + +required: + - compatible + - clocks + +unevaluatedProperties: false + +examples: + - | + clock-controller@39b00000 { + compatible = "qcom,ipq5332-nsscc"; + reg = <0x39b00000 0x80000>; + clocks = <&bias_pll_cc_clk>, + <&bias_pll_nss_noc_clk>, + <&gcc_gpll0_out_aux>, + <&uniphy 0>, + <&uniphy 1>, + <&uniphy 2>, + <&uniphy 3>, + <&xo_board_clk>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/include/dt-bindings/clock/qcom,ipq5332-nsscc.h b/include/dt-bindings/clock/qcom,ipq5332-nsscc.h new file mode 100644 index 000000000000..c077cde7f57d --- /dev/null +++ b/include/dt-bindings/clock/qcom,ipq5332-nsscc.h @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_NSS_CC_IPQ5332_H +#define _DT_BINDINGS_CLK_QCOM_NSS_CC_IPQ5332_H + +/* NSS_CC clocks */ +#define NSS_CC_CE_APB_CLK 0 +#define NSS_CC_CE_AXI_CLK 1 +#define NSS_CC_CE_CLK_SRC 2 +#define NSS_CC_CFG_CLK_SRC 3 +#define NSS_CC_DEBUG_CLK 4 +#define NSS_CC_EIP_BFDCD_CLK_SRC 5 +#define NSS_CC_EIP_CLK 6 +#define NSS_CC_NSS_CSR_CLK 7 +#define NSS_CC_NSSNOC_CE_APB_CLK 8 +#define NSS_CC_NSSNOC_CE_AXI_CLK 9 +#define NSS_CC_NSSNOC_EIP_CLK 10 +#define NSS_CC_NSSNOC_NSS_CSR_CLK 11 +#define NSS_CC_NSSNOC_PPE_CFG_CLK 12 +#define NSS_CC_NSSNOC_PPE_CLK 13 +#define NSS_CC_PORT1_MAC_CLK 14 +#define NSS_CC_PORT1_RX_CLK 15 +#define NSS_CC_PORT1_RX_CLK_SRC 16 +#define NSS_CC_PORT1_RX_DIV_CLK_SRC 17 +#define NSS_CC_PORT1_TX_CLK 18 +#define NSS_CC_PORT1_TX_CLK_SRC 19 +#define NSS_CC_PORT1_TX_DIV_CLK_SRC 20 +#define NSS_CC_PORT2_MAC_CLK 21 +#define NSS_CC_PORT2_RX_CLK 22 +#define NSS_CC_PORT2_RX_CLK_SRC 23 +#define NSS_CC_PORT2_RX_DIV_CLK_SRC 24 +#define NSS_CC_PORT2_TX_CLK 25 +#define NSS_CC_PORT2_TX_CLK_SRC 26 +#define NSS_CC_PORT2_TX_DIV_CLK_SRC 27 +#define NSS_CC_PPE_CLK_SRC 28 +#define NSS_CC_PPE_EDMA_CFG_CLK 29 +#define NSS_CC_PPE_EDMA_CLK 30 +#define NSS_CC_PPE_SWITCH_BTQ_CLK 31 +#define NSS_CC_PPE_SWITCH_CFG_CLK 32 +#define NSS_CC_PPE_SWITCH_CLK 33 +#define NSS_CC_PPE_SWITCH_IPE_CLK 34 +#define NSS_CC_UNIPHY_PORT1_RX_CLK 35 +#define NSS_CC_UNIPHY_PORT1_TX_CLK 36 +#define NSS_CC_UNIPHY_PORT2_RX_CLK 37 +#define NSS_CC_UNIPHY_PORT2_TX_CLK 38 +#define NSS_CC_XGMAC0_PTP_REF_CLK 39 +#define NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC 40 +#define NSS_CC_XGMAC1_PTP_REF_CLK 41 +#define NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC 42 + +#define NSS_CC_CE_APB_CLK_ARES 0 +#define NSS_CC_CE_AXI_CLK_ARES 1 +#define NSS_CC_DEBUG_CLK_ARES 2 +#define NSS_CC_EIP_CLK_ARES 3 +#define NSS_CC_NSS_CSR_CLK_ARES 4 +#define NSS_CC_NSSNOC_CE_APB_CLK_ARES 5 +#define NSS_CC_NSSNOC_CE_AXI_CLK_ARES 6 +#define NSS_CC_NSSNOC_EIP_CLK_ARES 7 +#define NSS_CC_NSSNOC_NSS_CSR_CLK_ARES 8 +#define NSS_CC_NSSNOC_PPE_CLK_ARES 9 +#define NSS_CC_NSSNOC_PPE_CFG_CLK_ARES 10 +#define NSS_CC_PORT1_MAC_CLK_ARES 11 +#define NSS_CC_PORT1_RX_CLK_ARES 12 +#define NSS_CC_PORT1_TX_CLK_ARES 13 +#define NSS_CC_PORT2_MAC_CLK_ARES 14 +#define NSS_CC_PORT2_RX_CLK_ARES 15 +#define NSS_CC_PORT2_TX_CLK_ARES 16 +#define NSS_CC_PPE_BCR 17 +#define NSS_CC_PPE_EDMA_CLK_ARES 18 +#define NSS_CC_PPE_EDMA_CFG_CLK_ARES 19 +#define NSS_CC_PPE_SWITCH_BTQ_CLK_ARES 20 +#define NSS_CC_PPE_SWITCH_CLK_ARES 21 +#define NSS_CC_PPE_SWITCH_CFG_CLK_ARES 22 +#define NSS_CC_PPE_SWITCH_IPE_CLK_ARES 23 +#define NSS_CC_UNIPHY_PORT1_RX_CLK_ARES 24 +#define NSS_CC_UNIPHY_PORT1_TX_CLK_ARES 25 +#define NSS_CC_UNIPHY_PORT2_RX_CLK_ARES 26 +#define NSS_CC_UNIPHY_PORT2_TX_CLK_ARES 27 +#define NSS_CC_XGMAC0_PTP_REF_CLK_ARES 28 +#define NSS_CC_XGMAC1_PTP_REF_CLK_ARES 29 + +#endif From patchwork Mon Oct 30 09:47:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 159593 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp2088853vqb; Mon, 30 Oct 2023 02:50:15 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGrqhIpeQLFbQdarIcpDCKoTmYZiFXRXsAYA9C6LH6SDUkfX7Zwpjesdes1dOVtuMND3a0m X-Received: by 2002:a05:690c:fd5:b0:5a7:cadb:c721 with SMTP id dg21-20020a05690c0fd500b005a7cadbc721mr8468290ywb.12.1698659414917; Mon, 30 Oct 2023 02:50:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698659414; cv=none; d=google.com; s=arc-20160816; b=oEEVKPCm5zH4LPaSD1JgqCxZt1Ejf0h6YUtCqPo13kfSZTkzwFNhszxTpdDOvusn+3 JD1qSJRIAflpl0UXyav5pPBskb5A/uzObjHZyvCJQp926JVFDS8ePU6cD7s5IoqUbM9K HAP/8wwlnCtpStLjAVpqRrEOk6wKUOuEBxDAKQFqNFPwwZea3WmyIFhNClpSiqQC/fwJ nh+2CxG1/r0+M++FQlqorsAIq1sPc/HTLW/B4biESE6qmL4FatSmkq0OcHaMl7m7sSUy cnJsqeKYaNHvYl8XtnodJ84XUrIc2KUAkOg/+Eid2rTwIxjXB+jEdzUGupefdeOKjTO3 Queg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=fp7DVePs5vizUXk+ROWOPuHwr1QlWvVrS/b+gp0jR7s=; fh=gfCwzJd/1auOn37TCxo+G+sybAUeroi1DxMWExaAZgc=; b=OgJ5Wa6fwkblWcKz6AEf/cTJz8qig+r5ndxg76kURoy6a7PBqutw94gpsE77KedQzJ yE9Sc1VZSB4bNSuNw22uXA2FZJU648nU/gTQutjULmYIpY3o2UF7kKD0AZg93BoCKrxj +1CwMvdVmfOBrJKzkXz57kvM+UJd4TZ6EGR6Z7NVbbK5G0rovk58BVw8j3gaOizgrY2N sZXA6kGCn/5efFEC+ibbR9fOervk2c+SA29Jd1odOd1xJyrig2vFHHHmfVaRZeMDu2Cx RXh+ob6dKLFAvjjIN0bsb6QwRCXMpKvQKMYFKZmmz+I5mTp2Zf+m7vc6ArtASWwvptPM wQ7A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=SFtIniUf; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from pete.vger.email (pete.vger.email. [2620:137:e000::3:6]) by mx.google.com with ESMTPS id q3-20020a632a03000000b0057760853706si816003pgq.578.2023.10.30.02.50.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Oct 2023 02:50:14 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) client-ip=2620:137:e000::3:6; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=SFtIniUf; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by pete.vger.email (Postfix) with ESMTP id B426580A9A9D; Mon, 30 Oct 2023 02:50:01 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at pete.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232753AbjJ3JtK (ORCPT + 31 others); Mon, 30 Oct 2023 05:49:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34484 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232635AbjJ3Jsm (ORCPT ); Mon, 30 Oct 2023 05:48:42 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8414310D7; Mon, 30 Oct 2023 02:48:17 -0700 (PDT) Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 39U57AA9013441; Mon, 30 Oct 2023 09:48:04 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : date : subject : mime-version : content-type : content-transfer-encoding : message-id : references : in-reply-to : to : cc; s=qcppdkim1; bh=fp7DVePs5vizUXk+ROWOPuHwr1QlWvVrS/b+gp0jR7s=; b=SFtIniUfQpl2g/4s1DyB7NVlue690PPFPyVOziajBw3RziT4Nfmw68EJhBd95kJgVJd6 duIF2vYAqHfNF1jAyu495fmZjPTWnXRvp5a6YGf01XwynFvTQgKni3LGVbyXVzT46PnK ohC4rMVu1ewtXAOLoWjR1rW3JrHyx2c/anjt3sSUVXVJJVkocNYkWbiIl4kc3BcKkjXi JfB8NkASgCmcqkEQAVjpHE84g47YFurVQ8TvLd4IjymPc80GuSX+FRQ1Tf3YdyDXrLDK 3Q6+DeZXr3CS2hx8KbBzppfP0jXrcnjUGtbzpaP8LMu3K9gWgjPYYOu3c7CsGkx7GhdA fA== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3u0tphue1a-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 30 Oct 2023 09:48:04 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 39U9m3Rm031517 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 30 Oct 2023 09:48:03 GMT Received: from hu-kathirav-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Mon, 30 Oct 2023 02:47:57 -0700 From: Kathiravan Thirumoorthy Date: Mon, 30 Oct 2023 15:17:21 +0530 Subject: [PATCH 6/8] clk: qcom: add NSS clock Controller driver for IPQ5332 MIME-Version: 1.0 Message-ID: <20231030-ipq5332-nsscc-v1-6-6162a2c65f0a@quicinc.com> References: <20231030-ipq5332-nsscc-v1-0-6162a2c65f0a@quicinc.com> In-Reply-To: <20231030-ipq5332-nsscc-v1-0-6162a2c65f0a@quicinc.com> To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Catalin Marinas , Will Deacon CC: , , , , , , "Kathiravan Thirumoorthy" X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1698659244; l=31771; i=quic_kathirav@quicinc.com; s=20230906; h=from:subject:message-id; bh=ipI472Raiv3frqk5dx/dNjGsrCzcFKnZwrNrt8S1wcg=; b=Ltvwsm99C6JtrQgnnYMCfuzWciHEeSdGAS59/nKN3LEqnXi9c2yy129VsX65nG9qIwaiWPSxv wXdZ15fyN5gCHbS/sNB7ZT+s+eO5W7Cx8lVW07jTCe5hQfXOUOtR3hA X-Developer-Key: i=quic_kathirav@quicinc.com; a=ed25519; pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: _8bpr59nKPVNODZSpn2DRT6mAxpHK8PX X-Proofpoint-GUID: _8bpr59nKPVNODZSpn2DRT6mAxpHK8PX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-30_08,2023-10-27_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 mlxlogscore=999 spamscore=0 lowpriorityscore=0 malwarescore=0 phishscore=0 clxscore=1015 priorityscore=1501 bulkscore=0 impostorscore=0 adultscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2310240000 definitions=main-2310300074 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Mon, 30 Oct 2023 02:50:01 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781173494461620211 X-GMAIL-MSGID: 1781173494461620211 Add Networking Sub System Clock Controller(NSSCC) driver for IPQ5332 based devices. Signed-off-by: Kathiravan Thirumoorthy --- drivers/clk/qcom/Kconfig | 7 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/nsscc-ipq5332.c | 1035 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 1043 insertions(+) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index ad1acd9b7426..2e3efcdef9fa 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -162,6 +162,13 @@ config IPQ_GCC_5332 Say Y if you want to use peripheral devices such as UART, SPI, i2c, USB, SD/eMMC, etc. +config IPQ_NSSCC_5332 + tristate "IPQ5332 NSS Clock Controller" + depends on ARM64 || COMPILE_TEST + depends on IPQ_GCC_5332 + help + Support for NSS clock controller on ipq5332 devices. + config IPQ_GCC_6018 tristate "IPQ6018 Global Clock Controller" help diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile index 17edd73f9839..3aab744ecc99 100644 --- a/drivers/clk/qcom/Makefile +++ b/drivers/clk/qcom/Makefile @@ -31,6 +31,7 @@ obj-$(CONFIG_IPQ_GCC_806X) += gcc-ipq806x.o obj-$(CONFIG_IPQ_GCC_8074) += gcc-ipq8074.o obj-$(CONFIG_IPQ_GCC_9574) += gcc-ipq9574.o obj-$(CONFIG_IPQ_LCC_806X) += lcc-ipq806x.o +obj-$(CONFIG_IPQ_NSSCC_5332) += nsscc-ipq5332.o obj-$(CONFIG_MDM_GCC_9607) += gcc-mdm9607.o obj-$(CONFIG_MDM_GCC_9615) += gcc-mdm9615.o obj-$(CONFIG_MSM_GCC_8660) += gcc-msm8660.o diff --git a/drivers/clk/qcom/nsscc-ipq5332.c b/drivers/clk/qcom/nsscc-ipq5332.c new file mode 100644 index 000000000000..56cd195cc38e --- /dev/null +++ b/drivers/clk/qcom/nsscc-ipq5332.c @@ -0,0 +1,1035 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2023, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "clk-alpha-pll.h" +#include "clk-branch.h" +#include "clk-pll.h" +#include "clk-rcg.h" +#include "clk-regmap.h" +#include "clk-regmap-divider.h" +#include "clk-regmap-mux.h" +#include "common.h" +#include "reset.h" + +enum { + DT_CMN_PLL_NSS_CLK_200M, + DT_CMN_PLL_NSS_CLK_300M, + DT_GCC_GPLL0_OUT_AUX, + DT_UNIPHY0_NSS_TX_CLK, + DT_UNIPHY0_NSS_RX_CLK, + DT_UNIPHY1_NSS_TX_CLK, + DT_UNIPHY1_NSS_RX_CLK, + DT_XO, +}; + +enum { + P_CMN_PLL_NSS_CLK_200M, + P_CMN_PLL_NSS_CLK_300M, + P_GCC_GPLL0_OUT_AUX, + P_UNIPHY0_NSS_TX_CLK, + P_UNIPHY0_NSS_RX_CLK, + P_UNIPHY1_NSS_TX_CLK, + P_UNIPHY1_NSS_RX_CLK, + P_XO, +}; + +static const struct parent_map nss_cc_parent_map_0[] = { + { P_XO, 0 }, + { P_GCC_GPLL0_OUT_AUX, 2 }, + { P_CMN_PLL_NSS_CLK_300M, 5 }, + { P_CMN_PLL_NSS_CLK_200M, 6 }, +}; + +static const struct clk_parent_data nss_cc_parent_data_0[] = { + { .index = DT_XO }, + { .index = DT_GCC_GPLL0_OUT_AUX }, + { .index = DT_CMN_PLL_NSS_CLK_300M }, + { .index = DT_CMN_PLL_NSS_CLK_200M }, +}; + +static const struct parent_map nss_cc_parent_map_1[] = { + { P_XO, 0 }, + { P_GCC_GPLL0_OUT_AUX, 2 }, + { P_UNIPHY0_NSS_RX_CLK, 3 }, + { P_UNIPHY0_NSS_TX_CLK, 4 }, + { P_CMN_PLL_NSS_CLK_300M, 5 }, + { P_CMN_PLL_NSS_CLK_200M, 6 }, +}; + +static const struct clk_parent_data nss_cc_parent_data_1[] = { + { .index = DT_XO }, + { .index = DT_GCC_GPLL0_OUT_AUX }, + { .index = DT_UNIPHY0_NSS_RX_CLK }, + { .index = DT_UNIPHY0_NSS_TX_CLK }, + { .index = DT_CMN_PLL_NSS_CLK_300M }, + { .index = DT_CMN_PLL_NSS_CLK_200M }, +}; + +static const struct parent_map nss_cc_parent_map_2[] = { + { P_XO, 0 }, + { P_GCC_GPLL0_OUT_AUX, 2 }, + { P_UNIPHY1_NSS_RX_CLK, 3 }, + { P_UNIPHY1_NSS_TX_CLK, 4 }, + { P_CMN_PLL_NSS_CLK_300M, 5 }, + { P_CMN_PLL_NSS_CLK_200M, 6 }, +}; + +static const struct clk_parent_data nss_cc_parent_data_2[] = { + { .index = DT_XO }, + { .index = DT_GCC_GPLL0_OUT_AUX }, + { .index = DT_UNIPHY1_NSS_RX_CLK }, + { .index = DT_UNIPHY1_NSS_TX_CLK }, + { .index = DT_CMN_PLL_NSS_CLK_300M }, + { .index = DT_CMN_PLL_NSS_CLK_200M }, +}; + +static const struct freq_tbl ftbl_nss_cc_ce_clk_src[] = { + F(24000000, P_XO, 1, 0, 0), + F(200000000, P_CMN_PLL_NSS_CLK_200M, 1, 0, 0), + { } +}; + +static struct clk_rcg2 nss_cc_ce_clk_src = { + .cmd_rcgr = 0x518, + .mnd_width = 0, + .hid_width = 5, + .parent_map = nss_cc_parent_map_0, + .freq_tbl = ftbl_nss_cc_ce_clk_src, + .clkr.hw.init = &(const struct clk_init_data){ + .name = "nss_cc_ce_clk_src", + .parent_data = nss_cc_parent_data_0, + .num_parents = ARRAY_SIZE(nss_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_nss_cc_cfg_clk_src[] = { + F(100000000, P_GCC_GPLL0_OUT_AUX, 8, 0, 0), + { } +}; + +static struct clk_rcg2 nss_cc_cfg_clk_src = { + .cmd_rcgr = 0x5e0, + .mnd_width = 0, + .hid_width = 5, + .parent_map = nss_cc_parent_map_0, + .freq_tbl = ftbl_nss_cc_cfg_clk_src, + .clkr.hw.init = &(const struct clk_init_data){ + .name = "nss_cc_cfg_clk_src", + .parent_data = nss_cc_parent_data_0, + .num_parents = ARRAY_SIZE(nss_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_tbl ftbl_nss_cc_eip_bfdcd_clk_src[] = { + F(300000000, P_CMN_PLL_NSS_CLK_300M, 1, 0, 0), + { } +}; + +static struct clk_rcg2 nss_cc_eip_bfdcd_clk_src = { + .cmd_rcgr = 0x57c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = nss_cc_parent_map_0, + .freq_tbl = ftbl_nss_cc_eip_bfdcd_clk_src, + .clkr.hw.init = &(const struct clk_init_data){ + .name = "nss_cc_eip_bfdcd_clk_src", + .parent_data = nss_cc_parent_data_0, + .num_parents = ARRAY_SIZE(nss_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_25[] = { + C(P_UNIPHY0_NSS_RX_CLK, 12.5, 0, 0), + C(P_UNIPHY0_NSS_RX_CLK, 5, 0, 0), +}; + +static const struct freq_conf ftbl_nss_cc_port1_rx_clk_src_125[] = { + C(P_UNIPHY0_NSS_RX_CLK, 2.5, 0, 0), + C(P_UNIPHY0_NSS_RX_CLK, 1, 0, 0), +}; + +static const struct freq_multi_tbl ftbl_nss_cc_port1_rx_clk_src[] = { + FMS(24000000, P_XO, 1, 0, 0), + FM(25000000, ftbl_nss_cc_port1_rx_clk_src_25), + FMS(78125000, P_UNIPHY0_NSS_RX_CLK, 4, 0, 0), + FM(125000000, ftbl_nss_cc_port1_rx_clk_src_125), + FMS(156250000, P_UNIPHY0_NSS_RX_CLK, 2, 0, 0), + FMS(312500000, P_UNIPHY0_NSS_RX_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 nss_cc_port1_rx_clk_src = { + .cmd_rcgr = 0x450, + .mnd_width = 0, + .hid_width = 5, + .parent_map = nss_cc_parent_map_1, + .freq_multi_tbl = ftbl_nss_cc_port1_rx_clk_src, + .clkr.hw.init = &(const struct clk_init_data){ + .name = "nss_cc_port1_rx_clk_src", + .parent_data = nss_cc_parent_data_1, + .num_parents = ARRAY_SIZE(nss_cc_parent_data_1), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_conf ftbl_nss_cc_port1_tx_clk_src_25[] = { + C(P_UNIPHY0_NSS_TX_CLK, 12.5, 0, 0), + C(P_UNIPHY0_NSS_TX_CLK, 5, 0, 0), +}; + +static const struct freq_conf ftbl_nss_cc_port1_tx_clk_src_125[] = { + C(P_UNIPHY0_NSS_TX_CLK, 2.5, 0, 0), + C(P_UNIPHY0_NSS_TX_CLK, 1, 0, 0), +}; + +static const struct freq_multi_tbl ftbl_nss_cc_port1_tx_clk_src[] = { + FMS(24000000, P_XO, 1, 0, 0), + FM(25000000, ftbl_nss_cc_port1_tx_clk_src_25), + FMS(78125000, P_UNIPHY0_NSS_TX_CLK, 4, 0, 0), + FM(125000000, ftbl_nss_cc_port1_tx_clk_src_125), + FMS(156250000, P_UNIPHY0_NSS_TX_CLK, 2, 0, 0), + FMS(312500000, P_UNIPHY0_NSS_TX_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 nss_cc_port1_tx_clk_src = { + .cmd_rcgr = 0x45c, + .mnd_width = 0, + .hid_width = 5, + .parent_map = nss_cc_parent_map_1, + .freq_multi_tbl = ftbl_nss_cc_port1_tx_clk_src, + .clkr.hw.init = &(const struct clk_init_data){ + .name = "nss_cc_port1_tx_clk_src", + .parent_data = nss_cc_parent_data_1, + .num_parents = ARRAY_SIZE(nss_cc_parent_data_1), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_conf ftbl_nss_cc_port2_rx_clk_src_25[] = { + C(P_UNIPHY1_NSS_RX_CLK, 12.5, 0, 0), + C(P_UNIPHY1_NSS_RX_CLK, 5, 0, 0), +}; + +static const struct freq_conf ftbl_nss_cc_port2_rx_clk_src_125[] = { + C(P_UNIPHY1_NSS_RX_CLK, 2.5, 0, 0), + C(P_UNIPHY1_NSS_RX_CLK, 1, 0, 0), +}; + +static const struct freq_multi_tbl ftbl_nss_cc_port2_rx_clk_src[] = { + FMS(24000000, P_XO, 1, 0, 0), + FM(25000000, ftbl_nss_cc_port2_rx_clk_src_25), + FMS(78125000, P_UNIPHY1_NSS_RX_CLK, 4, 0, 0), + FM(125000000, ftbl_nss_cc_port2_rx_clk_src_125), + FMS(156250000, P_UNIPHY1_NSS_RX_CLK, 2, 0, 0), + FMS(312500000, P_UNIPHY1_NSS_RX_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 nss_cc_port2_rx_clk_src = { + .cmd_rcgr = 0x468, + .mnd_width = 0, + .hid_width = 5, + .parent_map = nss_cc_parent_map_2, + .freq_multi_tbl = ftbl_nss_cc_port2_rx_clk_src, + .clkr.hw.init = &(const struct clk_init_data){ + .name = "nss_cc_port2_rx_clk_src", + .parent_data = nss_cc_parent_data_2, + .num_parents = ARRAY_SIZE(nss_cc_parent_data_2), + .ops = &clk_rcg2_ops, + }, +}; + +static const struct freq_conf ftbl_nss_cc_port2_tx_clk_src_25[] = { + C(P_UNIPHY1_NSS_TX_CLK, 12.5, 0, 0), + C(P_UNIPHY1_NSS_TX_CLK, 5, 0, 0), +}; + +static const struct freq_conf ftbl_nss_cc_port2_tx_clk_src_125[] = { + C(P_UNIPHY1_NSS_TX_CLK, 2.5, 0, 0), + C(P_UNIPHY1_NSS_TX_CLK, 1, 0, 0), +}; + +static const struct freq_multi_tbl ftbl_nss_cc_port2_tx_clk_src[] = { + FMS(24000000, P_XO, 1, 0, 0), + FM(25000000, ftbl_nss_cc_port2_tx_clk_src_25), + FMS(78125000, P_UNIPHY1_NSS_TX_CLK, 4, 0, 0), + FM(125000000, ftbl_nss_cc_port2_tx_clk_src_125), + FMS(156250000, P_UNIPHY1_NSS_TX_CLK, 2, 0, 0), + FMS(312500000, P_UNIPHY1_NSS_TX_CLK, 1, 0, 0), + { } +}; + +static struct clk_rcg2 nss_cc_port2_tx_clk_src = { + .cmd_rcgr = 0x474, + .mnd_width = 0, + .hid_width = 5, + .parent_map = nss_cc_parent_map_2, + .freq_multi_tbl = ftbl_nss_cc_port2_tx_clk_src, + .clkr.hw.init = &(const struct clk_init_data){ + .name = "nss_cc_port2_tx_clk_src", + .parent_data = nss_cc_parent_data_2, + .num_parents = ARRAY_SIZE(nss_cc_parent_data_2), + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_rcg2 nss_cc_ppe_clk_src = { + .cmd_rcgr = 0x3e8, + .mnd_width = 0, + .hid_width = 5, + .parent_map = nss_cc_parent_map_0, + .freq_tbl = ftbl_nss_cc_ce_clk_src, + .clkr.hw.init = &(const struct clk_init_data){ + .name = "nss_cc_ppe_clk_src", + .parent_data = nss_cc_parent_data_0, + .num_parents = ARRAY_SIZE(nss_cc_parent_data_0), + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_rcg2_ops, + }, +}; + +static struct clk_regmap_div nss_cc_port1_rx_div_clk_src = { + .reg = 0x458, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "nss_cc_port1_rx_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &nss_cc_port1_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ops, + }, +}; + +static struct clk_regmap_div nss_cc_port1_tx_div_clk_src = { + .reg = 0x464, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "nss_cc_port1_tx_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &nss_cc_port1_tx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ops, + }, +}; + +static struct clk_regmap_div nss_cc_port2_rx_div_clk_src = { + .reg = 0x470, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "nss_cc_port2_rx_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &nss_cc_port2_rx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ops, + }, +}; + +static struct clk_regmap_div nss_cc_port2_tx_div_clk_src = { + .reg = 0x47c, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "nss_cc_port2_tx_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &nss_cc_port2_tx_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ops, + }, +}; + +static struct clk_regmap_div nss_cc_xgmac0_ptp_ref_div_clk_src = { + .reg = 0x3f0, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "nss_cc_xgmac0_ptp_ref_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_regmap_div nss_cc_xgmac1_ptp_ref_div_clk_src = { + .reg = 0x3f4, + .shift = 0, + .width = 4, + .clkr.hw.init = &(const struct clk_init_data) { + .name = "nss_cc_xgmac1_ptp_ref_div_clk_src", + .parent_hws = (const struct clk_hw*[]){ + &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_regmap_div_ro_ops, + }, +}; + +static struct clk_branch nss_cc_ce_apb_clk = { + .halt_reg = 0x520, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x520, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "nss_cc_ce_apb_clk", + .parent_hws = (const struct clk_hw*[]){ + &nss_cc_ce_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ce_axi_clk = { + .halt_reg = 0x524, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x524, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "nss_cc_ce_axi_clk", + .parent_hws = (const struct clk_hw*[]){ + &nss_cc_ce_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_debug_clk = { + .halt_reg = 0x644, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x644, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "nss_cc_debug_clk", + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_eip_clk = { + .halt_reg = 0x590, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x590, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "nss_cc_eip_clk", + .parent_hws = (const struct clk_hw*[]){ + &nss_cc_eip_bfdcd_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_nss_csr_clk = { + .halt_reg = 0x5e8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5e8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "nss_cc_nss_csr_clk", + .parent_hws = (const struct clk_hw*[]){ + &nss_cc_cfg_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_nssnoc_ce_apb_clk = { + .halt_reg = 0x52c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x52c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "nss_cc_nssnoc_ce_apb_clk", + .parent_hws = (const struct clk_hw*[]){ + &nss_cc_ce_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_nssnoc_ce_axi_clk = { + .halt_reg = 0x530, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x530, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "nss_cc_nssnoc_ce_axi_clk", + .parent_hws = (const struct clk_hw*[]){ + &nss_cc_ce_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_nssnoc_eip_clk = { + .halt_reg = 0x598, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x598, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "nss_cc_nssnoc_eip_clk", + .parent_hws = (const struct clk_hw*[]){ + &nss_cc_eip_bfdcd_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_nssnoc_nss_csr_clk = { + .halt_reg = 0x5ec, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x5ec, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "nss_cc_nssnoc_nss_csr_clk", + .parent_hws = (const struct clk_hw*[]){ + &nss_cc_cfg_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_nssnoc_ppe_cfg_clk = { + .halt_reg = 0x424, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x424, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "nss_cc_nssnoc_ppe_cfg_clk", + .parent_hws = (const struct clk_hw*[]){ + &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_nssnoc_ppe_clk = { + .halt_reg = 0x420, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x420, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "nss_cc_nssnoc_ppe_clk", + .parent_hws = (const struct clk_hw*[]){ + &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_port1_mac_clk = { + .halt_reg = 0x428, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x428, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "nss_cc_port1_mac_clk", + .parent_hws = (const struct clk_hw*[]){ + &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_port1_rx_clk = { + .halt_reg = 0x480, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x480, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "nss_cc_port1_rx_clk", + .parent_hws = (const struct clk_hw*[]){ + &nss_cc_port1_rx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_port1_tx_clk = { + .halt_reg = 0x488, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x488, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "nss_cc_port1_tx_clk", + .parent_hws = (const struct clk_hw*[]){ + &nss_cc_port1_tx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_port2_mac_clk = { + .halt_reg = 0x430, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x430, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "nss_cc_port2_mac_clk", + .parent_hws = (const struct clk_hw*[]){ + &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_port2_rx_clk = { + .halt_reg = 0x490, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x490, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "nss_cc_port2_rx_clk", + .parent_hws = (const struct clk_hw*[]){ + &nss_cc_port2_rx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_port2_tx_clk = { + .halt_reg = 0x498, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x498, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "nss_cc_port2_tx_clk", + .parent_hws = (const struct clk_hw*[]){ + &nss_cc_port2_tx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ppe_edma_cfg_clk = { + .halt_reg = 0x41c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x41c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "nss_cc_ppe_edma_cfg_clk", + .parent_hws = (const struct clk_hw*[]){ + &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ppe_edma_clk = { + .halt_reg = 0x414, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x414, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "nss_cc_ppe_edma_clk", + .parent_hws = (const struct clk_hw*[]){ + &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ppe_switch_btq_clk = { + .halt_reg = 0x400, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x400, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "nss_cc_ppe_switch_btq_clk", + .parent_hws = (const struct clk_hw*[]){ + &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ppe_switch_cfg_clk = { + .halt_reg = 0x410, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x410, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "nss_cc_ppe_switch_cfg_clk", + .parent_hws = (const struct clk_hw*[]){ + &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ppe_switch_clk = { + .halt_reg = 0x408, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x408, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "nss_cc_ppe_switch_clk", + .parent_hws = (const struct clk_hw*[]){ + &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_ppe_switch_ipe_clk = { + .halt_reg = 0x3f8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x3f8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "nss_cc_ppe_switch_ipe_clk", + .parent_hws = (const struct clk_hw*[]){ + &nss_cc_ppe_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_uniphy_port1_rx_clk = { + .halt_reg = 0x4b4, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4b4, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "nss_cc_uniphy_port1_rx_clk", + .parent_hws = (const struct clk_hw*[]){ + &nss_cc_port1_rx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_uniphy_port1_tx_clk = { + .halt_reg = 0x4b8, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4b8, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "nss_cc_uniphy_port1_tx_clk", + .parent_hws = (const struct clk_hw*[]){ + &nss_cc_port1_tx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_uniphy_port2_rx_clk = { + .halt_reg = 0x4bc, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4bc, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "nss_cc_uniphy_port2_rx_clk", + .parent_hws = (const struct clk_hw*[]){ + &nss_cc_port2_rx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_uniphy_port2_tx_clk = { + .halt_reg = 0x4c0, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x4c0, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "nss_cc_uniphy_port2_tx_clk", + .parent_hws = (const struct clk_hw*[]){ + &nss_cc_port2_tx_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_xgmac0_ptp_ref_clk = { + .halt_reg = 0x438, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x438, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "nss_cc_xgmac0_ptp_ref_clk", + .parent_hws = (const struct clk_hw*[]){ + &nss_cc_xgmac0_ptp_ref_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch nss_cc_xgmac1_ptp_ref_clk = { + .halt_reg = 0x43c, + .halt_check = BRANCH_HALT, + .clkr = { + .enable_reg = 0x43c, + .enable_mask = BIT(0), + .hw.init = &(const struct clk_init_data){ + .name = "nss_cc_xgmac1_ptp_ref_clk", + .parent_hws = (const struct clk_hw*[]){ + &nss_cc_xgmac1_ptp_ref_div_clk_src.clkr.hw, + }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_regmap *nss_cc_ipq5332_clocks[] = { + [NSS_CC_CE_APB_CLK] = &nss_cc_ce_apb_clk.clkr, + [NSS_CC_CE_AXI_CLK] = &nss_cc_ce_axi_clk.clkr, + [NSS_CC_CE_CLK_SRC] = &nss_cc_ce_clk_src.clkr, + [NSS_CC_CFG_CLK_SRC] = &nss_cc_cfg_clk_src.clkr, + [NSS_CC_DEBUG_CLK] = &nss_cc_debug_clk.clkr, + [NSS_CC_EIP_BFDCD_CLK_SRC] = &nss_cc_eip_bfdcd_clk_src.clkr, + [NSS_CC_EIP_CLK] = &nss_cc_eip_clk.clkr, + [NSS_CC_NSS_CSR_CLK] = &nss_cc_nss_csr_clk.clkr, + [NSS_CC_NSSNOC_CE_APB_CLK] = &nss_cc_nssnoc_ce_apb_clk.clkr, + [NSS_CC_NSSNOC_CE_AXI_CLK] = &nss_cc_nssnoc_ce_axi_clk.clkr, + [NSS_CC_NSSNOC_EIP_CLK] = &nss_cc_nssnoc_eip_clk.clkr, + [NSS_CC_NSSNOC_NSS_CSR_CLK] = &nss_cc_nssnoc_nss_csr_clk.clkr, + [NSS_CC_NSSNOC_PPE_CFG_CLK] = &nss_cc_nssnoc_ppe_cfg_clk.clkr, + [NSS_CC_NSSNOC_PPE_CLK] = &nss_cc_nssnoc_ppe_clk.clkr, + [NSS_CC_PORT1_MAC_CLK] = &nss_cc_port1_mac_clk.clkr, + [NSS_CC_PORT1_RX_CLK] = &nss_cc_port1_rx_clk.clkr, + [NSS_CC_PORT1_RX_CLK_SRC] = &nss_cc_port1_rx_clk_src.clkr, + [NSS_CC_PORT1_RX_DIV_CLK_SRC] = &nss_cc_port1_rx_div_clk_src.clkr, + [NSS_CC_PORT1_TX_CLK] = &nss_cc_port1_tx_clk.clkr, + [NSS_CC_PORT1_TX_CLK_SRC] = &nss_cc_port1_tx_clk_src.clkr, + [NSS_CC_PORT1_TX_DIV_CLK_SRC] = &nss_cc_port1_tx_div_clk_src.clkr, + [NSS_CC_PORT2_MAC_CLK] = &nss_cc_port2_mac_clk.clkr, + [NSS_CC_PORT2_RX_CLK] = &nss_cc_port2_rx_clk.clkr, + [NSS_CC_PORT2_RX_CLK_SRC] = &nss_cc_port2_rx_clk_src.clkr, + [NSS_CC_PORT2_RX_DIV_CLK_SRC] = &nss_cc_port2_rx_div_clk_src.clkr, + [NSS_CC_PORT2_TX_CLK] = &nss_cc_port2_tx_clk.clkr, + [NSS_CC_PORT2_TX_CLK_SRC] = &nss_cc_port2_tx_clk_src.clkr, + [NSS_CC_PORT2_TX_DIV_CLK_SRC] = &nss_cc_port2_tx_div_clk_src.clkr, + [NSS_CC_PPE_CLK_SRC] = &nss_cc_ppe_clk_src.clkr, + [NSS_CC_PPE_EDMA_CFG_CLK] = &nss_cc_ppe_edma_cfg_clk.clkr, + [NSS_CC_PPE_EDMA_CLK] = &nss_cc_ppe_edma_clk.clkr, + [NSS_CC_PPE_SWITCH_BTQ_CLK] = &nss_cc_ppe_switch_btq_clk.clkr, + [NSS_CC_PPE_SWITCH_CFG_CLK] = &nss_cc_ppe_switch_cfg_clk.clkr, + [NSS_CC_PPE_SWITCH_CLK] = &nss_cc_ppe_switch_clk.clkr, + [NSS_CC_PPE_SWITCH_IPE_CLK] = &nss_cc_ppe_switch_ipe_clk.clkr, + [NSS_CC_UNIPHY_PORT1_RX_CLK] = &nss_cc_uniphy_port1_rx_clk.clkr, + [NSS_CC_UNIPHY_PORT1_TX_CLK] = &nss_cc_uniphy_port1_tx_clk.clkr, + [NSS_CC_UNIPHY_PORT2_RX_CLK] = &nss_cc_uniphy_port2_rx_clk.clkr, + [NSS_CC_UNIPHY_PORT2_TX_CLK] = &nss_cc_uniphy_port2_tx_clk.clkr, + [NSS_CC_XGMAC0_PTP_REF_CLK] = &nss_cc_xgmac0_ptp_ref_clk.clkr, + [NSS_CC_XGMAC0_PTP_REF_DIV_CLK_SRC] = &nss_cc_xgmac0_ptp_ref_div_clk_src.clkr, + [NSS_CC_XGMAC1_PTP_REF_CLK] = &nss_cc_xgmac1_ptp_ref_clk.clkr, + [NSS_CC_XGMAC1_PTP_REF_DIV_CLK_SRC] = &nss_cc_xgmac1_ptp_ref_div_clk_src.clkr, +}; + +static const struct qcom_reset_map nss_cc_ipq5332_resets[] = { + [NSS_CC_CE_APB_CLK_ARES] = { 0x520, 2 }, + [NSS_CC_CE_AXI_CLK_ARES] = { 0x524, 2 }, + [NSS_CC_DEBUG_CLK_ARES] = { 0x644, 2 }, + [NSS_CC_EIP_CLK_ARES] = { 0x590, 2 }, + [NSS_CC_NSS_CSR_CLK_ARES] = { 0x5e8, 2 }, + [NSS_CC_NSSNOC_CE_APB_CLK_ARES] = { 0x52c, 2 }, + [NSS_CC_NSSNOC_CE_AXI_CLK_ARES] = { 0x530, 2 }, + [NSS_CC_NSSNOC_EIP_CLK_ARES] = { 0x598, 2 }, + [NSS_CC_NSSNOC_NSS_CSR_CLK_ARES] = { 0x5ec, 2 }, + [NSS_CC_NSSNOC_PPE_CLK_ARES] = { 0x420, 2 }, + [NSS_CC_NSSNOC_PPE_CFG_CLK_ARES] = { 0x424, 2 }, + [NSS_CC_PORT1_MAC_CLK_ARES] = { 0x428, 2 }, + [NSS_CC_PORT1_RX_CLK_ARES] = { 0x480, 2 }, + [NSS_CC_PORT1_TX_CLK_ARES] = { 0x488, 2 }, + [NSS_CC_PORT2_MAC_CLK_ARES] = { 0x430, 2 }, + [NSS_CC_PORT2_RX_CLK_ARES] = { 0x490, 2 }, + [NSS_CC_PORT2_TX_CLK_ARES] = { 0x498, 2 }, + [NSS_CC_PPE_BCR] = { 0x3e4 }, + [NSS_CC_PPE_EDMA_CLK_ARES] = { 0x414, 2 }, + [NSS_CC_PPE_EDMA_CFG_CLK_ARES] = { 0x41c, 2 }, + [NSS_CC_PPE_SWITCH_BTQ_CLK_ARES] = { 0x400, 2 }, + [NSS_CC_PPE_SWITCH_CLK_ARES] = { 0x408, 2 }, + [NSS_CC_PPE_SWITCH_CFG_CLK_ARES] = { 0x410, 2 }, + [NSS_CC_PPE_SWITCH_IPE_CLK_ARES] = { 0x3f8, 2 }, + [NSS_CC_UNIPHY_PORT1_RX_CLK_ARES] = { 0x4b4, 2 }, + [NSS_CC_UNIPHY_PORT1_TX_CLK_ARES] = { 0x4b8, 2 }, + [NSS_CC_UNIPHY_PORT2_RX_CLK_ARES] = { 0x4bc, 2 }, + [NSS_CC_UNIPHY_PORT2_TX_CLK_ARES] = { 0x4c0, 2 }, + [NSS_CC_XGMAC0_PTP_REF_CLK_ARES] = { 0x438, 2 }, + [NSS_CC_XGMAC1_PTP_REF_CLK_ARES] = { 0x43c, 2 }, +}; + +static const struct regmap_config nss_cc_ipq5332_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x800, + .fast_io = true, +}; + +static const struct qcom_cc_desc nss_cc_ipq5332_desc = { + .config = &nss_cc_ipq5332_regmap_config, + .clks = nss_cc_ipq5332_clocks, + .num_clks = ARRAY_SIZE(nss_cc_ipq5332_clocks), + .resets = nss_cc_ipq5332_resets, + .num_resets = ARRAY_SIZE(nss_cc_ipq5332_resets), +}; + +static const struct of_device_id nss_cc_ipq5332_match_table[] = { + { .compatible = "qcom,ipq5332-nsscc" }, + { } +}; +MODULE_DEVICE_TABLE(of, nss_cc_ipq5332_match_table); + +static int nss_cc_ipq5332_probe(struct platform_device *pdev) +{ + return qcom_cc_probe(pdev, &nss_cc_ipq5332_desc); +} + +static struct platform_driver nss_cc_ipq5332_driver = { + .probe = nss_cc_ipq5332_probe, + .driver = { + .name = "qcom,ipq5332-nsscc", + .of_match_table = nss_cc_ipq5332_match_table, + }, +}; +module_platform_driver(nss_cc_ipq5332_driver); + +MODULE_DESCRIPTION("QTI NSS_CC MIAMI Driver"); +MODULE_LICENSE("GPL"); From patchwork Mon Oct 30 09:47:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 159591 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp2088823vqb; Mon, 30 Oct 2023 02:50:09 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEpUFSa+CUDaknCCYblVujLQ/vPtALmYNBL6BIPGMinEds2JXHntm6VKlkE+XY1g03Zws0C X-Received: by 2002:a05:6a21:7885:b0:172:eda5:36ea with SMTP id bf5-20020a056a21788500b00172eda536eamr8617436pzc.7.1698659409214; Mon, 30 Oct 2023 02:50:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698659409; cv=none; d=google.com; s=arc-20160816; b=aeBCIIopPit3iOq6EBx6koB616PI2Frx1rgWsPbPml1B9vdmL62Dd33sD3ITx9K8eR 84sU9AECJ4NW7VeOETcmPaVMIqDc5CaiuYDO9IOgAPHD7pQvmFKI8dn9exPzzUEdZr6O sGYOPbmGNkXgwaZc75T04tuWbMnMA8frLGzSND5Y3FtDJAPoNvMvcN1tfrLZyxxFRuGT 5qsJ94n4FURVJGXM2Jn3Bl+2jnf2GB724eiZTvpcsv755JIVzjjZU9Wt0r2XLMDqzpSc N1/Dypu+Xp564CjYVD44ffeRaYodXEX4gT6XJarD4WepURONn7dUB1GOLNv3k5gOGQr3 Gv1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=wft3AI9ReTIaoBvsIogBc4YkEKwVbPcyMLDBuUl9EYk=; fh=gfCwzJd/1auOn37TCxo+G+sybAUeroi1DxMWExaAZgc=; b=W9uYx/hoG2gi9EVQodfSe80FlMNK+fNQts9uxg7XLNYbXhD3zqixeHsar4UEUwIhXr 6Do7fSsww1y8ToBKqZ31cxrWD8sVkO8Fpt+mYyau8hHshppM9xdJykwoJJk1fLIo0tSa LfqfpkMNLLiTBsfM7QHWpZbiv9K27ydUMRm3i7HZf1o3X3grGcHlo+iVCfHp33KM0jn8 29+xj4NxlrWnb0kOobWEUzq12vDPZM7aZcEtQAj4cZG36AI6G1AWMDAQodUAsrmWsp98 O+TMU+NQ5rYJKbbcPl8rSFoA8g5Fsvuw7Sx4tT6L1LNbPatCDHR5uvK7anY5YXmpSqmA eyyg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=HX+0RV2I; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from groat.vger.email (groat.vger.email. [2620:137:e000::3:5]) by mx.google.com with ESMTPS id o19-20020a656a53000000b00578b487825asi4965574pgu.208.2023.10.30.02.50.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Oct 2023 02:50:09 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) client-ip=2620:137:e000::3:5; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=HX+0RV2I; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by groat.vger.email (Postfix) with ESMTP id 411FA8060061; Mon, 30 Oct 2023 02:49:56 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at groat.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232593AbjJ3JtN (ORCPT + 31 others); Mon, 30 Oct 2023 05:49:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47920 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232709AbjJ3Jsm (ORCPT ); Mon, 30 Oct 2023 05:48:42 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A53AD12B; Mon, 30 Oct 2023 02:48:18 -0700 (PDT) Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 39U63fSO005163; Mon, 30 Oct 2023 09:48:10 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : date : subject : mime-version : content-type : content-transfer-encoding : message-id : references : in-reply-to : to : cc; s=qcppdkim1; bh=wft3AI9ReTIaoBvsIogBc4YkEKwVbPcyMLDBuUl9EYk=; b=HX+0RV2IlOsmQGYbnUsONcRiV8nM8yEdH+EjO/cvp2Plwsm2qSOTOirUKB/K0vmOJVfl Ysh5QnwnMwGLi3ju3ppqbw1qljspm1fo/SdR3ymefpXPyPB98Ax9qbHw39+yYYFQSHFM OcRweJqRBLfO06AW3ducntHwy/8lHCwE9k6y7LDdjqR8EkCO7xkwBT7qYDMV+rTmE4Cd fTQzDy2De6p+CXkk6+Qa9QUY5r6mWBIQprJOlniQqXEv8bHPlaGPHLLyGAD86HSgDhtF h26hNWw4x8smaIy58rusifynNyW/P1dNByF7wBe3F6B1xRXGjF7bxKyN/mSh7iBPVr3n Pg== Received: from nalasppmta05.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3u0td23fma-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 30 Oct 2023 09:48:10 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 39U9m8hX027858 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 30 Oct 2023 09:48:09 GMT Received: from hu-kathirav-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Mon, 30 Oct 2023 02:48:03 -0700 From: Kathiravan Thirumoorthy Date: Mon, 30 Oct 2023 15:17:22 +0530 Subject: [PATCH 7/8] arm64: dts: qcom: ipq5332: add support for the NSSCC MIME-Version: 1.0 Message-ID: <20231030-ipq5332-nsscc-v1-7-6162a2c65f0a@quicinc.com> References: <20231030-ipq5332-nsscc-v1-0-6162a2c65f0a@quicinc.com> In-Reply-To: <20231030-ipq5332-nsscc-v1-0-6162a2c65f0a@quicinc.com> To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Catalin Marinas , Will Deacon CC: , , , , , , "Kathiravan Thirumoorthy" X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1698659244; l=1427; i=quic_kathirav@quicinc.com; s=20230906; h=from:subject:message-id; bh=ElCvVMU+zvLTN9g6r5iAat7MQowpzkwATm2h3cZnHRo=; b=wWUV7gLTR8/pDUHBelyQbfzImpXwumPSC2M/90B6ZvlhzLYoxig+Or/tLp67EhXK5uaBHVOwR 2cg7sUuh6mXAYByNfaefIFzSwu2TCb1bXnktLxu7SvpPOn0+idvYDr2 X-Developer-Key: i=quic_kathirav@quicinc.com; a=ed25519; pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: HcACAZEW7qvrDMFs3NAHqS8gnzCbrune X-Proofpoint-GUID: HcACAZEW7qvrDMFs3NAHqS8gnzCbrune X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-30_08,2023-10-27_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 mlxlogscore=794 lowpriorityscore=0 spamscore=0 bulkscore=0 adultscore=0 clxscore=1015 priorityscore=1501 impostorscore=0 malwarescore=0 mlxscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2310240000 definitions=main-2310300074 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Mon, 30 Oct 2023 02:49:56 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781173488852904593 X-GMAIL-MSGID: 1781173488852904593 Describe the NSS clock controller node and it's relevant external clocks. Signed-off-by: Kathiravan Thirumoorthy --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index 42e2e48b2bc3..291f14a3f10a 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -15,6 +15,18 @@ / { #size-cells = <2>; clocks { + cmn_pll_nss_clk_200m: cmn-pll-nss-clk-200m { + compatible = "fixed-clock"; + clock-frequency = <200000000>; + #clock-cells = <0>; + }; + + cmn_pll_nss_clk_300m: cmn-pll-nss-clk-300m { + compatible = "fixed-clock"; + clock-frequency = <300000000>; + #clock-cells = <0>; + }; + sleep_clk: sleep-clk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -473,6 +485,22 @@ frame@b128000 { status = "disabled"; }; }; + + nsscc: clock-controller@39b00000{ + compatible = "qcom,ipq5332-nsscc"; + reg = <0x39b00000 0x80000>; + clocks = <&cmn_pll_nss_clk_200m>, + <&cmn_pll_nss_clk_300m>, + <&gcc GPLL0_OUT_AUX>, + <0>, + <0>, + <0>, + <0>, + <&xo_board>; + #clock-cells = <0x1>; + #reset-cells = <0x1>; + #power-domain-cells = <1>; + }; }; timer { From patchwork Mon Oct 30 09:47:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kathiravan Thirumoorthy X-Patchwork-Id: 159587 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp2088631vqb; Mon, 30 Oct 2023 02:49:38 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFGEr5AwhnmlZzHyvEGMPwa+sSpirDSt6NwKVwr1R7djhyv+Dwza+FpanOdF1abfdtqUoaJ X-Received: by 2002:a17:902:e886:b0:1cc:3dc6:8cfc with SMTP id w6-20020a170902e88600b001cc3dc68cfcmr2600320plg.22.1698659378504; Mon, 30 Oct 2023 02:49:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698659378; cv=none; d=google.com; s=arc-20160816; b=jol7r0wZ2l1g2z3MGkas09I+UoWt2w8ULjrJDaidbV2YFB26VkKc4a7dg64CfSsuBf vZny/JzAujOL9TN4jAlm6k3fFFSftUkE01qBR9ncsElikxDrOCvtHy0k+v2MOfpjus7V TCRpnOjbftOaiy+6zuhBzxqTAkZiQDJcl2WDs1YMeKsXxaK2/JotbRdqx+bDLoCuAXSp BS0J2tRN0mfJGn01QIxX2ereAiDGKiK8BITzdZYVgOwrMB/ZzLojmi8FKKRwC2ujkmVD Najjj43dXE/NPe1p7NN5/SMu0xXEzUokxrQyrrDCXbGAbd5/J0TrY/lbweX167CN98++ RxEw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=M6YE6usfdiaDl6y22WzZBuFLQNHUK9IyY63njJBeIiI=; fh=gfCwzJd/1auOn37TCxo+G+sybAUeroi1DxMWExaAZgc=; b=KPWNeIsrCA7ZwXud8PJkvZrRlplOrGafOHfvRn3n05oZKVeI8deRxxYUtyw7g6LBNK M9jM8cNDujOaXntcXoSG9nEzlkNTjJ0NyGpUbcGdWJPn1lATG76d9+dn1PVM/RIlCG8M BpDx7f+UkaL7Rc4CUYU0hIHdYjlJQvCxu8JPbdZmtAH9DxNfSvd3IJHZ2jDmYYOEvFZX 8/TJ1jLEa6v/iQBkucNSGf/lBXJfqlfkCUfQNEd2qW1zGE765MaF2oLYhnlROIrmdUde AV1GC6MRJMmnQ8RpqNExl7WHExld3i6qBCW4bKy8sSM1mwt8JYfOZQtMVaxBLw++bCz0 L4ag== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=ZInvVHCK; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id jd9-20020a170903260900b001c9de48fc7asi4871066plb.170.2023.10.30.02.49.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Oct 2023 02:49:38 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=ZInvVHCK; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 9528180C2452; Mon, 30 Oct 2023 02:49:37 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232804AbjJ3Jt2 (ORCPT + 31 others); Mon, 30 Oct 2023 05:49:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59760 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232805AbjJ3Jsz (ORCPT ); Mon, 30 Oct 2023 05:48:55 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DE6B01A8; Mon, 30 Oct 2023 02:48:23 -0700 (PDT) Received: from pps.filterd (m0279862.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 39U9B7qq021806; Mon, 30 Oct 2023 09:48:15 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : date : subject : mime-version : content-type : content-transfer-encoding : message-id : references : in-reply-to : to : cc; s=qcppdkim1; bh=M6YE6usfdiaDl6y22WzZBuFLQNHUK9IyY63njJBeIiI=; b=ZInvVHCKKd/kwcx+YNztRkt4tRk3raYDjPhB3aXihDZqfs8wx4Fgagf5WuQFAm8tV0IT 70X/I/RczDP3RAXwSrU0cOzghmKtraqKarLqz7rWh4zgKiwYRs3auUZg9ky6Y9+Vckml gVB5+8o+JIYTmZOwJ5eEufwT99BUgMkzvqQLVjRaOVRAjWJhLJm+ZavufD7zYIAeTHbM +u3rIwp3yAR4FsyO2WEIoaS+MLhNNOT1C63LiVtIQQrrzYUaR9A/NAQaRtSckVVNim9p CbJDzCQcNmNH9D95RKbk6F/e9nrbo4In25I0WFycX8c+ASzYnZ9QZGE+l1Sn5qMRwhIl pQ== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3u0u2qkaqc-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 30 Oct 2023 09:48:15 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 39U9mEFi017824 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 30 Oct 2023 09:48:14 GMT Received: from hu-kathirav-blr.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.39; Mon, 30 Oct 2023 02:48:08 -0700 From: Kathiravan Thirumoorthy Date: Mon, 30 Oct 2023 15:17:23 +0530 Subject: [PATCH 8/8] arm64: defconfig: build NSS Clock Controller driver for IPQ5332 MIME-Version: 1.0 Message-ID: <20231030-ipq5332-nsscc-v1-8-6162a2c65f0a@quicinc.com> References: <20231030-ipq5332-nsscc-v1-0-6162a2c65f0a@quicinc.com> In-Reply-To: <20231030-ipq5332-nsscc-v1-0-6162a2c65f0a@quicinc.com> To: Bjorn Andersson , Andy Gross , Konrad Dybcio , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Catalin Marinas , Will Deacon CC: , , , , , , "Kathiravan Thirumoorthy" X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1698659244; l=619; i=quic_kathirav@quicinc.com; s=20230906; h=from:subject:message-id; bh=Ka2Puxp6GzvfCF+k1mTawKzWStf8whNbVMFFBPTF228=; b=i3HBsZuuL8VZD8ySQ4Ban1f5nOJsZ06tXSn6krN9Gd7P7+mqEAYzZX+NA3fBJffI4TY2phlw7 HDqkMoN9Px/DYTEQdbyZR5a+3rWVFARbx0aNvuBsq9I4wy5/KQ8b2+S X-Developer-Key: i=quic_kathirav@quicinc.com; a=ed25519; pk=xWsR7pL6ch+vdZ9MoFGEaP61JUaRf0XaZYWztbQsIiM= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 1Aw7B_IO2BhtIDyVc4vsUH20pVBjkOv2 X-Proofpoint-GUID: 1Aw7B_IO2BhtIDyVc4vsUH20pVBjkOv2 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.987,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2023-10-30_08,2023-10-27_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 clxscore=1015 malwarescore=0 suspectscore=0 mlxlogscore=685 priorityscore=1501 bulkscore=0 lowpriorityscore=0 adultscore=0 mlxscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2310240000 definitions=main-2310300074 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Mon, 30 Oct 2023 02:49:37 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781173456579626716 X-GMAIL-MSGID: 1781173456579626716 Build Qualcomm IPQ9574 NSSCC driver as module. Signed-off-by: Kathiravan Thirumoorthy --- arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index b60aa1f89343..c075202d255d 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1223,6 +1223,7 @@ CONFIG_QCOM_CLK_SMD_RPM=y CONFIG_QCOM_CLK_RPMH=y CONFIG_IPQ_APSS_6018=y CONFIG_IPQ_GCC_5332=y +CONFIG_IPQ_NSSCC_5332=m CONFIG_IPQ_APSS_5018=y CONFIG_IPQ_GCC_5018=y CONFIG_IPQ_GCC_6018=y