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Wysocki" , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , "Oleksandr Natalenko" , Meng Li Subject: [PATCH V10 1/7] x86: Drop CPU_SUP_INTEL from SCHED_MC_PRIO for the expansion. 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Tested-by: Oleksandr Natalenko Reviewed-by: Mario Limonciello Reviewed-by: Huang Rui Signed-off-by: Meng Li --- arch/x86/Kconfig | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 66bfabae8814..a2e163acf623 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1054,8 +1054,9 @@ config SCHED_MC config SCHED_MC_PRIO bool "CPU core priorities scheduler support" - depends on SCHED_MC && CPU_SUP_INTEL - select X86_INTEL_PSTATE + depends on SCHED_MC + select X86_INTEL_PSTATE if CPU_SUP_INTEL + select X86_AMD_PSTATE if CPU_SUP_AMD && ACPI select CPU_FREQ default y help From patchwork Mon Oct 30 06:33:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Meng Li X-Patchwork-Id: 159495 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp2017416vqb; Sun, 29 Oct 2023 23:36:04 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGFlQdhbRcRinCx70awvyGmNnjOtxw7NYk7cCdhHVmJV52BF5vI5SuFtAH/YYrm9b1exDQx X-Received: by 2002:a05:6a00:1389:b0:6be:5a1a:3b93 with SMTP id t9-20020a056a00138900b006be5a1a3b93mr8194055pfg.4.1698647764473; Sun, 29 Oct 2023 23:36:04 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1698647764; cv=pass; d=google.com; s=arc-20160816; b=hUzKzQGgZ5eNGbFqOs6+1qdL7xpcuH6PpLjrKMQOtega9NOjLOcxP1xOPCNiy0zcsN 0xbkwFPIXNGv8Rb7G17ojqQ9lvHqOry0bZPJ6xq9wFYFEh68l2cJMftQ2z1u278MGw/Z zQLH9NcOMyUSIj0dGWeR0SKz8mmO0M3UniVymUhlvDA1T5VefdfX9SnVPgh8p7xiU8dd VM170bgC+hlCLRkLUGgZABGrPVKUE9HeriAQSzKCv4/2t6OCkYSUJSQ52WgZ69Nm/otA S3Tunb4I0c/PR/BGE15J5UVH7Vnu89qaOQ8QsJjmwfL4ft4sRdCES6iGkYeK8C+ZRiOq JghQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=AlF2WKiSUPyODRJ7ueMUccEPh7maCKY1Dj6+XRqyp7A=; fh=px4bRiBuq3I9SXanjlkRNLIg6oMFdG8uo3HGDz2F7II=; b=RRlAUJ3gCDeVF/jZPMy1axRfpOcisacRwpE+VYd1Eri8yxmJqYNzZyTD9kC5nvzkC4 INkXCXpxziFtN+nFmfL9z8tuZ/+PVrdy7W5vydenZInpLOGqAPeqxzMMvDDbRKjbCj4S F8QqMQk429jQmoDRmHcjqxsW50DJWUr4lZMdN39r4PtviuL2ENet9v1E91NeC3Wm3TUR 9rtHk0Fl8pCMYmp7crDRLpsAZM4wj50Gu4yrJ83SS7l0CcJZ09wjUbM3yYRCOrBRFGII glpBrVX82R0u8hrolrh4XbC5kupNJ7/PXmuYtMSfogZhoFiUMY4CmSSavZJdYuv8vEM9 PNrQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=FD00Zt0d; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from snail.vger.email (snail.vger.email. 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Wysocki" , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , "Oleksandr Natalenko" , Meng Li , Wyes Karny Subject: [PATCH V10 2/7] acpi: cppc: Add get the highest performance cppc control Date: Mon, 30 Oct 2023 14:33:58 +0800 Message-ID: <20231030063403.3502816-3-li.meng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231030063403.3502816-1-li.meng@amd.com> References: <20231030063403.3502816-1-li.meng@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE32:EE_|CH3PR12MB8548:EE_ X-MS-Office365-Filtering-Correlation-Id: 794eddf4-1a9a-40ea-d8b7-08dbd9126217 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: OjP155DwLX+Wk7N2cK4X+tdrAaZiYfo7jD0yJDIuaTXOcW3l5HWku21iIeMQoNGlNU27rf2IpaozneNkmpCuPuhv9f8JJU6+pBvMs69EvY3Ld94L1vEGgC4SzHJjcpWXgVn/CD6OzhNQGzhbLT81FEp0eDItNgMo4S6TKZ4tzQhs6W9YY8o1nbyBof1Yublup6IMcyqPjO9eYN/omTbNHEbK341uvZJWXRu7AHfOPDZcNE2a710y53KIlNiQxwQ/EWG9pDkB0tPRQFEBehVUphNu973w4elKRF6lFRTNSyFD5ktXL+xyNgVU9QXOLMuLzw70WJKdZE/naR3CO6bwsTPUNy+SJn68YaSg2wYPh9EuwAVo19phPknYBiGwUsBr1Nyy2kg9X0VDF5k6vFLSl02HVm1MeQmNXGPM0Zpr0ZtFhVBkSZPOMJ7t01dUli24usU5g1mEggPQPHJAPrN13laoPod6YTpwbmDtDaMxbUgPAWlfzDARBxlHqvcUZGGxH2TZWdxNpl5meSdhlpyyLr1xgQDLzLjBWn9pYa6RWRGh5tmdJdrGc+rnkqWc4Yn2ZyO9Wcr1/AozIN+kEeQxel5kL24peRjlbmKNUxP7kyiAzRr834WKjHTw2wnIcpqMQsxd+8zSr3QFuvZv1QBEDl53Xzax8M3h2uQMLnbwyBSzUFfDdJKBem0ahg+FbbpaRs3KlABla8GsTVEJgOpqQici4mw3gK46J9RBTSFCCygtkt5t242eTcF9gdRQqpkA75N5HA8G3MayzG5M1chPVmTZfrpd7xauWGA58xr1Rc8= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(346002)(396003)(136003)(376002)(39860400002)(230922051799003)(64100799003)(82310400011)(186009)(1800799009)(451199024)(46966006)(40470700004)(36840700001)(7696005)(966005)(478600001)(16526019)(26005)(1076003)(2616005)(336012)(47076005)(426003)(2906002)(5660300002)(7416002)(54906003)(41300700001)(316002)(110136005)(70206006)(8676002)(8936002)(4326008)(70586007)(6636002)(36860700001)(86362001)(36756003)(356005)(81166007)(82740400003)(40480700001)(40460700003)(15583001)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Oct 2023 06:35:18.0332 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 794eddf4-1a9a-40ea-d8b7-08dbd9126217 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE32.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8548 X-Spam-Status: No, score=-1.2 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Sun, 29 Oct 2023 23:35:40 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781161278273470136 X-GMAIL-MSGID: 1781161278273470136 Add support for getting the highest performance to the generic CPPC driver. This enables downstream drivers such as amd-pstate to discover and use these values. Please refer to the ACPI_Spec for details on continuous performance control of CPPC. Tested-by: Oleksandr Natalenko Reviewed-by: Mario Limonciello Reviewed-by: Wyes Karny Acked-by: Huang Rui Signed-off-by: Meng Li Link: https://uefi.org/specs/ACPI/6.5/08_Processor_Configuration_and_Control.html?highlight=cppc#highest-performance --- drivers/acpi/cppc_acpi.c | 13 +++++++++++++ include/acpi/cppc_acpi.h | 5 +++++ 2 files changed, 18 insertions(+) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 7ff269a78c20..ad388a0e8484 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1154,6 +1154,19 @@ int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf) return cppc_get_perf(cpunum, NOMINAL_PERF, nominal_perf); } +/** + * cppc_get_highest_perf - Get the highest performance register value. + * @cpunum: CPU from which to get highest performance. + * @highest_perf: Return address. + * + * Return: 0 for success, -EIO otherwise. + */ +int cppc_get_highest_perf(int cpunum, u64 *highest_perf) +{ + return cppc_get_perf(cpunum, HIGHEST_PERF, highest_perf); +} +EXPORT_SYMBOL_GPL(cppc_get_highest_perf); + /** * cppc_get_epp_perf - Get the epp register value. * @cpunum: CPU from which to get epp preference value. diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index 6126c977ece0..c0b69ffe7bdb 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -139,6 +139,7 @@ struct cppc_cpudata { #ifdef CONFIG_ACPI_CPPC_LIB extern int cppc_get_desired_perf(int cpunum, u64 *desired_perf); extern int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf); +extern int cppc_get_highest_perf(int cpunum, u64 *highest_perf); extern int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs); extern int cppc_set_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls); extern int cppc_set_enable(int cpu, bool enable); @@ -165,6 +166,10 @@ static inline int cppc_get_nominal_perf(int cpunum, u64 *nominal_perf) { return -ENOTSUPP; } +static inline int cppc_get_highest_perf(int cpunum, u64 *highest_perf) +{ + return -ENOTSUPP; +} static inline int cppc_get_perf_ctrs(int cpu, struct cppc_perf_fb_ctrs *perf_fb_ctrs) { return -ENOTSUPP; From patchwork Mon Oct 30 06:33:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Meng Li X-Patchwork-Id: 159496 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp2017443vqb; Sun, 29 Oct 2023 23:36:07 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH5Uw275eRghdp4lGnaIKMKPllzeeoPjEOYV4YQFsUth9aOhia0UEHyTcivquo9X9tTnx1o X-Received: by 2002:a05:6808:646:b0:3b2:d8c8:7bfa with SMTP id z6-20020a056808064600b003b2d8c87bfamr10026729oih.8.1698647766729; Sun, 29 Oct 2023 23:36:06 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1698647766; cv=pass; d=google.com; s=arc-20160816; b=xhtniBrSuIreeESSrT02qRMsNEqtFfPTbiBSirwMfSVaBfdznRxEZQBR2vMq0Hycdg dsKzlOz36C8LBfGnswKnEf0P+lR+BkU6fbKpm4dCpIsIHZbCBWC2Fif/Ilon0E+Xrtg9 yXqncBeDXRdlJwwn53kHFUEK3QPKV1IcRZjN/drZbwPrPBRTa0kwaBrZyurtZUihoAY0 md2hrLWLJSi9gx7cYCwP7WJl1jcIlGymjVZZUtpw0Mj761CofJGLxHu96qC3a4hxgeiI CJgEfZFQL6bzJGGIWOv6M2FYWIhsbi99cKhWUHOzUCp7GGLBr26tkF1wPQ+IieTKFfTY hTZg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ZjRa7W9PTgSIh5GDUEyEvQZ2JJ3VM/S9oH6hIqdWHrI=; fh=px4bRiBuq3I9SXanjlkRNLIg6oMFdG8uo3HGDz2F7II=; b=n0vRZErSaMaMjTnzeriDzO2C7UUo3MJVV0carv65N+aWTilawjacl4UDHCuYR4F0Wz PHsdkJmuthtI85W2qlSyUGMd7rVpuGDDygBJWdFjFdwKDpVYpidwsMDOzoxSRwUaoXlW Pcsk8uBGlXM6kdR6uipNKkoIB43NS58HP93dBEBQVx9tXp6oEbXurRiZ9SxNyszfE1UK nYGpc/IVboZv1GxAIqO5/7jWMO54zcWAkTNIh8jIu/BtSIQaQjFDNn5TKghffGbfDzaI 7G/Jz6lzbNO3PMmo1b9JB9uYaX6g8oLUXHL7q6kXYobSbcq5WzkTRjBOWDvdMNpSGQra dnTQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=mEmum47t; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from snail.vger.email (snail.vger.email. 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Wysocki" , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , "Oleksandr Natalenko" , Meng Li , Wyes Karny Subject: [PATCH V10 3/7] cpufreq: amd-pstate: Enable amd-pstate preferred core supporting. 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We call it amd-pstate preferrred core. Here sched_set_itmt_core_prio() is called to set priorities and sched_set_itmt_support() is called to enable ITMT feature. amd-pstate driver uses the highest performance value to indicate the priority of CPU. The higher value has a higher priority. The initial core rankings are set up by amd-pstate when the system boots. Add a variable hw_prefcore in cpudata structure. It will check if the processor and power firmware support preferred core feature. Add one new early parameter `disable` to allow user to disable the preferred core. Only when hardware supports preferred core and user set `enabled` in early parameter, amd pstate driver supports preferred core featue. Tested-by: Oleksandr Natalenko Reviewed-by: Huang Rui Reviewed-by: Wyes Karny Reviewed-by: Mario Limonciello Co-developed-by: Perry Yuan Signed-off-by: Perry Yuan Signed-off-by: Meng Li --- drivers/cpufreq/amd-pstate.c | 141 +++++++++++++++++++++++++++++++---- include/linux/amd-pstate.h | 4 + 2 files changed, 129 insertions(+), 16 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 9a1e194d5cf8..2033e5e70017 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -37,6 +37,7 @@ #include #include #include +#include #include #include @@ -49,6 +50,7 @@ #define AMD_PSTATE_TRANSITION_LATENCY 20000 #define AMD_PSTATE_TRANSITION_DELAY 1000 +#define AMD_PSTATE_PREFCORE_THRESHOLD 166 /* * TODO: We need more time to fine tune processors with shared memory solution @@ -64,6 +66,7 @@ static struct cpufreq_driver amd_pstate_driver; static struct cpufreq_driver amd_pstate_epp_driver; static int cppc_state = AMD_PSTATE_UNDEFINED; static bool cppc_enabled; +static bool amd_pstate_prefcore = true; /* * AMD Energy Preference Performance (EPP) @@ -290,23 +293,21 @@ static inline int amd_pstate_enable(bool enable) static int pstate_init_perf(struct amd_cpudata *cpudata) { u64 cap1; - u32 highest_perf; int ret = rdmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1, &cap1); if (ret) return ret; - /* - * TODO: Introduce AMD specific power feature. - * - * CPPC entry doesn't indicate the highest performance in some ASICs. + /* For platforms that do not support the preferred core feature, the + * highest_pef may be configured with 166 or 255, to avoid max frequency + * calculated wrongly. we take the AMD_CPPC_HIGHEST_PERF(cap1) value as + * the default max perf. */ - highest_perf = amd_get_highest_perf(); - if (highest_perf > AMD_CPPC_HIGHEST_PERF(cap1)) - highest_perf = AMD_CPPC_HIGHEST_PERF(cap1); - - WRITE_ONCE(cpudata->highest_perf, highest_perf); + if (cpudata->hw_prefcore) + WRITE_ONCE(cpudata->highest_perf, AMD_PSTATE_PREFCORE_THRESHOLD); + else + WRITE_ONCE(cpudata->highest_perf, AMD_CPPC_HIGHEST_PERF(cap1)); WRITE_ONCE(cpudata->nominal_perf, AMD_CPPC_NOMINAL_PERF(cap1)); WRITE_ONCE(cpudata->lowest_nonlinear_perf, AMD_CPPC_LOWNONLIN_PERF(cap1)); @@ -318,17 +319,15 @@ static int pstate_init_perf(struct amd_cpudata *cpudata) static int cppc_init_perf(struct amd_cpudata *cpudata) { struct cppc_perf_caps cppc_perf; - u32 highest_perf; int ret = cppc_get_perf_caps(cpudata->cpu, &cppc_perf); if (ret) return ret; - highest_perf = amd_get_highest_perf(); - if (highest_perf > cppc_perf.highest_perf) - highest_perf = cppc_perf.highest_perf; - - WRITE_ONCE(cpudata->highest_perf, highest_perf); + if (cpudata->hw_prefcore) + WRITE_ONCE(cpudata->highest_perf, AMD_PSTATE_PREFCORE_THRESHOLD); + else + WRITE_ONCE(cpudata->highest_perf, cppc_perf.highest_perf); WRITE_ONCE(cpudata->nominal_perf, cppc_perf.nominal_perf); WRITE_ONCE(cpudata->lowest_nonlinear_perf, @@ -676,6 +675,80 @@ static void amd_perf_ctl_reset(unsigned int cpu) wrmsrl_on_cpu(cpu, MSR_AMD_PERF_CTL, 0); } +/* + * Set amd-pstate preferred core enable can't be done directly from cpufreq callbacks + * due to locking, so queue the work for later. + */ +static void amd_pstste_sched_prefcore_workfn(struct work_struct *work) +{ + sched_set_itmt_support(); +} +static DECLARE_WORK(sched_prefcore_work, amd_pstste_sched_prefcore_workfn); + +/* + * Get the highest performance register value. + * @cpu: CPU from which to get highest performance. + * @highest_perf: Return address. + * + * Return: 0 for success, -EIO otherwise. + */ +static int amd_pstate_get_highest_perf(int cpu, u32 *highest_perf) +{ + int ret; + + if (boot_cpu_has(X86_FEATURE_CPPC)) { + u64 cap1; + + ret = rdmsrl_safe_on_cpu(cpu, MSR_AMD_CPPC_CAP1, &cap1); + if (ret) + return ret; + WRITE_ONCE(*highest_perf, AMD_CPPC_HIGHEST_PERF(cap1)); + } else { + u64 cppc_highest_perf; + + ret = cppc_get_highest_perf(cpu, &cppc_highest_perf); + if (ret) + return ret; + WRITE_ONCE(*highest_perf, cppc_highest_perf); + } + + return (ret); +} + +#define CPPC_MAX_PERF U8_MAX + +static void amd_pstate_init_prefcore(struct amd_cpudata *cpudata) +{ + int ret, prio; + u32 highest_perf; + + ret = amd_pstate_get_highest_perf(cpudata->cpu, &highest_perf); + if (ret) + return; + + cpudata->hw_prefcore = true; + /* check if CPPC preferred core feature is enabled*/ + if (highest_perf < CPPC_MAX_PERF) + prio = (int)highest_perf; + else { + pr_debug("AMD CPPC preferred core is unsupported!\n"); + cpudata->hw_prefcore = false; + return; + } + + if (!amd_pstate_prefcore) + return; + + /* + * The priorities can be set regardless of whether or not + * sched_set_itmt_support(true) has been called and it is valid to + * update them at any time after it has been called. + */ + sched_set_itmt_core_prio(prio, cpudata->cpu); + + schedule_work(&sched_prefcore_work); +} + static int amd_pstate_cpu_init(struct cpufreq_policy *policy) { int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret; @@ -697,6 +770,8 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) cpudata->cpu = policy->cpu; + amd_pstate_init_prefcore(cpudata); + ret = amd_pstate_init_perf(cpudata); if (ret) goto free_cpudata1; @@ -845,6 +920,17 @@ static ssize_t show_amd_pstate_highest_perf(struct cpufreq_policy *policy, return sysfs_emit(buf, "%u\n", perf); } +static ssize_t show_amd_pstate_hw_prefcore(struct cpufreq_policy *policy, + char *buf) +{ + bool hw_prefcore; + struct amd_cpudata *cpudata = policy->driver_data; + + hw_prefcore = READ_ONCE(cpudata->hw_prefcore); + + return sysfs_emit(buf, "%s\n", hw_prefcore ? "supported" : "unsupported"); +} + static ssize_t show_energy_performance_available_preferences( struct cpufreq_policy *policy, char *buf) { @@ -1037,18 +1123,27 @@ static ssize_t status_store(struct device *a, struct device_attribute *b, return ret < 0 ? ret : count; } +static ssize_t prefcore_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sysfs_emit(buf, "%s\n", amd_pstate_prefcore ? "enabled" : "disabled"); +} + cpufreq_freq_attr_ro(amd_pstate_max_freq); cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); cpufreq_freq_attr_ro(amd_pstate_highest_perf); +cpufreq_freq_attr_ro(amd_pstate_hw_prefcore); cpufreq_freq_attr_rw(energy_performance_preference); cpufreq_freq_attr_ro(energy_performance_available_preferences); static DEVICE_ATTR_RW(status); +static DEVICE_ATTR_RO(prefcore); static struct freq_attr *amd_pstate_attr[] = { &amd_pstate_max_freq, &amd_pstate_lowest_nonlinear_freq, &amd_pstate_highest_perf, + &amd_pstate_hw_prefcore, NULL, }; @@ -1056,6 +1151,7 @@ static struct freq_attr *amd_pstate_epp_attr[] = { &amd_pstate_max_freq, &amd_pstate_lowest_nonlinear_freq, &amd_pstate_highest_perf, + &amd_pstate_hw_prefcore, &energy_performance_preference, &energy_performance_available_preferences, NULL, @@ -1063,6 +1159,7 @@ static struct freq_attr *amd_pstate_epp_attr[] = { static struct attribute *pstate_global_attributes[] = { &dev_attr_status.attr, + &dev_attr_prefcore.attr, NULL }; @@ -1114,6 +1211,8 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) cpudata->cpu = policy->cpu; cpudata->epp_policy = 0; + amd_pstate_init_prefcore(cpudata); + ret = amd_pstate_init_perf(cpudata); if (ret) goto free_cpudata1; @@ -1527,7 +1626,17 @@ static int __init amd_pstate_param(char *str) return amd_pstate_set_driver(mode_idx); } + +static int __init amd_prefcore_param(char *str) +{ + if (!strcmp(str, "disable")) + amd_pstate_prefcore = false; + + return 0; +} + early_param("amd_pstate", amd_pstate_param); +early_param("amd_prefcore", amd_prefcore_param); MODULE_AUTHOR("Huang Rui "); MODULE_DESCRIPTION("AMD Processor P-state Frequency Driver"); diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h index 446394f84606..87e140e9e6db 100644 --- a/include/linux/amd-pstate.h +++ b/include/linux/amd-pstate.h @@ -52,6 +52,9 @@ struct amd_aperf_mperf { * @prev: Last Aperf/Mperf/tsc count value read from register * @freq: current cpu frequency value * @boost_supported: check whether the Processor or SBIOS supports boost mode + * @hw_prefcore: check whether HW supports preferred core featue. + * Only when hw_prefcore and early prefcore param are true, + * AMD P-State driver supports preferred core featue. * @epp_policy: Last saved policy used to set energy-performance preference * @epp_cached: Cached CPPC energy-performance preference value * @policy: Cpufreq policy value @@ -81,6 +84,7 @@ struct amd_cpudata { u64 freq; bool boost_supported; + bool hw_prefcore; /* EPP feature related attributes*/ s16 epp_policy; From patchwork Mon Oct 30 06:34:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Meng Li X-Patchwork-Id: 159499 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp2017536vqb; Sun, 29 Oct 2023 23:36:23 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGchYlXx+Lgq8J3zvLxuemS1LFDSil8X2pt9/RRhP1wfscQmZiTc8Sw4840VIX9Vps/7cGC X-Received: by 2002:a05:6a20:3d03:b0:128:ffb7:dcfe with SMTP id y3-20020a056a203d0300b00128ffb7dcfemr12053183pzi.1.1698647783164; Sun, 29 Oct 2023 23:36:23 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1698647783; cv=pass; d=google.com; s=arc-20160816; b=G8FY0puJhxVGUJhXF8IHhGNC1MXg72ipFQTfT3MQ5OCHeTzADO92IttQ3hm8NdhCqx iIEpfvkhtI/SDQHUwLhj5fQUVt9LLmu33JsfjQOTVlEcF9tpl+9PFbabhYBWCdLPMbby 7aDZbNr4adtoSKQrw6R3FfVk7cFKFwoHmxnvNRLtDel37ZE/4ilXBiBsYohqylUHFOy7 p6/JVXQ2bnsR1CeC22fLLYerBFW95oVTUeTJrRYC33tjaBBXucIrSeLkAUKcZ7YaXurx 44ac6QDdY/zdyvD6OlDEH1LXpR5f9eXR0I0cWkjubpd7BU7AAK4Vkb5LbdlIXlOaMdE5 S1Fg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=iEG57ub2uyja18iSbeWFZGvSQXhoZh8gCxORPlmvouA=; fh=hGvksXpWJomenCq+IRP0QZoot/B1Zo6LHbgOlSKBIRE=; b=iBAGfybk1Zw2ikier+02R0XAxgqDAGCuH0bPfo7iNJKQXxToZGDP1g9dU1P3/GnsCm tVT5Vebp0V/DWQFPK5t/hJqlOk1UDO+QvtVioISunknzikPvc2OMmPFLYKDnVVALeOND 6HqTYllzjq603mPTWxDblYEI/2FU4lViOQz9cz7UCczF271p/Ml+4uqmdzH4FST0kNse WT9h6M/Tb4lfTnXsAjkOSNpKGqM8qdK8F8HF0yEv61CvRJKlKVesx8TQxiGUv4mubaMo nOTpMXuGKl9rL4eGHQ4NW1UrS9O5t1AHFcOgYJRXxhBXxGj6Rs575++36fdrfLtYbPDT QQ8w== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b="a8DNGrK/"; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from howler.vger.email (howler.vger.email. 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Wysocki" , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , "Oleksandr Natalenko" , Meng Li Subject: [PATCH V10 4/7] cpufreq: Add a notification message that the highest perf has changed Date: Mon, 30 Oct 2023 14:34:00 +0800 Message-ID: <20231030063403.3502816-5-li.meng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231030063403.3502816-1-li.meng@amd.com> References: <20231030063403.3502816-1-li.meng@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB74:EE_|SJ2PR12MB8941:EE_ X-MS-Office365-Filtering-Correlation-Id: 49dc4ece-0bd9-4d46-ab80-08dbd912685a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: s4CynvEVHF0RBX6m6nX7fjpdUDEQGGPlPSblLnk/mQBORzo17Yy4HSQPBz5bzV3OZzo0AZ10OAss+6TTRAGxvQQfBGeTrRP32rHt3t/Ehi1dXKCq7sfqO812IGl2j9py7T5zRJjnI7x8cI1so2e3dbKII6r5Xh8xWpB0q+IstdHMiQPVoWatzQiHu7sXc9OF/Aq/zELYEVBqyy59UpElE8630a34jgcKoeBXvHW7FZwYjUrbVBNGRLDNqhKTpWkxNnhVTsz+5XgiQcqSoiUQdN2no7W6s/KYlb6vdwIbSMPTaMap4A3V7f6z9kOwdT3kAMn9RjQaQIlJMDEhbGoyIjmg7CaaMblAgMRxZJHcSr1OiAeAVpyVLRysF+U9GLPlcvyY7eTk6M3UhTrj7erFzk1JEfCOVd1++FamCY9CQmUwPrpn+58Dqcs8F+YXWPl9rMF+u6Enxy4HC61x65+xCXoFnDsmXMBxGhoCtF0qoNYqXu5r/SgvmKB+tWTtbiJHa1zd1Tv4RsQ9JhW1RZzB+dby8rYv/zj2hJWJjzNAsD6qjjFGd4iwsiyuyUlN7LR2dtEK1kSbUKWuYJClOg2Oo+HtZvgO9xEXhOmcYbyME4B3Qc71iYs5t0m7i+Tvh8LBCypFYj5wItSuFsW2IPulQr9QKQinuSTeK1kBtlLWrnEzsY3l8Psj4OD5exE+HnI06UNm6JgAUaFzAm2dmQL5Otvx+cIrUdwGH2iYnRIiw0QecGWzL5y8CFCn5D6o4WfWSZ0zGJoxIyA3qLzlGgk5OK1jEFdSB8rTv/C0ABUiwLU= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(136003)(376002)(346002)(396003)(39860400002)(230922051799003)(82310400011)(186009)(1800799009)(64100799003)(451199024)(36840700001)(40470700004)(46966006)(40460700003)(2906002)(15650500001)(7416002)(5660300002)(41300700001)(4326008)(8936002)(8676002)(36756003)(40480700001)(86362001)(82740400003)(316002)(110136005)(54906003)(6636002)(36860700001)(47076005)(356005)(81166007)(70206006)(70586007)(83380400001)(426003)(1076003)(16526019)(336012)(2616005)(7696005)(966005)(478600001)(26005)(6666004)(226483002)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Oct 2023 06:35:28.5999 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 49dc4ece-0bd9-4d46-ab80-08dbd912685a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB74.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8941 X-Spam-Status: No, score=-1.3 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on howler.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Sun, 29 Oct 2023 23:36:16 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781161297777535416 X-GMAIL-MSGID: 1781161297777535416 ACPI 6.5 section 8.4.6.1.1.1 specifies that Notify event 0x85 can be emmitted to cause the the OSPM to re-evaluate the highest performance register. Add support for this event. Tested-by: Oleksandr Natalenko Reviewed-by: Mario Limonciello Reviewed-by: Huang Rui Signed-off-by: Meng Li Link: https://uefi.org/specs/ACPI/6.5/05_ACPI_Software_Programming_Model.html#processor-device-notification-values --- drivers/acpi/processor_driver.c | 6 ++++++ drivers/cpufreq/cpufreq.c | 13 +++++++++++++ include/linux/cpufreq.h | 5 +++++ 3 files changed, 24 insertions(+) diff --git a/drivers/acpi/processor_driver.c b/drivers/acpi/processor_driver.c index 4bd16b3f0781..29b2fb68a35d 100644 --- a/drivers/acpi/processor_driver.c +++ b/drivers/acpi/processor_driver.c @@ -27,6 +27,7 @@ #define ACPI_PROCESSOR_NOTIFY_PERFORMANCE 0x80 #define ACPI_PROCESSOR_NOTIFY_POWER 0x81 #define ACPI_PROCESSOR_NOTIFY_THROTTLING 0x82 +#define ACPI_PROCESSOR_NOTIFY_HIGEST_PERF_CHANGED 0x85 MODULE_AUTHOR("Paul Diefenbaugh"); MODULE_DESCRIPTION("ACPI Processor Driver"); @@ -83,6 +84,11 @@ static void acpi_processor_notify(acpi_handle handle, u32 event, void *data) acpi_bus_generate_netlink_event(device->pnp.device_class, dev_name(&device->dev), event, 0); break; + case ACPI_PROCESSOR_NOTIFY_HIGEST_PERF_CHANGED: + cpufreq_update_highest_perf(pr->id); + acpi_bus_generate_netlink_event(device->pnp.device_class, + dev_name(&device->dev), event, 0); + break; default: acpi_handle_debug(handle, "Unsupported event [0x%x]\n", event); break; diff --git a/drivers/cpufreq/cpufreq.c b/drivers/cpufreq/cpufreq.c index 4bc15634d49c..e66b040b0c61 100644 --- a/drivers/cpufreq/cpufreq.c +++ b/drivers/cpufreq/cpufreq.c @@ -2717,6 +2717,19 @@ void cpufreq_update_limits(unsigned int cpu) } EXPORT_SYMBOL_GPL(cpufreq_update_limits); +/** + * cpufreq_update_highest_perf - Update highest performance for a given CPU. + * @cpu: CPU to update the highest performance for. + * + * Invoke the driver's ->update_highest_perf callback if present + */ +void cpufreq_update_highest_perf(unsigned int cpu) +{ + if (cpufreq_driver->update_highest_perf) + cpufreq_driver->update_highest_perf(cpu); +} +EXPORT_SYMBOL_GPL(cpufreq_update_highest_perf); + /********************************************************************* * BOOST * *********************************************************************/ diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h index 1c5ca92a0555..f62257b2a42f 100644 --- a/include/linux/cpufreq.h +++ b/include/linux/cpufreq.h @@ -235,6 +235,7 @@ int cpufreq_get_policy(struct cpufreq_policy *policy, unsigned int cpu); void refresh_frequency_limits(struct cpufreq_policy *policy); void cpufreq_update_policy(unsigned int cpu); void cpufreq_update_limits(unsigned int cpu); +void cpufreq_update_highest_perf(unsigned int cpu); bool have_governor_per_policy(void); bool cpufreq_supports_freq_invariance(void); struct kobject *get_governor_parent_kobj(struct cpufreq_policy *policy); @@ -263,6 +264,7 @@ static inline bool cpufreq_supports_freq_invariance(void) return false; } static inline void disable_cpufreq(void) { } +static inline void cpufreq_update_highest_perf(unsigned int cpu) { } #endif #ifdef CONFIG_CPU_FREQ_STAT @@ -380,6 +382,9 @@ struct cpufreq_driver { /* Called to update policy limits on firmware notifications. */ void (*update_limits)(unsigned int cpu); + /* Called to update highest performance on firmware notifications. */ + void (*update_highest_perf)(unsigned int cpu); + /* optional */ int (*bios_limit)(int cpu, unsigned int *limit); From patchwork Mon Oct 30 06:34:01 2023 Content-Type: text/plain; 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Wysocki" , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , "Oleksandr Natalenko" , Meng Li , Wyes Karny Subject: [PATCH V10 5/7] cpufreq: amd-pstate: Update amd-pstate preferred core ranking dynamically Date: Mon, 30 Oct 2023 14:34:01 +0800 Message-ID: <20231030063403.3502816-6-li.meng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231030063403.3502816-1-li.meng@amd.com> References: <20231030063403.3502816-1-li.meng@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB78:EE_|IA1PR12MB8079:EE_ X-MS-Office365-Filtering-Correlation-Id: 83848946-3249-4772-2799-08dbd9126b61 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 0mRw208Z0nxomr0ZMyYtSBUdTQyLqvFUEuJBCTXsSt52dmeH6EN4dqb5WgVPrVKkVS7B/jfxwDemMJ5Q3oK4SHnnTx1/ZaAN0Wkle1aSSob20BOY3Txtnc1GjTsWlNSWjCFVsGq+rDzq1k9fpv4i3rYOajD6ehE9e7R7gB5E3FtVq1RsbSAKwC6CAPHUlmjvB5GJrrFw6hb5cRA3KCVRamgIU4xozNiLvaZQwMJvX9Y1Q+CXsV1vSyHc1+5knauCslIkY7qrUiiymMwZhF0knFtEz/Q4Xvh27fFd+Hdel0jX81g/LiretjG89t1vnf481jTGmsvEKJ4C2XCbfvrkzctq74rolLbFIQwafmz9M7QA3vrd4n4/YAiwrheLlkDs2KeLRGB6Q2SoRdoi39k8XwjgMs8oR3zdqwUtas/clUuxFjHTvFtQlSLz15eLgXmiqLi3DD8XdU3keZ6ZUdvJeQOCQ8RCXZKLTKOPvhOPjjNtksJUCWT1mZQX9YRQk9zWhceSO9IGBrIKklItpNTP4fOjV2Dbaltl/3wdldlc0h/i4XIf5mFqFGY5fjRXtL0LLmHqHlj2EEv67kuM+inpdOemjT9kR6tUAzWpltNGGBke9vQgj2VzmKAZUas0iBhX5mH4RnsnaPR3HbtbNL1G0s7Mh1soA4klxqNP0WSl2r7q84M/OcWAq/lByHMNOBi1vQXIMbtv2Lis8b52+ZEC+y/feHDa/8L1E1wBCZ/Lx36H5e76PDyjBzs2Tlkuk4NcGMogfeEEnuV1WhH7sizLcQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(39860400002)(396003)(376002)(136003)(346002)(230922051799003)(64100799003)(451199024)(1800799009)(186009)(82310400011)(36840700001)(40470700004)(46966006)(2906002)(86362001)(66899024)(41300700001)(8676002)(4326008)(8936002)(7416002)(5660300002)(15650500001)(40460700003)(36756003)(478600001)(40480700001)(47076005)(7696005)(6666004)(1076003)(81166007)(6636002)(316002)(54906003)(16526019)(110136005)(26005)(70206006)(426003)(336012)(70586007)(82740400003)(83380400001)(36860700001)(2616005)(356005)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Oct 2023 06:35:33.6756 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 83848946-3249-4772-2799-08dbd9126b61 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB78.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB8079 X-Spam-Status: No, score=-1.2 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Sun, 29 Oct 2023 23:36:01 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781161283347776143 X-GMAIL-MSGID: 1781161283347776143 Preferred core rankings can be changed dynamically by the platform based on the workload and platform conditions and accounting for thermals and aging. When this occurs, cpu priority need to be set. Tested-by: Oleksandr Natalenko Reviewed-by: Mario Limonciello Reviewed-by: Wyes Karny Reviewed-by: Huang Rui Signed-off-by: Meng Li --- drivers/cpufreq/amd-pstate.c | 46 ++++++++++++++++++++++++++++++++++++ include/linux/amd-pstate.h | 6 +++++ 2 files changed, 52 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 2033e5e70017..1be33f926678 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -312,6 +312,7 @@ static int pstate_init_perf(struct amd_cpudata *cpudata) WRITE_ONCE(cpudata->nominal_perf, AMD_CPPC_NOMINAL_PERF(cap1)); WRITE_ONCE(cpudata->lowest_nonlinear_perf, AMD_CPPC_LOWNONLIN_PERF(cap1)); WRITE_ONCE(cpudata->lowest_perf, AMD_CPPC_LOWEST_PERF(cap1)); + WRITE_ONCE(cpudata->prefcore_ranking, AMD_CPPC_HIGHEST_PERF(cap1)); return 0; } @@ -333,6 +334,7 @@ static int cppc_init_perf(struct amd_cpudata *cpudata) WRITE_ONCE(cpudata->lowest_nonlinear_perf, cppc_perf.lowest_nonlinear_perf); WRITE_ONCE(cpudata->lowest_perf, cppc_perf.lowest_perf); + WRITE_ONCE(cpudata->prefcore_ranking, cppc_perf.highest_perf); if (cppc_state == AMD_PSTATE_ACTIVE) return 0; @@ -749,6 +751,34 @@ static void amd_pstate_init_prefcore(struct amd_cpudata *cpudata) schedule_work(&sched_prefcore_work); } +static void amd_pstate_update_highest_perf(unsigned int cpu) +{ + struct cpufreq_policy *policy; + struct amd_cpudata *cpudata; + u32 prev_high = 0, cur_high = 0; + int ret; + + if ((!amd_pstate_prefcore) || (!cpudata->hw_prefcore)) + return; + + ret = amd_pstate_get_highest_perf(cpu, &cur_high); + if (ret) + return; + + policy = cpufreq_cpu_get(cpu); + cpudata = policy->driver_data; + prev_high = READ_ONCE(cpudata->prefcore_ranking); + + if (prev_high != cur_high) { + WRITE_ONCE(cpudata->prefcore_ranking, cur_high); + + if (cur_high < CPPC_MAX_PERF) + sched_set_itmt_core_prio((int)cur_high, cpu); + } + + cpufreq_cpu_put(policy); +} + static int amd_pstate_cpu_init(struct cpufreq_policy *policy) { int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret; @@ -920,6 +950,17 @@ static ssize_t show_amd_pstate_highest_perf(struct cpufreq_policy *policy, return sysfs_emit(buf, "%u\n", perf); } +static ssize_t show_amd_pstate_prefcore_ranking(struct cpufreq_policy *policy, + char *buf) +{ + u32 perf; + struct amd_cpudata *cpudata = policy->driver_data; + + perf = READ_ONCE(cpudata->prefcore_ranking); + + return sysfs_emit(buf, "%u\n", perf); +} + static ssize_t show_amd_pstate_hw_prefcore(struct cpufreq_policy *policy, char *buf) { @@ -1133,6 +1174,7 @@ cpufreq_freq_attr_ro(amd_pstate_max_freq); cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); cpufreq_freq_attr_ro(amd_pstate_highest_perf); +cpufreq_freq_attr_ro(amd_pstate_prefcore_ranking); cpufreq_freq_attr_ro(amd_pstate_hw_prefcore); cpufreq_freq_attr_rw(energy_performance_preference); cpufreq_freq_attr_ro(energy_performance_available_preferences); @@ -1143,6 +1185,7 @@ static struct freq_attr *amd_pstate_attr[] = { &amd_pstate_max_freq, &amd_pstate_lowest_nonlinear_freq, &amd_pstate_highest_perf, + &amd_pstate_prefcore_ranking, &amd_pstate_hw_prefcore, NULL, }; @@ -1151,6 +1194,7 @@ static struct freq_attr *amd_pstate_epp_attr[] = { &amd_pstate_max_freq, &amd_pstate_lowest_nonlinear_freq, &amd_pstate_highest_perf, + &amd_pstate_prefcore_ranking, &amd_pstate_hw_prefcore, &energy_performance_preference, &energy_performance_available_preferences, @@ -1491,6 +1535,7 @@ static struct cpufreq_driver amd_pstate_driver = { .suspend = amd_pstate_cpu_suspend, .resume = amd_pstate_cpu_resume, .set_boost = amd_pstate_set_boost, + .update_highest_perf = amd_pstate_update_highest_perf, .name = "amd-pstate", .attr = amd_pstate_attr, }; @@ -1505,6 +1550,7 @@ static struct cpufreq_driver amd_pstate_epp_driver = { .online = amd_pstate_epp_cpu_online, .suspend = amd_pstate_epp_suspend, .resume = amd_pstate_epp_resume, + .update_highest_perf = amd_pstate_update_highest_perf, .name = "amd-pstate-epp", .attr = amd_pstate_epp_attr, }; diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h index 87e140e9e6db..426822612373 100644 --- a/include/linux/amd-pstate.h +++ b/include/linux/amd-pstate.h @@ -39,11 +39,16 @@ struct amd_aperf_mperf { * @cppc_req_cached: cached performance request hints * @highest_perf: the maximum performance an individual processor may reach, * assuming ideal conditions + * For platforms that do not support the preferred core feature, the + * highest_pef may be configured with 166 or 255, to avoid max frequency + * calculated wrongly. we take the fixed value as the highest_perf. * @nominal_perf: the maximum sustained performance level of the processor, * assuming ideal operating conditions * @lowest_nonlinear_perf: the lowest performance level at which nonlinear power * savings are achieved * @lowest_perf: the absolute lowest performance level of the processor + * @prefcore_ranking: the preferred core ranking, the higher value indicates a higher + * priority. * @max_freq: the frequency that mapped to highest_perf * @min_freq: the frequency that mapped to lowest_perf * @nominal_freq: the frequency that mapped to nominal_perf @@ -73,6 +78,7 @@ struct amd_cpudata { u32 nominal_perf; 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Wysocki" , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , "Oleksandr Natalenko" , Meng Li , Wyes Karny Subject: [PATCH V10 6/7] Documentation: amd-pstate: introduce amd-pstate preferred core Date: Mon, 30 Oct 2023 14:34:02 +0800 Message-ID: <20231030063403.3502816-7-li.meng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231030063403.3502816-1-li.meng@amd.com> References: <20231030063403.3502816-1-li.meng@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB73:EE_|SA1PR12MB6680:EE_ X-MS-Office365-Filtering-Correlation-Id: 867c4433-cc14-4a81-8da1-08dbd9126ebc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: x1BrHWTNp5VXafcUwA/Ap9qFpFWgpRFG8YHT4bdFBMVMHzZqMP7+g7HqsDqGNiP9ifvM07R+3CGrQsH0YrS0clGLcymLZpel9v9yaOrKwJJXiXzdI+yChl9To7JgypsTAvgtK1IeL7JtRqoPz3GrCpDOMPt+pR3KiZaQktX8ly4Rv0iiupbH1w3BWkvBTNZbuBvb1VUAWhzRyE5lB2ezciwcCFJPN7XyO1u0RJKnCOsLOKEYfisg05vQZoSPajR2rUc4LmIMIZc4rSGiQyDCNbVg2p2FsceeqwlodXhANENVHgt8BS3k+jm5cWziTg5BVHW/1n8sWZCvIhN8V68H5NBsk9FNIlEJPwj87L83pqWe2teBTZkD7k/PaDZjuxndBL9q2+gGDxV6Qy7WklQibWzXDs1X5poh2L/b0c+emnyAEq+Cia9tiCEeCCojLTHu2GQWvA3bnPgZyKKJJ1aRVGKpPS+2fYQUHnECz0eV5W6TyoZ5gE4LmhUEm+QJp3ve3RIkGIrvArZGRxxjHqN87tEFTj+hiEa2UDgv7JjtnenJilVniEFF845NgtWySCCwUERe0WJUxPoY4oFsJzZD791PyTWVzhbpoL8kQfsrfso179H58PKCCnoU/yVZxOXtf0SlOR5rRSScpsmLv+3mH+nx2bETgzTdO0UlYNzsiAvKJ+TUu9pbEFlFLLNiI2KR5wF5WTFGnYhh+/axDl++ViWX75nIz//x8Cu3aHmzGu/4UGfB36jANjLin9i+l2TDpU11gy0LMPei3zfDS/MAZA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(346002)(136003)(376002)(39860400002)(396003)(230922051799003)(82310400011)(186009)(1800799009)(451199024)(64100799003)(40470700004)(46966006)(36840700001)(5660300002)(40460700003)(7416002)(81166007)(356005)(86362001)(47076005)(82740400003)(336012)(426003)(1076003)(16526019)(26005)(83380400001)(7696005)(36756003)(478600001)(6666004)(2616005)(36860700001)(40480700001)(2906002)(70586007)(70206006)(110136005)(41300700001)(8676002)(6636002)(316002)(54906003)(8936002)(4326008)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Oct 2023 06:35:39.3077 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 867c4433-cc14-4a81-8da1-08dbd9126ebc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB73.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB6680 X-Spam-Status: No, score=-1.2 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_SPF_HELO, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_NONE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Sun, 29 Oct 2023 23:36:19 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781161295358537713 X-GMAIL-MSGID: 1781161295358537713 Introduce amd-pstate preferred core. check preferred core state set by the kernel parameter: $ cat /sys/devices/system/cpu/amd-pstate/prefcore Tested-by: Oleksandr Natalenko Reviewed-by: Wyes Karny Reviewed-by: Mario Limonciello Reviewed-by: Huang Rui Signed-off-by: Meng Li --- Documentation/admin-guide/pm/amd-pstate.rst | 59 ++++++++++++++++++++- 1 file changed, 57 insertions(+), 2 deletions(-) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst index 1cf40f69278c..0b832ff529db 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -300,8 +300,8 @@ platforms. The AMD P-States mechanism is the more performance and energy efficiency frequency management method on AMD processors. -AMD Pstate Driver Operation Modes -================================= +``amd-pstate`` Driver Operation Modes +====================================== ``amd_pstate`` CPPC has 3 operation modes: autonomous (active) mode, non-autonomous (passive) mode and guided autonomous (guided) mode. @@ -353,6 +353,48 @@ is activated. In this mode, driver requests minimum and maximum performance level and the platform autonomously selects a performance level in this range and appropriate to the current workload. +``amd-pstate`` Preferred Core +================================= + +The core frequency is subjected to the process variation in semiconductors. +Not all cores are able to reach the maximum frequency respecting the +infrastructure limits. Consequently, AMD has redefined the concept of +maximum frequency of a part. This means that a fraction of cores can reach +maximum frequency. To find the best process scheduling policy for a given +scenario, OS needs to know the core ordering informed by the platform through +highest performance capability register of the CPPC interface. + +``amd-pstate`` preferred core enables the scheduler to prefer scheduling on +cores that can achieve a higher frequency with lower voltage. The preferred +core rankings can dynamically change based on the workload, platform conditions, +thermals and ageing. + +The priority metric will be initialized by the ``amd-pstate`` driver. The ``amd-pstate`` +driver will also determine whether or not ``amd-pstate`` preferred core is +supported by the platform. + +``amd-pstate`` driver will provide an initial core ordering when the system boots. +The platform uses the CPPC interfaces to communicate the core ranking to the +operating system and scheduler to make sure that OS is choosing the cores +with highest performance firstly for scheduling the process. When ``amd-pstate`` +driver receives a message with the highest performance change, it will +update the core ranking and set the cpu's priority. + +``amd-pstate`` Preferred Core Switch +================================= +Kernel Parameters +----------------- + +``amd-pstate`` peferred core`` has two states: enable and disable. +Enable/disable states can be chosen by different kernel parameters. +Default enable ``amd-pstate`` preferred core. + +``amd_prefcore=disable`` + +For systems that support ``amd-pstate`` preferred core, the core rankings will +always be advertised by the platform. But OS can choose to ignore that via the +kernel parameter ``amd_prefcore=disable``. + User Space Interface in ``sysfs`` - General =========================================== @@ -385,6 +427,19 @@ control its functionality at the system level. They are located in the to the operation mode represented by that string - or to be unregistered in the "disable" case. +``prefcore`` + Preferred core state of the driver: "enabled" or "disabled". + + "enabled" + Enable the ``amd-pstate`` preferred core. + + "disabled" + Disable the ``amd-pstate`` preferred core + + + This attribute is read-only to check the state of preferred core set + by the kernel parameter. + ``cpupower`` tool support for ``amd-pstate`` =============================================== From patchwork Mon Oct 30 06:34:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Meng Li X-Patchwork-Id: 159500 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp2017686vqb; Sun, 29 Oct 2023 23:36:55 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFVokB4Oida0tbAXt9HdLHE0slpmU27siNfUSOV8TII4PlyljdjZ/jD5ps3SI69n3yHgoFV X-Received: by 2002:a17:90a:740b:b0:27d:32ba:3403 with SMTP id a11-20020a17090a740b00b0027d32ba3403mr5688523pjg.22.1698647815619; Sun, 29 Oct 2023 23:36:55 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1698647815; cv=pass; d=google.com; s=arc-20160816; b=Gt69K4xHJS3XOXctJcPYtkVxb45GgzudLoCzJQHao8YNAHhIGtX3izstivnMhDNINQ 34CoX1In4gXJ+5PR/rHElZ9lhUEVgb1+l2tEY9Kn9rAe/i/0lq9XWrZzmXfuMSIJOWEc tylPwbVLDcI497PgKJsZx9oaXDGmgL7wRAGBK5ZDcUpyD/vVkKaxYiHkjcfwUuQbdKuP USsvZsrqMafMTmDTy9FKvUNtkLSx0kUlH0O5aIZfBwhJC1y5SmQQAc1YOczCOoxBmkWH ts2zNOWNriecl87w2rRlNRvIlcTC+6vfiJ3HVd8E3trAD5IIZnQZ0Aj0U1oaC3OP6h52 L46Q== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=3BATVT8xDKQmxK5ddKWQeikq5vTddHGyEfuh2meRohc=; fh=px4bRiBuq3I9SXanjlkRNLIg6oMFdG8uo3HGDz2F7II=; b=JEosZ2r9oG0wIeGh3IYdFwrdmLgsos96J4Tt/Npex0EkXnE2JPBae1o9egObvnq49o pKf7XZ5roUKGYYBK/D4ErbbwNyscsi6aIc/u9EB1fvR2XU2DfRSnEdT+qSkagbVjKqGO /rD72GMqq0uOvTtdlNPfPqbQbzJSr4ABSUfBlvtZI0yOXfHkpYEApTLNzcI8HUPklak9 zUFPfSXB5Tf60yZD1a6Oj75ZkJ+EotUJa1CuYR+hdBw2L9Od/pxxQGxppD7g74yjE1Ip /DBaTA724sVu7SfOK+WCN8nrlilc1Dtp/yX85dJqmG2O8Aa7MjxJvUDw65yRsfJQ0gcM SlnA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b="S/yCjRB3"; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from fry.vger.email (fry.vger.email. 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Wysocki" , Huang Rui CC: , , , , Shuah Khan , , "Nathan Fontenot" , Deepak Sharma , Alex Deucher , Mario Limonciello , Shimmer Huang , "Perry Yuan" , Xiaojian Du , Viresh Kumar , Borislav Petkov , "Oleksandr Natalenko" , Meng Li , Wyes Karny Subject: [PATCH V10 7/7] Documentation: introduce amd-pstate preferrd core mode kernel command line options Date: Mon, 30 Oct 2023 14:34:03 +0800 Message-ID: <20231030063403.3502816-8-li.meng@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231030063403.3502816-1-li.meng@amd.com> References: <20231030063403.3502816-1-li.meng@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB78:EE_|PH0PR12MB7790:EE_ X-MS-Office365-Filtering-Correlation-Id: d2ffeb8c-0822-4f34-eba1-08dbd912714f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: o3PXIWQaIP6cw1g/cWry3rmRTyho5edsRoQ3A+jFzuC9CEJ8FGpAmZRRsl62qJEtoZq2rWYABXEfwj2jrCVF1XTEjkfCwQp9mtRAA+LpG1kQ2AINWrgtJN/p2E1V22nKfdy7Ka5W4zlwGA1FzByjU2qbBZmpEIDnr4y9hX5R03SySipbPXsrKRHOYOln1im6s0EyvS6pC1eJ2ZJtp7+7riVpFLkF9j1+zZk4OzgW2E4ir7Kph2a0hVfGazP+UF7um9XWZ9nRywKiNE5YLba3KCECdu3hnO/4SLEX5pk/XgUc2gs3vl9rzEYlV1uwU/3Z5EzzNGwlr8+pBUV65Cvsg53oMGLIQ77tYnF3hubj2Dlo0X8oYW9QcNNdoM7TBsuduidlGAbglVdLnsyInQfGg1MPD3+AwRfAuNoqnb7HS622/9NCNP6mrIP0qoYkhScF9Nig+HMyDujgfcQaPK/XlJacEKBHTsXGEOh9dRSPNER/Mdwn4owCf1ZV1PZDoqQ9Ctj4UStkvhcDi7XzTjHL3ZKt3RniSVk9ylrgEBSknw53eYNBVWuFEgHkmG6Z7oep5Blo/Sa5pv/96jTetfH76NyBCy8/Ot/+vqLy5sJfRKJ44PHUUD/c0whQKjDfqixziReODehJF/H77/Vi1HueLF21Sx2OFnzpt/Il4Xntu8daVQEMF7Qfs1aIjPZeFHDwNE2SzvO7heSTmxtbXWaA4i/2o1oqeFAJCUeR7LZE6XAxWHsg30WSNwoszSY52V909gqVeOOj77+KY+b9OjZUYaPFv6Tz4YnhXo/VMV3Kxw/HYXOWJs+VqFU1rRq0j8nw X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230031)(4636009)(346002)(39860400002)(376002)(396003)(136003)(230922051799003)(82310400011)(451199024)(186009)(64100799003)(1800799009)(36840700001)(40470700004)(46966006)(1076003)(26005)(16526019)(2616005)(336012)(83380400001)(478600001)(6666004)(47076005)(7696005)(36860700001)(426003)(7416002)(5660300002)(2906002)(41300700001)(110136005)(70206006)(70586007)(8936002)(8676002)(6636002)(4326008)(316002)(54906003)(40460700003)(356005)(82740400003)(81166007)(36756003)(86362001)(40480700001)(36900700001)(14943795004);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Oct 2023 06:35:43.6290 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d2ffeb8c-0822-4f34-eba1-08dbd912714f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB78.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7790 X-Spam-Status: No, score=-1.3 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Sun, 29 Oct 2023 23:36:53 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1781161331703423800 X-GMAIL-MSGID: 1781161331703423800 amd-pstate driver support enable/disable preferred core. Default enabled on platforms supporting amd-pstate preferred core. Disable amd-pstate preferred core with "amd_prefcore=disable" added to the kernel command line. Signed-off-by: Meng Li Reviewed-by: Mario Limonciello Reviewed-by: Wyes Karny Reviewed-by: Huang Rui Tested-by: Oleksandr Natalenko --- Documentation/admin-guide/kernel-parameters.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 0a1731a0f0ef..e35b795aa8aa 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -363,6 +363,11 @@ selects a performance level in this range and appropriate to the current workload. + amd_prefcore= + [X86] + disable + Disable amd-pstate preferred core. + amijoy.map= [HW,JOY] Amiga joystick support Map of devices attached to JOY0DAT and JOY1DAT Format: ,