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Fri, 27 Oct 2023 18:11:12 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, tsbogend@alpha.franken.de, gregory.clement@bootlin.com, vladimir.kondratiev@intel.com, Jiaxun Yang Subject: [PATCH v2 01/10] MIPS: Export higher/highest relocation functions in uasm Date: Fri, 27 Oct 2023 23:10:57 +0100 Message-Id: <20231027221106.405666-2-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027221106.405666-1-jiaxun.yang@flygoat.com> References: <20231027221106.405666-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Fri, 27 Oct 2023 15:11:25 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780948411837708326 X-GMAIL-MSGID: 1780948411837708326 Export uasm_rel_{higher,highest} functions. Those functions can be helpful in dealing with 64bit immediates. Signed-off-by: Jiaxun Yang --- arch/mips/include/asm/uasm.h | 2 ++ arch/mips/mm/uasm.c | 6 ++++-- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h index 296bcf31abb5..12db6d2fca07 100644 --- a/arch/mips/include/asm/uasm.h +++ b/arch/mips/include/asm/uasm.h @@ -196,6 +196,8 @@ void uasm_build_label(struct uasm_label **lab, u32 *addr, #ifdef CONFIG_64BIT int uasm_in_compat_space_p(long addr); #endif +int uasm_rel_highest(long val); +int uasm_rel_higher(long val); int uasm_rel_hi(long val); int uasm_rel_lo(long val); void UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr); diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c index 125140979d62..6846bf2084c5 100644 --- a/arch/mips/mm/uasm.c +++ b/arch/mips/mm/uasm.c @@ -425,7 +425,7 @@ int uasm_in_compat_space_p(long addr) } UASM_EXPORT_SYMBOL(uasm_in_compat_space_p); -static int uasm_rel_highest(long val) +int uasm_rel_highest(long val) { #ifdef CONFIG_64BIT return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000; @@ -433,8 +433,9 @@ static int uasm_rel_highest(long val) return 0; #endif } +UASM_EXPORT_SYMBOL(uasm_rel_highest); -static int uasm_rel_higher(long val) +int uasm_rel_higher(long val) { #ifdef CONFIG_64BIT return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000; @@ -442,6 +443,7 @@ static int uasm_rel_higher(long val) return 0; #endif } +UASM_EXPORT_SYMBOL(uasm_rel_higher); int uasm_rel_hi(long val) { From patchwork Fri Oct 27 22:10:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 159178 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp913451vqb; Fri, 27 Oct 2023 15:12:40 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHR7RW79x3GHXSPdvxEIwyQSVvaAxGKNAuOJpM6WAAERlLlDeOxfeYO+SlXMGadaxIzDKcm X-Received: by 2002:a05:6a21:19b:b0:154:d3ac:2076 with SMTP id le27-20020a056a21019b00b00154d3ac2076mr4490750pzb.40.1698444759904; Fri, 27 Oct 2023 15:12:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698444759; cv=none; d=google.com; s=arc-20160816; b=YB2daifDbaLsie639ZPeK5NC8og8TsZPMDQfw2XQlpbKSckE2bHiSCYa3mbCOhr5PK w83dK3Wt9JcLgV65Exr8RwLh/1fNlHCvDuuUL4I1tWbehjbEsvrQIsrmMfGjHRuCNjkM rPCJfJ4Ijzi8vJkCZoPS1SPx+b6Se0sl73M6Wzu4jI/uQAG1jQrAEfk1gIcAJtzZn0kI NqHSsF+wmHG2Twr+G9pz139AHzrYdTEOtPmW5b8yAO5Lya684+hXSEvVJUghXRfu6sFn TNf8ogQzuAEjcKXauBk+a/O6cWKQU4BHvLao649fT0r05dTfYTaNgMSbTu/G7IOF8E+O xp2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :feedback-id:dkim-signature:dkim-signature; bh=1fai2oRGpMFX3YIWYq1Mi7aFvcDk/EldREaoCLVKnm8=; fh=34VXqKbbbRVUWYKB0XlF9D4jmhXxe51P2+smd1zcTfU=; b=uZsE/WhhvpcbK9qSRaLGJbgVIct6hJMK3QXCGAnaCM+DZ/FAxAg1b93B9MoTrOq8Yt S5Fc+rBV93bdQvQmv56KNq7ZCJ0a+Zjt2+Ol48QSDDKtZ+VU4MZcuF7gVLI8WwINz9/S Pg/OnunHnPoXREFJ9Yl3iosl7s5eMg9EwrAe03VDxYKHLzE4pMD4yKevJMf/06TXFdUF UdtzBfowjU6EOaVVC7wTixh/xu5omQ4/LkBTCjauKkW8DKokiCzMCui3uPNWdat8ZfGg HBHduSCnqbH7tM3mSvPLjwNilYmQWSTT3UpHyyRCnK1cAoXfs0hNFWx7Z5GpsDNZbnwY FmmA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@flygoat.com header.s=fm1 header.b=uG36gus0; dkim=pass header.i=@messagingengine.com header.s=fm3 header.b=DHgNU1kp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=flygoat.com Received: from snail.vger.email (snail.vger.email. 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Fri, 27 Oct 2023 18:11:14 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, tsbogend@alpha.franken.de, gregory.clement@bootlin.com, vladimir.kondratiev@intel.com, Jiaxun Yang Subject: [PATCH v2 02/10] MIPS: spaces: Define a couple of handy macros Date: Fri, 27 Oct 2023 23:10:58 +0100 Message-Id: <20231027221106.405666-3-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027221106.405666-1-jiaxun.yang@flygoat.com> References: <20231027221106.405666-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL,SPF_HELO_PASS,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Fri, 27 Oct 2023 15:11:34 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780948412401215423 X-GMAIL-MSGID: 1780948412401215423 KSEGX_SIZE is defined to size of each KSEG segment. TO_CAC and TO_UNCAC are brought to 32bit builds as well, TO_PHYS remains to be 64bit only as we want people to use __pa to avoid mixup compat address space. Signed-off-by: Jiaxun Yang --- arch/mips/include/asm/addrspace.h | 5 +++++ arch/mips/include/asm/mach-generic/spaces.h | 5 +++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h index 59a48c60a065..03a5e2c8b5dc 100644 --- a/arch/mips/include/asm/addrspace.h +++ b/arch/mips/include/asm/addrspace.h @@ -47,6 +47,11 @@ */ #define KSEGX(a) ((_ACAST32_(a)) & _ACAST32_(0xe0000000)) +/* + * Gives the size of each kernel segment + */ +#define KSEGX_SIZE 0x20000000 + /* * Returns the physical address of a CKSEGx / XKPHYS address */ diff --git a/arch/mips/include/asm/mach-generic/spaces.h b/arch/mips/include/asm/mach-generic/spaces.h index b247575c5e69..05db19521e81 100644 --- a/arch/mips/include/asm/mach-generic/spaces.h +++ b/arch/mips/include/asm/mach-generic/spaces.h @@ -79,11 +79,12 @@ #endif #define TO_PHYS(x) ( ((x) & TO_PHYS_MASK)) -#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) -#define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) #endif /* CONFIG_64BIT */ +#define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) +#define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) + /* * This handles the memory map. */ From patchwork Fri Oct 27 22:10:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 159171 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp913214vqb; Fri, 27 Oct 2023 15:12:11 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE8gUUIM0AzLprdgmml4t1UuEutDqvZCF7yM5urHoDc11pT230lyj2d+vKY2m3t/UhhNodD X-Received: by 2002:a81:b207:0:b0:594:e97b:f6fa with SMTP id q7-20020a81b207000000b00594e97bf6famr4263031ywh.30.1698444731025; Fri, 27 Oct 2023 15:12:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698444731; cv=none; d=google.com; s=arc-20160816; b=yTyNleBj/hZoO3h8pNsiGTdaxFZwtIltXABpvTyGHss/npYjWaGyKJ0wuLWMruvniM oKKIXyIP/ToYQqaYRz+xRhBcwxSjMIND7uI9sQodPP51+93KDfwACOrGHRhQUcpCBurt /PCvciM4R0NSMmcXLIpeZv6HmGu9xVWvutpj4mAZaqBBDqcweTlxXV3KWESZumMJKtfu 9TSQYFPR2MwHasUyU3rrxKrl90y+8h3BzXhs1rjh2xdQxXUbjnSEXRM/SZR/fzpwcL5C +HSQ/c5IMHM7aABjXN+2O00R6obhZso98EvsyS7vUyMe2eno88TRx9XwKUxIQ1fYWrsf 7AYA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :feedback-id:dkim-signature:dkim-signature; bh=JcLDvuqq+aysWCP3Ln7wvhxjBzjiN4xGl+qlurq8eWo=; fh=34VXqKbbbRVUWYKB0XlF9D4jmhXxe51P2+smd1zcTfU=; b=i6Dmkg5T5+bHI9Sqsskhi/azXS+fzwPajetrQLLOFmmGo+7tfVWvrFEThvhKEC+GTd 00yylGW8cUfVpB4CiHGoZVDUOLgjHCZ13UkxOifXercqFr0BkOaCfGcjJ5D0LcuQraZW jXLEyXZ67tEBlNnW/XfIY9yM1+MDAtdO2gIUVihAAJAxjQ3gP7aq5JMnAZqm0fCPy9Bu bhBdJkbUS7J7tX4BhDBqrY6TZlrrwa1ZQuzzbobXaSUXPoZueZx3QVGyZRNXCdIK5pg+ xTKngxaKSj9+1Jr2ezZqXhsUuGLNrGIG8h2vlkbFiSoV2sSfG2bihxN+kaACX/iEOTlB 4UtQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@flygoat.com header.s=fm1 header.b=IHoYk5b3; dkim=pass header.i=@messagingengine.com header.s=fm3 header.b=n929qJ+d; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=flygoat.com Received: from pete.vger.email (pete.vger.email. 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Fri, 27 Oct 2023 18:11:17 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, tsbogend@alpha.franken.de, gregory.clement@bootlin.com, vladimir.kondratiev@intel.com, Jiaxun Yang Subject: [PATCH v2 03/10] MIPS: genex: Fix except_vec_vi for kernel in XKPHYS Date: Fri, 27 Oct 2023 23:10:59 +0100 Message-Id: <20231027221106.405666-4-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027221106.405666-1-jiaxun.yang@flygoat.com> References: <20231027221106.405666-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Fri, 27 Oct 2023 15:11:58 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780948382601066636 X-GMAIL-MSGID: 1780948382601066636 Use {highest, higher, hi, lo} immediate loading sequence to load 64 bit jump address for handler when kernel is loaded to XKPHYS. Co-developed-by: Vladimir Kondratiev Signed-off-by: Vladimir Kondratiev Co-developed-by: Gregory CLEMENT Signed-off-by: Gregory CLEMENT Signed-off-by: Jiaxun Yang --- arch/mips/kernel/genex.S | 19 +++++++++++++++---- arch/mips/kernel/traps.c | 34 ++++++++++++++++++++++++---------- 2 files changed, 39 insertions(+), 14 deletions(-) diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index b6de8e88c1bd..fd765ad9ecac 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -272,11 +272,22 @@ NESTED(except_vec_vi, 0, sp) .set push .set noreorder PTR_LA v1, except_vec_vi_handler -FEXPORT(except_vec_vi_lui) - lui v0, 0 /* Patched */ +#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) +FEXPORT(except_vec_vi_hi) + lui v0, 0 /* Patched */ +#else +FEXPORT(except_vec_vi_highest) + lui v0, 0 /* Patched */ +FEXPORT(except_vec_vi_higher) + daddiu v0, 0 /* Patched */ + dsll v0, 16 +FEXPORT(except_vec_vi_hi) + daddiu v0, 0 /* Patched */ + dsll v0, 16 +#endif jr v1 -FEXPORT(except_vec_vi_ori) - ori v0, 0 /* Patched */ +FEXPORT(except_vec_vi_lo) + PTR_ADDIU v0, 0 /* Patched */ .set pop END(except_vec_vi) EXPORT(except_vec_vi_end) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 246c6a6b0261..60c513c51684 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -2091,18 +2091,26 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) * If no shadow set is selected then use the default handler * that does normal register saving and standard interrupt exit */ - extern const u8 except_vec_vi[], except_vec_vi_lui[]; - extern const u8 except_vec_vi_ori[], except_vec_vi_end[]; + extern const u8 except_vec_vi[], except_vec_vi_hi[]; + extern const u8 except_vec_vi_lo[], except_vec_vi_end[]; +#if defined(CONFIG_64BIT) && !defined(KBUILD_64BIT_SYM32) + extern const u8 except_vec_vi_highest[], except_vec_vi_higher[]; +#endif extern const u8 rollback_except_vec_vi[]; const u8 *vec_start = using_rollback_handler() ? rollback_except_vec_vi : except_vec_vi; #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN) - const int lui_offset = except_vec_vi_lui - vec_start + 2; - const int ori_offset = except_vec_vi_ori - vec_start + 2; + const int imm_offset = 2; #else - const int lui_offset = except_vec_vi_lui - vec_start; - const int ori_offset = except_vec_vi_ori - vec_start; + const int imm_offset = 0; +#endif +#if defined(CONFIG_64BIT) && !defined(KBUILD_64BIT_SYM32) + const int highest_offset = except_vec_vi_highest - vec_start + imm_offset; + const int higher_offset = except_vec_vi_higher - vec_start + imm_offset; #endif + const int hi_offset = except_vec_vi_hi - vec_start + imm_offset; + const int lo_offset = except_vec_vi_lo - vec_start + imm_offset; + const int handler_len = except_vec_vi_end - vec_start; if (handler_len > VECTORSPACING) { @@ -2119,10 +2127,16 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) #else handler_len); #endif - h = (u16 *)(b + lui_offset); - *h = (handler >> 16) & 0xffff; - h = (u16 *)(b + ori_offset); - *h = (handler & 0xffff); +#if defined(CONFIG_64BIT) && !defined(KBUILD_64BIT_SYM32) + h = (u16 *)(b + highest_offset); + *h = uasm_rel_highest(handler); + h = (u16 *)(b + higher_offset); + *h = uasm_rel_higher(handler); +#endif + h = (u16 *)(b + hi_offset); + *h = uasm_rel_hi(handler); + h = (u16 *)(b + lo_offset); + *h = uasm_rel_lo(handler); local_flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len)); } From patchwork Fri Oct 27 22:11:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 159172 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp913237vqb; Fri, 27 Oct 2023 15:12:13 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFMimKV1SKOKNuTrFcs2Svs3VtIacOFO5UPbrs+iwUI5hIkLJPwLYrB3A01jVCL5/riGk2F X-Received: by 2002:a17:90b:790:b0:27d:4ab9:fcd9 with SMTP id l16-20020a17090b079000b0027d4ab9fcd9mr3658593pjz.21.1698444733249; Fri, 27 Oct 2023 15:12:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698444733; cv=none; d=google.com; s=arc-20160816; b=cuGVDnDd8/vUDzZvz+tlbnLcjagnJx1wemb6ttIPIVR02VdEUEByhT5/R5BDvoOCYi tZObQg4Q6+DL8Yg+fKyYjp1iHrRaTRI2ggbF3QLM9T/9eb0kU1W6vQx3RUpaX1/e75tI v7yejlfvSMQSAu2xvY5qKuQZaaowlw7WvemMlTrmN/KU4ptRWKG9x86NlT8Q0/xvh7r4 Hz5KYMPM2Q0fIozQ3O47nvN1z4JqT7caYZMr3wpHHCtxQ2eQP74r2PSdNoa1SCCU8TrK hiolIhqaK5lNbVbQLjFb8WmQXmt6oDPiAxiMTCCHX5lqjBboP9w2+58DYQNRDKw5W7+g zKow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :feedback-id:dkim-signature:dkim-signature; bh=z1/hT0gfhZcXEOcRfnRggstjECOl2aSsJ7lZKpBlqTw=; fh=34VXqKbbbRVUWYKB0XlF9D4jmhXxe51P2+smd1zcTfU=; b=exYc6TD+m1RLCkdG5c/v22fBO0jQ36QfVbAQyDxIWggSxG3jAKtkUR9ugQiBr0mPlJ jJU7Hi9NuKJyj3wQQ1/GIWNY1/s+AOpzEW1aA4QVQFWBGNw6suFnNPcYV2mj7G+Cottn pghFgNi7P3rxTgYTwnlrEV3ru3avnUo9MteOxosP0Xlr+HVs5HVSaqL+lNGSJ5ZAI384 VNTB+0K6IcCZI+bbLF5a6yRmyJv2BB2NUOZFhyED7xQj4nWDR1sGRXIjOr2EFNk65crq IpuEdVZ/o0IuqoDzZ/yMn1oAhy0r0yDpucbQVjE/CK2+2Puk/tBa39GniJKjZix1UWUB ArrQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@flygoat.com header.s=fm1 header.b=ie76scIs; dkim=pass header.i=@messagingengine.com header.s=fm3 header.b=mUpktjBn; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=flygoat.com Received: from howler.vger.email (howler.vger.email. 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Fri, 27 Oct 2023 18:11:19 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, tsbogend@alpha.franken.de, gregory.clement@bootlin.com, vladimir.kondratiev@intel.com, Jiaxun Yang Subject: [PATCH v2 04/10] MIPS: Fix set_uncached_handler for ebase in XKPHYS Date: Fri, 27 Oct 2023 23:11:00 +0100 Message-Id: <20231027221106.405666-5-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027221106.405666-1-jiaxun.yang@flygoat.com> References: <20231027221106.405666-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on howler.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Fri, 27 Oct 2023 15:12:07 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780948384688499620 X-GMAIL-MSGID: 1780948384688499620 ebase may be in XKPHYS if memblock unable to allocate memory within KSEG0 physical range. To map ebase into uncached space we just convert it back to physical address and then use platform's TO_UNCAC helper to create mapping. Co-developed-by: Vladimir Kondratiev Signed-off-by: Vladimir Kondratiev Co-developed-by: Gregory CLEMENT Signed-off-by: Gregory CLEMENT Signed-off-by: Jiaxun Yang --- arch/mips/kernel/traps.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 60c513c51684..230728d76d11 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -2346,7 +2346,7 @@ static const char panic_null_cerr[] = void set_uncached_handler(unsigned long offset, void *addr, unsigned long size) { - unsigned long uncached_ebase = CKSEG1ADDR(ebase); + unsigned long uncached_ebase = TO_UNCAC(__pa(ebase)); if (!addr) panic(panic_null_cerr); From patchwork Fri Oct 27 22:11:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 159179 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp913537vqb; Fri, 27 Oct 2023 15:12:54 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGXakqku7McfRN5iETvvSF7IjZ/jxEQLOvf1wWuqZjf1CZXDvhXLGHEcpw84nxgGD4lFXfc X-Received: by 2002:a81:ef0c:0:b0:589:8b55:f7f7 with SMTP id o12-20020a81ef0c000000b005898b55f7f7mr3878279ywm.39.1698444774184; Fri, 27 Oct 2023 15:12:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698444774; cv=none; d=google.com; s=arc-20160816; b=THVGqd0817M6D6PPfN+SJCEw0I9CcoFa04vHIDJ1HbIeJeb8K4l/YzAzW2ofXyOcNo f5E/kcznuJhD0HIfGQ9WO7i4xGxSSmTbT3d/ARMtXgqut6ocwOJnCvL8PKoHYXnu3ImH Kn+6xLDE/IuB9JdA1yhND3PQVGcdsKLfJwdl5V9QUlxr94H+v6q6czrlpsF1phOdmpM5 Ub4VAW+WJlapb1eKFYR4qbldhERxqS7sd04qO+THwes3pAOU10hrmmQkricI9drrVpql bcqleinwO3ruF+vaDvuOwrv/7IcPYh4StaxoF2BFHlp+3CS1NeuZetWywqO4wPpxO6WU zYOg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :feedback-id:dkim-signature:dkim-signature; bh=B/eSduiT5SSuDZgp+rtGBx4PnZ8+7CU6vuXEb/G0fc4=; fh=34VXqKbbbRVUWYKB0XlF9D4jmhXxe51P2+smd1zcTfU=; b=tAwUlo4HseaR000kUw9sCojs5hvufS3rzhRCvfcukP9LXenxvc9xlve6Xdndlg26vU DNQ/a47KqfgJ2S0Az+VGi+e4IJA5Wlgu7zUC7gPGxHSeWDyh/43txPreCnLOsjkwRAaz ZvXLaE3hLFPgiS+oP7WdOuYuvxN6iqiuQyg7dVxq8KucVZHv8XhLm1shOyl+O7FgvfI6 rCYa+tY3fwefHhtTj7xXUb+BhWdmMvfkqJFWZUeSNwP7OXl9cjwgUdX0S22KCzySEkSm /vgWDwgj+x6MCgRXcFkcWbqobnz2jPSY2rNYsc2RB2DMNtZmhZfMbbobgZT67U3auoj2 lUjw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@flygoat.com header.s=fm1 header.b=mN9rnu7T; dkim=pass header.i=@messagingengine.com header.s=fm3 header.b=TMpResMz; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=flygoat.com Received: from fry.vger.email (fry.vger.email. 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Fri, 27 Oct 2023 18:11:22 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, tsbogend@alpha.franken.de, gregory.clement@bootlin.com, vladimir.kondratiev@intel.com, Jiaxun Yang Subject: [PATCH v2 05/10] MIPS: Refactor mips_cps_core_entry implementation Date: Fri, 27 Oct 2023 23:11:01 +0100 Message-Id: <20231027221106.405666-6-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027221106.405666-1-jiaxun.yang@flygoat.com> References: <20231027221106.405666-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Fri, 27 Oct 2023 15:12:50 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780948427468366930 X-GMAIL-MSGID: 1780948427468366930 Now the exception vector for CPS systems are allocated on-fly with memblock as well. It will try to allocate from KSEG1 first, and then try to allocate in low 4G if possible. The main reset vector is now generated by uasm, to avoid tons of patches to the code. Other vectors are copied to the location later. Signed-off-by: Jiaxun Yang --- arch/mips/include/asm/mips-cm.h | 1 + arch/mips/include/asm/smp-cps.h | 4 +- arch/mips/kernel/cps-vec.S | 110 ++++++++------------- arch/mips/kernel/smp-cps.c | 167 +++++++++++++++++++++++++++----- arch/mips/kernel/traps.c | 2 + 5 files changed, 186 insertions(+), 98 deletions(-) diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h index 23c67c0871b1..15d8d69de455 100644 --- a/arch/mips/include/asm/mips-cm.h +++ b/arch/mips/include/asm/mips-cm.h @@ -311,6 +311,7 @@ GCR_CX_ACCESSOR_RW(32, 0x018, other) /* GCR_Cx_RESET_BASE - Configure where powered up cores will fetch from */ GCR_CX_ACCESSOR_RW(32, 0x020, reset_base) #define CM_GCR_Cx_RESET_BASE_BEVEXCBASE GENMASK(31, 12) +#define CM_GCR_Cx_RESET_BASE_MODE BIT(1) /* GCR_Cx_ID - Identify the current core */ GCR_CX_ACCESSOR_RO(32, 0x028, id) diff --git a/arch/mips/include/asm/smp-cps.h b/arch/mips/include/asm/smp-cps.h index 22a572b70fe3..39a602e5fecc 100644 --- a/arch/mips/include/asm/smp-cps.h +++ b/arch/mips/include/asm/smp-cps.h @@ -24,7 +24,7 @@ struct core_boot_config { extern struct core_boot_config *mips_cps_core_bootcfg; -extern void mips_cps_core_entry(void); +extern void mips_cps_core_boot(int cca, void __iomem *gcr_base); extern void mips_cps_core_init(void); extern void mips_cps_boot_vpes(struct core_boot_config *cfg, unsigned vpe); @@ -32,8 +32,6 @@ extern void mips_cps_boot_vpes(struct core_boot_config *cfg, unsigned vpe); extern void mips_cps_pm_save(void); extern void mips_cps_pm_restore(void); -extern void *mips_cps_core_entry_patch_end; - #ifdef CONFIG_MIPS_CPS extern bool mips_cps_smp_in_use(void); diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S index 64ecfdac6580..8870a2dbc35a 100644 --- a/arch/mips/kernel/cps-vec.S +++ b/arch/mips/kernel/cps-vec.S @@ -4,6 +4,8 @@ * Author: Paul Burton */ +#include + #include #include #include @@ -81,40 +83,48 @@ nop .endm + __INIT +LEAF(excep_tlbfill) + DUMP_EXCEP("TLB Fill") + b . + nop + END(excep_tlbfill) -.balign 0x1000 +LEAF(excep_xtlbfill) + DUMP_EXCEP("XTLB Fill") + b . + nop + END(excep_xtlbfill) -LEAF(mips_cps_core_entry) - /* - * These first several instructions will be patched by cps_smp_setup to load the - * CCA to use into register s0 and GCR base address to register s1. - */ - .rept CPS_ENTRY_PATCH_INSNS - nop - .endr +LEAF(excep_cache) + DUMP_EXCEP("Cache") + b . + nop + END(excep_cache) - .global mips_cps_core_entry_patch_end -mips_cps_core_entry_patch_end: +LEAF(excep_genex) + DUMP_EXCEP("General") + b . + nop + END(excep_genex) - /* Check whether we're here due to an NMI */ - mfc0 k0, CP0_STATUS - and k0, k0, ST0_NMI - beqz k0, not_nmi +LEAF(excep_intex) + DUMP_EXCEP("Interrupt") + b . nop + END(excep_intex) - /* This is an NMI */ - PTR_LA k0, nmi_handler +LEAF(excep_ejtag) + PTR_LA k0, ejtag_debug_handler jr k0 nop + END(excep_ejtag) + __FINIT -not_nmi: - /* Setup Cause */ - li t0, CAUSEF_IV - mtc0 t0, CP0_CAUSE - - /* Setup Status */ - li t0, ST0_CU1 | ST0_CU0 | ST0_BEV | STATUS_BITDEPS - mtc0 t0, CP0_STATUS +LEAF(mips_cps_core_boot) + /* Save CCA and GCR base */ + move s0, a0 + move s1, a1 /* We don't know how to do coherence setup on earlier ISA */ #if MIPS_ISA_REV > 0 @@ -178,49 +188,7 @@ not_nmi: PTR_L sp, VPEBOOTCFG_SP(v1) jr t1 nop - END(mips_cps_core_entry) - -.org 0x200 -LEAF(excep_tlbfill) - DUMP_EXCEP("TLB Fill") - b . - nop - END(excep_tlbfill) - -.org 0x280 -LEAF(excep_xtlbfill) - DUMP_EXCEP("XTLB Fill") - b . - nop - END(excep_xtlbfill) - -.org 0x300 -LEAF(excep_cache) - DUMP_EXCEP("Cache") - b . - nop - END(excep_cache) - -.org 0x380 -LEAF(excep_genex) - DUMP_EXCEP("General") - b . - nop - END(excep_genex) - -.org 0x400 -LEAF(excep_intex) - DUMP_EXCEP("Interrupt") - b . - nop - END(excep_intex) - -.org 0x480 -LEAF(excep_ejtag) - PTR_LA k0, ejtag_debug_handler - jr k0 - nop - END(excep_ejtag) + END(mips_cps_core_boot) LEAF(mips_cps_core_init) #ifdef CONFIG_MIPS_MT_SMP @@ -428,7 +396,7 @@ LEAF(mips_cps_boot_vpes) /* Calculate a pointer to the VPEs struct vpe_boot_config */ li t0, VPEBOOTCFG_SIZE mul t0, t0, ta1 - addu t0, t0, ta3 + PTR_ADDU t0, t0, ta3 /* Set the TC restart PC */ lw t1, VPEBOOTCFG_PC(t0) @@ -603,10 +571,10 @@ dcache_done: lw $1, TI_CPU(gp) sll $1, $1, LONGLOG PTR_LA \dest, __per_cpu_offset - addu $1, $1, \dest + PTR_ADDU $1, $1, \dest lw $1, 0($1) PTR_LA \dest, cps_cpu_state - addu \dest, \dest, $1 + PTR_ADDU \dest, \dest, $1 .set pop .endm diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index dd55d59b88db..9aad678a32bd 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -25,7 +26,33 @@ #include #include +#define BEV_VEC_SIZE 0x500 +#define BEV_VEC_ALIGN 0x1000 + +#define A0 4 +#define A1 5 +#define T9 25 +#define K0 26 +#define K1 27 + +#define C0_STATUS 12, 0 +#define C0_CAUSE 13, 0 + +#define ST0_NMI_BIT 19 +#ifdef CONFIG_64BIT +#define ST0_KX_IF_64 ST0_KX +#else +#define ST0_KX_IF_64 0 +#endif + +enum label_id { + label_not_nmi = 1, +}; + +UASM_L_LA(_not_nmi) + static DECLARE_BITMAP(core_power, NR_CPUS); +static uint32_t core_entry_reg; struct core_boot_config *mips_cps_core_bootcfg; @@ -34,10 +61,113 @@ static unsigned __init core_vpe_count(unsigned int cluster, unsigned core) return min(smp_max_threads, mips_cps_numvps(cluster, core)); } +static void __init *mips_cps_build_core_entry(void *addr) +{ + extern void (*nmi_handler)(void); + u32 *p = addr; + u32 val; + struct uasm_label labels[2]; + struct uasm_reloc relocs[2]; + struct uasm_label *l = labels; + struct uasm_reloc *r = relocs; + + memset(labels, 0, sizeof(labels)); + memset(relocs, 0, sizeof(relocs)); + + uasm_i_mfc0(&p, K0, C0_STATUS); + if (cpu_has_mips_r2_r6) + uasm_i_ext(&p, K0, K0, ST0_NMI_BIT, 1); + else { + uasm_i_srl(&p, K0, K0, ST0_NMI_BIT); + uasm_i_andi(&p, K0, K0, 0x1); + } + + uasm_il_bnez(&p, &r, K0, label_not_nmi); + uasm_i_nop(&p); + UASM_i_LA(&p, K0, (long)&nmi_handler); + + uasm_l_not_nmi(&l, p); + + val = CAUSEF_IV; + uasm_i_lui(&p, K0, val >> 16); + uasm_i_ori(&p, K0, K0, val & 0xffff); + uasm_i_mtc0(&p, K0, C0_CAUSE); + val = ST0_CU1 | ST0_CU0 | ST0_BEV | ST0_KX_IF_64; + uasm_i_lui(&p, K0, val >> 16); + uasm_i_ori(&p, K0, K0, val & 0xffff); + uasm_i_mtc0(&p, K0, C0_STATUS); + uasm_i_ehb(&p); + uasm_i_ori(&p, A0, 0, read_c0_config() & CONF_CM_CMASK); + UASM_i_LA(&p, A1, (long)mips_gcr_base); +#if defined(KBUILD_64BIT_SYM32) || defined(CONFIG_32BIT) + UASM_i_LA(&p, T9, CKSEG1ADDR(__pa_symbol(mips_cps_core_boot))); +#else + UASM_i_LA(&p, T9, TO_UNCAC(__pa_symbol(mips_cps_core_boot))); +#endif + uasm_i_jr(&p, T9); + uasm_i_nop(&p); + + uasm_resolve_relocs(relocs, labels); + + return p; +} + +static int __init setup_cps_vecs(void) +{ + extern void excep_tlbfill(void); + extern void excep_xtlbfill(void); + extern void excep_cache(void); + extern void excep_genex(void); + extern void excep_intex(void); + extern void excep_ejtag(void); + phys_addr_t cps_vec_pa; + void *cps_vec; + + /* Try to allocate in KSEG1 first */ + cps_vec_pa = memblock_phys_alloc_range(BEV_VEC_SIZE, BEV_VEC_ALIGN, + 0x0, KSEGX_SIZE - 1); + + if (cps_vec_pa) + core_entry_reg = CKSEG1ADDR(cps_vec_pa) & + CM_GCR_Cx_RESET_BASE_BEVEXCBASE; + + if (!cps_vec_pa && mips_cm_is64) { + cps_vec_pa = memblock_phys_alloc_range(BEV_VEC_SIZE, BEV_VEC_ALIGN, + 0x0, SZ_4G - 1); + if (cps_vec_pa) + core_entry_reg = (cps_vec_pa & CM_GCR_Cx_RESET_BASE_BEVEXCBASE) | + CM_GCR_Cx_RESET_BASE_MODE; + } + + if (!cps_vec_pa) + return -ENOMEM; + + /* We want to ensure cache is clean before writing uncached mem */ + blast_dcache_range(TO_CAC(cps_vec_pa), TO_CAC(cps_vec_pa) + BEV_VEC_SIZE); + bc_wback_inv(TO_CAC(cps_vec_pa), BEV_VEC_SIZE); + __sync(); + + cps_vec = (void *)TO_UNCAC(cps_vec_pa); + mips_cps_build_core_entry(cps_vec); + + memcpy(cps_vec + 0x200, &excep_tlbfill, 0x80); + memcpy(cps_vec + 0x280, &excep_xtlbfill, 0x80); + memcpy(cps_vec + 0x300, &excep_cache, 0x80); + memcpy(cps_vec + 0x380, &excep_genex, 0x80); + memcpy(cps_vec + 0x400, &excep_intex, 0x80); + memcpy(cps_vec + 0x480, &excep_ejtag, 0x80); + + /* Make sure no prefetched data in cache */ + blast_inv_dcache_range(TO_CAC(cps_vec_pa), TO_CAC(cps_vec_pa) + BEV_VEC_SIZE); + bc_inv(TO_CAC(cps_vec_pa), BEV_VEC_SIZE); + __sync(); + + return 0; +} + static void __init cps_smp_setup(void) { unsigned int nclusters, ncores, nvpes, core_vpes; - unsigned long core_entry; int cl, c, v; /* Detect & record VPE topology */ @@ -94,10 +224,11 @@ static void __init cps_smp_setup(void) /* Make core 0 coherent with everything */ write_gcr_cl_coherence(0xff); - if (mips_cm_revision() >= CM_REV_CM3) { - core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry); - write_gcr_bev_base(core_entry); - } + if (setup_cps_vecs()) + pr_err("Failed to setup CPS vectors\n"); + + if (core_entry_reg && mips_cm_revision() >= CM_REV_CM3) + write_gcr_bev_base(core_entry_reg); #ifdef CONFIG_MIPS_MT_FPAFF /* If we have an FPU, enroll ourselves in the FPU-full mask */ @@ -110,10 +241,14 @@ static void __init cps_prepare_cpus(unsigned int max_cpus) { unsigned ncores, core_vpes, c, cca; bool cca_unsuitable, cores_limited; - u32 *entry_code; mips_mt_set_cpuoptions(); + if (!core_entry_reg) { + pr_err("core_entry address unsuitable, disabling smp-cps\n"); + goto err_out; + } + /* Detect whether the CCA is unsuited to multi-core SMP */ cca = read_c0_config() & CONF_CM_CMASK; switch (cca) { @@ -145,20 +280,6 @@ static void __init cps_prepare_cpus(unsigned int max_cpus) (cca_unsuitable && cpu_has_dc_aliases) ? " & " : "", cpu_has_dc_aliases ? "dcache aliasing" : ""); - /* - * Patch the start of mips_cps_core_entry to provide: - * - * s0 = kseg0 CCA - */ - entry_code = (u32 *)&mips_cps_core_entry; - uasm_i_addiu(&entry_code, 16, 0, cca); - UASM_i_LA(&entry_code, 17, (long)mips_gcr_base); - BUG_ON((void *)entry_code > (void *)&mips_cps_core_entry_patch_end); - blast_dcache_range((unsigned long)&mips_cps_core_entry, - (unsigned long)entry_code); - bc_wback_inv((unsigned long)&mips_cps_core_entry, - (void *)entry_code - (void *)&mips_cps_core_entry); - __sync(); /* Allocate core boot configuration structs */ ncores = mips_cps_numcores(0); @@ -213,7 +334,7 @@ static void boot_core(unsigned int core, unsigned int vpe_id) mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL); /* Set its reset vector */ - write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry)); + write_gcr_co_reset_base(core_entry_reg); /* Ensure its coherency is disabled */ write_gcr_co_coherence(0); @@ -290,7 +411,6 @@ static int cps_boot_secondary(int cpu, struct task_struct *idle) unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]); struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core]; struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id]; - unsigned long core_entry; unsigned int remote; int err; @@ -314,8 +434,7 @@ static int cps_boot_secondary(int cpu, struct task_struct *idle) if (cpu_has_vp) { mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL); - core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry); - write_gcr_co_reset_base(core_entry); + write_gcr_co_reset_base(core_entry_reg); mips_cm_unlock_other(); } diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 230728d76d11..ea59d321f713 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -74,6 +74,8 @@ #include "access-helper.h" +#define MAX(a, b) ((a) >= (b) ? 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Fri, 27 Oct 2023 18:11:24 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, tsbogend@alpha.franken.de, gregory.clement@bootlin.com, vladimir.kondratiev@intel.com, Jiaxun Yang Subject: [PATCH v2 06/10] MIPS: Allow kernel base to be set from Kconfig for all platforms Date: Fri, 27 Oct 2023 23:11:02 +0100 Message-Id: <20231027221106.405666-7-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027221106.405666-1-jiaxun.yang@flygoat.com> References: <20231027221106.405666-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Fri, 27 Oct 2023 15:12:18 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780948398451222553 X-GMAIL-MSGID: 1780948398451222553 There are some platforms in wild that generic loading address won't work with them due to memory layout. Allow PHYSICAL_START to be override from Kconfig, introduce PHYSICAL_START_BOOL symbol as powerpc did. Signed-off-by: Jiaxun Yang --- arch/mips/Kconfig | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index bc8421859006..bfedc8b48a81 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2884,12 +2884,22 @@ config ARCH_SUPPORTS_KEXEC config ARCH_SUPPORTS_CRASH_DUMP def_bool y +config PHYSICAL_START_BOOL + bool "Set physical address where the kernel is loaded" + default y if CRASH_DUMP + help + This gives the CKSEG0, KSEG0 or XKPHYS address where the kernel + is loaded. + + Say N here unless you know what you are doing. + config PHYSICAL_START - hex "Physical address where the kernel is loaded" - default "0xffffffff84000000" - depends on CRASH_DUMP + hex "Physical address where the kernel is loaded" if PHYSICAL_START_BOOL + default "0xffffffff84000000" if CRASH_DUMP + default "0xffffffff80100000" help - This gives the CKSEG0 or KSEG0 address where the kernel is loaded. + This gives the CKSEG0, KSEG0 or XKPHYS address where the kernel + is loaded. If you plan to use kernel for capturing the crash dump change this value to start of the reserved region (the "X" value as specified in the "crashkernel=YM@XM" command line boot parameter From patchwork Fri Oct 27 22:11:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 159170 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp913196vqb; Fri, 27 Oct 2023 15:12:09 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEuh7z8moBt59ehfVMLT8sc/eTlYLuXDtQyr/uHSGpVI6qUVLrFU3s51iXMXkezVuc9AfLG X-Received: by 2002:a25:ade8:0:b0:d9a:3bbb:8602 with SMTP id d40-20020a25ade8000000b00d9a3bbb8602mr3633883ybe.64.1698444729261; Fri, 27 Oct 2023 15:12:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698444729; cv=none; d=google.com; s=arc-20160816; b=DcL5JFBpCPLtdiYNz4Qo1sxofBIpPo4OChKHVMz6JLebUiAUQ9bUovhgphE+e0BQoI FtbJetV1ZdJh6NSxbt4DR0pheMCljA6odi+kPqc0ym3Iv3qjDeXwCSnb0J1dP19YGJ2e bJVfYJnW13vGyb2D7RJCjh4nzSsDEuyA+lu4JaYDL4tWKItpO5Wgo46P8jQdbhAXGNSv 9CXAqhwLn8DmqMWuSNCrvKWQLgiPTn+91fmkHJ/QfEvvfQICLqDS3+oEcflv0dq+Qqmg Brsb+xvt+XV0V3Vob2QbPDVevLAfOqofYtYpZEP4k8IUeuzRwssfMRGP1sY1ub6NqVPI ABpQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :feedback-id:dkim-signature:dkim-signature; bh=GQtOu2SP23PEZmWtQVCsoCbcovZ67XlhJHkFJBQ+htw=; fh=34VXqKbbbRVUWYKB0XlF9D4jmhXxe51P2+smd1zcTfU=; b=rDZkYDVmUI13QW0LKFRRGnd10MXtjZxmJHLlxyZx7Gwd3rIW6hOCdE4Zwl9/OD7/d3 Sv2w2ODcuD+mz6cPbt3T2AFhiZIEYaPQEwNeVzBQRN3VeHhQMvWp8ayshrTj8vJRg+vM DmXH50Nxk6e7BuEBrW8gun4+SnPTtJR1NOW1jR2mUC4H4TxGxlUcPLBD12eQk9SGrbXe UdAmDwK/2JqOh3CJHX5a7/NXa9R6uQZD69eRZRotNnJy0/7RzzT4+77NvYY1oF/0hVre 1v9Fx8gpxY7KC0CluihZvwjkhPZxqNOrB7J7l6xRZrCG3hGDJ4wD0pmLaS3jadbZr4Zg 6XTA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@flygoat.com header.s=fm1 header.b=dPUABwfk; dkim=pass header.i=@messagingengine.com header.s=fm3 header.b=tXtfXF8a; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=flygoat.com Received: from lipwig.vger.email (lipwig.vger.email. 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Fri, 27 Oct 2023 18:11:27 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, tsbogend@alpha.franken.de, gregory.clement@bootlin.com, vladimir.kondratiev@intel.com, Jiaxun Yang Subject: [PATCH v2 07/10] MIPS: traps: Handle CPU with non standard vint offset Date: Fri, 27 Oct 2023 23:11:03 +0100 Message-Id: <20231027221106.405666-8-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027221106.405666-1-jiaxun.yang@flygoat.com> References: <20231027221106.405666-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Fri, 27 Oct 2023 15:12:06 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780948380405226490 X-GMAIL-MSGID: 1780948380405226490 Some BMIPS cpus has none standard start offset for vector interrupts. Handle those CPUs in vector size calculation and handler setup process. Signed-off-by: Jiaxun Yang --- arch/mips/kernel/traps.c | 32 +++++++++++++++++++++++--------- 1 file changed, 23 insertions(+), 9 deletions(-) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index ea59d321f713..651c9ec6265a 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -74,7 +74,6 @@ #include "access-helper.h" -#define MAX(a, b) ((a) >= (b) ? (a) : (b)) extern void check_wait(void); extern asmlinkage void rollback_handle_int(void); @@ -2005,6 +2004,7 @@ void __noreturn nmi_exception_handler(struct pt_regs *regs) unsigned long ebase; EXPORT_SYMBOL_GPL(ebase); unsigned long exception_handlers[32]; +static unsigned long vi_vecbase; unsigned long vi_handlers[64]; void reserve_exception_space(phys_addr_t addr, unsigned long size) @@ -2074,7 +2074,7 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) handler = (unsigned long) addr; vi_handlers[n] = handler; - b = (unsigned char *)(ebase + 0x200 + n*VECTORSPACING); + b = (unsigned char *)(vi_vecbase + n*VECTORSPACING); if (srs >= srssets) panic("Shadow register set %d not supported", srs); @@ -2370,20 +2370,33 @@ void __init trap_init(void) extern char except_vec3_generic; extern char except_vec4; extern char except_vec3_r4000; - unsigned long i, vec_size; + unsigned long i, vec_size, vi_vec_offset; phys_addr_t ebase_pa; check_wait(); + if (cpu_has_veic || cpu_has_vint) { + switch (current_cpu_type()) { + case CPU_BMIPS3300: + case CPU_BMIPS4380: + vi_vec_offset = 0x400; + break; + case CPU_BMIPS5000: + vi_vec_offset = 0x1000; + break; + default: + vi_vec_offset = 0x200; + break; + } + vec_size = vi_vec_offset + VECTORSPACING*64; + } else { + vec_size = 0x400; + } + if (!cpu_has_mips_r2_r6) { ebase = CAC_BASE; - vec_size = 0x400; } else { - if (cpu_has_veic || cpu_has_vint) - vec_size = 0x200 + VECTORSPACING*64; - else - vec_size = PAGE_SIZE; - + vec_size = max(vec_size, PAGE_SIZE); ebase_pa = memblock_phys_alloc(vec_size, 1 << fls(vec_size)); if (!ebase_pa) panic("%s: Failed to allocate %lu bytes align=0x%x\n", @@ -2450,6 +2463,7 @@ void __init trap_init(void) * Initialise interrupt handlers */ if (cpu_has_veic || cpu_has_vint) { + vi_vecbase = ebase + vi_vec_offset; int nvec = cpu_has_veic ? 64 : 8; for (i = 0; i < nvec; i++) set_vi_handler(i, NULL); From patchwork Fri Oct 27 22:11:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 159176 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp913446vqb; Fri, 27 Oct 2023 15:12:39 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEjyf2eWcMuZhrjAe7sFXGQ4SLyKYf5bVFwK/3srgnLy43C0iDeinIsAKAzVZWVIoKptoMY X-Received: by 2002:a17:903:1385:b0:1cc:23ad:c2d5 with SMTP id jx5-20020a170903138500b001cc23adc2d5mr2692396plb.39.1698444759604; Fri, 27 Oct 2023 15:12:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698444759; cv=none; d=google.com; s=arc-20160816; b=hmU9/VCGOiCB1IDstF/TRiRW+2CnAlHns2d7llA83V/TYELUpuVdyZs3Tiz8sH+Kvk avlMjurE5hiMkKx2tpmmwRIaKo2O6hzqHIE5pT9IFX883J8Fcjk9I7jMmQSdPusErsQH oLCTsnI5gEGGDF/KeXyfaazlACnTIw2veKNxe4j7j9uvHQ/CoERen1QwLhj7XJVEQdPc OEJEHjD03jori/tpDAf8ftPZLS9wyB9FCPwLnq5Cb2sJA+l6MFoa9kZxI2v83LbiOu9B 2jSwk4xOwe50daMHwK+S7C5ugIyqaOdV9CrgCi2nOfxvO1T3mpRGZ8ZVHUApkaT0h5fb wdiA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :feedback-id:dkim-signature:dkim-signature; bh=GfLwAORI6DxI0P9SZsCprbtQo1SdXn/VrLRSxzuwQR4=; fh=34VXqKbbbRVUWYKB0XlF9D4jmhXxe51P2+smd1zcTfU=; b=LhPZZa4RcwP1/dbKF+v/cU9MCAhDsloMeqE73jKykZZiXDCPqDBIc17erMRpjAb+S2 bGiF0ENPNU4wkpIaG/XTOTJ6t19vwPs7dORnFEnD6kZs5BSTpPhnRES28zOkPNCpSzYN npChaRCBB4KyfpagMyKa4HoBb+vRm+LIoSFs2+j6dCo7tXI5Q5voQwEDsFgFhBmOaey2 Xmi7r+Ncyk5lCCeXT1/uWBRbt2Sji3/Eg8t/Bjyb1r7TyaVBwXb31wxTxbwBI1GGDFL6 0j+OnqLFXPEebNnay2YRBYdDE/rDpl1h8CXQO6OFnmwAtmONfYPeCqxpN+Qf3ibadBPm BpfA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@flygoat.com header.s=fm1 header.b=nYG6TLE9; dkim=pass header.i=@messagingengine.com header.s=fm3 header.b=MEdwpHWM; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=flygoat.com Received: from howler.vger.email (howler.vger.email. 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Fri, 27 Oct 2023 18:11:29 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, tsbogend@alpha.franken.de, gregory.clement@bootlin.com, vladimir.kondratiev@intel.com, Jiaxun Yang Subject: [PATCH v2 08/10] MIPS: Avoid unnecessary reservation of exception space Date: Fri, 27 Oct 2023 23:11:04 +0100 Message-Id: <20231027221106.405666-9-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027221106.405666-1-jiaxun.yang@flygoat.com> References: <20231027221106.405666-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on howler.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Fri, 27 Oct 2023 15:12:33 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780948412552850169 X-GMAIL-MSGID: 1780948412552850169 Nowadays we allocate exception base from memblock for r2_r6, so we don't need to reverse exception space at the start of the memory for r2_r6 processors. For older processors the reservation is moved to traps_init where we have knowledge of exact size we need. We also add a sanity check to detect possible overlap with kernel. Signed-off-by: Jiaxun Yang --- arch/mips/include/asm/traps.h | 1 - arch/mips/kernel/cpu-probe.c | 5 ----- arch/mips/kernel/cpu-r3k-probe.c | 2 -- arch/mips/kernel/traps.c | 12 +++++++----- 4 files changed, 7 insertions(+), 13 deletions(-) diff --git a/arch/mips/include/asm/traps.h b/arch/mips/include/asm/traps.h index 15cde638b407..d3dddd1c083a 100644 --- a/arch/mips/include/asm/traps.h +++ b/arch/mips/include/asm/traps.h @@ -24,7 +24,6 @@ extern void (*board_ebase_setup)(void); extern void (*board_cache_error_setup)(void); extern int register_nmi_notifier(struct notifier_block *nb); -extern void reserve_exception_space(phys_addr_t addr, unsigned long size); extern char except_vec_nmi[]; #define VECTORSPACING 0x100 /* for EI/VI mode */ diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index b406d8bfb15a..54e8b0fd4a2a 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c @@ -1570,7 +1570,6 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) c->cputype = CPU_BMIPS3300; __cpu_name[cpu] = "Broadcom BMIPS3300"; set_elf_platform(cpu, "bmips3300"); - reserve_exception_space(0x400, VECTORSPACING * 64); break; case PRID_IMP_BMIPS43XX: { int rev = c->processor_id & PRID_REV_MASK; @@ -1581,7 +1580,6 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) __cpu_name[cpu] = "Broadcom BMIPS4380"; set_elf_platform(cpu, "bmips4380"); c->options |= MIPS_CPU_RIXI; - reserve_exception_space(0x400, VECTORSPACING * 64); } else { c->cputype = CPU_BMIPS4350; __cpu_name[cpu] = "Broadcom BMIPS4350"; @@ -1598,7 +1596,6 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) __cpu_name[cpu] = "Broadcom BMIPS5000"; set_elf_platform(cpu, "bmips5000"); c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI; - reserve_exception_space(0x1000, VECTORSPACING * 64); break; } } @@ -1996,8 +1993,6 @@ void cpu_probe(void) if (cpu == 0) __ua_limit = ~((1ull << cpu_vmbits) - 1); #endif - - reserve_exception_space(0, 0x1000); } void cpu_report(void) diff --git a/arch/mips/kernel/cpu-r3k-probe.c b/arch/mips/kernel/cpu-r3k-probe.c index be93469c0e0e..05410b743e57 100644 --- a/arch/mips/kernel/cpu-r3k-probe.c +++ b/arch/mips/kernel/cpu-r3k-probe.c @@ -137,8 +137,6 @@ void cpu_probe(void) cpu_set_fpu_opts(c); else cpu_set_nofpu_opts(c); - - reserve_exception_space(0, 0x400); } void cpu_report(void) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 651c9ec6265a..b6e94654f621 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -2007,10 +2007,6 @@ unsigned long exception_handlers[32]; static unsigned long vi_vecbase; unsigned long vi_handlers[64]; -void reserve_exception_space(phys_addr_t addr, unsigned long size) -{ - memblock_reserve(addr, size); -} void __init *set_except_vector(int n, void *addr) { @@ -2394,7 +2390,13 @@ void __init trap_init(void) } if (!cpu_has_mips_r2_r6) { - ebase = CAC_BASE; + ebase_pa = 0x0; + ebase = CKSEG0ADDR(ebase_pa); + + if (__pa_symbol(_stext) < (ebase_pa + vec_size)) + pr_err("Insufficient space for exception vectors\n"); + + memblock_reserve(ebase_pa, vec_size); } else { vec_size = max(vec_size, PAGE_SIZE); ebase_pa = memblock_phys_alloc(vec_size, 1 << fls(vec_size)); From patchwork Fri Oct 27 22:11:05 2023 Content-Type: text/plain; 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Fri, 27 Oct 2023 18:11:32 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, tsbogend@alpha.franken.de, gregory.clement@bootlin.com, vladimir.kondratiev@intel.com, Jiaxun Yang Subject: [PATCH v2 09/10] MIPS: traps: Enhance memblock ebase allocation process Date: Fri, 27 Oct 2023 23:11:05 +0100 Message-Id: <20231027221106.405666-10-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027221106.405666-1-jiaxun.yang@flygoat.com> References: <20231027221106.405666-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Fri, 27 Oct 2023 15:12:33 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780948408165584204 X-GMAIL-MSGID: 1780948408165584204 We try to allocate from KSEG0 accessible space first, and then if we really can't allocate any memory from KSEG0 and we are sure that we support ebase in higher segment, give it another go without restriction. This can maximize the possibility of having ebase in KSEG0. Signed-off-by: Jiaxun Yang --- arch/mips/kernel/traps.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index b6e94654f621..68f1dd54cde1 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -2399,7 +2399,12 @@ void __init trap_init(void) memblock_reserve(ebase_pa, vec_size); } else { vec_size = max(vec_size, PAGE_SIZE); - ebase_pa = memblock_phys_alloc(vec_size, 1 << fls(vec_size)); + ebase_pa = memblock_phys_alloc_range(vec_size, 1 << fls(vec_size), + 0x0, KSEGX_SIZE - 1); + + if (!ebase_pa && (IS_ENABLED(CONFIG_EVA) || cpu_has_ebase_wg)) + ebase_pa = memblock_phys_alloc(vec_size, 1 << fls(vec_size)); + if (!ebase_pa) panic("%s: Failed to allocate %lu bytes align=0x%x\n", __func__, vec_size, 1 << fls(vec_size)); From patchwork Fri Oct 27 22:11:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 159175 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp913438vqb; Fri, 27 Oct 2023 15:12:38 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEKyKbLaAYan3+SBAgk3rwUBRgFsm3hq7Ok9T6yvtbyScKnI8Rl44YJMz5YPZ8tkPafWG1x X-Received: by 2002:a05:6a21:3393:b0:14c:c511:387d with SMTP id yy19-20020a056a21339300b0014cc511387dmr5160142pzb.9.1698444758521; Fri, 27 Oct 2023 15:12:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698444758; cv=none; d=google.com; s=arc-20160816; b=NK0ZUlyvvKx+oHZF3vhqryR2Z2kBlHMwtxqTWFxQAKGYQ5nvtivcSsjiZjuW5lTULs g0Oj1MYVkep1r2UOl2+imagLJbLvPbRi5uITrKETSFWiPyqX5M4LNwE405WZbYW8Yy2l AD9fsCZwOXc5Zup8VMOVpvT4q6P5VwwrHyvPmHfOjSIqrM0nnAuInvlRhcF5K8QciMrV W+Gbjef7MPMGHGBluiTeCUFjoZZhriSPV9TdepM9pve5kJYte3kpShGl80mDleU8VkCW 8iDVbmOAqr/EC6DR1HYF+YfaM9+A0n+DxLBJbZ3bcIeqUPp/nQ6VDu2mfANM2ujU/Vxi lXDA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :feedback-id:dkim-signature:dkim-signature; bh=ovE6ErC2FU6MOXhQYQRXjYJQxqoUgfjvz+3gaCNVsfA=; fh=34VXqKbbbRVUWYKB0XlF9D4jmhXxe51P2+smd1zcTfU=; b=y3Cvggjxy9rQ/+0Xe4SDt1OY+EmAvsW7hdW2nmuRlJh+B2iqMJVhBMXuuUXPeTFNSd NbBQ9UssLj60y+vM0gfexP3+JAm8T1DPZNlorEc3ZsmHtu5TqNiJhQxhRgl9vyLbwx2Q gSPDb50D10fSaPOSDm3vXJxzHWX4o1b8suSdFDpMMZ2dovOjiFBu6D7TbDz59yYEqpG1 vT3gAlbH4jtG5++RHAhhxftPr1qVAbSysXFjjOew1ARleB1mQSm8SF4SFwJVDLflA93y ttPKSJbshGlMADjo018TL1VgdKKSEHnJ+ZDIu33CaWv8YkQcZeto3chWWRIChTdlUa4f yqsQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@flygoat.com header.s=fm1 header.b=ue7ck+5i; dkim=pass header.i=@messagingengine.com header.s=fm3 header.b=EYng0q4p; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=flygoat.com Received: from agentk.vger.email (agentk.vger.email. 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Fri, 27 Oct 2023 18:11:34 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, tsbogend@alpha.franken.de, gregory.clement@bootlin.com, vladimir.kondratiev@intel.com, Jiaxun Yang Subject: [PATCH v2 10/10] MIPS: Get rid of CONFIG_NO_EXCEPT_FILL Date: Fri, 27 Oct 2023 23:11:06 +0100 Message-Id: <20231027221106.405666-11-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231027221106.405666-1-jiaxun.yang@flygoat.com> References: <20231027221106.405666-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Fri, 27 Oct 2023 15:12:36 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780948410998067089 X-GMAIL-MSGID: 1780948410998067089 NO_EXCEPT_FILL is used to indicate platform that does not need to reserve ebase memory at start of kernel. This is true for all R2+ platform as they allocate ebase memory on fly, and also true for any platform that does not load kernel at start of physical memory. Get rid this Kconfig symbol by use macro to detect conditions above. Signed-off-by: Jiaxun Yang --- arch/mips/Kconfig | 9 --------- arch/mips/kernel/head.S | 7 +++++-- 2 files changed, 5 insertions(+), 11 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index bfedc8b48a81..e928ebc2cd1f 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -149,7 +149,6 @@ config MIPS_GENERIC_KERNEL select MIPS_CPU_SCACHE select MIPS_GIC select MIPS_L1_CACHE_SHIFT_7 - select NO_EXCEPT_FILL select PCI_DRIVERS_GENERIC select SMP_UP if SMP select SWAP_IO_SPACE @@ -210,7 +209,6 @@ config AR7 select CEVT_R4K select CSRC_R4K select IRQ_MIPS_CPU - select NO_EXCEPT_FILL select SWAP_IO_SPACE select SYS_HAS_CPU_MIPS32_R1 select SYS_HAS_EARLY_PRINTK @@ -265,7 +263,6 @@ config BMIPS_GENERIC select ARCH_HAS_RESET_CONTROLLER select ARCH_HAS_SYNC_DMA_FOR_CPU_ALL select BOOT_RAW - select NO_EXCEPT_FILL select USE_OF select CEVT_R4K select CSRC_R4K @@ -309,7 +306,6 @@ config BCM47XX select HAVE_PCI select IRQ_MIPS_CPU select SYS_HAS_CPU_MIPS32_R1 - select NO_EXCEPT_FILL select SYS_SUPPORTS_32BIT_KERNEL select SYS_SUPPORTS_LITTLE_ENDIAN select SYS_SUPPORTS_MIPS16 @@ -445,7 +441,6 @@ config LANTIQ select IRQ_MIPS_CPU select CEVT_R4K select CSRC_R4K - select NO_EXCEPT_FILL select SYS_HAS_CPU_MIPS32_R1 select SYS_HAS_CPU_MIPS32_R2 select SYS_SUPPORTS_BIG_ENDIAN @@ -494,7 +489,6 @@ config MACH_LOONGSON64 select ISA select I8259 select IRQ_MIPS_CPU - select NO_EXCEPT_FILL select NR_CPUS_DEFAULT_64 select USE_GENERIC_EARLY_PRINTK_8250 select PCI_DRIVERS_GENERIC @@ -1177,9 +1171,6 @@ config PCI_GT64XXX_PCI0 config PCI_XTALK_BRIDGE bool -config NO_EXCEPT_FILL - bool - config MIPS_SPRAM bool diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S index b825ed4476c7..4af53b1628f5 100644 --- a/arch/mips/kernel/head.S +++ b/arch/mips/kernel/head.S @@ -59,10 +59,13 @@ #endif .endm -#ifndef CONFIG_NO_EXCEPT_FILL +#if (MIPS_ISA_REV < 2) && \ + ((VMLINUX_LOAD_ADDRESS == KSEG0) || \ + (VMLINUX_LOAD_ADDRESS == CKSEG0)) /* * Reserved space for exception handlers. - * Necessary for machines which link their kernels at KSEG0. + * Necessary for machines which link their kernels at KSEG0 + * and incapable of moving ebase. */ .fill 0x400 #endif