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[8.43.85.97]) by mx.google.com with ESMTPS id c9-20020ac87dc9000000b0041cc346426asi790628qte.135.2023.10.27.07.22.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 07:22:28 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=fail header.i=@nextmovesoftware.com header.s=default header.b="bsAzG/KA"; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0FF3A3861803 for ; Fri, 27 Oct 2023 14:22:28 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id 13A7A3857C43 for ; Fri, 27 Oct 2023 14:22:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 13A7A3857C43 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nextmovesoftware.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 13A7A3857C43 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=162.254.253.69 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698416524; cv=none; b=lG4Kl1WU6wKGBKcHviI7BghnbNWgB49Q5YJ+VfoEbFZtLkz9h4MOJgShHuvLsuGKJJS+8Q3lSNF5oOywmuj1risSN3zg63fy+MF6vsoqrwGcveNgC950J2fx37rKbKZIyJq0OjDKgnvhZQygVvA/r4RgNn+pPh++QbhZuy2RXSQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698416524; c=relaxed/simple; bh=ViTxpIrTCQYFyx6yozBUdZWkS4cpLlFXeaNlNDqsVr8=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=ncQJ8AmyoxAM6FKTsm6hz97d2/VwXKha3vHs+nEKZuT5eJzGSyoOUplFnuPEWMhKscMrE9shASscdZP4KI4VXLlm5fTMnEd2FI+vYEWd69POYGdTS7/Snb9SlHHnnHULHVNhsHsWui5ycq9hjzRFA3g2EvkEkhizM8NiDsL+gcI= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Type:MIME-Version:Message-ID: Date:Subject:Cc:To:From:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=37p0dH0XOitvFAXUL4AN+LD9YScRj6dGBQ8ItXebpu8=; b=bsAzG/KAhuyKa5+hWsRKgGt/kZ eeLsB5A9ubLxzwH9pKwUockKpheqsnSCmtJI7++XeE7Mc+zyTb0+3OePBeSIiSwUDU5SZ6qinEdI/ DlsyKU0PZm53bj4qkz6Q7zsIcih5nS/gibTbHIy9Wu4ThGIwofWrgY/OonfCegGtjktOOPX3UTuU+ /J2DLufHKWexI9ox9pqEjV97JubA9vM/w4b31vG3d2NXoljWP31YP1bikbLZXggGbt9a7Mb5g6lPq 2eAvf9h74da0/o4zX4wmqnhmcdvRezkRlsBE0mE4UYndtN4tA3HtqwCm16lNtCBvecrc0Op3OcIeK /TSoXvCw==; Received: from [185.62.158.67] (port=64640 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96.2) (envelope-from ) id 1qwNir-0003EK-3D; Fri, 27 Oct 2023 10:22:02 -0400 From: "Roger Sayle" To: Cc: "'Claudiu Zissulescu'" Subject: [ARC PATCH] Improved SImode shifts and rotates with -mswap. Date: Fri, 27 Oct 2023 15:22:00 +0100 Message-ID: <005001da08e0$f42fa2b0$dc8ee810$@nextmovesoftware.com> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: AdoI3/yqlQu0LfCRSZqFE3XFzNxHRQ== Content-Language: en-gb X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780918830103348659 X-GMAIL-MSGID: 1780918830103348659 This patch improves the code generated by the ARC back-end for CPUs without a barrel shifter but with -mswap. The -mswap option provides a SWAP instruction that implements SImode rotations by 16, but also logical shift instructions (left and right) by 16 bits. Clearly these are also useful building blocks for implementing shifts by 17, 18, etc. which would otherwise require a loop. As a representative example: int shl20 (int x) { return x << 20; } GCC with -O2 -mcpu=em -mswap would previously generate: shl20: mov lp_count,10 lp 2f add r0,r0,r0 add r0,r0,r0 2: # end single insn loop j_s [blink] with this patch we now generate: shl20: mov_s r2,0 ;3 lsl16 r0,r0 add3 r0,r2,r0 j_s.d [blink] asl_s r0,r0 Although both are four instructions (excluding the j_s), the original takes ~22 cycles, and replacement ~4 cycles. Tested with a cross-compiler to arc-linux hosted on x86_64, with no new (compile-only) regressions from make -k check. Ok for mainline if this passes Claudiu's nightly testing? 2023-10-27 Roger Sayle gcc/ChangeLog * config/arc/arc.cc (arc_split_ashl): Use lsl16 on TARGET_SWAP. (arc_split_ashr): Use swap and sign-extend on TARGET_SWAP. (arc_split_lshr): Use lsr16 on TARGET_SWAP. (arc_split_rotl): Use swap on TARGET_SWAP. (arc_split_rotr): Likewise. * config/arc/arc.md (ANY_ROTATE): New code iterator. (si2_cnt16): New define_insn for alternate form of swap instruction on TARGET_SWAP. (ashlsi2_cnt16): Rename from *ashlsi16_cnt16 and move earlier. (lshrsi2_cnt16): New define_insn for LSR16 instruction. (*ashlsi2_cnt16): See above. gcc/testsuite/ChangeLog * gcc.target/arc/lsl16-1.c: New test case. * gcc.target/arc/lsr16-1.c: Likewise. * gcc.target/arc/swap-1.c: Likewise. * gcc.target/arc/swap-2.c: Likewise. Thanks in advance, Roger diff --git a/gcc/config/arc/arc.cc b/gcc/config/arc/arc.cc index 353ac69..e98692a 100644 --- a/gcc/config/arc/arc.cc +++ b/gcc/config/arc/arc.cc @@ -4256,6 +4256,17 @@ arc_split_ashl (rtx *operands) } return; } + else if (n >= 16 && n <= 22 && TARGET_SWAP && TARGET_V2) + { + emit_insn (gen_ashlsi2_cnt16 (operands[0], operands[1])); + if (n > 16) + { + operands[1] = operands[0]; + operands[2] = GEN_INT (n - 16); + arc_split_ashl (operands); + } + return; + } else if (n >= 29) { if (n < 31) @@ -4300,6 +4311,15 @@ arc_split_ashr (rtx *operands) emit_move_insn (operands[0], operands[1]); return; } + else if (n >= 16 && n <= 18 && TARGET_SWAP) + { + emit_insn (gen_rotrsi2_cnt16 (operands[0], operands[1])); + emit_insn (gen_extendhisi2 (operands[0], + gen_lowpart (HImode, operands[0]))); + while (--n >= 16) + emit_insn (gen_ashrsi3_cnt1 (operands[0], operands[0])); + return; + } else if (n == 30) { rtx tmp = gen_reg_rtx (SImode); @@ -4339,6 +4359,13 @@ arc_split_lshr (rtx *operands) emit_move_insn (operands[0], operands[1]); return; } + else if (n >= 16 && n <= 19 && TARGET_SWAP && TARGET_V2) + { + emit_insn (gen_lshrsi2_cnt16 (operands[0], operands[1])); + while (--n >= 16) + emit_insn (gen_lshrsi3_cnt1 (operands[0], operands[0])); + return; + } else if (n == 30) { rtx tmp = gen_reg_rtx (SImode); @@ -4385,6 +4412,19 @@ arc_split_rotl (rtx *operands) emit_insn (gen_rotrsi3_cnt1 (operands[0], operands[0])); return; } + else if (n >= 13 && n <= 16 && TARGET_SWAP) + { + emit_insn (gen_rotlsi2_cnt16 (operands[0], operands[1])); + while (++n <= 16) + emit_insn (gen_rotrsi3_cnt1 (operands[0], operands[0])); + return; + } + else if (n == 17 && TARGET_SWAP) + { + emit_insn (gen_rotlsi2_cnt16 (operands[0], operands[1])); + emit_insn (gen_rotlsi3_cnt1 (operands[0], operands[0])); + return; + } else if (n >= 16 || n == 12 || n == 14) { emit_insn (gen_rotrsi3_loop (operands[0], operands[1], @@ -4415,6 +4455,19 @@ arc_split_rotr (rtx *operands) emit_move_insn (operands[0], operands[1]); return; } + else if (n == 15 && TARGET_SWAP) + { + emit_insn (gen_rotrsi2_cnt16 (operands[0], operands[1])); + emit_insn (gen_rotlsi3_cnt1 (operands[0], operands[0])); + return; + } + else if (n >= 16 && n <= 19 && TARGET_SWAP) + { + emit_insn (gen_rotrsi2_cnt16 (operands[0], operands[1])); + while (--n >= 16) + emit_insn (gen_rotrsi3_cnt1 (operands[0], operands[0])); + return; + } else if (n >= 30) { emit_insn (gen_rotlsi3_cnt1 (operands[0], operands[1])); diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md index ee43887..7d5a124 100644 --- a/gcc/config/arc/arc.md +++ b/gcc/config/arc/arc.md @@ -3353,6 +3353,7 @@ archs4x, archs4xd" ;; Shift instructions. +(define_code_iterator ANY_ROTATE [rotate rotatert]) (define_code_iterator ANY_SHIFT_ROTATE [ashift ashiftrt lshiftrt rotate rotatert]) @@ -3415,6 +3416,37 @@ archs4x, archs4xd" (set_attr "predicable" "no,no,yes,no,no") (set_attr "cond" "nocond,canuse,canuse,nocond,nocond")]) +(define_insn "si2_cnt16" + [(set (match_operand:SI 0 "dest_reg_operand" "=w") + (ANY_ROTATE:SI (match_operand:SI 1 "register_operand" "c") + (const_int 16)))] + "TARGET_SWAP" + "swap\\t%0,%1" + [(set_attr "length" "4") + (set_attr "type" "two_cycle_core")]) + +(define_insn "ashlsi2_cnt16" + [(set (match_operand:SI 0 "register_operand" "=r") + (ashift:SI (match_operand:SI 1 "nonmemory_operand" "rL") + (const_int 16)))] + "TARGET_SWAP && TARGET_V2" + "lsl16\\t%0,%1" + [(set_attr "type" "shift") + (set_attr "iscompact" "false") + (set_attr "length" "4") + (set_attr "predicable" "no")]) + +(define_insn "lshrsi2_cnt16" + [(set (match_operand:SI 0 "register_operand" "=r") + (lshiftrt:SI (match_operand:SI 1 "nonmemory_operand" "rL") + (const_int 16)))] + "TARGET_SWAP && TARGET_V2" + "lsr16\\t%0,%1" + [(set_attr "type" "shift") + (set_attr "iscompact" "false") + (set_attr "length" "4") + (set_attr "predicable" "no")]) + ;; Split asl dst,1,src into bset dst,0,src. (define_insn_and_split "*ashlsi3_1" [(set (match_operand:SI 0 "dest_reg_operand") @@ -5929,17 +5961,6 @@ archs4x, archs4xd" (set_attr "length" "4") (set_attr "predicable" "no")]) -(define_insn "*ashlsi2_cnt16" - [(set (match_operand:SI 0 "register_operand" "=r") - (ashift:SI (match_operand:SI 1 "nonmemory_operand" "rL") - (const_int 16)))] - "TARGET_SWAP && TARGET_V2" - "lsl16\\t%0,%1" - [(set_attr "type" "shift") - (set_attr "iscompact" "false") - (set_attr "length" "4") - (set_attr "predicable" "no")]) - (define_insn "lshrsi3_cnt1" [(set (match_operand:SI 0 "dest_reg_operand" "=q,w") (lshiftrt:SI (match_operand:SI 1 "register_operand" "q,c") diff --git a/gcc/testsuite/gcc.target/arc/lsl16-1.c b/gcc/testsuite/gcc.target/arc/lsl16-1.c new file mode 100644 index 0000000..cbd0dae --- /dev/null +++ b/gcc/testsuite/gcc.target/arc/lsl16-1.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mcpu=em -mswap" } */ + +int foo(int x) +{ + return x << 16; +} + +/* { dg-final { scan-assembler "lsl16\\s+r0,r0" } } */ + diff --git a/gcc/testsuite/gcc.target/arc/lsr16-1.c b/gcc/testsuite/gcc.target/arc/lsr16-1.c new file mode 100644 index 0000000..8ce5f13 --- /dev/null +++ b/gcc/testsuite/gcc.target/arc/lsr16-1.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mcpu=em -mswap" } */ + +unsigned int foo(unsigned int x) +{ + return x >> 16; +} + +/* { dg-final { scan-assembler "lsr16\\s+r0,r0" } } */ + diff --git a/gcc/testsuite/gcc.target/arc/swap-1.c b/gcc/testsuite/gcc.target/arc/swap-1.c new file mode 100644 index 0000000..71afc75 --- /dev/null +++ b/gcc/testsuite/gcc.target/arc/swap-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mcpu=em -mswap" } */ + +int foo(int x) +{ + return ((unsigned int)x >> 16) | (x << 16); +} + +/* { dg-final { scan-assembler "swap\\s+r0,r0" } } */ diff --git a/gcc/testsuite/gcc.target/arc/swap-2.c b/gcc/testsuite/gcc.target/arc/swap-2.c new file mode 100644 index 0000000..bf12392 --- /dev/null +++ b/gcc/testsuite/gcc.target/arc/swap-2.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mcpu=em -mswap" } */ + +int foo(int x) +{ + return x >> 16; +} + +/* { dg-final { scan-assembler "swap\\s+r0,r0" } } */ +/* { dg-final { scan-assembler "sexh_s\\s+r0,r0" } } */ +