From patchwork Fri Oct 27 09:26:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Victor Do Nascimento X-Patchwork-Id: 158873 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp471449vqb; Fri, 27 Oct 2023 02:28:26 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF8VaNTL04lU7IGafZAHQh6ubl8zh4thgS2lX3b5K2r88JBZuXW7NI+5XlOxFs6jvPWP929 X-Received: by 2002:a0c:f112:0:b0:66d:1b62:5c22 with SMTP id i18-20020a0cf112000000b0066d1b625c22mr1955619qvl.0.1698398906453; Fri, 27 Oct 2023 02:28:26 -0700 (PDT) ARC-Seal: i=4; a=rsa-sha256; t=1698398906; cv=pass; d=google.com; s=arc-20160816; b=iBwKvIod6ywKibayUFRQiNLfSXA3Tll/JTsxXZRwjx5A82tyvgsbzv5UEAFbK8DFRL Np5LU8LEbbgdnICWgnUYRfAdLP9LTp6i3DqAqn60dY74iOVYsWkNStYhgoIt9uxxkYqK v74JXVWpXB/jUnm2BL8F7t5eQ5C+ArS8qIv6rOHftSOITihudcAflK7ReYX63cKDhc3t /7JBVWYxHHfWJ+W8SqIl+gWW+xg0JvuZlfM1Uc5DvSgs2a2EUtnEXo6nkq/aE33kk2yP q3GgsaIGOjCKcarqkEyc7XTVcS9R3r/EeNfsCtbpcCHG1SBXX82rDBAN+Wgift7DVxR3 qiNQ== ARC-Message-Signature: i=4; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:nodisclaimer :content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:dkim-signature:dkim-signature:arc-filter:dmarc-filter :delivered-to; bh=aKstKvc/LJvGOPS62o34bya6RgPBgS/INsRJO1+zdVI=; fh=puYCM8FRHzins9HjEsl9lyIrPa8b21rR+m5ND3mNx7M=; b=hQaI/W56T7E64/bISL+KmubYBQZe4Iw10/bmDlbpL7JYf0Xua9wL4b48H5DmO04WrU YPgERXmM/lmHuJNdHbto+TXfmpR5QrKdq5DPtYQ/enpg2T4XBYEN4AgFrz9H7C7DgLQc lmEjCbOHMX9qE7tF3bFqDn9wj78KjCQJ4U0GsvRBic4XMeKK6K3gYyaIopX26RHjyd7t Fmq8jUQay5D94lkE03dC+SQSkOIzsg7v4OrzI8n4lGhD7PwEGokXSXz4pYst+uOlzdJ7 mGbKynj7TN7sX849KLuGdhliohlhYF5MVojhfoDGNrXwoJ+izdRgwczRjvpPjDiTgv7d /yJQ== ARC-Authentication-Results: i=4; mx.google.com; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=UxfSVYjG; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=UxfSVYjG; arc=pass (i=3); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id ee9-20020a0562140a4900b0065b13b5cbe9si577144qvb.459.2023.10.27.02.28.26 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 27 Oct 2023 02:28:26 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=UxfSVYjG; dkim=pass header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=UxfSVYjG; arc=pass (i=3); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=arm.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 22161385350D for ; Fri, 27 Oct 2023 09:28:26 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from EUR04-DB3-obe.outbound.protection.outlook.com (mail-db3eur04on2085.outbound.protection.outlook.com [40.107.6.85]) by sourceware.org (Postfix) with ESMTPS id A138A3858D35 for ; Fri, 27 Oct 2023 09:27:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A138A3858D35 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=arm.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org A138A3858D35 Authentication-Results: server2.sourceware.org; arc=pass smtp.remote-ip=40.107.6.85 ARC-Seal: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1698398880; cv=pass; b=fPN2KdWSqJLBogSXTjcObA/q/vaHtpiZn3t6LP58wa+X6H8DgUuB6AJkqR0LvoNnLmRUi5z8KRfGhrcBk/85UdlaSvNdolFFDfLLMeW1EgPM9xjCZ792R3dSdeUbwek+Ir+Gisn4/1N7kNrcD7pidQqumEiAqlgU4wBeYrDSxBk= ARC-Message-Signature: i=3; a=rsa-sha256; d=sourceware.org; s=key; t=1698398880; c=relaxed/simple; bh=fgOYLUCjXLXF0d2DclzJEElNOR+ki/+6sykqWc9Ucvg=; h=DKIM-Signature:DKIM-Signature:From:To:Subject:Date:Message-ID: MIME-Version; b=VgCSpSOSD41YRG2ep3UeT48KsmLiyUX3BFLHPJB5Vw0QFf6LUqnEoZIRPuBPlkNIPervSfzQ6uOWmSmUkVNgs02Ce7zN8lKjRsINjmjKtoNwE3KH88Okh0Qmv5kjcUD487KPBzMpHLxR/bTfsdObuQyrKCYdV8qEWX76nVBKgF4= ARC-Authentication-Results: i=3; server2.sourceware.org ARC-Seal: i=2; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=pass; b=MVBQI6n18+0GRHrLv1nN/L79D7+cNLuuTuO4CF5jkhfGZnVFmB4nDQF+Z650TKCtF3MaNHupkV5JIvz5V2hpoF9KYili68McgWjutPNM/NM2KxvoFiKk/ceLQasi2ZwMqP5D4RTzs1hdpIEsXD1IxWNvKpk9LGGzgIaLCkwhQ/6JDWc0mAhbjgjOjDO0EugVIxtZH/fbC2RUIx4ouIW53KqLQKjCMFBwsF+vVUwWgClwBRUszP7tIe36RZn0s7Ps0cGuCb2AKWOTI5qhkqHBav9rWaQrJN4Im7PEyOttrxhKVIsaS6bFp1A+12kmDecpIMRE4pM8ZVwQ/JV8UQYmOg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=aKstKvc/LJvGOPS62o34bya6RgPBgS/INsRJO1+zdVI=; b=GRYWix2p9pwSVZmJJRnpQoIDIlR8LFRvNvY4QOUgzgeQQIXWtdjkiWXkpR0Dz1W4M9Abxq1GuA0c8Uq+u+INiMVIHEqgIuIk/Dq6e37RHVRfGXfMVH61W9kRKDtROUBEnMEPHwWyQVPaSPMQItVwabiDB1JrmFdS4MPCJlelPepeMFB1Lkw43sAHZkPQZBXaOkbhYEtLJBEcX1KZT+JJ3CtFcGR7PuzfZnCw5FpvXDOiau5WG8NBaobj8DaYu3BZU+QdqPPHfUenTUjFWTJD9B0Z2rula553oAnBXAXSQBESNQ9SadWCMJs2mWD4L14KniPm4rgGqI2jyd5Ge/QqTw== ARC-Authentication-Results: i=2; mx.microsoft.com 1; spf=pass (sender ip is 63.35.35.123) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com; arc=pass (0 oda=1 ltdi=1 spf=[1,1,smtp.mailfrom=arm.com] dmarc=[1,1,header.from=arm.com]) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=aKstKvc/LJvGOPS62o34bya6RgPBgS/INsRJO1+zdVI=; b=UxfSVYjG4YVo9PSdkZvh0Uyr5k5+znbPGCRWYrXdWzz7XnQR2L7fTUn0UBsi8nl30+VxRkGfa1FAqg0nRw2jSm4JYZlHyz1LhuhWqb6u+0TdZy6y/75Vp/pQSsOjQr/t0f4u7kGTf0o+RTSsQv0SNNJSCiXxZ8ZKGwAWf8o/32Q= Received: from AS9PR06CA0577.eurprd06.prod.outlook.com (2603:10a6:20b:486::17) by AS8PR08MB10078.eurprd08.prod.outlook.com (2603:10a6:20b:63c::6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6907.25; Fri, 27 Oct 2023 09:27:53 +0000 Received: from AM3PEPF0000A798.eurprd04.prod.outlook.com (2603:10a6:20b:486:cafe::c) by AS9PR06CA0577.outlook.office365.com (2603:10a6:20b:486::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6933.24 via Frontend Transport; Fri, 27 Oct 2023 09:27:53 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; pr=C Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by AM3PEPF0000A798.mail.protection.outlook.com (10.167.16.103) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6933.15 via Frontend Transport; Fri, 27 Oct 2023 09:27:52 +0000 Received: ("Tessian outbound 26ee1d40577c:v228"); Fri, 27 Oct 2023 09:27:52 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: 0c5c754ac5e041af X-CR-MTA-TID: 64aa7808 Received: from c4c066895928.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id B1CE3A7C-8B7B-46F2-920E-B33DDB27C731.1; Fri, 27 Oct 2023 09:27:45 +0000 Received: from EUR02-AM0-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id c4c066895928.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Fri, 27 Oct 2023 09:27:45 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=HpCU0BMeOtr9GKWO1yCoAZCR/6wYAdcNtY9FfozemSiqM0NoJWcVZureLlYotPrFZqVhA0OHE9PNfNgcrmVK6V7gqR6lHDM5gGf/Eno0pC7NaO20weC3VUmNQ2Qr+PmMif4u6NiZMCwT+O4oJR931UDqaGxnKPrgCtmfEloRtYbptHSRzSKr1D11jxjEzi3ZL6425tHgyp2ohGmmb4HftCMt/P8QlkSRUuPW2c0WDJlXSBg/iyoLbIopfZQ3FjEav2U2iGqCRJB6hoIRn/AA8bwzUrvj5PUfmLuzUoa4JIgqHrp5WhYW4OavhXyYHRV/GP7U9aSZnqVyIUysRs7ZgA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=aKstKvc/LJvGOPS62o34bya6RgPBgS/INsRJO1+zdVI=; b=G75v5YRa7gaSYgxhYEr+0kLiHETtKITyN0hPRuexNJV0Du4LToEf08B9J3z3GaJSRUPoQ0Lha43zJgr9zJBXNB78x4BAgHpNC8jpUuXhiq0jDLgOnKNrqYO/W+/ZfHkHLSd+LjTVcXh4D4XCAUkxO1DfT/2eV0E60TRHXlHMpsnMKk+pjZZFN2Tg5/Ol5IB04xQ2FcftWhXSAeGlqCbkERruY2gliPpQifp1ENHD+ePOyfvQsOT0/91xXdOaFVADJlkVzX5E9/BGGsIPGYpXULdTUm2O9yw3pLtFKN4gmovbl6p2IbUvADCDKu10lTeTH1qQiyY2EABPDk4Z8pbpMA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 40.67.248.234) smtp.rcpttodomain=gcc.gnu.org smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=none (message not signed); arc=none (0) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=aKstKvc/LJvGOPS62o34bya6RgPBgS/INsRJO1+zdVI=; b=UxfSVYjG4YVo9PSdkZvh0Uyr5k5+znbPGCRWYrXdWzz7XnQR2L7fTUn0UBsi8nl30+VxRkGfa1FAqg0nRw2jSm4JYZlHyz1LhuhWqb6u+0TdZy6y/75Vp/pQSsOjQr/t0f4u7kGTf0o+RTSsQv0SNNJSCiXxZ8ZKGwAWf8o/32Q= Received: from DUZPR01CA0265.eurprd01.prod.exchangelabs.com (2603:10a6:10:4b9::15) by AS2PR08MB9024.eurprd08.prod.outlook.com (2603:10a6:20b:5fe::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6907.33; Fri, 27 Oct 2023 09:27:43 +0000 Received: from DB5PEPF00014B99.eurprd02.prod.outlook.com (2603:10a6:10:4b9:cafe::ab) by DUZPR01CA0265.outlook.office365.com (2603:10a6:10:4b9::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.6933.24 via Frontend Transport; Fri, 27 Oct 2023 09:27:43 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 40.67.248.234) smtp.mailfrom=arm.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; pr=C Received: from nebula.arm.com (40.67.248.234) by DB5PEPF00014B99.mail.protection.outlook.com (10.167.8.166) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6933.18 via Frontend Transport; Fri, 27 Oct 2023 09:27:43 +0000 Received: from AZ-NEU-EX04.Arm.com (10.251.24.32) by AZ-NEU-EX04.Arm.com (10.251.24.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.32; Fri, 27 Oct 2023 09:27:42 +0000 Received: from e125768.cambridge.arm.com (10.2.78.50) by mail.arm.com (10.251.24.32) with Microsoft SMTP Server id 15.1.2507.32 via Frontend Transport; Fri, 27 Oct 2023 09:27:42 +0000 From: Victor Do Nascimento To: CC: , , , Victor Do Nascimento Subject: [PATCH] aarch64: Implement ACLE instruction/data prefetch functions. Date: Fri, 27 Oct 2023 10:26:47 +0100 Message-ID: <20231027092737.4115519-1-victor.donascimento@arm.com> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-TrafficTypeDiagnostic: DB5PEPF00014B99:EE_|AS2PR08MB9024:EE_|AM3PEPF0000A798:EE_|AS8PR08MB10078:EE_ X-MS-Office365-Filtering-Correlation-Id: 9da52429-30ef-498f-db30-08dbd6cefec4 x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: esziRAR4v1DB5/BPzmm3YCV5Zr3N0QmtRoRptzzD4hAi6OrLuW4uVRaxjHWCCRm7yxZYQyLXNA4NTw34W2kGP96ZOuk9Ni8clZasZ97BnpKVl8sj1ZiLG9g+FoBYztgJXoa1vJpvFEx0UCb2mxNjXqSnR9nAd2hGEf1zjlc032PMWEErvavzdCUp7GNQ1ZFkPQcrLO1gzVpBbfZAjktHEgMDlvvMxhv47tgXCMTRWTOkyGqbZQBaX30/LfQCucfpvP7QLY/45oYciGGOyi+jdJJ0JJwSPmXMuPtKaS0moSZSZ3JNrOtYRbCYzLyG9u5GoUjXT4ilC3fCmjCODZRDa9w8wazNKvY53ArzRngdw+O6UFJ++uGcXXIiPJTVJHn9/znDL5ayLJXzkuBVZg76ONjfUw13ZmEDC9vvWJOziRWE9O3RBnJ7AYV1vbjtQ07B19ptzuIUeM9GWIKhvI7iG8PxXdp8QvM7BAwxxeQZ70LRTFTDz/KRS9g1noy5sLXcuBFZhewIUiQrhhVf2BeSZXCivNIqZcvBs7+XVfAbVLn6qPybPcxIcWBnqXM3C6o8LxTXWTwTt38ko49b9P1CbmCtSXkpQpM1xkDdC7wiRjjFoWlaOj7mwe785bG3+H91D0RR/QTcO8VgYTSMmx87Ho5aXdzK5NucdgJt+mIhIhm9xv45TRAzoN8ZJv4ditTFhO1NRF8bFQVGxI0pPzQUZ/GoucjS9urq/KkOLEd7PQCfeUET6TUGM1Gjbwfq2+3SyUvo6QUUD1E16f2zd5gL42lDCcUa8O3V/SoHWpUUydzqhqKY+4/TQuBwTamrXq/M4a/yhocH03SJsTeNWKBLYA== X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:nebula.arm.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230031)(4636009)(396003)(346002)(136003)(376002)(39860400002)(230922051799003)(230273577357003)(230173577357003)(64100799003)(1800799009)(451199024)(186009)(82310400011)(36840700001)(40470700004)(46966006)(30864003)(81166007)(36756003)(36860700001)(2906002)(54906003)(478600001)(2616005)(70206006)(316002)(6916009)(1076003)(70586007)(426003)(336012)(82740400003)(47076005)(83380400001)(966005)(40480700001)(40460700003)(41300700001)(5660300002)(86362001)(7696005)(356005)(8676002)(4326008)(8936002)(84970400001)(26005)(36900700001); DIR:OUT; SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS2PR08MB9024 X-MS-Exchange-Transport-CrossTenantHeadersStripped: AM3PEPF0000A798.eurprd04.prod.outlook.com X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id-Prvs: 9e9eda4f-6e36-4bcf-a533-08dbd6cef919 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: +c8nTZxlLYVcf/AwOwZzkUX8N2cDAxg0fPMUuW/00TOur4JKW3pIIMbJxRhEWQaAnLkDXmz4yZwlPVjjzn/o+Gdi640Wldu+5hP3arztqrGylj7P8JuDeTxRIHqGHJ5kmjkTEOBVb16fJQTGzMWm3iH5/38BM95Lnf9D2zZrP+E/jZAjLWrbaQ2i7fS4+dhuWzgegd1OZJ8kmjNfjXtib87KUyeCeGMXmBUQdQf0e+sFxODnC4VghV1V44Hp9v5Ov9JJSP7tdGtc7O1Z1E4QK0WSZEustuIIO2ooxgJc3OXQ4owDLnj9I/WOdS0np/KKE+N48nrSZnEKlCQ0cCBPEckydeEnQLE49CMwcvvWxiAs0iJ24yXAJ5ZRzck4JROpAyxT3F/6mg+wwrm3YYbOetLzZrXEXXhAyzUhSxTobJxYa9y1dxtRdvlEaMj0iXItxb6H86o8kVzcf3TXCEbC9phEB1DmmSCY/OfMAiGSyzrQUDy0CAAk6nVrB8fqTGf6gC8KYyeDvCOPlbQBoFtaDNRkGQj8e4zWfPFuBdWGuLjw/TwQOJ2+R9cgcgfyvN6cFL71Npxp+YwJqJSbouJl2oovlCH4mlopqm/teUyCyiMmKAIEefx6BZra1nuWmYL2bfSfTE9VzVnIx5GH1BeHeB8MfoocSvQVUMPFs3Qn9ibQrFrn2x4p94ykA11iU5LMdQh+bStvp/tuuYDZtTbVzaeEErTe9lAsOOJHhntuinf0bxqoa9j5iR5Zsie8s9l3nuMB7NfCkWDSwWbRsDy4rVRF3xXMpvTF3hauDJq68G5zJsfBpjwDUn+fJJNaEU0W X-Forefront-Antispam-Report: CIP:63.35.35.123; CTRY:IE; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:64aa7808-outbound-1.mta.getcheckrecipient.com; PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com; CAT:NONE; SFS:(13230031)(4636009)(346002)(136003)(396003)(39860400002)(376002)(230922051799003)(230273577357003)(230173577357003)(82310400011)(451199024)(64100799003)(1800799009)(186009)(46966006)(40470700004)(36840700001)(6916009)(40460700003)(2906002)(7696005)(81166007)(70586007)(2616005)(70206006)(1076003)(966005)(26005)(478600001)(54906003)(4326008)(36860700001)(82740400003)(47076005)(426003)(83380400001)(336012)(5660300002)(8936002)(40480700001)(8676002)(41300700001)(30864003)(316002)(36756003)(84970400001)(86362001); DIR:OUT; SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Oct 2023 09:27:52.8197 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9da52429-30ef-498f-db30-08dbd6cefec4 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d; Ip=[63.35.35.123]; Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: AM3PEPF0000A798.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB10078 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_NONE, KAM_SHORT, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_NONE, TXREP, UNPARSEABLE_RELAY autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780900331878004043 X-GMAIL-MSGID: 1780900331878004043 Implement the ACLE data and instruction prefetch functions[1] with the following signatures: 1. Data prefetch intrinsics: ---------------------------- void __pldx (/*constant*/ unsigned int /*access_kind*/, /*constant*/ unsigned int /*cache_level*/, /*constant*/ unsigned int /*retention_policy*/, void const volatile *addr); void __pld (void const volatile *addr); 2. Instruction prefetch intrinsics: ----------------------------------- void __plix (/*constant*/ unsigned int /*cache_level*/, /*constant*/ unsigned int /*retention_policy*/, void const volatile *addr); void __pli (void const volatile *addr); `__pldx' affords the programmer more fine-grained control over the data prefetch behavior than the analogous GCC builtin `__builtin_prefetch', and allows access to the "SLC" cache level. While `__builtin_prefetch' chooses both cache-level and retention policy automatically via the optional `locality' parameter, `__pldx' expects 2 (mandatory) arguments to explicitly define the desired cache-level and retention policies. `__plix' on the other hand, generates a code prefetch instruction and so extends functionality on aarch64 targets beyond that which is exposed by `builtin_prefetch'. `__pld' and `__pli' do prefetch of data and instructions, respectively, using default values for both cache-level and retention policies. Bootstrapped and tested on aarch64-none-linux-gnu. [1] https://arm-software.github.io/acle/main/acle.html#memory-prefetch-intrinsics gcc/ChangeLog: * config/aarch64/aarch64-builtins.cc: (AARCH64_PLD): New enum aarch64_builtins entry. (AARCH64_PLDX): Likewise. (AARCH64_PLI): Likewise. (AARCH64_PLIX): Likewise. (aarch64_init_prefetch_builtin): New. (aarch64_general_init_builtins): Call prefetch init function. (aarch64_expand_prefetch_builtin): New. (aarch64_general_expand_builtin): Add prefetch expansion. * config/aarch64/aarch64.md (UNSPEC_PLDX): New. (aarch64_pldx): New. gcc/testsuite/ChangeLog: * gcc.target/aarch64/builtin_pld_pli.c: New. --- gcc/config/aarch64/aarch64-builtins.cc | 160 ++++++++++++++++++ gcc/config/aarch64/aarch64.md | 12 ++ gcc/config/aarch64/arm_acle.h | 30 ++++ .../gcc.target/aarch64/builtin_pldx.c | 90 ++++++++++ 4 files changed, 292 insertions(+) create mode 100644 gcc/testsuite/gcc.target/aarch64/builtin_pldx.c diff --git a/gcc/config/aarch64/aarch64-builtins.cc b/gcc/config/aarch64/aarch64-builtins.cc index 04f59fd9a54..307e7617548 100644 --- a/gcc/config/aarch64/aarch64-builtins.cc +++ b/gcc/config/aarch64/aarch64-builtins.cc @@ -808,6 +808,10 @@ enum aarch64_builtins AARCH64_RBIT, AARCH64_RBITL, AARCH64_RBITLL, + AARCH64_PLD, + AARCH64_PLDX, + AARCH64_PLI, + AARCH64_PLIX, AARCH64_BUILTIN_MAX }; @@ -1798,6 +1802,33 @@ aarch64_init_rng_builtins (void) AARCH64_BUILTIN_RNG_RNDRRS); } +/* Add builtins for data and instrution prefetch. */ +static void +aarch64_init_prefetch_builtin (void) +{ +#define AARCH64_INIT_PREFETCH_BUILTIN(INDEX, N) \ + aarch64_builtin_decls[INDEX] = \ + aarch64_general_add_builtin ("__builtin_aarch64_" N, ftype, INDEX) + + tree ftype; + tree void_const_vol_ptr_type = build_type_variant (ptr_type_node, 1, 1); + + ftype = build_function_type_list (void_type_node, void_const_vol_ptr_type, + NULL); + AARCH64_INIT_PREFETCH_BUILTIN (AARCH64_PLD, "pld"); + AARCH64_INIT_PREFETCH_BUILTIN (AARCH64_PLI, "pli"); + + ftype = build_function_type_list (void_type_node, unsigned_type_node, + unsigned_type_node, unsigned_type_node, + void_const_vol_ptr_type, NULL); + AARCH64_INIT_PREFETCH_BUILTIN (AARCH64_PLDX, "pldx"); + + ftype = build_function_type_list (void_type_node, unsigned_type_node, + unsigned_type_node, void_const_vol_ptr_type, + NULL); + AARCH64_INIT_PREFETCH_BUILTIN (AARCH64_PLIX, "plix"); +} + /* Initialize the memory tagging extension (MTE) builtins. */ struct { @@ -2019,6 +2050,8 @@ aarch64_general_init_builtins (void) aarch64_init_rng_builtins (); aarch64_init_data_intrinsics (); + aarch64_init_prefetch_builtin (); + tree ftype_jcvt = build_function_type_list (intSI_type_node, double_type_node, NULL); aarch64_builtin_decls[AARCH64_JSCVT] @@ -2599,6 +2632,127 @@ aarch64_expand_rng_builtin (tree exp, rtx target, int fcode, int ignore) return target; } +/* Expand a prefetch builtin EXP. */ +void +aarch64_expand_prefetch_builtin (tree exp, int fcode) +{ + +#define EXPAND_CONST_INT(IN_IDX, OUT_IDX, ERRMSG) \ + if (TREE_CODE (args[IN_IDX]) != INTEGER_CST) \ + { \ + error_at (EXPR_LOCATION (exp), ERRMSG); \ + args[IN_IDX] = integer_zero_node; \ + } \ + ops[OUT_IDX] = expand_normal (args[IN_IDX]) + +#define WARN_INVALID(VAR, ERRMSG) \ + do { \ + warning_at (EXPR_LOCATION (exp), 0, ERRMSG); \ + VAR = 0; \ + } while (0) + + unsigned narg; + + tree args[4]; + rtx ops[4]; + int kind_id, level_id, rettn_id; + char prfop[11]; + + char kind_s[3][4] = {"PLD", "PST", "PLI"}; + char level_s[4][4] = {"L1", "L2", "L3", "SLC"}; + char rettn_s[2][5] = {"KEEP", "STRM"}; + + /* Each of the four prefetch builtins takes a different number of + arguments, but proceeds to call the PRFM insn which requires 4 + pieces of information to be fully defined. + + Specify the total number of arguments for each builtin and, where + one of these takes less than 4 arguments, set sensible defaults. */ + switch (fcode) + { + case AARCH64_PLDX: + kind_id = -1; + narg = 4; + break; + case AARCH64_PLIX: + kind_id = 2; + narg = 3; + break; + case AARCH64_PLI: + case AARCH64_PLD: + default: + kind_id = (fcode == AARCH64_PLD) ? 0 : 2; + level_id = 0; + rettn_id = 0; + narg = 1; + break; + } + + int addr_arg_index = narg - 1; + + /* Extract the correct number of arguments from our function call. */ + for (unsigned i = 0; i < narg; i++) + args[i] = CALL_EXPR_ARG (exp, i); + + /* Check address argument. */ + if (!(POINTER_TYPE_P (TREE_TYPE (args[addr_arg_index]))) + || (TREE_CODE (TREE_TYPE (TREE_TYPE (args[addr_arg_index]))) + != VOID_TYPE)) + error_at (EXPR_LOCATION (exp), "invalid address type specified;" + " void const volatile * required"); + + ops[3] = expand_expr (args[addr_arg_index], NULL_RTX, Pmode, EXPAND_NORMAL); + + /* Check arguments common to both pldx and plix. */ + if (fcode == AARCH64_PLDX || fcode == AARCH64_PLIX) + { + int cache_index = (fcode == AARCH64_PLIX) ? 0 : 1; + int policy_index = cache_index + 1; + + /* Cache level must be 0, 1, 2 or 3. */ + EXPAND_CONST_INT (cache_index, 1, + "Cache-level argument must be a constant"); + level_id = INTVAL (ops[1]); + if (level_id < 0 || level_id > 3) + WARN_INVALID (level_id, "invalid cache level selected; using zero"); + + /* Retention policy must be either zero or one. */ + EXPAND_CONST_INT (policy_index, 2, + "Retention policy argument must be a constant"); + rettn_id = INTVAL (ops[2]); + if (rettn_id != 0 && rettn_id != 1) + WARN_INVALID (rettn_id, "invalid retention policy selected; " + "using zero"); + } + + /* For PLDX, validate the access kind argument. */ + if (fcode == AARCH64_PLDX) + { + /* Argument 0 must be either zero or one. */ + EXPAND_CONST_INT (0, 0, "Access kind argument must be a constant"); + kind_id = INTVAL (ops[0]); + if (kind_id != 0 && kind_id != 1) + WARN_INVALID (kind_id, "invalid access kind argument; using zero"); + } + + sprintf (prfop, "%s%s%s", kind_s[kind_id], + level_s[level_id], + rettn_s[rettn_id]); + + rtx const_str = rtx_alloc (CONST_STRING); + PUT_CODE (const_str, CONST_STRING); + XSTR (const_str, 0) = xstrdup (prfop); + + class expand_operand exp_ops[2]; + + create_fixed_operand (&exp_ops[0], const_str); + create_address_operand (&exp_ops[1], ops[3]); + maybe_expand_insn (CODE_FOR_aarch64_pldx, 2, exp_ops); + + #undef EXPAND_CONST_INT + #undef WARN_INVALID +} + /* Expand an expression EXP that calls a MEMTAG built-in FCODE with result going to TARGET. */ static rtx @@ -2832,6 +2986,12 @@ aarch64_general_expand_builtin (unsigned int fcode, tree exp, rtx target, case AARCH64_BUILTIN_RNG_RNDR: case AARCH64_BUILTIN_RNG_RNDRRS: return aarch64_expand_rng_builtin (exp, target, fcode, ignore); + case AARCH64_PLD: + case AARCH64_PLDX: + case AARCH64_PLI: + case AARCH64_PLIX: + aarch64_expand_prefetch_builtin (exp, fcode); + return target; } if (fcode >= AARCH64_SIMD_BUILTIN_BASE && fcode <= AARCH64_SIMD_BUILTIN_MAX) diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 5bb8c772be8..7b1cc4c137b 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -281,6 +281,7 @@ UNSPEC_UPDATE_FFRT UNSPEC_RDFFR UNSPEC_WRFFR + UNSPEC_PLDX ;; Represents an SVE-style lane index, in which the indexing applies ;; within the containing 128-bit block. UNSPEC_SVE_LANE_SELECT @@ -844,6 +845,17 @@ [(set_attr "type" "load_4")] ) +(define_insn "aarch64_pldx" + [(unspec [(match_operand 0 "" "") + (match_operand:DI 1 "aarch64_prefetch_operand" "Dp")] UNSPEC_PLDX)] + "" + { + operands[1] = gen_rtx_MEM (DImode, operands[1]); + return "prfm\\t%0, %1"; + } + [(set_attr "type" "load_4")] +) + (define_insn "trap" [(trap_if (const_int 1) (const_int 8))] "" diff --git a/gcc/config/aarch64/arm_acle.h b/gcc/config/aarch64/arm_acle.h index 7599a32301d..40e5aa61be2 100644 --- a/gcc/config/aarch64/arm_acle.h +++ b/gcc/config/aarch64/arm_acle.h @@ -78,6 +78,36 @@ _GCC_ARM_ACLE_DATA_FN (revll, bswap64, uint64_t, uint64_t) #undef _GCC_ARM_ACLE_DATA_FN +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__pld (void const volatile *__addr) +{ + return __builtin_aarch64_pld (__addr); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__pli (void const volatile *__addr) +{ + return __builtin_aarch64_pli (__addr); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__plix (unsigned int __cache, unsigned int __rettn, + void const volatile *__addr) +{ + return __builtin_aarch64_plix (__cache, __rettn, __addr); +} + +__extension__ extern __inline void +__attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) +__pldx (unsigned int __access, unsigned int __cache, unsigned int __rettn, + void const volatile *__addr) +{ + return __builtin_aarch64_pldx (__access, __cache, __rettn, __addr); +} + __extension__ extern __inline unsigned long __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) __revl (unsigned long __value) diff --git a/gcc/testsuite/gcc.target/aarch64/builtin_pldx.c b/gcc/testsuite/gcc.target/aarch64/builtin_pldx.c new file mode 100644 index 00000000000..9d52a9e5a8a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/builtin_pldx.c @@ -0,0 +1,90 @@ +/* { dg-do compile } */ +/* { dg-options "-march=armv8-a -O2" } */ + +#include + +/* Check that we can generate the immediate-offset addressing + mode for PRFM. */ + +/* Access kind specifiers. */ +#define PLD 0 +#define PST 1 +/* Cache levels. */ +#define L1 0 +#define L2 1 +#define L3 2 +#define SLC 3 +/* Retention policies. */ +#define KEEP 0 +#define STRM 1 + +void +prefetch_for_read_write (void *a) +{ + __pldx (PLD, L1, KEEP, a); + __pldx (PLD, L1, STRM, a); + __pldx (PLD, L2, KEEP, a); + __pldx (PLD, L2, STRM, a); + __pldx (PLD, L3, KEEP, a); + __pldx (PLD, L3, STRM, a); + __pldx (PLD, SLC, KEEP, a); + __pldx (PLD, SLC, STRM, a); + __pldx (PST, L1, KEEP, a); + __pldx (PST, L1, STRM, a); + __pldx (PST, L2, KEEP, a); + __pldx (PST, L2, STRM, a); + __pldx (PST, L3, KEEP, a); + __pldx (PST, L3, STRM, a); + __pldx (PST, SLC, KEEP, a); + __pldx (PST, SLC, STRM, a); +} + +/* { dg-final { scan-assembler "prfm\tPLDL1KEEP, \\\[x\[0-9\]+\\\]" } } */ +/* { dg-final { scan-assembler "prfm\tPLDL1STRM, \\\[x\[0-9\]+\\\]" } } */ +/* { dg-final { scan-assembler "prfm\tPLDL2KEEP, \\\[x\[0-9\]+\\\]" } } */ +/* { dg-final { scan-assembler "prfm\tPLDL2STRM, \\\[x\[0-9\]+\\\]" } } */ +/* { dg-final { scan-assembler "prfm\tPLDL3KEEP, \\\[x\[0-9\]+\\\]" } } */ +/* { dg-final { scan-assembler "prfm\tPLDL3STRM, \\\[x\[0-9\]+\\\]" } } */ +/* { dg-final { scan-assembler "prfm\tPLDSLCKEEP, \\\[x\[0-9\]+\\\]" } } */ +/* { dg-final { scan-assembler "prfm\tPLDSLCSTRM, \\\[x\[0-9\]+\\\]" } } +/* { dg-final { scan-assembler "prfm\tPSTL1KEEP, \\\[x\[0-9\]+\\\]" } } */ +/* { dg-final { scan-assembler "prfm\tPSTL1STRM, \\\[x\[0-9\]+\\\]" } } */ +/* { dg-final { scan-assembler "prfm\tPSTL2KEEP, \\\[x\[0-9\]+\\\]" } } */ +/* { dg-final { scan-assembler "prfm\tPSTL2STRM, \\\[x\[0-9\]+\\\]" } } */ +/* { dg-final { scan-assembler "prfm\tPSTL3KEEP, \\\[x\[0-9\]+\\\]" } } */ +/* { dg-final { scan-assembler "prfm\tPSTL3STRM, \\\[x\[0-9\]+\\\]" } } */ +/* { dg-final { scan-assembler "prfm\tPSTSLCKEEP, \\\[x\[0-9\]+\\\]" } } */ +/* { dg-final { scan-assembler "prfm\tPSTSLCSTRM, \\\[x\[0-9\]+\\\]" } } */ + +void +prefetch_simple (void *a) +{ + __pld (a); + __pli (a); +} + +/* { dg-final { scan-assembler "prfm\tPLDL1KEEP, \\\[x\[0-9\]+\\\]" } } */ +/* { dg-final { scan-assembler "prfm\tPLIL1KEEP, \\\[x\[0-9\]+\\\]" } } */ + +void +prefetch_instructions (void *a) +{ + __plix (L1, KEEP, a); + __plix (L1, STRM, a); + __plix (L2, KEEP, a); + __plix (L2, STRM, a); + __plix (L3, KEEP, a); + __plix (L3, STRM, a); + __plix (SLC, KEEP, a); + __plix (SLC, STRM, a); +} + +/* { dg-final { scan-assembler "prfm\tPLIL1KEEP, \\\[x\[0-9\]+\\\]" } } */ +/* { dg-final { scan-assembler "prfm\tPLIL1STRM, \\\[x\[0-9\]+\\\]" } } */ +/* { dg-final { scan-assembler "prfm\tPLIL2KEEP, \\\[x\[0-9\]+\\\]" } } */ +/* { dg-final { scan-assembler "prfm\tPLIL2STRM, \\\[x\[0-9\]+\\\]" } } */ +/* { dg-final { scan-assembler "prfm\tPLIL3KEEP, \\\[x\[0-9\]+\\\]" } } */ +/* { dg-final { scan-assembler "prfm\tPLIL3STRM, \\\[x\[0-9\]+\\\]" } } */ +/* { dg-final { scan-assembler "prfm\tPLISLCKEEP, \\\[x\[0-9\]+\\\]" } } */ +/* { dg-final { scan-assembler "prfm\tPLISLCSTRM, \\\[x\[0-9\]+\\\]" } } */ +