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Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 01/21] arm64: PCI: Migrate ACPI related functions to pci-acpi.c Date: Thu, 26 Oct 2023 01:53:24 +0530 Message-Id: <20231025202344.581132-2-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=2.7 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Level: ** X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Wed, 25 Oct 2023 13:24:40 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780760428850266905 X-GMAIL-MSGID: 1780760428850266905 The functions defined in arm64 for ACPI support are required for RISC-V also. To avoid duplication, move these functions to common location. Signed-off-by: Sunil V L Acked-by: Bjorn Helgaas Acked-by: Catalin Marinas --- arch/arm64/kernel/pci.c | 191 ---------------------------------------- drivers/pci/pci-acpi.c | 182 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 182 insertions(+), 191 deletions(-) diff --git a/arch/arm64/kernel/pci.c b/arch/arm64/kernel/pci.c index f872c57e9909..fd9a7bed83ce 100644 --- a/arch/arm64/kernel/pci.c +++ b/arch/arm64/kernel/pci.c @@ -6,28 +6,7 @@ * Copyright (C) 2014 ARM Ltd. */ -#include -#include -#include -#include -#include #include -#include -#include -#include - -#ifdef CONFIG_ACPI -/* - * Try to assign the IRQ number when probing a new device - */ -int pcibios_alloc_irq(struct pci_dev *dev) -{ - if (!acpi_disabled) - acpi_pci_irq_enable(dev); - - return 0; -} -#endif /* * raw_pci_read/write - Platform-specific PCI config space access. @@ -61,173 +40,3 @@ int pcibus_to_node(struct pci_bus *bus) EXPORT_SYMBOL(pcibus_to_node); #endif - -#ifdef CONFIG_ACPI - -struct acpi_pci_generic_root_info { - struct acpi_pci_root_info common; - struct pci_config_window *cfg; /* config space mapping */ -}; - -int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) -{ - struct pci_config_window *cfg = bus->sysdata; - struct acpi_device *adev = to_acpi_device(cfg->parent); - struct acpi_pci_root *root = acpi_driver_data(adev); - - return root->segment; -} - -int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) -{ - struct pci_config_window *cfg; - struct acpi_device *adev; - struct device *bus_dev; - - if (acpi_disabled) - return 0; - - cfg = bridge->bus->sysdata; - - /* - * On Hyper-V there is no corresponding ACPI device for a root bridge, - * therefore ->parent is set as NULL by the driver. And set 'adev' as - * NULL in this case because there is no proper ACPI device. - */ - if (!cfg->parent) - adev = NULL; - else - adev = to_acpi_device(cfg->parent); - - bus_dev = &bridge->bus->dev; - - ACPI_COMPANION_SET(&bridge->dev, adev); - set_dev_node(bus_dev, acpi_get_node(acpi_device_handle(adev))); - - return 0; -} - -static int pci_acpi_root_prepare_resources(struct acpi_pci_root_info *ci) -{ - struct resource_entry *entry, *tmp; - int status; - - status = acpi_pci_probe_root_resources(ci); - resource_list_for_each_entry_safe(entry, tmp, &ci->resources) { - if (!(entry->res->flags & IORESOURCE_WINDOW)) - resource_list_destroy_entry(entry); - } - return status; -} - -/* - * Lookup the bus range for the domain in MCFG, and set up config space - * mapping. - */ -static struct pci_config_window * -pci_acpi_setup_ecam_mapping(struct acpi_pci_root *root) -{ - struct device *dev = &root->device->dev; - struct resource *bus_res = &root->secondary; - u16 seg = root->segment; - const struct pci_ecam_ops *ecam_ops; - struct resource cfgres; - struct acpi_device *adev; - struct pci_config_window *cfg; - int ret; - - ret = pci_mcfg_lookup(root, &cfgres, &ecam_ops); - if (ret) { - dev_err(dev, "%04x:%pR ECAM region not found\n", seg, bus_res); - return NULL; - } - - adev = acpi_resource_consumer(&cfgres); - if (adev) - dev_info(dev, "ECAM area %pR reserved by %s\n", &cfgres, - dev_name(&adev->dev)); - else - dev_warn(dev, FW_BUG "ECAM area %pR not reserved in ACPI namespace\n", - &cfgres); - - cfg = pci_ecam_create(dev, &cfgres, bus_res, ecam_ops); - if (IS_ERR(cfg)) { - dev_err(dev, "%04x:%pR error %ld mapping ECAM\n", seg, bus_res, - PTR_ERR(cfg)); - return NULL; - } - - return cfg; -} - -/* release_info: free resources allocated by init_info */ -static void pci_acpi_generic_release_info(struct acpi_pci_root_info *ci) -{ - struct acpi_pci_generic_root_info *ri; - - ri = container_of(ci, struct acpi_pci_generic_root_info, common); - pci_ecam_free(ri->cfg); - kfree(ci->ops); - kfree(ri); -} - -/* Interface called from ACPI code to setup PCI host controller */ -struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) -{ - struct acpi_pci_generic_root_info *ri; - struct pci_bus *bus, *child; - struct acpi_pci_root_ops *root_ops; - struct pci_host_bridge *host; - - ri = kzalloc(sizeof(*ri), GFP_KERNEL); - if (!ri) - return NULL; - - root_ops = kzalloc(sizeof(*root_ops), GFP_KERNEL); - if (!root_ops) { - kfree(ri); - return NULL; - } - - ri->cfg = pci_acpi_setup_ecam_mapping(root); - if (!ri->cfg) { - kfree(ri); - kfree(root_ops); - return NULL; - } - - root_ops->release_info = pci_acpi_generic_release_info; - root_ops->prepare_resources = pci_acpi_root_prepare_resources; - root_ops->pci_ops = (struct pci_ops *)&ri->cfg->ops->pci_ops; - bus = acpi_pci_root_create(root, root_ops, &ri->common, ri->cfg); - if (!bus) - return NULL; - - /* If we must preserve the resource configuration, claim now */ - host = pci_find_host_bridge(bus); - if (host->preserve_config) - pci_bus_claim_resources(bus); - - /* - * Assign whatever was left unassigned. If we didn't claim above, - * this will reassign everything. - */ - pci_assign_unassigned_root_bus_resources(bus); - - list_for_each_entry(child, &bus->children, node) - pcie_bus_configure_settings(child); - - return bus; -} - -void pcibios_add_bus(struct pci_bus *bus) -{ - acpi_pci_add_bus(bus); -} - -void pcibios_remove_bus(struct pci_bus *bus) -{ - acpi_pci_remove_bus(bus); -} - -#endif diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index a05350a4e49c..58497b25d2ab 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -1518,3 +1519,184 @@ static int __init acpi_pci_init(void) return 0; } arch_initcall(acpi_pci_init); + +#if defined(CONFIG_ARM64) + +/* + * Try to assign the IRQ number when probing a new device + */ +int pcibios_alloc_irq(struct pci_dev *dev) +{ + if (!acpi_disabled) + acpi_pci_irq_enable(dev); + + return 0; +} + +struct acpi_pci_generic_root_info { + struct acpi_pci_root_info common; + struct pci_config_window *cfg; /* config space mapping */ +}; + +int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) +{ + struct pci_config_window *cfg = bus->sysdata; + struct acpi_device *adev = to_acpi_device(cfg->parent); + struct acpi_pci_root *root = acpi_driver_data(adev); + + return root->segment; +} + +int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge) +{ + struct pci_config_window *cfg; + struct acpi_device *adev; + struct device *bus_dev; + + if (acpi_disabled) + return 0; + + cfg = bridge->bus->sysdata; + + /* + * On Hyper-V there is no corresponding ACPI device for a root bridge, + * therefore ->parent is set as NULL by the driver. And set 'adev' as + * NULL in this case because there is no proper ACPI device. + */ + if (!cfg->parent) + adev = NULL; + else + adev = to_acpi_device(cfg->parent); + + bus_dev = &bridge->bus->dev; + + ACPI_COMPANION_SET(&bridge->dev, adev); + set_dev_node(bus_dev, acpi_get_node(acpi_device_handle(adev))); + + return 0; +} + +static int pci_acpi_root_prepare_resources(struct acpi_pci_root_info *ci) +{ + struct resource_entry *entry, *tmp; + int status; + + status = acpi_pci_probe_root_resources(ci); + resource_list_for_each_entry_safe(entry, tmp, &ci->resources) { + if (!(entry->res->flags & IORESOURCE_WINDOW)) + resource_list_destroy_entry(entry); + } + return status; +} + +/* + * Lookup the bus range for the domain in MCFG, and set up config space + * mapping. + */ +static struct pci_config_window * +pci_acpi_setup_ecam_mapping(struct acpi_pci_root *root) +{ + struct device *dev = &root->device->dev; + struct resource *bus_res = &root->secondary; + u16 seg = root->segment; + const struct pci_ecam_ops *ecam_ops; + struct resource cfgres; + struct acpi_device *adev; + struct pci_config_window *cfg; + int ret; + + ret = pci_mcfg_lookup(root, &cfgres, &ecam_ops); + if (ret) { + dev_err(dev, "%04x:%pR ECAM region not found\n", seg, bus_res); + return NULL; + } + + adev = acpi_resource_consumer(&cfgres); + if (adev) + dev_info(dev, "ECAM area %pR reserved by %s\n", &cfgres, + dev_name(&adev->dev)); + else + dev_warn(dev, FW_BUG "ECAM area %pR not reserved in ACPI namespace\n", + &cfgres); + + cfg = pci_ecam_create(dev, &cfgres, bus_res, ecam_ops); + if (IS_ERR(cfg)) { + dev_err(dev, "%04x:%pR error %ld mapping ECAM\n", seg, bus_res, + PTR_ERR(cfg)); + return NULL; + } + + return cfg; +} + +/* release_info: free resources allocated by init_info */ +static void pci_acpi_generic_release_info(struct acpi_pci_root_info *ci) +{ + struct acpi_pci_generic_root_info *ri; + + ri = container_of(ci, struct acpi_pci_generic_root_info, common); + pci_ecam_free(ri->cfg); + kfree(ci->ops); + kfree(ri); +} + +/* Interface called from ACPI code to setup PCI host controller */ +struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) +{ + struct acpi_pci_generic_root_info *ri; + struct pci_bus *bus, *child; + struct acpi_pci_root_ops *root_ops; + struct pci_host_bridge *host; + + ri = kzalloc(sizeof(*ri), GFP_KERNEL); + if (!ri) + return NULL; + + root_ops = kzalloc(sizeof(*root_ops), GFP_KERNEL); + if (!root_ops) { + kfree(ri); + return NULL; + } + + ri->cfg = pci_acpi_setup_ecam_mapping(root); + if (!ri->cfg) { + kfree(ri); + kfree(root_ops); + return NULL; + } + + root_ops->release_info = pci_acpi_generic_release_info; + root_ops->prepare_resources = pci_acpi_root_prepare_resources; + root_ops->pci_ops = (struct pci_ops *)&ri->cfg->ops->pci_ops; + bus = acpi_pci_root_create(root, root_ops, &ri->common, ri->cfg); + if (!bus) + return NULL; + + /* If we must preserve the resource configuration, claim now */ + host = pci_find_host_bridge(bus); + if (host->preserve_config) + pci_bus_claim_resources(bus); + + /* + * Assign whatever was left unassigned. If we didn't claim above, + * this will reassign everything. + */ + pci_assign_unassigned_root_bus_resources(bus); + + list_for_each_entry(child, &bus->children, node) + pcie_bus_configure_settings(child); + + return bus; +} + +void pcibios_add_bus(struct pci_bus *bus) +{ + acpi_pci_add_bus(bus); +} + +void pcibios_remove_bus(struct pci_bus *bus) +{ + acpi_pci_remove_bus(bus); +} + +#endif From patchwork Wed Oct 25 20:23:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 158272 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp217495vqb; Wed, 25 Oct 2023 13:24:39 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFXJMOCsfeIDumaFXAgltx+FUOtm05ivfOH3EWh30/Di1W7K2KNiO8/qbIhmEaPBUPOfa0T X-Received: by 2002:a25:50c7:0:b0:d9a:e337:b6a with SMTP id e190-20020a2550c7000000b00d9ae3370b6amr15020267ybb.61.1698265478933; Wed, 25 Oct 2023 13:24:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698265478; cv=none; d=google.com; s=arc-20160816; b=m50Y/h5lSXjruKdeienysPFnicIYmENISYWJ9eiCwHLmKyoSCq1RVSFouYoEmZZkPr g6IvDcJpJS1Q/CGn0ZZd7R5p5c8EoIbgpilYG/W/NDroOjAD7jlo3Cpvuum1NQuqIkWZ s3tbdVCo9tvDupPBxDX6xeyNupJ3Iiu5XcsxNx0Oetbl1xC2uZlPiVkTeNEzKv7xxpEy zaBAqp/L2QbIR10SPxF8dH0D85ldcm2NCI0fXX/GoPlYuNWcNauDohBxj9eJMpktwSVL nNLnV4JvbhMFNmfH3r6uO61MU35Pbc3kW7lSp1kGqOyxmySn2cKB/yf5Qfjsg1GVWWYG 8UlQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=il/rbbBih8ETNOL/0gi7mQnwMr9PQruIC4HVqlbsTs0=; fh=/fEAwM0ftwV2z3MN/iSYq1lv8IFPZ2fY8Kg8RoFcxjU=; b=1Jwsz5SSNwYmPnq4KBijloa3QZYX0KocTaPSp8yhBdihZ+c0Mo+Mvox5H+R5aEW2Nx aZjI8GkRHCtN6KCwgP6ne7i94Yo7FMTFL/cytVkbNT/KGbYZW4e8u6WmcAgrKdrm+bYy c6tcNwOWDbt2J2MibTCC4E7gPHbd+0t6jxmdq2u3asqu3my/6GwwfnmyLTBYbg80OcMk whlXzwyZqwyXASwPg43b5W8zVmb/EXbohHmJtr59P5+yxKbCnywaXXGzB+vWgwuRjFUR vgCEXoz5qASlbBI5ZDQYfOavja6ISV96K1EyK+016me5IaEDDwfX95PIgXhnj3pAJV6g R20g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=cpHqw6Ko; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from snail.vger.email (snail.vger.email. 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Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 02/21] RISC-V: ACPI: Implement PCI related functionality Date: Thu, 26 Oct 2023 01:53:25 +0530 Message-Id: <20231025202344.581132-3-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=1.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Level: * X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 25 Oct 2023 13:24:36 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780760423001955165 X-GMAIL-MSGID: 1780760423001955165 Replace the dummy implementation for PCI related functions with actual implementation. This needs ECAM and MCFG CONFIG options to be enabled for RISC-V. Signed-off-by: Sunil V L --- arch/riscv/Kconfig | 2 ++ arch/riscv/kernel/acpi.c | 31 ++++++++++++++----------------- drivers/pci/pci-acpi.c | 2 +- 3 files changed, 17 insertions(+), 18 deletions(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index c3c3f3562082..8c105a151e12 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -13,6 +13,7 @@ config 32BIT config RISCV def_bool y select ACPI_GENERIC_GSI if ACPI + select ACPI_MCFG if (ACPI && PCI) select ACPI_REDUCED_HARDWARE_ONLY if ACPI select ARCH_DMA_DEFAULT_COHERENT select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION @@ -152,6 +153,7 @@ config RISCV select OF_EARLY_FLATTREE select OF_IRQ select PCI_DOMAINS_GENERIC if PCI + select PCI_ECAM if (ACPI && PCI) select PCI_MSI if PCI select RISCV_ALTERNATIVE if !XIP_KERNEL select RISCV_APLIC diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c index e619edc8b0cc..41aa77c8484b 100644 --- a/arch/riscv/kernel/acpi.c +++ b/arch/riscv/kernel/acpi.c @@ -306,29 +306,26 @@ void __iomem *acpi_os_ioremap(acpi_physical_address phys, acpi_size size) #ifdef CONFIG_PCI /* - * These interfaces are defined just to enable building ACPI core. - * TODO: Update it with actual implementation when external interrupt - * controller support is added in RISC-V ACPI. + * raw_pci_read/write - Platform-specific PCI config space access. */ -int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, - int reg, int len, u32 *val) +int raw_pci_read(unsigned int domain, unsigned int bus, + unsigned int devfn, int reg, int len, u32 *val) { - return PCIBIOS_DEVICE_NOT_FOUND; -} + struct pci_bus *b = pci_find_bus(domain, bus); -int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, - int reg, int len, u32 val) -{ - return PCIBIOS_DEVICE_NOT_FOUND; + if (!b) + return PCIBIOS_DEVICE_NOT_FOUND; + return b->ops->read(b, devfn, reg, len, val); } -int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) +int raw_pci_write(unsigned int domain, unsigned int bus, + unsigned int devfn, int reg, int len, u32 val) { - return -1; -} + struct pci_bus *b = pci_find_bus(domain, bus); -struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) -{ - return NULL; + if (!b) + return PCIBIOS_DEVICE_NOT_FOUND; + return b->ops->write(b, devfn, reg, len, val); } + #endif /* CONFIG_PCI */ diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index 58497b25d2ab..c8c3369fd69f 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -1520,7 +1520,7 @@ static int __init acpi_pci_init(void) } arch_initcall(acpi_pci_init); -#if defined(CONFIG_ARM64) +#if defined(CONFIG_ARM64) || defined(CONFIG_RISCV) /* * Try to assign the IRQ number when probing a new device From patchwork Wed Oct 25 20:23:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 158275 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp217645vqb; Wed, 25 Oct 2023 13:25:00 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGYdxARf54X9gyOzMOB9Ccz3T2rEwDIjBWsrLamklvf3MndAedMd2zngufgSraQHdOHkQGz X-Received: by 2002:a05:6870:1d07:b0:1e9:94c1:9179 with SMTP id pa7-20020a0568701d0700b001e994c19179mr18575294oab.21.1698265500712; Wed, 25 Oct 2023 13:25:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698265500; cv=none; d=google.com; s=arc-20160816; b=HLGMbfOJjaA3RidJ4yqVKF3HfkxV6xezc6Xa/T7Ioqxz9Txq0bVlGY/eZuCZJUT0Ks o54WOhh4XYDpa9iXqKOOhpe46m5xzMG9zzVMA4nk4nLSiqA/rwL4AJVem6SGFMVpAMBZ Kg8XQ1FHa8gNz6ZaNZsLncoD3rv0m3zyg4FKHAeMWj/7FRZCvpzckHaKwHXefbhaLc5y ktpnUX6Ce6lt5AnxIfg2JlExgAI8ZaEFrAYmWYZQKFPh/iFghJFmO6rQuwnMbGDiScqF maHSSnH9PA3U8i8QJc3A7i8Xviq2JeesqefyKeVQgo76l5R3IzqTkqd3HA2l4H7krCiW Pgww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=W8oe0TQ1+zZd/3zKJQAEE+us/MvQWSBihayeSKyJW3A=; fh=/fEAwM0ftwV2z3MN/iSYq1lv8IFPZ2fY8Kg8RoFcxjU=; b=thYMAiDL2E+Gtft530xxyM4csC+dARcNoSpSO3K9ByeTnUUeI+9pAKqnLNGo6NcxaS gqLQM03XEFhcPyBkTdttSVK2kPMdVKZ5MiK7qS+xGJVJt6ktu4MNOaMOFl7LSw7X9rx4 Hf/corUuTgVRwSZW7+fkzvzNqDqs3n1Ybeav/V6ahy5+anRBqQ5J+nq/bbcuU7EbmGut U4q0RSrNKjrgjt3wByzJ3DnkHonHrk/ME179O8bdq+zJFkDCjlYR0o/SdHRqxDQqNBXi Y6dS87ywvkze5Vtpij8Kd5OWBl1Xf5NqD214ErKs0Z19f0fTL0CHX4w/mobVGfgNv3Mw 2gpw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=B2QZEsvN; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from agentk.vger.email (agentk.vger.email. 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Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 03/21] ACPI: Kconfig: Introduce new option to support deferred GSI probe Date: Thu, 26 Oct 2023 01:53:26 +0530 Message-Id: <20231025202344.581132-4-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=2.7 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Level: ** X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Wed, 25 Oct 2023 13:24:58 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780760445921872447 X-GMAIL-MSGID: 1780760445921872447 On some architectures like RISC-V, the interrupt controllers for Global System Interrupts (GSI) are not probed early during boot. So, the device drivers which need to register their GSI, need to be deferred until the actual interrupt controller driver is probed. To reduce the impact of such change, add a new CONFIG option which can be set only by the architecture which needs deferred GSI probing. Signed-off-by: Sunil V L --- drivers/acpi/Kconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig index cee82b473dc5..4399e793f1d2 100644 --- a/drivers/acpi/Kconfig +++ b/drivers/acpi/Kconfig @@ -51,6 +51,9 @@ config ARCH_MIGHT_HAVE_ACPI_PDC config ACPI_GENERIC_GSI bool +config ARCH_ACPI_DEFERRED_GSI + bool + config ACPI_SYSTEM_POWER_STATES_SUPPORT bool From patchwork Wed Oct 25 20:23:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 158274 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp217631vqb; Wed, 25 Oct 2023 13:24:58 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF4zItkr0zJ/lsI+W+0DiXDa7C8IuNYcv6gW7MT/nUhbnPyTSpdsbqp97dqCgN1ficVrQnT X-Received: by 2002:a25:5007:0:b0:d9c:7c97:7fcd with SMTP id e7-20020a255007000000b00d9c7c977fcdmr14558826ybb.27.1698265498176; Wed, 25 Oct 2023 13:24:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698265498; cv=none; d=google.com; s=arc-20160816; b=x4pIHD4yXLye1ziRv8Tg1gbD6ltmpC7wqzH66CCeZ+V8nJwsgIdaeP3g56/z8qV4FQ xzcAK1FqBM2JTB4akRlXWBkpk2R7Efg8RNa9OXNLI3nq4g4psIsQByk01sCuZncwGM+r yOv+mDYI6fGo7/jKDmUfbzmP/lB9u6LMRFIpIm8BYdvLnLS9Xj3o7/KtWkCfE1VFPnZw +9TeD46CRcF8WW8IfkTkkQlm5V0qKpHcjIfy3dkuJuNB4DH0tkMi/Lkjq18G8xvE64f5 fn2ObLIPWizfvCuNtG+VK9psGFAH72eEi/MWC400wYCDzRH/QAK6I4ywe6bY7pWlVGUu vp6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=6XsFHpyMSXpsQo/vHxUfuExbd7P0HKVdbzIKlbRfdpg=; fh=/fEAwM0ftwV2z3MN/iSYq1lv8IFPZ2fY8Kg8RoFcxjU=; b=Xe53cCp9XtvAdD0THKJgsikeIdg9Bkuz5BziAiDF2agLkJR8K7rtSmKGXeelW6gr0N J4H0ZUvllDo6ROLJN9fwaLOOdSpz7bp9MWD8YOz8RgatYv95GYstOSOdVu0Sq87jvZ7H vRkysPqoptbG2c5d4v1RWvpcmJS4F8pCGV/EdE9MqP58uIQE3bGLUtlXxi1cPGX0IANX GwTYtQlVXd2eOKnti2R6a4/iVVo9dU1bYY9B1db8REeYVZDPSWJJMICvhQCCGF9Bf9b/ ahzvdzBh8QkXbWqHBZ02+X864DfdmQgr7RL2NoZO33QW4DQ9IDMN2meAvvhtntSfpIDN J6AA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=IFtzf0U2; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from lipwig.vger.email (lipwig.vger.email. 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Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 04/21] ACPI: irq: Add support for deferred probe in acpi_register_gsi() Date: Thu, 26 Oct 2023 01:53:27 +0530 Message-Id: <20231025202344.581132-5-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=2.7 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Level: ** X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Wed, 25 Oct 2023 13:24:55 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780760443320310517 X-GMAIL-MSGID: 1780760443320310517 The chip which provides the GSI support may not be initialized at the time of acpi_register_gsi(). Return -EPROBE_DEFER to support deferred probing similar to acpi_irq_get(). Signed-off-by: Sunil V L --- drivers/acpi/irq.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/drivers/acpi/irq.c b/drivers/acpi/irq.c index 1687483ff319..c06cfc9725cb 100644 --- a/drivers/acpi/irq.c +++ b/drivers/acpi/irq.c @@ -51,19 +51,23 @@ EXPORT_SYMBOL_GPL(acpi_gsi_to_irq); * @polarity: polarity of the GSI to be mapped * * Returns: a valid linux IRQ number on success + * -EPROBE_DEFER if irqdomain is not available. * -EINVAL on failure */ int acpi_register_gsi(struct device *dev, u32 gsi, int trigger, int polarity) { + struct irq_domain *domain; struct irq_fwspec fwspec; unsigned int irq; fwspec.fwnode = acpi_get_gsi_domain_id(gsi); - if (WARN_ON(!fwspec.fwnode)) { - pr_warn("GSI: No registered irqchip, giving up\n"); - return -EINVAL; - } + if (!fwspec.fwnode) + return -EPROBE_DEFER; + + domain = irq_find_matching_fwnode(fwspec.fwnode, DOMAIN_BUS_ANY); + if (!domain) + return -EPROBE_DEFER; fwspec.param[0] = gsi; fwspec.param[1] = acpi_dev_get_irq_type(trigger, polarity); From patchwork Wed Oct 25 20:23:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 158276 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp217748vqb; Wed, 25 Oct 2023 13:25:11 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGbYbxXpltIuJ/zXQ+yUzrC71CQB2N4rP1zL7p+Uzsrz/64u+ogejF6VEWj2n8V/Z3/ulXC X-Received: by 2002:a81:4cc2:0:b0:59b:cd92:779f with SMTP id z185-20020a814cc2000000b0059bcd92779fmr1271002ywa.6.1698265510861; Wed, 25 Oct 2023 13:25:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698265510; cv=none; d=google.com; s=arc-20160816; b=YMtpjTw0OZy/Np+zMpoqbu8REq72jA/Rz9ga50sSdjzFCFk06uvWQcGQWyzxXqKqy1 iRsBLoKUmsDu5jLnWdWweHOpBKzBLp2zpimCCz+F+ip9mE2nO95bNh6IJEzCy0LzS+5U +XJsJHhVixDkNM31/dGjR9qhObPcMK9Jfaj34rqkNClPWuCIBz/hBZpXWN7gSmNsDmIB Gojj9v5vxyZdW+8LCmXhGMn5tKtfcPwhuHCvEaAw2rut3ock3X9FwJSOysRHlKyrq2aN tA5biIbqnJXyMY9KToRodZXThq1gUyxZWAxGOpmylcl+V5L3AqsPACD8eO7lAJRBRcPk QYjg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=J8S/JDCmwBJX/s4tcuif01AJjqTYAtUjVSzvHHCYv3Q=; fh=/fEAwM0ftwV2z3MN/iSYq1lv8IFPZ2fY8Kg8RoFcxjU=; b=V9f2+SpDyponSbBoUWQsHyVLR7WtWJe9Atyt5p2JnjnW6gkXUDvjR+kjZWSPq19rQ6 smSe6MPHF20v9Od6nOIptUXGiTuhpGQDYe4Y1IK+Y3ghV7YgFVzLAFCPPJwo0DADavTF 2P8YLMDy+WOL099aUuT3NGb3poFIShHOIBQ71sJYnA9m56Sy8jIPEEjjPBnqCQRJ6nLZ PKZU9SLQeyyakdHDw+G4f4S6vWW7qtS1KvmfRBTqJuC2ENVQFtCfNyvwxL/zl5v7zz7D MHow/6Nk4c/ZzaMzXVZ2TKMq+HePNCURPELem29pJUlPmxVxR+ArCZfODr2bmjo3+CWg Xp8w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=nNqvGjA6; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from lipwig.vger.email (lipwig.vger.email. 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Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 05/21] pnp.h: Return -EPROBE_DEFER for disabled IRQ resource in pnp_irq() Date: Thu, 26 Oct 2023 01:53:28 +0530 Message-Id: <20231025202344.581132-6-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=2.7 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Level: ** X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Wed, 25 Oct 2023 13:25:08 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780760456161281915 X-GMAIL-MSGID: 1780760456161281915 To support deferred PNP driver probe, pnp_irq() must return -EPROBE_DEFER so that the device driver can do deferred probe if the interrupt controller is not probed early. Signed-off-by: Sunil V L --- include/linux/pnp.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/include/linux/pnp.h b/include/linux/pnp.h index c2a7cfbca713..21cf833789fb 100644 --- a/include/linux/pnp.h +++ b/include/linux/pnp.h @@ -147,12 +147,18 @@ static inline resource_size_t pnp_mem_len(struct pnp_dev *dev, } -static inline resource_size_t pnp_irq(struct pnp_dev *dev, unsigned int bar) +static inline int pnp_irq(struct pnp_dev *dev, unsigned int bar) { struct resource *res = pnp_get_resource(dev, IORESOURCE_IRQ, bar); - if (pnp_resource_valid(res)) + if (pnp_resource_valid(res)) { +#if IS_ENABLED(CONFIG_ARCH_ACPI_DEFERRED_GSI) + if (!pnp_resource_enabled(res)) + return -EPROBE_DEFER; +#endif + return res->start; + } return -1; } From patchwork Wed Oct 25 20:23:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 158277 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp217788vqb; Wed, 25 Oct 2023 13:25:15 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHqOVr1mZlnWUMaoZ7cX1Woif5zcJxtVBnrIj7neWux5Bv2h+BgaPHNYFBaYBiSZXrPdMtk X-Received: by 2002:a81:4c82:0:b0:5a7:fcad:e865 with SMTP id z124-20020a814c82000000b005a7fcade865mr1308989ywa.2.1698265515279; Wed, 25 Oct 2023 13:25:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698265515; cv=none; d=google.com; s=arc-20160816; b=ijgs0ondcTRs9Byx52FY4u329phZ5Q1pz7UgwW8s9rOojaC1bG9SJC3DIz+jyrlZuz 9pLDIUhIpbaNxqDZ9JANqfSqwQDZh0xL43XCOD6PUJ3xS9Pbxb0z7S/f277LYY5F2Cdi aUAC8O9NaDqDFqW2HnSziOiw0sGwv5vBUmL63su7qiIR5jzhEguX2OE86nYeQBHF2S5q y7MJ7UktySrQpei+NK7GgsjrfO/JBdCg8H7KeEdkKqtDMQSGW1Wk4fCEkKumX1flBhKi apP3BSxfWRehTRVfau7CBUJSPXTe1sVt5tUaO7TpbPY8YIH14lK/OjLrpOPKCSn4OhLF mF6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=GmA5kOKekb5h3Uw1k+e0LhCWijGnTH8utnJ5szxpch8=; fh=/fEAwM0ftwV2z3MN/iSYq1lv8IFPZ2fY8Kg8RoFcxjU=; b=bsGP4Y24rVmAB3L4yvYisvQwTdirnVRNqPvdMgEbOUAtl75y+jVbjRoWaZOwiNkMiQ ASnz198MofYr9bhQEvbWPLLh2mXU2AmfrjyLFK1PtUdaqIhAQTay/yZiyqZ4ln9RXiZc lYq5oyLKZvejQ2+QK0zpXnCeAVSWUxSehaGSr8y430PO2rgsu1ed5Lw0tY+5qgVKWoJu ecmz0icr2ViJSh3fSnEx1yBuDpz+3GBNC6AvGiD9mxheukI7U5Ph8LQyUODhXEzjMyqs bDiL7OrXjy8T2oBaWIgwwUTt/QnbiYuzXfeJ6Cdyk6l4HpOlGS3bFrPnzO3ergiaTJ+k o0OA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b="auVS/K/J"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from groat.vger.email (groat.vger.email. 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Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 06/21] RISC-V: Kconfig: Select deferred GSI probe for ACPI systems Date: Thu, 26 Oct 2023 01:53:29 +0530 Message-Id: <20231025202344.581132-7-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=2.7 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Level: ** X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Wed, 25 Oct 2023 13:25:11 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780760460739987256 X-GMAIL-MSGID: 1780760460739987256 On RISC-V platforms, apart from root interrupt controllers (which provide local interrupts and IPI), other interrupt controllers in the hierarchy are probed late. Enable this select this CONFIG option for RISC-V platforms so that device drivers which connect to deferred interrupt controllers can take appropriate action. Signed-off-by: Sunil V L --- arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 8c105a151e12..b62441aefa6a 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -12,6 +12,7 @@ config 32BIT config RISCV def_bool y + select ARCH_ACPI_DEFERRED_GSI if ACPI select ACPI_GENERIC_GSI if ACPI select ACPI_MCFG if (ACPI && PCI) select ACPI_REDUCED_HARDWARE_ONLY if ACPI From patchwork Wed Oct 25 20:23:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 158278 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp217874vqb; Wed, 25 Oct 2023 13:25:27 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFJGk8+W68FLpjEfjyjUbQP0mietSWsIwNGwpYYHTWt8g4Np8MKlbIfizhDbvIKQU2Po2+B X-Received: by 2002:a05:6870:829f:b0:1ea:12c:5e6e with SMTP id q31-20020a056870829f00b001ea012c5e6emr21299941oae.17.1698265527533; Wed, 25 Oct 2023 13:25:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698265527; cv=none; d=google.com; s=arc-20160816; b=oLLxtn6mU1Ca39pm+2Nfdop74csMQaOGtqx0jxPvwOyIvtPalgDASEGNTWQeCb6/wm 1BDg+n6q24HaT6KLH57B4p8FjxF7YtQPTBtfIRcCqJPdSBl6yL7PeUjVRVHaOGiNjrNJ B7feeOslG80xUzgpZ2GdMLUNrnWiKgsR3oWJHtvOgxaWV5u9blebSqlYfpRGZXKFRDW5 WjlXYEWCUIblMBs5osAgBkI4gCnEKIy1Tpo5RZXYWPH5C1BZdH15HmeWEFRcpPajObKG rovMqpPVybuN3T7JiJRGLIz119yDU2K8tE3ccQKd32rbI4IPcTyfqXR3ky8El49LYPDw CS6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=2bjA2IFkbvQ+cjwZ90V9r6vmNOzBSbezE1qJqMO1A+c=; fh=/fEAwM0ftwV2z3MN/iSYq1lv8IFPZ2fY8Kg8RoFcxjU=; b=ci/MNXUKif418VylNhWttA2nxbSek7M0SW4YQLRGvR4jG6Y/99LqR3W+24p131zU2c ZdYJ45y02t0XfFnH5sn2FUKr3BtrHRuRNvvXWC0xn7oq/hFu06CClVGV+hzPH5qsW3RW 2aZ0rlhs68+szLgE9tZ6yL9Sm0DSQbRUU1h1QlCH5/S+XhmU7OMiGt0Wi5UaZSmhosGK woaWM95pn8aY+nNNcbqp5ebcc2loU9WSzLYjGAW4LYG4bH1Hzj2zwKA88GFzJE1CIgK4 odLVWE6rV6nreCT9NCC2NURI/ClmBN828igJ8MqFussw8UhlXT4ZwJwhuwHWJ9KZpNqw oOaA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=eJujG6QR; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from pete.vger.email (pete.vger.email. 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Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 07/21] serial: 8250_pnp: Add support for deferred probe Date: Thu, 26 Oct 2023 01:53:30 +0530 Message-Id: <20231025202344.581132-8-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=2.7 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Level: ** X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Wed, 25 Oct 2023 13:25:25 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780760473820292538 X-GMAIL-MSGID: 1780760473820292538 With pnp_irq() able to return error code, enhance the serial pnp driver to support deferred probing. Return -EPROBE_DEFER when pnp_irq() returns the same so that the driver probe is deferred. Signed-off-by: Sunil V L --- drivers/tty/serial/8250/8250_pnp.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/tty/serial/8250/8250_pnp.c b/drivers/tty/serial/8250/8250_pnp.c index 1974bbadc975..dcb3daf7c816 100644 --- a/drivers/tty/serial/8250/8250_pnp.c +++ b/drivers/tty/serial/8250/8250_pnp.c @@ -8,6 +8,7 @@ * * Ported to the Linux PnP Layer - (C) Adam Belay. */ +#include #include #include #include @@ -443,8 +444,21 @@ serial_pnp_probe(struct pnp_dev *dev, const struct pnp_device_id *dev_id) } memset(&uart, 0, sizeof(uart)); - if (pnp_irq_valid(dev, 0)) - uart.port.irq = pnp_irq(dev, 0); + if (pnp_irq_valid(dev, 0)) { + ret = pnp_irq(dev, 0); + if (ret == -EPROBE_DEFER) { + struct resource r; + + ret = acpi_irq_get(ACPI_HANDLE(&dev->dev), 0, &r); + if (!ret) + uart.port.irq = r.start; + else + return ret; + } else { + uart.port.irq = ret; + } + } + if ((flags & CIR_PORT) && pnp_port_valid(dev, 2)) { uart.port.iobase = pnp_port_start(dev, 2); uart.port.iotype = UPIO_PORT; From patchwork Wed Oct 25 20:23:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 158279 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp218004vqb; Wed, 25 Oct 2023 13:25:42 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHBtS+oCrjUhm4bbbOkdZBMXw9qd6D8kkv83fvgznT46MmHPyQU6jYAXzpUPIyvsqPUJm1D X-Received: by 2002:a25:9184:0:b0:d81:9cdf:1795 with SMTP id w4-20020a259184000000b00d819cdf1795mr14793479ybl.57.1698265542613; Wed, 25 Oct 2023 13:25:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698265542; cv=none; d=google.com; s=arc-20160816; b=ANT30xilNchesDypzSXh35cBE4fNcEL4Iw8a1T+eIVgjynYsBnUUrpj/J7GTISdSNy c68k9mPbivuKMafSHOARClKPdQeWdGeC2GmBLx4m5crq7vAp8nWCjWZPNbBDnjHRErnP VQSvnRvNzIFxMnOKJAwIetUJelWgXhMN+ML0Y7IsgrOavTN6NONEeai5VOsj9vGBHIm2 6ann9TdMxPecX5WJ6owAJchB1D/bNuNybgKVp3xK2VIPLH+rR19hxPgIAeXHKA0KzHLb ouqCqU6I7EVLNytr5ekSGWP4BF6iNvS399TldcKNU9k6njr/Pr/P0T8OtTPMERkr3bfw 6wkg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=jdOBYbLR+bXetJ+YmrkOyswglZ/H3DLDZKjYZYq4pUE=; fh=/fEAwM0ftwV2z3MN/iSYq1lv8IFPZ2fY8Kg8RoFcxjU=; b=Jry41Yj9qz/EH+30i2C2Dhm0PNdj/3T1QFYGXVuW7Mzuw6LFQnPdqeMLF+MGssmvxm c+p2XKG13LvYQq+lpNdUGjnq6Hk+vA3MbiTz/XhA68TIbqqkMoqU2aRJMmqEQ2QmEyzy w5N1Z568BkllYi6PjZiBH/oc7J2U9lnzg4N2F2iz1+1SIkY5OGQskTOJL82yL7G7yfRS MNyTPCetnKk+WPQ3GHCqm1GyyvjZw+P8r/8jrufmfSgqyuJ7cVa0zHiTZJFmBY4ZmzVX RdhT/1NdaZU6GadQ62PESNqPoZIyQYZaGKg+S87eKwHuBAumg3YyyGglC+SvSSpgtA9M zlvA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=HmX0WIx5; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from lipwig.vger.email (lipwig.vger.email. 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Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 08/21] ACPI: pci_irq: Avoid warning for deferred probe in acpi_pci_irq_enable() Date: Thu, 26 Oct 2023 01:53:31 +0530 Message-Id: <20231025202344.581132-9-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=2.7 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Level: ** X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Wed, 25 Oct 2023 13:25:38 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780760489570954750 X-GMAIL-MSGID: 1780760489570954750 When the architecture like RISC-V supports deferred GSI interrupt controller probe, acpi_register_gsi() can return -EPROBE_DEFER which is a valid use case to delay the dependent driver probe. So, avoid printing the warning for the deferred probe case. Signed-off-by: Sunil V L --- drivers/acpi/pci_irq.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/acpi/pci_irq.c b/drivers/acpi/pci_irq.c index ff30ceca2203..f7d0822da08f 100644 --- a/drivers/acpi/pci_irq.c +++ b/drivers/acpi/pci_irq.c @@ -452,8 +452,11 @@ int acpi_pci_irq_enable(struct pci_dev *dev) rc = acpi_register_gsi(&dev->dev, gsi, triggering, polarity); if (rc < 0) { - dev_warn(&dev->dev, "PCI INT %c: failed to register GSI\n", - pin_name(pin)); + if (rc != -EPROBE_DEFER) { + dev_warn(&dev->dev, "PCI INT %c: failed to register GSI\n", + pin_name(pin)); + } + kfree(entry); return rc; } From patchwork Wed Oct 25 20:23:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 158280 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp218043vqb; Wed, 25 Oct 2023 13:25:47 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEpxA46QuSjtX3Q04xyV1hrOu3EIXgCn/5ZdGTrjFaUhdx0GstWgMGu+Xbv6R0cvfMQQ0Yc X-Received: by 2002:a25:abe2:0:b0:da0:94fb:fd7e with SMTP id v89-20020a25abe2000000b00da094fbfd7emr1267497ybi.45.1698265547374; Wed, 25 Oct 2023 13:25:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698265547; cv=none; d=google.com; s=arc-20160816; b=XROkTLGkjQNnXIJGoX0kwVAIdagr6wvyThEkPsHK/REv1R1GntBPJ3ZUxgmcgfy/40 yV3zBH+gQrohqqNfa9y8P8R8QuxF2v5qIuIfn5sgAJsEMZCGrg+PgJqj3WEMZNZXh0cY woe7QKgaC4R88OtAFzODkcSJdgagm80dXjweiDjwmh/40qW7TaSGLi8oslGLbbRnDyp6 J78Hg56/6x7ETlFuW5TiamQVTKRlAAgLZJMKcZsIn0kZAu6r7lBF+0KlfmJduRTg9Wng TcYN0rpwlUAwbzFugZpmyCVVBorfbMhhcA3ZM6cE14HDbxN7w0Tk3FZtx0aYAlkMaoFJ 36hQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=rTitWHvbkwllUIYzM7TBpB/hreitIS32ztyb9Cf5EZw=; fh=/fEAwM0ftwV2z3MN/iSYq1lv8IFPZ2fY8Kg8RoFcxjU=; b=RmZ4glkfe06haJhE7CJnTw6JOW9aXn/brezkN/854SVYzQAq5KDekQ7+cKFJjKd1So VDXZ8ov6q/ygl6maA0gTOuhBd7dJ75gplHGwv3bwvwg436rdQVCSrhQzAEbJUQFjig2D VOwJsgEFwdkIMKS0n85iJ7+vPLkQLfFaxMgbVKa5I52dAnfhUB7wJ7/L9KCOXQJtbqaf tDlqF3Qco8Qk9u5/f148YzQbXUi7MsKWZ+PsiLAq3r6StDWUJzvSWMXB6q2vMQGFnods ZUqous+WZHhQG5+ijkJVoeDEjax5MJLPjTbp6UXZEmcFxaF0aE/gZDez08vmPIpRWkqN 7qVA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=D4SzcIRp; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from lipwig.vger.email (lipwig.vger.email. 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Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 09/21] ACPI: scan.c: Add weak arch specific function to reorder the IRQCHIP probe Date: Thu, 26 Oct 2023 01:53:32 +0530 Message-Id: <20231025202344.581132-10-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=2.7 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Level: ** X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Wed, 25 Oct 2023 13:25:44 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780760494933965332 X-GMAIL-MSGID: 1780760494933965332 Unlike OF framework, the irqchip probe using IRQCHIP_ACPI_DECLARE has no order defined. Depending on the driver Makefile is not a good idea. So, usually it is worked around by mandating only root interrupt controller probed using IRQCHIP_ACPI_DECLARE and other interrupt controllers are probed via cascade mechanism. However, this is also not a clean solution because if there are multiple root controllers (ex: RINTC in RISC-V which is per CPU) which need to be probed first, then the cascade will happen for every root controller. So, introduce a architecture specific weak function to order the probing of the interrupt controllers which can be implemented by different architectures as per their interrupt controller hierarchy. Signed-off-by: Sunil V L --- drivers/acpi/scan.c | 3 +++ include/linux/acpi.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c index 691d4b7686ee..87f4baebd497 100644 --- a/drivers/acpi/scan.c +++ b/drivers/acpi/scan.c @@ -2685,6 +2685,8 @@ static int __init acpi_match_madt(union acpi_subtable_headers *header, return 0; } +void __weak arch_sort_irqchip_probe(struct acpi_probe_entry *ap_head, int nr) { } + int __init __acpi_probe_device_table(struct acpi_probe_entry *ap_head, int nr) { int count = 0; @@ -2693,6 +2695,7 @@ int __init __acpi_probe_device_table(struct acpi_probe_entry *ap_head, int nr) return 0; mutex_lock(&acpi_probe_mutex); + arch_sort_irqchip_probe(ap_head, nr); for (ape = ap_head; nr; ape++, nr--) { if (ACPI_COMPARE_NAMESEG(ACPI_SIG_MADT, ape->id)) { acpi_probe_count = 0; diff --git a/include/linux/acpi.h b/include/linux/acpi.h index afd94c9b8b8a..4ad256a0039c 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -1338,6 +1338,8 @@ struct acpi_probe_entry { kernel_ulong_t driver_data; }; +void arch_sort_irqchip_probe(struct acpi_probe_entry *ap_head, int nr); + #define ACPI_DECLARE_PROBE_ENTRY(table, name, table_id, subtable, \ valid, data, fn) \ static const struct acpi_probe_entry __acpi_probe_##name \ From patchwork Wed Oct 25 20:23:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 158281 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp218279vqb; Wed, 25 Oct 2023 13:26:19 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHS5ZMswSRhJG2B1JFAt9tCEPMyFsQfXfYcwTlk7e48FkLEWwAUJFvgkN5CTxpROIj8NNEx X-Received: by 2002:a54:4893:0:b0:3b2:e70e:b448 with SMTP id r19-20020a544893000000b003b2e70eb448mr19283286oic.8.1698265579274; Wed, 25 Oct 2023 13:26:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698265579; cv=none; d=google.com; s=arc-20160816; b=wvDDURpAl1ZOq1wa/2jUJP9VIQGkN+zJZmxMr1v/nr1TlShCeGOQot4ijpfunQcQov i8auHtEzWE6NaolaCJc87vz4h7++OqNzpetCAmMSr2R/1FvZpEu4xyzCVOLJ3eEQ5iSb beqcWEu9URA/ty5oZLM+ARBAbBmGTMpyVG7DwiTWD7U3dcW/8N7A6mhiwKb4FetTkIsx 2C0uCkbG52xg4hTX7cY3kym6bWagXgdUZU1zluIk3WO6b7pwU1ySH/Uk6NbR9/qZtC4f iu2xr+GPValBMvcDRSLPmKKMKSCNyvEzp8OHXb+eQHhn7EcqazOOljFDzAy+jV3isuRx SWkA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=DxzCTJ+m1lwBq+RMy/cftySc6UneYPqTwJF8JhbniDw=; fh=/fEAwM0ftwV2z3MN/iSYq1lv8IFPZ2fY8Kg8RoFcxjU=; b=L7q1AYSLMNt7SDlzhDgVJyB7k0gEJP+Tg7bGaqBDwj5wniXjdfBLyob0/B4zLhMz1p eWODOgmMstV9vdMDjeVYKqKaNg310oY7l+j8BWyUydOs4Ixpt5gORiLVHZmf4NRTIzoz P91kQmY0NeKL4Kq7HjQc1RYOaFpSNcOalte3M5zdtybx7NnxFoNLjIfDl/za9Rm7aHsk j1yWnrb8pIJE3/OldjZ7IjJTMnH8IrtCBX0gg0s3UoTqBYEZXHb5oaI2/lYefTXfbolb LqqUh1IvK0Ww3ryFsL6X9quSvcUY6rusc2aVOknwEXX6n8k2fqDKbnk8tmcItjD6bTVn 3Ueg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=ZPLmnXDK; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from groat.vger.email (groat.vger.email. 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Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 10/21] ACPI: RISC-V: Implement arch function to reorder irqchip probe entries Date: Thu, 26 Oct 2023 01:53:33 +0530 Message-Id: <20231025202344.581132-11-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=2.7 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Level: ** X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Wed, 25 Oct 2023 13:26:16 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780760528077927368 X-GMAIL-MSGID: 1780760528077927368 ACPI MADT entries for interrupt controllers don't have a way to describe the hierarchy. However, the hierarchy is known to the architecture and on RISC-V platforms, the MADT sub table types are ordered in the incremental order from the root controller which is RINTC. So, add architecture function for RISC-V to reorder the interrupt controller probing as per the hierarchy as below. RINTC->IMSIC->APLIC->PLIC Signed-off-by: Sunil V L --- drivers/acpi/riscv/Makefile | 2 +- drivers/acpi/riscv/irq.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+), 1 deletion(-) create mode 100644 drivers/acpi/riscv/irq.c diff --git a/drivers/acpi/riscv/Makefile b/drivers/acpi/riscv/Makefile index 8b3b126e0b94..f80b3da230e9 100644 --- a/drivers/acpi/riscv/Makefile +++ b/drivers/acpi/riscv/Makefile @@ -1,2 +1,2 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-y += rhct.o +obj-y += rhct.o irq.o diff --git a/drivers/acpi/riscv/irq.c b/drivers/acpi/riscv/irq.c new file mode 100644 index 000000000000..36e0525b3235 --- /dev/null +++ b/drivers/acpi/riscv/irq.c @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023, Ventana Micro Systems Inc + * Author: Sunil V L + * + */ + +#include +#include + +static int irqchip_cmp_func(const void *in0, const void *in1) +{ + struct acpi_probe_entry *elem0 = (struct acpi_probe_entry *)in0; + struct acpi_probe_entry *elem1 = (struct acpi_probe_entry *)in1; + + return (elem0->type > elem1->type) - (elem0->type < elem1->type); +} + +/* + * RISC-V irqchips in MADT of ACPI spec are defined in the same order how + * they should be probed. Since IRQCHIP_ACPI_DECLARE doesn't define any + * order, this arch function will reorder the probe functions as per the + * required order for the architecture. + */ +void arch_sort_irqchip_probe(struct acpi_probe_entry *ap_head, int nr) +{ + struct acpi_probe_entry *ape = ap_head; + + if (nr == 1 || !ACPI_COMPARE_NAMESEG(ACPI_SIG_MADT, ape->id)) + return; + sort(ape, nr, sizeof(*ape), irqchip_cmp_func, NULL); +} From patchwork Wed Oct 25 20:23:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 158282 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp218298vqb; Wed, 25 Oct 2023 13:26:23 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF+9w2xgFs7xQ0S3D9DBUCk4ky1HJrNJXvb1U+KHzaNdBiAeOwBwMJBAq/j98Jea9rzwGS2 X-Received: by 2002:a25:8747:0:b0:d86:4342:290 with SMTP id e7-20020a258747000000b00d8643420290mr1186999ybn.21.1698265582866; Wed, 25 Oct 2023 13:26:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698265582; cv=none; d=google.com; s=arc-20160816; b=m6/65prQlxkmQnRDUnki44GM0cGEsATHxQorWQnk0axU1eDc6GiJi03UlyKGKTKZGh 1BGFbEr5tf9FZ7Ss+I/e4tyi0WBdOXW+J/frSCBCsXHpEn9KXy2+G2975eEoU0weJNtF vVdOzKhd5fuzdfiCi8Vr4TlfReGyNTpBW5kI70cfcnv5lP9SqEFv/H53alrLqiwud+80 qRbialdbOent9IcBjcyaEc69x1Fgfnr3tK+KlIRDR5qm+pRsd8uZaSNV170tXIOPVKMM 7LGiwvM3AWcSkMGXNF8+gTI+fUm2XdRjOY7QC3c3vdRAEIgV7wiUj2SP0WX3p6hWCIld q8WA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=ksJT9a6E7b+AgWOW+0QqZAQKxEPs+GfkSTk4Wygp/9k=; fh=/fEAwM0ftwV2z3MN/iSYq1lv8IFPZ2fY8Kg8RoFcxjU=; b=VMUohHNjrUPXqm9SoedoEyfZXXmIVLuX+GruC+vPrxIu17f2Q21rht2JB5vqTZQklX Q9SzcpxgobypwmjiuOEx/DuUsDiJkEEoDOCDDkFbC5OVrHG7GJOF0F34S9hwxnkf/8PH fd494NlGA3Nz+RE4zdXUWwNpbnH8fl7v2x+EFKnkaORluCjswsBmFKAOzPWCoRZvLXsa Vl5xdes51X52/VRYc6QsPAlrDvMVIhYOna6oEeuvp/mOKxXU8rdytDxRrl5J79Glc0lI H+8aOwmr/SYRrzMyps8iZ5+jp+uqskVw5j7T/a89juNW+nRg8v2Tev4Bex26u+dJo9It IPlg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=JPtX39iv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from agentk.vger.email (agentk.vger.email. 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Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 11/21] PCI: MSI: Add helper function to set system wide MSI support Date: Thu, 26 Oct 2023 01:53:34 +0530 Message-Id: <20231025202344.581132-12-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=2.7 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Level: ** X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Wed, 25 Oct 2023 13:26:19 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780760531802794592 X-GMAIL-MSGID: 1780760531802794592 Like pci_no_msi() used to disable MSI support, add a function to enable system wide MSI support. Signed-off-by: Sunil V L --- drivers/pci/msi/msi.c | 5 +++++ drivers/pci/pci.h | 2 ++ 2 files changed, 7 insertions(+) diff --git a/drivers/pci/msi/msi.c b/drivers/pci/msi/msi.c index ef1d8857a51b..e76ccb8b5f0b 100644 --- a/drivers/pci/msi/msi.c +++ b/drivers/pci/msi/msi.c @@ -913,3 +913,8 @@ void pci_no_msi(void) { pci_msi_enable = 0; } + +void pci_set_msi(void) +{ + pci_msi_enable = 1; +} diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h index 39a8932dc340..2f876c29f75c 100644 --- a/drivers/pci/pci.h +++ b/drivers/pci/pci.h @@ -167,8 +167,10 @@ extern unsigned int pci_pm_d3hot_delay; #ifdef CONFIG_PCI_MSI void pci_no_msi(void); +void pci_set_msi(void); #else static inline void pci_no_msi(void) { } +static inline void pci_set_msi(void) { } #endif void pci_realloc_get_opt(char *); From patchwork Wed Oct 25 20:23:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 158283 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp218466vqb; Wed, 25 Oct 2023 13:26:45 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGtL/BpioYsoGNTB12ctsDWfmT/NUeqcXYQfcHghmNdHz2UK0yHVETsu+tM7wfZg0a82Y4n X-Received: by 2002:a81:844b:0:b0:5a7:d51d:62b3 with SMTP id u72-20020a81844b000000b005a7d51d62b3mr16489961ywf.10.1698265604885; Wed, 25 Oct 2023 13:26:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698265604; cv=none; d=google.com; s=arc-20160816; b=vZGtY3ffHmtv82Gf2UXkxTkvFw0cOBBxLhJDWz43Gt8P28yNQb0cOwmPx08NGTd1F4 /7eSzraSja5ljbaZWgDoy+tHYFdFgvF66AOmmdiJxmBbV/emKbZGOKCWkmheW1zdK0VS XkrvkDyhbF/klhZ1cD53SY/ANjM4PQVepajfO17sgl9xOh0Q6EYWrSXaFz5Ubka14HLd ojF6j6TGi1ZRHuMCqwm0s+FHdwapzI2tkEmXpO3PF6oxLqSHwVBwokz2WNpAznr1mTra r2qhgr1B4zpP0tqhAHHPYEFJWqsVp2FUUTTdgUyPxWA50disFGWRog90suuK0wTNy76V 1UkA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=5kojFGf2ZSJMlibBdobzZmgsjyx4Ywkx3WkwDcrmlX4=; fh=/fEAwM0ftwV2z3MN/iSYq1lv8IFPZ2fY8Kg8RoFcxjU=; b=CkuMftXHazoW1/Wz9kv8oe4zNffFCnR8wGfMh6JrJGpJBqs5K9plnUg/1rY+IJyZ4q 25D//qwpF1KALg2P9/OTVqUrABk8b//380gGeLs5PXgOR/6pM4k8CbqI+a4P9iTS2Tbq brjGK8+fhDrlvDb7+soZQhpxFxjP7j0VImMCH6OwvrarQEgNPmrO2A4ApHFgAVXV6ZiF 620rqyBLe0Kbwsvh4KPmZOGzxPEJWJ1yxE0ukZbia1dVEPplBF008UoaengJM1Oyv1Oh s0BeBjscVCCnDMYoOR1YWV7QncBwVQqrN8GXiPNQesgaQ36pVOjNDnfE+nbF8hrSh0fA RvuQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=bc4o5R2u; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from groat.vger.email (groat.vger.email. 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Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 12/21] PCI: pci-acpi.c: Return correct value from pcibios_alloc_irq() Date: Thu, 26 Oct 2023 01:53:35 +0530 Message-Id: <20231025202344.581132-13-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=2.7 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Level: ** X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Wed, 25 Oct 2023 13:26:39 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780760554650057472 X-GMAIL-MSGID: 1780760554650057472 Return the correct value from pcibios_alloc_irq(). Signed-off-by: Sunil V L --- drivers/pci/pci-acpi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/pci-acpi.c b/drivers/pci/pci-acpi.c index c8c3369fd69f..80dc0b290544 100644 --- a/drivers/pci/pci-acpi.c +++ b/drivers/pci/pci-acpi.c @@ -1528,7 +1528,7 @@ arch_initcall(acpi_pci_init); int pcibios_alloc_irq(struct pci_dev *dev) { if (!acpi_disabled) - acpi_pci_irq_enable(dev); + return acpi_pci_irq_enable(dev); return 0; } From patchwork Wed Oct 25 20:23:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 158284 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp218689vqb; Wed, 25 Oct 2023 13:27:11 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEFRVpA8BasJ9Lo4+OHzxtD6eL/nS34v5dR0skp/vo7krX2pA9eF1b6eCsk7XKat/ExQBET X-Received: by 2002:a25:6911:0:b0:da0:39ed:3ebb with SMTP id e17-20020a256911000000b00da039ed3ebbmr6742238ybc.3.1698265631268; Wed, 25 Oct 2023 13:27:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698265631; cv=none; d=google.com; s=arc-20160816; b=ZiMOiKiA84aEbruzxzsBRDI1smoxVqghQb1RA8v3XJka9Deccu6A19PiMKtl68eohl N4Ic/QzB9vYGT7nKtFDJJfmYYb+BBNKYbRp8/kWB7XPtqdPMP5MeqpQE5LBmhJqdVukS QkIsTRaV2L7rXqRQrl7qrGJjVZGb49sVnzOplwEGFUY9tb0/QutRxIN3M4LyBL1P8odP pbHmkmlQpvTPmoN8WpBRlIxB33wiNVJdVv6kH4FPYMdZqwjVpkMjGrkMiPxekjQWeceO H9eO4FnyxsdWiP8mDgtdnokf5L7i7GJRTILI/yfTnylMyPn0xn7m8Wz6QlMz/d5jQzIk BEGw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=TxxAoj3PrwWmIOe2p0tfNOdKkVyofyMHFnQehndBZcc=; fh=/fEAwM0ftwV2z3MN/iSYq1lv8IFPZ2fY8Kg8RoFcxjU=; b=1CHduQBYsno4GocQvxZICKdiP36afJQIrJVDedmLEFvmvkye5NJob4Cr2T1ZdCMj/X EREdLdsuPfWa7ADwUoXYZNv8LxddeTZxhRYjPOCxx2g9CwyCOs8sb8QqHKRAlWbJ4zZ7 SzTT0eDCqQUW+Onl6R5aqxsltwoADrb1Zz+qg1N40AkFvEoxyHmEfy8e8Ihw0PHpXFOu WLCR5jR1A6coaJXzg2/lqRvnX29YVPEhOIPwucNuvEN5Go1i+XymxWWs4RjjUnD6/XJo FeBERpXlS2ga7fpNCUelwoOyTOWzrov7qYNf16jWgVLnU9veiE01SbTQ0vfe+JSWOve9 SKyw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=URUZqepl; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from groat.vger.email (groat.vger.email. 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Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 13/21] irqchip: riscv-intc: Add ACPI support for AIA Date: Thu, 26 Oct 2023 01:53:36 +0530 Message-Id: <20231025202344.581132-14-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=2.7 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Level: ** X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Wed, 25 Oct 2023 13:27:07 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780760582951960383 X-GMAIL-MSGID: 1780760582951960383 The RINTC subtype structure in MADT also has information about other interrupt controllers like MMIO. So, save those information and provide interfaces to retrieve them when required by corresponding drivers. Signed-off-by: Sunil V L --- arch/riscv/include/asm/irq.h | 19 ++++++ drivers/irqchip/irq-riscv-intc.c | 102 ++++++++++++++++++++++++++++++- 2 files changed, 120 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h index 8e10a94430a2..ef102b6fa86e 100644 --- a/arch/riscv/include/asm/irq.h +++ b/arch/riscv/include/asm/irq.h @@ -12,8 +12,27 @@ #include +#ifdef CONFIG_ACPI + +/* + * The ext_intc_id format is as follows: + * Bits [31:24] APLIC/PLIC ID + * Bits [15:0] APLIC IDC ID / PLIC S-Mode Context ID for this hart + */ +#define APLIC_PLIC_ID(x) ((x) >> 24) +#define IDC_CONTEXT_ID(x) ((x) & 0x0000ffff) + +int __init acpi_get_intc_index_hartid(u32 index, unsigned long *hartid); +int acpi_get_ext_intc_parent_hartid(u8 id, u32 idx, unsigned long *hartid); +void acpi_get_plic_nr_contexts(u8 id, int *nr_contexts); +int acpi_get_plic_context(u8 id, u32 idx, int *context_id); +int __init acpi_get_imsic_mmio_info(u32 index, struct resource *res); + +#endif + void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void)); struct fwnode_handle *riscv_get_intc_hwnode(void); +int acpi_imsic_probe(struct fwnode_handle *parent); #endif /* _ASM_RISCV_IRQ_H */ diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index bab536bbaf2c..f3aaecde12dd 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -18,6 +18,7 @@ #include #include #include +#include "../pci/pci.h" static struct irq_domain *intc_domain; @@ -195,13 +196,100 @@ IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init); #ifdef CONFIG_ACPI +struct rintc_data { + u32 ext_intc_id; + unsigned long hart_id; + u64 imsic_addr; + u32 imsic_size; +}; + +static u32 nr_rintc; +static struct rintc_data *rintc_acpi_data[NR_CPUS]; + +int acpi_get_intc_index_hartid(u32 index, unsigned long *hartid) +{ + if (index >= nr_rintc) + return -1; + + *hartid = rintc_acpi_data[index]->hart_id; + return 0; +} + +int acpi_get_ext_intc_parent_hartid(u8 id, u32 idx, unsigned long *hartid) +{ + int i, j = 0; + + for (i = 0; i < nr_rintc; i++) { + if (APLIC_PLIC_ID(rintc_acpi_data[i]->ext_intc_id) == id) { + if (idx == j) { + *hartid = rintc_acpi_data[i]->hart_id; + return 0; + } + j++; + } + } + + return -1; +} + +void acpi_get_plic_nr_contexts(u8 id, int *nr_contexts) +{ + int i, j = 0; + + for (i = 0; i < nr_rintc; i++) { + if (APLIC_PLIC_ID(rintc_acpi_data[i]->ext_intc_id) == id) + j++; + } + + *nr_contexts = j; +} + +int acpi_get_plic_context(u8 id, u32 idx, int *context_id) +{ + int i, j = 0; + + for (i = 0; i < nr_rintc; i++) { + if (APLIC_PLIC_ID(rintc_acpi_data[i]->ext_intc_id) == id) { + if (idx == j) { + *context_id = IDC_CONTEXT_ID(rintc_acpi_data[i]->ext_intc_id); + return 0; + } + + j++; + } + } + + return -1; +} + +int acpi_get_imsic_mmio_info(u32 index, struct resource *res) +{ + if (index >= nr_rintc) + return -1; + + res->start = rintc_acpi_data[index]->imsic_addr; + res->end = res->start + rintc_acpi_data[index]->imsic_size - 1; + res->flags = IORESOURCE_MEM; + return 0; +} + static int __init riscv_intc_acpi_init(union acpi_subtable_headers *header, const unsigned long end) { struct fwnode_handle *fn; struct acpi_madt_rintc *rintc; + int rc; rintc = (struct acpi_madt_rintc *)header; + rintc_acpi_data[nr_rintc] = kzalloc(sizeof(*rintc_acpi_data[0]), GFP_KERNEL); + if (!rintc_acpi_data[nr_rintc]) + return -ENOMEM; + + rintc_acpi_data[nr_rintc]->ext_intc_id = rintc->ext_intc_id; + rintc_acpi_data[nr_rintc]->hart_id = rintc->hart_id; + rintc_acpi_data[nr_rintc]->imsic_addr = rintc->imsic_addr; + rintc_acpi_data[nr_rintc]->imsic_size = rintc->imsic_size; + nr_rintc++; /* * The ACPI MADT will have one INTC for each CPU (or HART) @@ -218,7 +306,19 @@ static int __init riscv_intc_acpi_init(union acpi_subtable_headers *header, return -ENOMEM; } - return riscv_intc_init_common(fn); + rc = riscv_intc_init_common(fn); + if (rc) { + irq_domain_free_fwnode(fn); + return rc; + } + + /* + * MSI controller (IMSIC) in RISC-V is optional. So, unless + * IMSIC is discovered, set system wide MSI support as + * unsupported. Once IMSIC is probed, MSI support will be set. + */ + pci_no_msi(); + return 0; } IRQCHIP_ACPI_DECLARE(riscv_intc, ACPI_MADT_TYPE_RINTC, NULL, From patchwork Wed Oct 25 20:23:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 158285 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp218786vqb; Wed, 25 Oct 2023 13:27:22 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF3YQek3FtTgFEMs1LhaRYWNiByuecmEjMnafPjGTRixbknO/fCd1TNBgG8W2atryE6IAaz X-Received: by 2002:a05:6871:3147:b0:1e9:bb3a:9a89 with SMTP id lu7-20020a056871314700b001e9bb3a9a89mr20676081oac.47.1698265642387; Wed, 25 Oct 2023 13:27:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698265642; cv=none; d=google.com; s=arc-20160816; b=t/Bb9pBegexxV6GzKua/qmrPTNuq+KAfdNzzYTmKYgscGZREuBLBWClwy2fPspAzI8 DxIVSQHzEvhUoTQisk/mJzM+QB01LynxJNv+7eWyqMc33C/rU1WPfMoD+n0a0c5z6hUb 87g23E2NxAO/7ZrSZf4B+P2G96tx30ddB6qjXkLw2NLa/irfVH4RT/TXORxCRt1iKQXe J4NUEe68E3Rq1fmjBKiDzZWVV/eLd4AxjsMvKKmtNCdfKttUpp/kx/qIEqFCq2QGRgqH 3rHPohpGc8FXAPAFRgPdqSqW3mcS2Q9OKwbXYm0u9RuRVvqtjxgRIKw2S+dqL+ZtJMSC niiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=59OuHyNaU3fGic7bU/ykRVEj1ISi+51hzxPyHqKgiHU=; fh=/fEAwM0ftwV2z3MN/iSYq1lv8IFPZ2fY8Kg8RoFcxjU=; b=Di+vAxaFqwKzTry8gReMppRVv8ojydLep4GN59cZgaUed0gNjaiXYfP3o2rKyhWx9h h373yZYD7ZvF3tP1vRQ9CVfsgzrX3eZqhwp+nEViXka5J579OA/YDU4TKSVprfoXRtf4 WRxQDJtCpE0hqwvC3nZBmQHoNxlNZGZiVk6tawiIuKBXQALw6hEIckHyesCch5ICTf73 I7LGzkPj/4nrjcxcisWGM2oAUmpD794tG2hd67N5Su5WUkLynHMMGG2wn1NvyoFgC2KK eER4HxV/ZCwE/UIhj8PADOCuUsngMLUWTPN+zEWPrN+KLaYe5ImYC1+j2BjRGjRkj5Tc 4qhw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=WSI2LI3U; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from snail.vger.email (snail.vger.email. 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Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 14/21] irqchip: riscv-imsic: Add ACPI support Date: Thu, 26 Oct 2023 01:53:37 +0530 Message-Id: <20231025202344.581132-15-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=1.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Level: * X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 25 Oct 2023 13:26:43 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780760594114676902 X-GMAIL-MSGID: 1780760594114676902 RISC-V IMSIC interrupt controller provides IPI and MSI support. Currently, DT based drivers setup the IPI feature early during boot but defer setting up the MSI functionality. However, in ACPI systems, PCI scan happens early during boot and PCI subsystem expects MSI controller is already setup. Hence, in case of ACPI, both IPI and MSI features are initialized early itself. Signed-off-by: Sunil V L --- drivers/irqchip/irq-riscv-imsic-early.c | 52 ++++++++- drivers/irqchip/irq-riscv-imsic-platform.c | 51 +++++--- drivers/irqchip/irq-riscv-imsic-state.c | 128 ++++++++++----------- drivers/irqchip/irq-riscv-imsic-state.h | 2 +- include/linux/irqchip/riscv-imsic.h | 10 ++ 5 files changed, 160 insertions(+), 83 deletions(-) diff --git a/drivers/irqchip/irq-riscv-imsic-early.c b/drivers/irqchip/irq-riscv-imsic-early.c index 23f689ff5807..8ce864a7e4dd 100644 --- a/drivers/irqchip/irq-riscv-imsic-early.c +++ b/drivers/irqchip/irq-riscv-imsic-early.c @@ -5,16 +5,20 @@ */ #define pr_fmt(fmt) "riscv-imsic: " fmt +#include #include #include #include #include #include #include +#include #include +#include #include #include +#include "../pci/pci.h" #include "irq-riscv-imsic-state.h" static int imsic_parent_irq; @@ -216,7 +220,7 @@ static int __init imsic_early_dt_init(struct device_node *node, struct fwnode_handle *fwnode = &node->fwnode; /* Setup IMSIC state */ - rc = imsic_setup_state(fwnode); + rc = imsic_setup_state(fwnode, NULL); if (rc) { pr_err("%pfwP: failed to setup state (error %d)\n", fwnode, rc); @@ -233,3 +237,49 @@ static int __init imsic_early_dt_init(struct device_node *node, return 0; } IRQCHIP_DECLARE(riscv_imsic, "riscv,imsics", imsic_early_dt_init); + +#ifdef CONFIG_ACPI + +static struct fwnode_handle *imsic_acpi_fwnode; + +struct fwnode_handle *imsic_acpi_get_fwnode(struct device *dev) +{ + return imsic_acpi_fwnode; +} + +static int __init imsic_early_acpi_init(union acpi_subtable_headers *header, + const unsigned long end) +{ + struct acpi_madt_imsic *imsic = (struct acpi_madt_imsic *)header; + int rc; + + imsic_acpi_fwnode = irq_domain_alloc_named_fwnode("imsic"); + if (!imsic_acpi_fwnode) { + pr_err("unable to allocate IMSIC FW node\n"); + return -ENOMEM; + } + + /* Setup IMSIC state */ + rc = imsic_setup_state(imsic_acpi_fwnode, (void *)imsic); + if (rc) { + pr_err("%pfwP: failed to setup state (error %d)\n", imsic_acpi_fwnode, rc); + return rc; + } + + /* Do early setup of IMSIC state and IPIs */ + rc = imsic_early_probe(imsic_acpi_fwnode); + if (rc) + return rc; + + rc = imsic_platform_acpi_probe(imsic_acpi_fwnode); + if (!rc) { + pci_msi_register_fwnode_provider(&imsic_acpi_get_fwnode); + pci_set_msi(); + } + + return rc; +} + +IRQCHIP_ACPI_DECLARE(riscv_imsic, ACPI_MADT_TYPE_IMSIC, NULL, + 1, imsic_early_acpi_init); +#endif diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip/irq-riscv-imsic-platform.c index cdb659401199..f905340d24e6 100644 --- a/drivers/irqchip/irq-riscv-imsic-platform.c +++ b/drivers/irqchip/irq-riscv-imsic-platform.c @@ -5,6 +5,7 @@ */ #define pr_fmt(fmt) "riscv-imsic: " fmt +#include #include #include #include @@ -308,43 +309,47 @@ static int imsic_irq_domains_init(struct fwnode_handle *fwnode) return 0; } -static int imsic_platform_probe(struct platform_device *pdev) +static int imsic_platform_probe_common(struct fwnode_handle *fwnode) { - struct device *dev = &pdev->dev; struct imsic_global_config *global; int rc; if (!imsic) { - dev_err(dev, "early driver not probed\n"); + pr_err("%pfwP: early driver not probed\n", fwnode); return -ENODEV; } if (imsic->base_domain) { - dev_err(dev, "irq domain already created\n"); + pr_err("%pfwP: irq domain already created\n", fwnode); return -ENODEV; } global = &imsic->global; /* Initialize IRQ and MSI domains */ - rc = imsic_irq_domains_init(dev->fwnode); + rc = imsic_irq_domains_init(fwnode); if (rc) { - dev_err(dev, "failed to initialize IRQ and MSI domains\n"); + pr_err("%pfwP: failed to initialize IRQ and MSI domains\n", fwnode); return rc; } - dev_info(dev, " hart-index-bits: %d, guest-index-bits: %d\n", - global->hart_index_bits, global->guest_index_bits); - dev_info(dev, " group-index-bits: %d, group-index-shift: %d\n", - global->group_index_bits, global->group_index_shift); - dev_info(dev, " per-CPU IDs %d at base PPN %pa\n", - global->nr_ids, &global->base_addr); - dev_info(dev, " total %d interrupts available\n", - imsic->nr_hwirqs); + pr_info("%pfwP: hart-index-bits: %d, guest-index-bits: %d\n", fwnode, + global->hart_index_bits, global->guest_index_bits); + pr_info("%pfwP: group-index-bits: %d, group-index-shift: %d\n", fwnode, + global->group_index_bits, global->group_index_shift); + pr_info("%pfwP: per-CPU IDs %d at base PPN %pa\n", fwnode, + global->nr_ids, &global->base_addr); + pr_info("%pfwP: total %d interrupts available\n", fwnode, + imsic->nr_hwirqs); return 0; } +static int imsic_platform_dt_probe(struct platform_device *pdev) +{ + return imsic_platform_probe_common(pdev->dev.fwnode); +} + static const struct of_device_id imsic_platform_match[] = { { .compatible = "riscv,imsics" }, {} @@ -355,6 +360,22 @@ static struct platform_driver imsic_platform_driver = { .name = "riscv-imsic", .of_match_table = imsic_platform_match, }, - .probe = imsic_platform_probe, + .probe = imsic_platform_dt_probe, }; builtin_platform_driver(imsic_platform_driver); + +#ifdef CONFIG_ACPI + +/* + * On ACPI based systems, PCI enumeration happens early during boot in + * acpi_scan_init(). PCI enumeration expects MSI domain setup before + * it calls pci_set_msi_domain(). Hence, unlike in DT where + * imsic-platform drive probe happens late during boot, ACPI based + * systems need to setup the MSI domain early. + */ +int imsic_platform_acpi_probe(struct fwnode_handle *fwnode) +{ + return imsic_platform_probe_common(fwnode); +} + +#endif diff --git a/drivers/irqchip/irq-riscv-imsic-state.c b/drivers/irqchip/irq-riscv-imsic-state.c index 54465e47851c..b842c499df0a 100644 --- a/drivers/irqchip/irq-riscv-imsic-state.c +++ b/drivers/irqchip/irq-riscv-imsic-state.c @@ -5,6 +5,7 @@ */ #define pr_fmt(fmt) "riscv-imsic: " fmt +#include #include #include #include @@ -593,12 +594,8 @@ static int __init imsic_get_parent_hartid(struct fwnode_handle *fwnode, int rc; struct of_phandle_args parent; - /* - * Currently, only OF fwnode is supported so extend this - * function for ACPI support. - */ if (!is_of_node(fwnode)) - return -EINVAL; + return acpi_get_intc_index_hartid(index, hartid); rc = of_irq_parse_one(to_of_node(fwnode), index, &parent); if (rc) @@ -617,12 +614,8 @@ static int __init imsic_get_parent_hartid(struct fwnode_handle *fwnode, static int __init imsic_get_mmio_resource(struct fwnode_handle *fwnode, u32 index, struct resource *res) { - /* - * Currently, only OF fwnode is supported so extend this - * function for ACPI support. - */ if (!is_of_node(fwnode)) - return -EINVAL; + return acpi_get_imsic_mmio_info(index, res); return of_address_to_resource(to_of_node(fwnode), index, res); } @@ -630,20 +623,15 @@ static int __init imsic_get_mmio_resource(struct fwnode_handle *fwnode, static int __init imsic_parse_fwnode(struct fwnode_handle *fwnode, struct imsic_global_config *global, u32 *nr_parent_irqs, - u32 *nr_mmios) + u32 *nr_mmios, + void *opaque) { + struct acpi_madt_imsic *imsic = (struct acpi_madt_imsic *)opaque; unsigned long hartid; struct resource res; int rc; u32 i; - /* - * Currently, only OF fwnode is supported so extend this - * function for ACPI support. - */ - if (!is_of_node(fwnode)) - return -EINVAL; - *nr_parent_irqs = 0; *nr_mmios = 0; @@ -656,58 +644,66 @@ static int __init imsic_parse_fwnode(struct fwnode_handle *fwnode, return -EINVAL; } - /* Find number of guest index bits in MSI address */ - rc = of_property_read_u32(to_of_node(fwnode), - "riscv,guest-index-bits", - &global->guest_index_bits); - if (rc) - global->guest_index_bits = 0; + if (is_of_node(fwnode)) { + /* Find number of guest index bits in MSI address */ + rc = of_property_read_u32(to_of_node(fwnode), + "riscv,guest-index-bits", + &global->guest_index_bits); + if (rc) + global->guest_index_bits = 0; - /* Find number of HART index bits */ - rc = of_property_read_u32(to_of_node(fwnode), - "riscv,hart-index-bits", - &global->hart_index_bits); - if (rc) { - /* Assume default value */ - global->hart_index_bits = __fls(*nr_parent_irqs); - if (BIT(global->hart_index_bits) < *nr_parent_irqs) - global->hart_index_bits++; - } + /* Find number of HART index bits */ + rc = of_property_read_u32(to_of_node(fwnode), + "riscv,hart-index-bits", + &global->hart_index_bits); + if (rc) { + /* Assume default value */ + global->hart_index_bits = __fls(*nr_parent_irqs); + if (BIT(global->hart_index_bits) < *nr_parent_irqs) + global->hart_index_bits++; + } - /* Find number of group index bits */ - rc = of_property_read_u32(to_of_node(fwnode), - "riscv,group-index-bits", - &global->group_index_bits); - if (rc) - global->group_index_bits = 0; + /* Find number of group index bits */ + rc = of_property_read_u32(to_of_node(fwnode), + "riscv,group-index-bits", + &global->group_index_bits); + if (rc) + global->group_index_bits = 0; - /* - * Find first bit position of group index. - * If not specified assumed the default APLIC-IMSIC configuration. - */ - rc = of_property_read_u32(to_of_node(fwnode), - "riscv,group-index-shift", - &global->group_index_shift); - if (rc) - global->group_index_shift = IMSIC_MMIO_PAGE_SHIFT * 2; + /* + * Find first bit position of group index. + * If not specified assumed the default APLIC-IMSIC configuration. + */ + rc = of_property_read_u32(to_of_node(fwnode), + "riscv,group-index-shift", + &global->group_index_shift); + if (rc) + global->group_index_shift = IMSIC_MMIO_PAGE_SHIFT * 2; + + /* Find number of interrupt identities */ + rc = of_property_read_u32(to_of_node(fwnode), + "riscv,num-ids", + &global->nr_ids); + if (rc) { + pr_err("%pfwP: number of interrupt identities not found\n", fwnode); + return rc; + } - /* Find number of interrupt identities */ - rc = of_property_read_u32(to_of_node(fwnode), - "riscv,num-ids", - &global->nr_ids); - if (rc) { - pr_err("%pfwP: number of interrupt identities not found\n", - fwnode); - return rc; + /* Find number of guest interrupt identities */ + rc = of_property_read_u32(to_of_node(fwnode), + "riscv,num-guest-ids", + &global->nr_guest_ids); + if (rc) + global->nr_guest_ids = global->nr_ids; + } else { + global->guest_index_bits = imsic->guest_index_bits; + global->hart_index_bits = imsic->hart_index_bits; + global->group_index_bits = imsic->group_index_bits; + global->group_index_shift = imsic->group_index_shift; + global->nr_ids = imsic->num_ids; + global->nr_guest_ids = imsic->num_guest_ids; } - /* Find number of guest interrupt identities */ - rc = of_property_read_u32(to_of_node(fwnode), - "riscv,num-guest-ids", - &global->nr_guest_ids); - if (rc) - global->nr_guest_ids = global->nr_ids; - /* Sanity check guest index bits */ i = BITS_PER_LONG - IMSIC_MMIO_PAGE_SHIFT; if (i < global->guest_index_bits) { @@ -775,7 +771,7 @@ static int __init imsic_parse_fwnode(struct fwnode_handle *fwnode, return 0; } -int __init imsic_setup_state(struct fwnode_handle *fwnode) +int __init imsic_setup_state(struct fwnode_handle *fwnode, void *opaque) { int rc, cpu; phys_addr_t base_addr; @@ -817,7 +813,7 @@ int __init imsic_setup_state(struct fwnode_handle *fwnode) } /* Parse IMSIC fwnode */ - rc = imsic_parse_fwnode(fwnode, global, &nr_parent_irqs, &nr_mmios); + rc = imsic_parse_fwnode(fwnode, global, &nr_parent_irqs, &nr_mmios, opaque); if (rc) goto out_free_local; diff --git a/drivers/irqchip/irq-riscv-imsic-state.h b/drivers/irqchip/irq-riscv-imsic-state.h index 8d209e77432e..ee1f52891e89 100644 --- a/drivers/irqchip/irq-riscv-imsic-state.h +++ b/drivers/irqchip/irq-riscv-imsic-state.h @@ -105,6 +105,6 @@ void imsic_vector_debug_show_summary(struct seq_file *m, int ind); int imsic_hwirqs_alloc(unsigned int order); void imsic_hwirqs_free(unsigned int base_hwirq, unsigned int order); -int imsic_setup_state(struct fwnode_handle *fwnode); +int imsic_setup_state(struct fwnode_handle *fwnode, void *opaque); #endif diff --git a/include/linux/irqchip/riscv-imsic.h b/include/linux/irqchip/riscv-imsic.h index cbb7bcd0e4dd..c112e5559d88 100644 --- a/include/linux/irqchip/riscv-imsic.h +++ b/include/linux/irqchip/riscv-imsic.h @@ -84,4 +84,14 @@ static inline const struct imsic_global_config *imsic_get_global_config(void) #endif +#ifdef CONFIG_ACPI +int imsic_platform_acpi_probe(struct fwnode_handle *fwnode); +struct fwnode_handle *imsic_acpi_get_fwnode(struct device *dev); +#else +static inline struct fwnode_handle *imsic_acpi_get_fwnode(struct device *dev) +{ + return NULL; +} +#endif + #endif From patchwork Wed Oct 25 20:23:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 158286 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp218790vqb; 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Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 15/21] irqchip: riscv-aplic: Add ACPI support Date: Thu, 26 Oct 2023 01:53:38 +0530 Message-Id: <20231025202344.581132-16-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=1.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Level: * X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 25 Oct 2023 13:26:45 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780760594472413601 X-GMAIL-MSGID: 1780760594472413601 Add ACPI support in APLIC drivers. In ACPI, IO devices use Global System Interrupts (GSI) which is a flat space split across multiple APLICs. So, the driver also need to provide the mapping from GSI to correct APLIC. Signed-off-by: Sunil V L --- arch/riscv/include/asm/irq.h | 6 ++ drivers/irqchip/irq-riscv-aplic-direct.c | 22 +++-- drivers/irqchip/irq-riscv-aplic-main.c | 105 +++++++++++++++++------ drivers/irqchip/irq-riscv-aplic-main.h | 1 + drivers/irqchip/irq-riscv-aplic-msi.c | 10 ++- 5 files changed, 109 insertions(+), 35 deletions(-) diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h index ef102b6fa86e..00eb8b0333c2 100644 --- a/arch/riscv/include/asm/irq.h +++ b/arch/riscv/include/asm/irq.h @@ -22,6 +22,12 @@ #define APLIC_PLIC_ID(x) ((x) >> 24) #define IDC_CONTEXT_ID(x) ((x) & 0x0000ffff) +#ifdef CONFIG_RISCV_APLIC +struct fwnode_handle *aplic_get_gsi_domain_id(u32 gsi); +#else +static inline struct fwnode_handle *aplic_get_gsi_domain_id(u32 gsi) { return NULL; } +#endif + int __init acpi_get_intc_index_hartid(u32 index, unsigned long *hartid); int acpi_get_ext_intc_parent_hartid(u8 id, u32 idx, unsigned long *hartid); void acpi_get_plic_nr_contexts(u8 id, int *nr_contexts); diff --git a/drivers/irqchip/irq-riscv-aplic-direct.c b/drivers/irqchip/irq-riscv-aplic-direct.c index 9ed2666bfb5e..3902e6d32856 100644 --- a/drivers/irqchip/irq-riscv-aplic-direct.c +++ b/drivers/irqchip/irq-riscv-aplic-direct.c @@ -4,6 +4,7 @@ * Copyright (C) 2022 Ventana Micro Systems Inc. */ +#include #include #include #include @@ -14,6 +15,7 @@ #include #include #include +#include #include "irq-riscv-aplic-main.h" @@ -203,17 +205,20 @@ static int aplic_direct_starting_cpu(unsigned int cpu) static int aplic_direct_parse_parent_hwirq(struct device *dev, u32 index, u32 *parent_hwirq, - unsigned long *parent_hartid) + unsigned long *parent_hartid, + struct aplic_priv *priv) { struct of_phandle_args parent; int rc; - /* - * Currently, only OF fwnode is supported so extend this - * function for ACPI support. - */ - if (!is_of_node(dev->fwnode)) - return -EINVAL; + if (!is_of_node(dev->fwnode)) { + rc = acpi_get_ext_intc_parent_hartid(priv->id, index, parent_hartid); + if (rc) + return rc; + + *parent_hwirq = RV_IRQ_EXT; + return 0; + } rc = of_irq_parse_one(to_of_node(dev->fwnode), index, &parent); if (rc) @@ -251,7 +256,7 @@ int aplic_direct_setup(struct device *dev, void __iomem *regs) /* Setup per-CPU IDC and target CPU mask */ for (i = 0; i < priv->nr_idcs; i++) { - rc = aplic_direct_parse_parent_hwirq(dev, i, &hwirq, &hartid); + rc = aplic_direct_parse_parent_hwirq(dev, i, &hwirq, &hartid, priv); if (rc) { dev_warn(dev, "parent irq for IDC%d not found\n", i); continue; @@ -335,6 +340,7 @@ int aplic_direct_setup(struct device *dev, void __iomem *regs) return -ENOMEM; } + dev_set_drvdata(dev, priv); /* Advertise the interrupt controller */ dev_info(dev, "%d interrupts directly connected to %d CPUs\n", priv->nr_irqs, priv->nr_idcs); diff --git a/drivers/irqchip/irq-riscv-aplic-main.c b/drivers/irqchip/irq-riscv-aplic-main.c index d1b342b66551..f0ba1411c95e 100644 --- a/drivers/irqchip/irq-riscv-aplic-main.c +++ b/drivers/irqchip/irq-riscv-aplic-main.c @@ -4,12 +4,15 @@ * Copyright (C) 2022 Ventana Micro Systems Inc. */ +#include #include #include #include #include #include #include +#include +#include #include "irq-riscv-aplic-main.h" @@ -137,38 +140,44 @@ int aplic_setup_priv(struct aplic_priv *priv, struct device *dev, void __iomem *regs) { struct of_phandle_args parent; + struct acpi_madt_aplic *aplic; int rc; - /* - * Currently, only OF fwnode is supported so extend this - * function for ACPI support. - */ - if (!is_of_node(dev->fwnode)) - return -EINVAL; - /* Save device pointer and register base */ priv->dev = dev; priv->regs = regs; - /* Find out number of interrupt sources */ - rc = of_property_read_u32(to_of_node(dev->fwnode), - "riscv,num-sources", - &priv->nr_irqs); - if (rc) { - dev_err(dev, "failed to get number of interrupt sources\n"); - return rc; - } - - /* - * Find out number of IDCs based on parent interrupts - * - * If "msi-parent" property is present then we ignore the - * APLIC IDCs which forces the APLIC driver to use MSI mode. - */ - if (!of_property_present(to_of_node(dev->fwnode), "msi-parent")) { - while (!of_irq_parse_one(to_of_node(dev->fwnode), - priv->nr_idcs, &parent)) - priv->nr_idcs++; + if (is_of_node(dev->fwnode)) { + /* Find out number of interrupt sources */ + rc = of_property_read_u32(to_of_node(dev->fwnode), + "riscv,num-sources", + &priv->nr_irqs); + if (rc) { + dev_err(dev, "failed to get number of interrupt sources\n"); + return rc; + } + + /* + * Find out number of IDCs based on parent interrupts + * + * If "msi-parent" property is present then we ignore the + * APLIC IDCs which forces the APLIC driver to use MSI mode. + */ + if (!of_property_present(to_of_node(dev->fwnode), "msi-parent")) { + while (!of_irq_parse_one(to_of_node(dev->fwnode), + priv->nr_idcs, &parent)) + priv->nr_idcs++; + } + } else { + aplic = *(struct acpi_madt_aplic **)dev_get_platdata(dev); + if (!aplic) { + dev_err(dev, "APLIC platform data is NULL!\n"); + return -1; + } + priv->gsi_base = aplic->gsi_base; + priv->nr_irqs = aplic->num_sources; + priv->nr_idcs = aplic->num_idcs; + priv->id = aplic->id; } /* Setup initial state APLIC interrupts */ @@ -177,9 +186,36 @@ int aplic_setup_priv(struct aplic_priv *priv, struct device *dev, return 0; } +#ifdef CONFIG_ACPI + +LIST_HEAD(aplic_list); +struct aplic_priv_list { + struct aplic_priv *priv; + struct list_head list; +}; + +struct fwnode_handle *aplic_get_gsi_domain_id(u32 gsi) +{ + struct aplic_priv_list *aplic_element; + struct list_head *i, *tmp; + + /* Find the APLIC that manages this GSI. */ + list_for_each_safe(i, tmp, &aplic_list) { + aplic_element = list_entry(i, struct aplic_priv_list, list); + if (gsi >= aplic_element->priv->gsi_base && + gsi < (aplic_element->priv->gsi_base + aplic_element->priv->nr_irqs)) + return aplic_element->priv->dev->fwnode; + } + + return NULL; +} + +#endif + static int aplic_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; + struct aplic_priv *priv; bool msi_mode = false; struct resource *res; void __iomem *regs; @@ -204,6 +240,9 @@ static int aplic_probe(struct platform_device *pdev) if (is_of_node(dev->fwnode)) msi_mode = of_property_present(to_of_node(dev->fwnode), "msi-parent"); + else + msi_mode = imsic_acpi_get_fwnode(NULL) ? 1 : 0; + if (msi_mode) rc = aplic_msi_setup(dev, regs); else @@ -214,6 +253,20 @@ static int aplic_probe(struct platform_device *pdev) return rc; } +#ifdef CONFIG_ACPI + struct aplic_priv_list *aplic_element; + + priv = dev_get_drvdata(dev); + if (priv) { + aplic_element = devm_kzalloc(dev, sizeof(*aplic_element), GFP_KERNEL); + if (!aplic_element) + return -ENOMEM; + + aplic_element->priv = priv; + list_add_tail(&aplic_element->list, &aplic_list); + } +#endif + return 0; } diff --git a/drivers/irqchip/irq-riscv-aplic-main.h b/drivers/irqchip/irq-riscv-aplic-main.h index 78267ec58098..dc022e89bc97 100644 --- a/drivers/irqchip/irq-riscv-aplic-main.h +++ b/drivers/irqchip/irq-riscv-aplic-main.h @@ -28,6 +28,7 @@ struct aplic_priv { u32 gsi_base; u32 nr_irqs; u32 nr_idcs; + u32 id; void __iomem *regs; struct aplic_msicfg msicfg; }; diff --git a/drivers/irqchip/irq-riscv-aplic-msi.c b/drivers/irqchip/irq-riscv-aplic-msi.c index 086d00e0429e..433ab2f270d9 100644 --- a/drivers/irqchip/irq-riscv-aplic-msi.c +++ b/drivers/irqchip/irq-riscv-aplic-msi.c @@ -178,6 +178,7 @@ static void aplic_msi_write_msg(struct msi_desc *desc, struct msi_msg *msg) int aplic_msi_setup(struct device *dev, void __iomem *regs) { const struct imsic_global_config *imsic_global; + struct irq_domain *msi_domain; struct irq_domain *irqdomain; struct aplic_priv *priv; struct aplic_msicfg *mc; @@ -261,8 +262,14 @@ int aplic_msi_setup(struct device *dev, void __iomem *regs) * IMSIC and the IMSIC MSI domains are created later through * the platform driver probing so we set it explicitly here. */ - if (is_of_node(dev->fwnode)) + if (is_of_node(dev->fwnode)) { of_msi_configure(dev, to_of_node(dev->fwnode)); + } else { + msi_domain = irq_find_matching_fwnode(imsic_acpi_get_fwnode(dev), + DOMAIN_BUS_PLATFORM_MSI); + if (msi_domain) + dev_set_msi_domain(dev, msi_domain); + } } /* Create irq domain instance for the APLIC MSI-mode */ @@ -276,6 +283,7 @@ int aplic_msi_setup(struct device *dev, void __iomem *regs) return -ENOMEM; } + dev_set_drvdata(dev, priv); /* Advertise the interrupt controller */ pa = priv->msicfg.base_ppn << APLIC_xMSICFGADDR_PPN_SHIFT; dev_info(dev, "%d interrupts forwared to MSI base %pa\n", From patchwork Wed Oct 25 20:23:39 2023 Content-Type: text/plain; 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Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 16/21] irqchip: irq-sifive-plic: Add ACPI support Date: Thu, 26 Oct 2023 01:53:39 +0530 Message-Id: <20231025202344.581132-17-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=1.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Level: * X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 25 Oct 2023 13:26:53 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780760599170773077 X-GMAIL-MSGID: 1780760599170773077 Add ACPI support in PLIC driver. In ACPI, IO devices use Global System Interrupts (GSI) which is a flat space split across multiple PLICs. So, the driver also need to provide the mapping from GSI to correct PLIC. Signed-off-by: Sunil V L Co-developed-by: Haibo Xu Signed-off-by: Haibo Xu --- arch/riscv/include/asm/irq.h | 6 ++ drivers/irqchip/irq-sifive-plic.c | 113 +++++++++++++++++++++++++----- 2 files changed, 101 insertions(+), 18 deletions(-) diff --git a/arch/riscv/include/asm/irq.h b/arch/riscv/include/asm/irq.h index 00eb8b0333c2..eff442766c87 100644 --- a/arch/riscv/include/asm/irq.h +++ b/arch/riscv/include/asm/irq.h @@ -28,6 +28,12 @@ struct fwnode_handle *aplic_get_gsi_domain_id(u32 gsi); static inline struct fwnode_handle *aplic_get_gsi_domain_id(u32 gsi) { return NULL; } #endif +#ifdef CONFIG_SIFIVE_PLIC +struct fwnode_handle *plic_get_gsi_domain_id(u32 gsi); +#else +static inline struct fwnode_handle *plic_get_gsi_domain_id(u32 gsi) { return NULL; } +#endif + int __init acpi_get_intc_index_hartid(u32 index, unsigned long *hartid); int acpi_get_ext_intc_parent_hartid(u8 id, u32 idx, unsigned long *hartid); void acpi_get_plic_nr_contexts(u8 id, int *nr_contexts); diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index c8f8a8cdcce1..9c61084a74eb 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -3,6 +3,7 @@ * Copyright (C) 2017 SiFive * Copyright (C) 2018 Christoph Hellwig */ +#include #include #include #include @@ -70,6 +71,8 @@ struct plic_priv { unsigned long plic_quirks; unsigned int nr_irqs; unsigned long *prio_save; + u32 gsi_base; + int id; }; struct plic_handler { @@ -316,6 +319,10 @@ static int plic_irq_domain_translate(struct irq_domain *d, { struct plic_priv *priv = d->host_data; + /* For DT, gsi_base is always zero. */ + if (fwspec->param[0] >= priv->gsi_base) + fwspec->param[0] = fwspec->param[0] - priv->gsi_base; + if (test_bit(PLIC_QUIRK_EDGE_INTERRUPT, &priv->plic_quirks)) return irq_domain_translate_twocell(d, fwspec, hwirq, type); @@ -417,17 +424,31 @@ static const struct of_device_id plic_match[] = { }; static int plic_parse_nr_irqs_and_contexts(struct platform_device *pdev, - u32 *nr_irqs, u32 *nr_contexts) + u32 *nr_irqs, u32 *nr_contexts, + u32 *gsi_base, u32 *id) { struct device *dev = &pdev->dev; + struct acpi_madt_plic *plic; int rc; - /* - * Currently, only OF fwnode is supported so extend this - * function for ACPI support. - */ - if (!is_of_node(dev->fwnode)) - return -EINVAL; + if (!is_of_node(dev->fwnode)) { + plic = *(struct acpi_madt_plic **)dev_get_platdata(dev); + if (!plic) { + dev_err(dev, "PLIC platform data is NULL!\n"); + return -EINVAL; + } + + *nr_irqs = plic->num_irqs; + acpi_get_plic_nr_contexts(plic->id, nr_contexts); + if (WARN_ON(!*nr_contexts)) { + dev_err(dev, "no PLIC context available\n"); + return -EINVAL; + } + + *gsi_base = plic->gsi_base; + *id = plic->id; + return 0; + } rc = of_property_read_u32(to_of_node(dev->fwnode), "riscv,ndev", nr_irqs); @@ -442,23 +463,28 @@ static int plic_parse_nr_irqs_and_contexts(struct platform_device *pdev, return -EINVAL; } + *gsi_base = 0; + *id = 0; + return 0; } static int plic_parse_context_parent_hwirq(struct platform_device *pdev, - u32 context, u32 *parent_hwirq, + u32 context, u32 id, u32 *parent_hwirq, unsigned long *parent_hartid) { struct device *dev = &pdev->dev; struct of_phandle_args parent; int rc; - /* - * Currently, only OF fwnode is supported so extend this - * function for ACPI support. - */ - if (!is_of_node(dev->fwnode)) - return -EINVAL; + if (!is_of_node(dev->fwnode)) { + rc = acpi_get_ext_intc_parent_hartid(id, context, parent_hartid); + if (rc) + return rc; + + *parent_hwirq = RV_IRQ_EXT; + return 0; + } rc = of_irq_parse_one(to_of_node(dev->fwnode), context, &parent); if (rc) @@ -472,6 +498,32 @@ static int plic_parse_context_parent_hwirq(struct platform_device *pdev, return 0; } +#ifdef CONFIG_ACPI + +LIST_HEAD(plic_list); +struct plic_priv_list { + struct plic_priv *priv; + struct list_head list; +}; + +struct fwnode_handle *plic_get_gsi_domain_id(u32 gsi) +{ + struct plic_priv_list *plic_element; + struct list_head *i, *tmp; + + /* Find the PLIC that manages this GSI. */ + list_for_each_safe(i, tmp, &plic_list) { + plic_element = list_entry(i, struct plic_priv_list, list); + if (gsi >= plic_element->priv->gsi_base && + gsi <= (plic_element->priv->gsi_base + plic_element->priv->nr_irqs)) + return plic_element->priv->dev->fwnode; + } + + return NULL; +} + +#endif + static int plic_probe(struct platform_device *pdev) { int rc, nr_contexts, nr_handlers = 0, i, cpu; @@ -483,7 +535,9 @@ static int plic_probe(struct platform_device *pdev) struct plic_priv *priv; irq_hw_number_t hwirq; struct resource *res; + int id, context_id; bool cpuhp_setup; + u32 gsi_base; if (is_of_node(dev->fwnode)) { const struct of_device_id *id; @@ -510,19 +564,21 @@ static int plic_probe(struct platform_device *pdev) return -EIO; } - rc = plic_parse_nr_irqs_and_contexts(pdev, &nr_irqs, &nr_contexts); + rc = plic_parse_nr_irqs_and_contexts(pdev, &nr_irqs, &nr_contexts, &gsi_base, &id); if (rc) { dev_err(dev, "failed to parse irqs and contexts\n"); return rc; } priv->nr_irqs = nr_irqs; + priv->gsi_base = gsi_base; + priv->id = id; priv->prio_save = devm_bitmap_zalloc(dev, nr_irqs, GFP_KERNEL); if (!priv->prio_save) return -ENOMEM; for (i = 0; i < nr_contexts; i++) { - rc = plic_parse_context_parent_hwirq(pdev, i, + rc = plic_parse_context_parent_hwirq(pdev, i, priv->id, &parent_hwirq, &hartid); if (rc) { dev_warn(dev, "hwirq for context%d not found\n", i); @@ -574,13 +630,23 @@ static int plic_probe(struct platform_device *pdev) goto done; } + if (is_of_node(dev->fwnode)) { + context_id = i; + } else { + rc = acpi_get_plic_context(priv->id, i, &context_id); + if (rc) { + dev_warn(dev, "invalid context id for context%d\n", i); + continue; + } + } + cpumask_set_cpu(cpu, &priv->lmask); handler->present = true; handler->hart_base = priv->regs + CONTEXT_BASE + - i * CONTEXT_SIZE; + context_id * CONTEXT_SIZE; raw_spin_lock_init(&handler->enable_lock); handler->enable_base = priv->regs + CONTEXT_ENABLE_BASE + - i * CONTEXT_ENABLE_SIZE; + context_id * CONTEXT_ENABLE_SIZE; handler->priv = priv; handler->enable_save = devm_kcalloc(dev, @@ -624,6 +690,17 @@ static int plic_probe(struct platform_device *pdev) register_syscore_ops(&plic_irq_syscore_ops); } +#ifdef CONFIG_ACPI + struct plic_priv_list *plic_element; + + plic_element = devm_kzalloc(dev, sizeof(*plic_element), GFP_KERNEL); + if (!plic_element) + return -ENOMEM; + + plic_element->priv = priv; + list_add_tail(&plic_element->list, &plic_list); +#endif + dev_info(dev, "mapped %d interrupts with %d handlers for" " %d contexts.\n", nr_irqs, nr_handlers, nr_contexts); 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Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 17/21] ACPI: bus: Add RINTC IRQ model for RISC-V Date: Thu, 26 Oct 2023 01:53:40 +0530 Message-Id: <20231025202344.581132-18-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=2.7 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Level: ** X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Wed, 25 Oct 2023 13:27:28 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780760603768197084 X-GMAIL-MSGID: 1780760603768197084 Add the IRQ model for RISC-V INTC so that acpi_set_irq_model can use this for RISC-V. Signed-off-by: Sunil V L --- drivers/acpi/bus.c | 3 +++ include/linux/acpi.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c index a4aa53b7e2bb..9eace6c7042e 100644 --- a/drivers/acpi/bus.c +++ b/drivers/acpi/bus.c @@ -1158,6 +1158,9 @@ static int __init acpi_bus_init_irq(void) case ACPI_IRQ_MODEL_LPIC: message = "LPIC"; break; + case ACPI_IRQ_MODEL_RINTC: + message = "RINTC"; + break; default: pr_info("Unknown interrupt routing model\n"); return -ENODEV; diff --git a/include/linux/acpi.h b/include/linux/acpi.h index 4ad256a0039c..19c3dda9c2ed 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -95,6 +95,7 @@ enum acpi_irq_model_id { ACPI_IRQ_MODEL_PLATFORM, ACPI_IRQ_MODEL_GIC, ACPI_IRQ_MODEL_LPIC, + ACPI_IRQ_MODEL_RINTC, ACPI_IRQ_MODEL_COUNT }; From patchwork Wed Oct 25 20:23:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 158289 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp218905vqb; Wed, 25 Oct 2023 13:27:38 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHqdxHYXURW4bD017WzIDcCTkIEZiBhQbp/kKTeJpK5tJacVa3CgaZ65LwgzrVZfqeDbWs+ X-Received: by 2002:a05:690c:95:b0:59b:ec85:54ee with SMTP id be21-20020a05690c009500b0059bec8554eemr17733704ywb.39.1698265657872; Wed, 25 Oct 2023 13:27:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698265657; cv=none; d=google.com; s=arc-20160816; b=QoQBhsq0W5ZiqkmYFQfNiHOe1uZjKnwYCLhKBMq+5YvJH1eDtgkUvK/aeoGRxbgpoH buGXiFymktH/M48R5W5mjD0MEb3Mit11ZblYxzW8xoSWS0ZLsLTbIXs1rO8xg8kzGRkR cWLZz0iLB+4PUtXJ3n7KOrK6urM1OqMSs6uGw1yhxZQMlGz1iHPgR6hsvtRg6sA0zJgj wMO8PwhYqB6nHgtJ9WWCwY7UxTLOJIJ26VvBeuZO4wYfNnVHtqaUCMDViEEVqW3pPxXt PUTsVtmAfCoGrl1mNuMrzPm4xlz1i1pesVtzFsw8EkwzwbBUPQ9xte9AnuGTS1SsImaa sLTA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=VwZ9IOYC0gRC/owt7RZ2EBdGuffYJiDuVuQ5+XRLwVw=; fh=/fEAwM0ftwV2z3MN/iSYq1lv8IFPZ2fY8Kg8RoFcxjU=; b=0PijKfDlOVW0tUDy4PEKxnWfMb0KOKjaJgRh3U+XXxFwyj6oeTe6NkMaHTO2mctmgs OUVCkN/XflAac8T6UsVPYsRsM/zcyHHTC5+uLVqv9d4+1r5fUze9qn6z4GgIFAl/Tu/P HUqLFBrXezI8sMVPL6v2fHEHmpi043DNfS84YavEnXqpvQvyN6FdefyKFSDDs9uDriDc Vh+qltMg7BmJpmB4vt894unmnHTwI0vt/cn/05feMdzqhh3XJhJGDkkQCbCROkAucOIX bgRvmFWeA3uJpO0oCOL2O/dw7ueOkvOFqxREpne1XiMpFB6cT8ZtY66818EbTx/t0WAM FjZQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b="gni9otB/"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from pete.vger.email (pete.vger.email. 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Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 18/21] irqchip: riscv-intc: Set ACPI irqmodel Date: Thu, 26 Oct 2023 01:53:41 +0530 Message-Id: <20231025202344.581132-19-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=2.7 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Level: ** X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Wed, 25 Oct 2023 13:27:35 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780760610856073881 X-GMAIL-MSGID: 1780760610856073881 INTC being the root interrupt controller, set the ACPI irqmodel with callback function to get the GSI domain id. Signed-off-by: Sunil V L --- drivers/irqchip/irq-riscv-intc.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index f3aaecde12dd..627723d72b01 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -273,6 +273,17 @@ int acpi_get_imsic_mmio_info(u32 index, struct resource *res) return 0; } +static struct fwnode_handle *riscv_get_gsi_domain_id(u32 gsi) +{ + struct fwnode_handle *gsi_fwnode = NULL; + + gsi_fwnode = aplic_get_gsi_domain_id(gsi); + if (!gsi_fwnode) + gsi_fwnode = plic_get_gsi_domain_id(gsi); + + return gsi_fwnode; +} + static int __init riscv_intc_acpi_init(union acpi_subtable_headers *header, const unsigned long end) { @@ -318,6 +329,7 @@ static int __init riscv_intc_acpi_init(union acpi_subtable_headers *header, * unsupported. Once IMSIC is probed, MSI support will be set. */ pci_no_msi(); + acpi_set_irq_model(ACPI_IRQ_MODEL_RINTC, riscv_get_gsi_domain_id); return 0; } From patchwork Wed Oct 25 20:23:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 158290 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp218925vqb; Wed, 25 Oct 2023 13:27:40 -0700 (PDT) X-Google-Smtp-Source: AGHT+IENzbyVetR1iHIv/5DmOZXp0wvvbAIJ3ev15kUsybVRDi9bri4pRIBmcM7jGO3xm0gxb8i8 X-Received: by 2002:a05:6830:310f:b0:6ce:40f1:e9f0 with SMTP id b15-20020a056830310f00b006ce40f1e9f0mr16211334ots.11.1698265659893; Wed, 25 Oct 2023 13:27:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698265659; cv=none; d=google.com; s=arc-20160816; b=nRHgvkKmMuv9PyGmP+x1r5JPk4ptyPnbDFuBbPxZx9YPmofDp8h/gU/3WTh7MAkSYe bDIZHNYGbLt+RXyLaFved3Ve+7pFpQayocpd6u3PD/2f7KOV5ZqTvkEnaMIK8yfC1lY6 oJAedeTsaVPW42GsnXxzg7ekSRi48HhyRaoiZCS5YE4yY4VY0BjKoSciZKC0Eb0zbyCH N8qNXo0Kpjgf/rdb9a1ZKHU6bM1Yyosplco/vPAjOveqfibRgF057qKwW00FE09P1k/b CqES9XOqFbU3wx26QvlhMTBFiisS+yqGCrI4fGlgr7HpZMt3eBL5bNgbexuOmTmvObDg N6FQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=6iZbx/IhbkeIBI8+FFzeu8yqPtMDZXtB3E1NSIPmMj8=; fh=/fEAwM0ftwV2z3MN/iSYq1lv8IFPZ2fY8Kg8RoFcxjU=; b=yutUZ/BgKKWsY0xQVYm31oBYKroTLjEKmE1SqL58OrW53phlrFJcCOpM5o3yv+/uE5 8tQ2xw9xscauq6XbfNQmQb43DdWFGHIgAy3L9vmYbGXplMJ3lwzqQzmuGmZVacp9s4ry Ofer5ULZQ6pQ7bxzQy6yF+vO+vUN9UKo0rMRGTm3aqHkvjIWLoE/3ucQWPUTSuV3ge9R 4dmf5hLmoOQ/lfjfgUDeEyV8U+ft9f9Enjjjs8Ky125CmGOSm7CjMC53o66ZTyKiLdOk Q9G1dnjOfXgn90LA3ZJmV4Ta4tYC1venRIcQusN77mpUa8RD1IAPEU227M9d+s8U7k7y jGGg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=QEHaA3wc; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from howler.vger.email (howler.vger.email. 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Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 19/21] ACPI: bus: Add acpi_riscv_init function Date: Thu, 26 Oct 2023 01:53:42 +0530 Message-Id: <20231025202344.581132-20-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=2.7 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Level: ** X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on howler.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Wed, 25 Oct 2023 13:27:36 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780760612076159442 X-GMAIL-MSGID: 1780760612076159442 Add a new function for RISC-V to do any architecture specific initialization. This function will be used to create platform devices like APLIC, PLIC, RISC-V IOMMU etc. This is similar to acpi_arm_init(). Signed-off-by: Sunil V L --- drivers/acpi/bus.c | 1 + drivers/acpi/riscv/Makefile | 2 +- drivers/acpi/riscv/init.c | 12 ++++++++++++ include/linux/acpi.h | 6 ++++++ 4 files changed, 20 insertions(+), 1 deletion(-) create mode 100644 drivers/acpi/riscv/init.c diff --git a/drivers/acpi/bus.c b/drivers/acpi/bus.c index 9eace6c7042e..f7ac0caf04cf 100644 --- a/drivers/acpi/bus.c +++ b/drivers/acpi/bus.c @@ -1417,6 +1417,7 @@ static int __init acpi_init(void) acpi_hest_init(); acpi_ghes_init(); acpi_arm_init(); + acpi_riscv_init(); acpi_scan_init(); acpi_ec_init(); acpi_debugfs_init(); diff --git a/drivers/acpi/riscv/Makefile b/drivers/acpi/riscv/Makefile index f80b3da230e9..c4d679b1359e 100644 --- a/drivers/acpi/riscv/Makefile +++ b/drivers/acpi/riscv/Makefile @@ -1,2 +1,2 @@ # SPDX-License-Identifier: GPL-2.0-only -obj-y += rhct.o irq.o +obj-y += rhct.o irq.o init.o diff --git a/drivers/acpi/riscv/init.c b/drivers/acpi/riscv/init.c new file mode 100644 index 000000000000..b5807bbdb171 --- /dev/null +++ b/drivers/acpi/riscv/init.c @@ -0,0 +1,12 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023, Ventana Micro Systems Inc + * Author: Sunil V L + * + */ + +#include + +void __init acpi_riscv_init(void) +{ +} diff --git a/include/linux/acpi.h b/include/linux/acpi.h index 19c3dda9c2ed..c408070ac52e 100644 --- a/include/linux/acpi.h +++ b/include/linux/acpi.h @@ -1527,6 +1527,12 @@ void acpi_arm_init(void); static inline void acpi_arm_init(void) { } #endif +#ifdef CONFIG_RISCV +void acpi_riscv_init(void); +#else +static inline void acpi_riscv_init(void) { } +#endif + #ifdef CONFIG_ACPI_PCC void acpi_init_pcc(void); #else From patchwork Wed Oct 25 20:23:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 158291 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp219000vqb; Wed, 25 Oct 2023 13:27:50 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH7Psmp0vlL38z/pB+0i15zztJo3Uo2d5RRdnxeThe9c1fgOYHcbSAJkfb6BBFK6gFmrmUN X-Received: by 2002:aca:2110:0:b0:3a7:1e86:e83f with SMTP id 16-20020aca2110000000b003a71e86e83fmr16534732oiz.51.1698265670165; Wed, 25 Oct 2023 13:27:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698265670; cv=none; d=google.com; s=arc-20160816; b=Kx/E53Y8NG4jG2IQ53iBgkNC3QxCxyP3xaR4817cDu2t9QTkccGJnM7K8THjYVpU9Y hL9PtrNDu8ygaTsQDkZiE6UPx7ArH2Fh4ynKZZVIt5o69nsI5nnAxgTmYvOtjjCTSI/s Gq2yER238LC5zCINVdub7OvA9YBgmEMCOK5ccDH5EYb/YQ+KhpnhDx+3a+hl+VR4zzbD rPeWuMMTlu/u0Hm85apA+LvUBn/IZHcNG02CQGpaLYNIfjVAfeR5ZnSqvDjeRvJqf5+E 5aaehuHaCzmPRX3f++CNZUy9cvoVD5QcUTSyD/q2zuCkpoxmYdmOu0A7tqE2iEE0Ao93 J7/g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=YyAbjmaR4eN/4ltFJMCVbHeHJN24CQKSdc3guUQ+sXY=; fh=/fEAwM0ftwV2z3MN/iSYq1lv8IFPZ2fY8Kg8RoFcxjU=; b=VN2PtO92q04H/TgakUgkp03K9kW8A+/BPtvomkik5zKE8MhHEuxO9FkVQ4vjBek7qj BVS5eM+QRtEpWzNqfim2gkUnYvXkDptmyTQtQDqyKxVeMl2AxcTwXBOx6g1Kc2UxvJ0v xT0MCwfJpHnXV+WwXur4an8zXWWpCKzsJhawQOkUokpPlVgA0f+DQ9aHYLkHC/VlXANA 0hSuo0Mg12aFk8kmfgZ+K1U1Q+ckzEOsLug4uOSkt90baDVkysIOzQXUahZkFrmvf+vx NRiTgrWCFbQL6qkFuXrmXGAVvBGpYplhMlmuTXKM6xZDyKCTf+98vdsKnfi0fpZjVn5H H9DA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=lYxzdUsu; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from groat.vger.email (groat.vger.email. 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Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 20/21] ACPI: RISC-V: Create APLIC platform device Date: Thu, 26 Oct 2023 01:53:43 +0530 Message-Id: <20231025202344.581132-21-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=2.7 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Level: ** X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Wed, 25 Oct 2023 13:27:47 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780760623091452564 X-GMAIL-MSGID: 1780760623091452564 Since APLIC needs to be a platform device, probe the MADT and create platform devices for each APLIC in the system. Signed-off-by: Sunil V L --- drivers/acpi/riscv/init.c | 2 ++ drivers/acpi/riscv/init.h | 5 +++ drivers/acpi/riscv/irq.c | 74 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 81 insertions(+) create mode 100644 drivers/acpi/riscv/init.h diff --git a/drivers/acpi/riscv/init.c b/drivers/acpi/riscv/init.c index b5807bbdb171..e7eff7ab1474 100644 --- a/drivers/acpi/riscv/init.c +++ b/drivers/acpi/riscv/init.c @@ -6,7 +6,9 @@ */ #include +#include "init.h" void __init acpi_riscv_init(void) { + riscv_acpi_aplic_platform_init(); } diff --git a/drivers/acpi/riscv/init.h b/drivers/acpi/riscv/init.h new file mode 100644 index 000000000000..17bcf0baaadb --- /dev/null +++ b/drivers/acpi/riscv/init.h @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include + +void __init riscv_acpi_imsic_platform_init(void); +void __init riscv_acpi_aplic_platform_init(void); diff --git a/drivers/acpi/riscv/irq.c b/drivers/acpi/riscv/irq.c index 36e0525b3235..fbccecdcbf8b 100644 --- a/drivers/acpi/riscv/irq.c +++ b/drivers/acpi/riscv/irq.c @@ -6,6 +6,8 @@ */ #include +#include +#include #include static int irqchip_cmp_func(const void *in0, const void *in1) @@ -30,3 +32,75 @@ void arch_sort_irqchip_probe(struct acpi_probe_entry *ap_head, int nr) return; sort(ape, nr, sizeof(*ape), irqchip_cmp_func, NULL); } + +static int __init irqchip_add_platform_device(char *irqchip_name, u32 irqchip_id, + resource_size_t iomem_res_start, + resource_size_t iomem_res_size, + union acpi_subtable_headers *header) +{ + struct platform_device *pdev; + struct fwnode_handle *fn; + struct resource *res; + int ret; + + fn = irq_domain_alloc_named_id_fwnode(irqchip_name, irqchip_id); + if (!fn) + return -ENOMEM; + + pdev = platform_device_alloc(irqchip_name, irqchip_id); + if (!pdev) { + irq_domain_free_fwnode(fn); + return -ENOMEM; + } + + res = kcalloc(1, sizeof(*res), GFP_KERNEL); + if (!res) { + irq_domain_free_fwnode(fn); + platform_device_put(pdev); + return -ENOMEM; + } + + res->start = iomem_res_start; + res->end = res->start + iomem_res_size - 1; + res->flags = IORESOURCE_MEM; + ret = platform_device_add_resources(pdev, res, 1); + /* + * Resources are duplicated in platform_device_add_resources, + * free their allocated memory + */ + kfree(res); + + /* + * Add copy of aplic pointer so that platform driver get aplic details. + */ + ret = platform_device_add_data(pdev, &header, sizeof(header)); + if (ret) { + irq_domain_free_fwnode(fn); + platform_device_put(pdev); + return ret; + } + + pdev->dev.fwnode = fn; + ret = platform_device_add(pdev); + if (ret) { + irq_domain_free_fwnode(fn); + platform_device_put(pdev); + return ret; + } + + return 0; +} + +static int __init aplic_parse_madt(union acpi_subtable_headers *header, + const unsigned long end) +{ + struct acpi_madt_aplic *aplic = (struct acpi_madt_aplic *)header; + + return irqchip_add_platform_device("riscv-aplic", aplic->id, aplic->base_addr, + aplic->size, header); +} + +void __init riscv_acpi_aplic_platform_init(void) +{ + acpi_table_parse_madt(ACPI_MADT_TYPE_APLIC, aplic_parse_madt, 0); +} From patchwork Wed Oct 25 20:23:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 158292 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:d641:0:b0:403:3b70:6f57 with SMTP id cy1csp219069vqb; Wed, 25 Oct 2023 13:27:57 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF07ruXp6VcCMhIhXBGVPv38lVxJaJ6pSlhG5xD275fzK65k4SrnId5lLVkyhzFVa3CEDS/ X-Received: by 2002:a05:6902:1242:b0:d9c:aa50:2b5a with SMTP id t2-20020a056902124200b00d9caa502b5amr19616384ybu.53.1698265677604; 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Wysocki" , Len Brown , Bjorn Helgaas , Anup Patel , Thomas Gleixner , Greg Kroah-Hartman , Jiri Slaby , Conor Dooley , Andrew Jones , Atish Kumar Patra , Haibo Xu , Sunil V L Subject: [RFC PATCH v2 21/21] ACPI: RISC-V: Create PLIC platform device Date: Thu, 26 Oct 2023 01:53:44 +0530 Message-Id: <20231025202344.581132-22-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20231025202344.581132-1-sunilvl@ventanamicro.com> References: <20231025202344.581132-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=1.2 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_SBL_CSS,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Level: * X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 25 Oct 2023 13:27:56 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780760631332155767 X-GMAIL-MSGID: 1780760631332155767 Since PLIC needs to be a platform device, probe the MADT and create platform devices for each PLIC in the system. Signed-off-by: Sunil V L --- drivers/acpi/riscv/init.c | 1 + drivers/acpi/riscv/init.h | 1 + drivers/acpi/riscv/irq.c | 14 ++++++++++++++ 3 files changed, 16 insertions(+) diff --git a/drivers/acpi/riscv/init.c b/drivers/acpi/riscv/init.c index e7eff7ab1474..c6fd4097e8ae 100644 --- a/drivers/acpi/riscv/init.c +++ b/drivers/acpi/riscv/init.c @@ -11,4 +11,5 @@ void __init acpi_riscv_init(void) { riscv_acpi_aplic_platform_init(); + riscv_acpi_plic_platform_init(); } diff --git a/drivers/acpi/riscv/init.h b/drivers/acpi/riscv/init.h index 17bcf0baaadb..b4b305d83b3a 100644 --- a/drivers/acpi/riscv/init.h +++ b/drivers/acpi/riscv/init.h @@ -3,3 +3,4 @@ void __init riscv_acpi_imsic_platform_init(void); void __init riscv_acpi_aplic_platform_init(void); +void __init riscv_acpi_plic_platform_init(void); diff --git a/drivers/acpi/riscv/irq.c b/drivers/acpi/riscv/irq.c index fbccecdcbf8b..90b0738e2b9f 100644 --- a/drivers/acpi/riscv/irq.c +++ b/drivers/acpi/riscv/irq.c @@ -104,3 +104,17 @@ void __init riscv_acpi_aplic_platform_init(void) { acpi_table_parse_madt(ACPI_MADT_TYPE_APLIC, aplic_parse_madt, 0); } + +static int __init plic_parse_madt(union acpi_subtable_headers *header, + const unsigned long end) +{ + struct acpi_madt_plic *plic = (struct acpi_madt_plic *)header; + + return irqchip_add_platform_device("riscv-plic", plic->id, plic->base_addr, + plic->size, header); +} + +void __init riscv_acpi_plic_platform_init(void) +{ + acpi_table_parse_madt(ACPI_MADT_TYPE_PLIC, plic_parse_madt, 0); +}