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[37.212.12.58]) by smtp.gmail.com with ESMTPSA id p11-20020a05640210cb00b004637489cf08sm4994444edu.88.2022.11.07.20.53.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Nov 2022 20:53:54 -0800 (PST) From: Siarhei Volkau Cc: Siarhei Volkau , Paul Cercueil , Rob Herring , Krzysztof Kozlowski , Thomas Bogendoerfer , Ulf Hansson , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org Subject: [PATCH 1/2] mmc: jz4740: Don't change parent clock rate for some SoCs Date: Tue, 8 Nov 2022 07:52:59 +0300 Message-Id: <20221108045300.2084671-2-lis8215@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221108045300.2084671-1-lis8215@gmail.com> References: <20221108045300.2084671-1-lis8215@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748902604544018267?= X-GMAIL-MSGID: =?utf-8?q?1748902651804147981?= Some SoCs have one clock divider for all MMC units, thus changing one affects others as well. This leads to random hangs and memory corruptions, observed on the JZ4755 based device with two MMC slots used at the same time. List of SoCs affected includes: JZ4725b, JZ4755, JZ4760 and JZ4760b. However, the MMC driver doesn't distinguish JZ4760 and JZ4770 which shall remain its behavior. For the JZ4755 is sufficient to use JZ4725b's binding. JZ4750 is outside of the patch. The MMC core has its own clock divisor, rather coarse but suitable well, and it shall keep the role of tuning clock for the MMC host in that case. Signed-off-by: Siarhei Volkau --- drivers/mmc/host/jz4740_mmc.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/jz4740_mmc.c b/drivers/mmc/host/jz4740_mmc.c index dc2db9c18..d390ff31d 100644 --- a/drivers/mmc/host/jz4740_mmc.c +++ b/drivers/mmc/host/jz4740_mmc.c @@ -114,6 +114,7 @@ enum jz4740_mmc_version { JZ_MMC_JZ4740, JZ_MMC_JZ4725B, JZ_MMC_JZ4760, + JZ_MMC_JZ4770, JZ_MMC_JZ4780, JZ_MMC_X1000, }; @@ -887,7 +888,13 @@ static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate) int real_rate; jz4740_mmc_clock_disable(host); - clk_set_rate(host->clk, host->mmc->f_max); + + /* + * Changing rate on these SoCs affects other MMC units too. + * Make sure the rate is configured properly by the CGU driver. + */ + if (host->version != JZ_MMC_JZ4725B && host->version != JZ_MMC_JZ4760) + clk_set_rate(host->clk, host->mmc->f_max); real_rate = clk_get_rate(host->clk); @@ -992,6 +999,7 @@ static const struct of_device_id jz4740_mmc_of_match[] = { { .compatible = "ingenic,jz4740-mmc", .data = (void *) JZ_MMC_JZ4740 }, { .compatible = "ingenic,jz4725b-mmc", .data = (void *)JZ_MMC_JZ4725B }, { .compatible = "ingenic,jz4760-mmc", .data = (void *) JZ_MMC_JZ4760 }, + { .compatible = "ingenic,jz4770-mmc", .data = (void *) JZ_MMC_JZ4770 }, { .compatible = "ingenic,jz4775-mmc", .data = (void *) JZ_MMC_JZ4780 }, { .compatible = "ingenic,jz4780-mmc", .data = (void *) JZ_MMC_JZ4780 }, { .compatible = "ingenic,x1000-mmc", .data = (void *) JZ_MMC_X1000 }, From patchwork Tue Nov 8 04:53:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siarhei Volkau X-Patchwork-Id: 16871 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2486429wru; Mon, 7 Nov 2022 20:59:34 -0800 (PST) X-Google-Smtp-Source: AMsMyM4LzbjVDiqOqiBAwHJ5PLrzypP2IFaxqXGHEz0kEPE8dBOEIs0crBEv3y8M0k9NZfzZ4NwE X-Received: by 2002:a17:902:be03:b0:17b:80c1:78c2 with SMTP id r3-20020a170902be0300b0017b80c178c2mr54669095pls.34.1667883574117; Mon, 07 Nov 2022 20:59:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1667883574; cv=none; d=google.com; s=arc-20160816; b=0y+5SQPWo+bdktYIKWITmhrqOogjEtmvS6bDgtvLC3NW6xr2qXlzvg5tTisoNFGnsj QG7E7LktkbhUgWR7IG41n60fTOJjkjVBNzZaGJymOULt4ogPycMK1TNJWdZ7D/jaxQ2a HX+SAgNex1bX7c/2S1ClKkY7bo/0cnvbQMBKBktMpLC5Bqt7zNytKZzLhUSnoK/aCJEg ZTPVkMTz19Cs+1yTDPtJrrITmo894S9GLu6pn37yhlt7XM1EijL/vyfCh7IWupWzdsC8 Qn3JhozX0ckeVJTIzeSnfJkUrm841Nx/Q0wf1D2MJmnK0AXzTVXWE5TpGwEM0I16ln4L 3Xlg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:to:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:from :dkim-signature; bh=snUtTBHDSnPgKxJzYe5m09ZTxD4YzrDQEzl3/KiB5BQ=; b=LaZ6fiOq6FYSpyy+dgU6OBc+aQR3t2ARnDdSmxfzUmi4j/EPQssT/5bFxihCmPWVAQ FL5NUZp9MdIaw1xvHHfMMVBz2JW48mwXaltqMHyYUQAdGUwMszBBBqqEBEziyiGul8ai 68jpItUVhHxpgSUhRfEnP+rj+2pUMfkTgG2HUNfehI2b8Vi7UG2/lV1vjEFTnGPyOwa8 JwvL2gByQ+RaELr1u8HqB0jMqqxcnnT7Jsaron8zWxA3XatwTpUlSNrfoTU26gPSfJT7 rDIAm6aNnMGGrhzEkoGK7SGz3zEWJ8n5YGNsFmc6dRQEiQamVuxqgMtyqRjHFA51Wabf Oxpw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@gmail.com header.s=20210112 header.b=O5V4m3Np; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=fail (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from out1.vger.email (out1.vger.email. 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[37.212.12.58]) by smtp.gmail.com with ESMTPSA id p11-20020a05640210cb00b004637489cf08sm4994444edu.88.2022.11.07.20.53.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Nov 2022 20:53:56 -0800 (PST) From: Siarhei Volkau Cc: Siarhei Volkau , Paul Cercueil , Rob Herring , Krzysztof Kozlowski , Thomas Bogendoerfer , Ulf Hansson , linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org Subject: [PATCH 2/2] MIPS: ingenic: rs90: set MMC_MUX clock Date: Tue, 8 Nov 2022 07:53:00 +0300 Message-Id: <20221108045300.2084671-3-lis8215@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221108045300.2084671-1-lis8215@gmail.com> References: <20221108045300.2084671-1-lis8215@gmail.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.8 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FREEMAIL_ENVFROM_END_DIGIT, FREEMAIL_FROM,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748902686266861516?= X-GMAIL-MSGID: =?utf-8?q?1748902686266861516?= Since the MMC driver can't change the common MMC_MUX clock anymore, the CGU shall configure that clock properly. Signed-off-by: Siarhei Volkau --- arch/mips/boot/dts/ingenic/rs90.dts | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/mips/boot/dts/ingenic/rs90.dts b/arch/mips/boot/dts/ingenic/rs90.dts index e8df70dd4..d874abaa6 100644 --- a/arch/mips/boot/dts/ingenic/rs90.dts +++ b/arch/mips/boot/dts/ingenic/rs90.dts @@ -295,8 +295,9 @@ partition@20000 { &cgu { /* Use 32kHz oscillator as the parent of the RTC clock */ - assigned-clocks = <&cgu JZ4725B_CLK_RTC>; - assigned-clock-parents = <&cgu JZ4725B_CLK_OSC32K>; + assigned-clocks = <&cgu JZ4725B_CLK_MMC_MUX>, <&cgu JZ4725B_CLK_RTC>; + assigned-clock-parents = <0>, <&cgu JZ4725B_CLK_OSC32K>; + assigned-clock-rates = <48000000>; }; &tcu {