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[2620:137:e000::3:1]) by mx.google.com with ESMTPS id o7-20020a0de507000000b0059ea6c982bdsi10133466ywe.490.2023.10.25.03.22.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 03:22:31 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) client-ip=2620:137:e000::3:1; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=dtYfoyF9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by morse.vger.email (Postfix) with ESMTP id 1DC10801F35E; Wed, 25 Oct 2023 03:22:29 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at morse.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234590AbjJYKWL (ORCPT + 26 others); Wed, 25 Oct 2023 06:22:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46050 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234511AbjJYKWK (ORCPT ); Wed, 25 Oct 2023 06:22:10 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8642313A; Wed, 25 Oct 2023 03:22:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1698229326; x=1729765326; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zSkOZ12TKc1wwVLKvzsXxeC5tl7G/J3ooSzJ/My7COk=; b=dtYfoyF930juvfEIYDqEWu6ebbQzvSjfroVNhTMmUu/kQ5S+BQuOkdzb uUSuTik28Ham2wHB7hLiMJuzZJJ+2RqSWLHwKHp3EZ2rDiNGBu94rQfus 2oFDFOpGxUaiFA/At/KdVz7i1J7mkRuhBMt3mt77k9qitaHttenGAUnjt oObgC/ZXYzOzauEgXKKywZUC3OO76RIn7pvzcwZm5KDcvj4ZLpfd1oaLD QkwT/Zn/A9l+zTAlXeqqPZiFJP2r8Gov407sw59ZGFak/IljfUmtWtj67 Z6CnOVqeHinkK7t4bjyYDUOmaUErYpUSjpwM8AlH4NvCG0egi7AoHnDE8 g==; X-CSE-ConnectionGUID: lZ11uPMKRAauSrL+tx1Dsw== X-CSE-MsgGUID: mq3IHkvsRjy/Gl6qLK7KjA== X-ThreatScanner-Verdict: Negative X-IronPort-AV: E=Sophos;i="6.03,250,1694761200"; d="scan'208";a="10565833" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 25 Oct 2023 03:22:05 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Wed, 25 Oct 2023 03:21:50 -0700 Received: from microchip1-OptiPlex-9020.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Wed, 25 Oct 2023 03:21:45 -0700 From: shravan chippa To: , , , , , , CC: , , , , , , Subject: [PATCH v3 1/4] dmaengine: sf-pdma: Support of_dma_controller_register() Date: Wed, 25 Oct 2023 15:52:48 +0530 Message-ID: <20231025102251.3369472-2-shravan.chippa@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231025102251.3369472-1-shravan.chippa@microchip.com> References: <20231025102251.3369472-1-shravan.chippa@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Wed, 25 Oct 2023 03:22:29 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780722540827279729 X-GMAIL-MSGID: 1780722540827279729 From: Shravan Chippa Update sf-pdma driver to adopt generic DMA device tree bindings. It calls of_dma_controller_register() with sf-pdma specific of_dma_xlate to get the generic DMA device tree helper support and the DMA clients can look up the sf-pdma controller using standard APIs. Signed-off-by: Shravan Chippa --- drivers/dma/sf-pdma/sf-pdma.c | 44 +++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/dma/sf-pdma/sf-pdma.c b/drivers/dma/sf-pdma/sf-pdma.c index d1c6956af452..4c456bdef882 100644 --- a/drivers/dma/sf-pdma/sf-pdma.c +++ b/drivers/dma/sf-pdma/sf-pdma.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include "sf-pdma.h" @@ -490,6 +491,33 @@ static void sf_pdma_setup_chans(struct sf_pdma *pdma) } } +static struct dma_chan *sf_pdma_of_xlate(struct of_phandle_args *dma_spec, + struct of_dma *ofdma) +{ + struct sf_pdma *pdma = ofdma->of_dma_data; + struct device *dev = pdma->dma_dev.dev; + struct sf_pdma_chan *chan; + struct dma_chan *c; + u32 channel_id; + + if (dma_spec->args_count != 1) { + dev_err(dev, "Bad number of cells\n"); + return NULL; + } + + channel_id = dma_spec->args[0]; + + chan = &pdma->chans[channel_id]; + + c = dma_get_slave_channel(&chan->vchan.chan); + if (!c) { + dev_err(dev, "No more channels available\n"); + return NULL; + } + + return c; +} + static int sf_pdma_probe(struct platform_device *pdev) { struct sf_pdma *pdma; @@ -563,7 +591,20 @@ static int sf_pdma_probe(struct platform_device *pdev) return ret; } + ret = of_dma_controller_register(pdev->dev.of_node, + sf_pdma_of_xlate, pdma); + if (ret < 0) { + dev_err(&pdev->dev, + "Can't register SiFive Platform OF_DMA. (%d)\n", ret); + goto err_unregister; + } + return 0; + +err_unregister: + dma_async_device_unregister(&pdma->dma_dev); + + return ret; } static int sf_pdma_remove(struct platform_device *pdev) @@ -583,6 +624,9 @@ static int sf_pdma_remove(struct platform_device *pdev) tasklet_kill(&ch->err_tasklet); } + if (pdev->dev.of_node) + of_dma_controller_free(pdev->dev.of_node); + dma_async_device_unregister(&pdma->dma_dev); return 0; From patchwork Wed Oct 25 10:22:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: shravan chippa X-Patchwork-Id: 157995 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:ce89:0:b0:403:3b70:6f57 with SMTP id p9csp2496826vqx; Wed, 25 Oct 2023 03:22:54 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHQMDBF5/BQF6iNQ0orTEipO1/+BJBxyye93B0EqI/G5NPX3Xhds8Cv2xyktiVufz1Qok/0 X-Received: by 2002:a81:6d56:0:b0:5a8:1ff3:ef96 with SMTP id i83-20020a816d56000000b005a81ff3ef96mr15413624ywc.7.1698229374587; Wed, 25 Oct 2023 03:22:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698229374; cv=none; d=google.com; s=arc-20160816; b=rZxb9L8Go61UIvTw3ghr7E0riKA6jdE/RCn/SfLUTog1ZSv8EsAfjKp9d7BEXQq6OC 5GQvxVHU2Go8P3UL8/8TxCATLwEO5uq1VZQaXZe6iuSEX5TnTcm3OFDKgVzN407MMcUB 2ci6e5TLptnLi4mODEfTdrbq+NoFOM/NPBnHXDOJpH037ivtGlWLHQA/tbQjndQu+TWw 0ll7DqLySaUDcRW1NC4GIxG7Ol97+OPrytO6ycpILBBiKjBpJ5j636xCYZl8YTw6ASfw 7nTyRcuZXPcSQ2rIqip6tELFMe3HzBw6dzC8mZSCekDvrJnroHxaIGQoB4SElpfLTZ8p Jnng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=2AhRWMcEq8tmHBamltUSruil65DVvqAHbhJZ3g+WpCc=; fh=G3bdubTV0+o+8hUeMfd0vNMrcf0Z3JqHvJT+qGOcRCw=; b=FQ4PoCpmQAJfC5b6ut/bhzFVdf5/lKmH4UUvR42JgXopMoRDN81ESDuDf78Ztsuuig FJz4gGQWed0Zavuzasi94Gd6FSgnzVWMc1WiumQ7iCqYuucdV2gJFqkT8ltf3hGjkgcR llIPKlsQkAm2nH0hEz8yRVVt5GfbGH683dsLHyJMdsnfL0nykNuLRa+xoLIeoBlBFlNt TuzmwJ5/ZZ/cKzwGI9Vmq76JRjSEpgrGtHPQ10UsUYuVooOG/uy53HOfsoUzkAnEZVbD i4ckM0YLCAp3AxBx8I4wnlVnrydY4726RcaY7hlWEgHTaPF2Z7nSqQVJipV/pOcnVwUT qQsQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=IeiPe65e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from pete.vger.email (pete.vger.email. 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X-CSE-ConnectionGUID: hCRWSLnNROWYEPYDprosFg== X-CSE-MsgGUID: pAnaJDpLSHSLKPTJCWvjMQ== X-ThreatScanner-Verdict: Negative X-IronPort-AV: E=Sophos;i="6.03,250,1694761200"; d="scan'208";a="10660975" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 25 Oct 2023 03:22:28 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Wed, 25 Oct 2023 03:21:59 -0700 Received: from microchip1-OptiPlex-9020.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Wed, 25 Oct 2023 03:21:53 -0700 From: shravan chippa To: , , , , , , CC: , , , , , , , Conor Dooley Subject: [PATCH v3 2/4] dt-bindings: dma: sf-pdma: add new compatible name Date: Wed, 25 Oct 2023 15:52:49 +0530 Message-ID: <20231025102251.3369472-3-shravan.chippa@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231025102251.3369472-1-shravan.chippa@microchip.com> References: <20231025102251.3369472-1-shravan.chippa@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.9 required=5.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Wed, 25 Oct 2023 03:22:48 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780722564696931555 X-GMAIL-MSGID: 1780722564696931555 From: Shravan Chippa Add new compatible name microchip,mpfs-pdma to support out of order dma transfers Reviewed-by: Conor Dooley Signed-off-by: Shravan Chippa --- .../devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml b/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml index a1af0b906365..3b22183a1a37 100644 --- a/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml +++ b/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml @@ -29,6 +29,7 @@ properties: compatible: items: - enum: + - microchip,mpfs-pdma - sifive,fu540-c000-pdma - const: sifive,pdma0 description: From patchwork Wed Oct 25 10:22:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: shravan chippa X-Patchwork-Id: 157993 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:ce89:0:b0:403:3b70:6f57 with SMTP id p9csp2496729vqx; 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Wed, 25 Oct 2023 03:22:40 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780722551298982908 X-GMAIL-MSGID: 1780722551298982908 From: Shravan Chippa Sifive platform dma does not allow out-of-order transfers, Add a PolarFire SoC specific compatible and code to support for out-of-order dma transfers Signed-off-by: Shravan Chippa Reviewed-by: Emil Renner Berthing --- drivers/dma/sf-pdma/sf-pdma.c | 27 ++++++++++++++++++++++++--- drivers/dma/sf-pdma/sf-pdma.h | 8 +++++++- 2 files changed, 31 insertions(+), 4 deletions(-) diff --git a/drivers/dma/sf-pdma/sf-pdma.c b/drivers/dma/sf-pdma/sf-pdma.c index 4c456bdef882..9cc4beec40f0 100644 --- a/drivers/dma/sf-pdma/sf-pdma.c +++ b/drivers/dma/sf-pdma/sf-pdma.c @@ -25,6 +25,8 @@ #include "sf-pdma.h" +#define PDMA_QUIRK_NO_STRICT_ORDERING BIT(0) + #ifndef readq static inline unsigned long long readq(void __iomem *addr) { @@ -66,7 +68,7 @@ static struct sf_pdma_desc *sf_pdma_alloc_desc(struct sf_pdma_chan *chan) static void sf_pdma_fill_desc(struct sf_pdma_desc *desc, u64 dst, u64 src, u64 size) { - desc->xfer_type = PDMA_FULL_SPEED; + desc->xfer_type = desc->chan->pdma->transfer_type; desc->xfer_size = size; desc->dst_addr = dst; desc->src_addr = src; @@ -520,6 +522,7 @@ static struct dma_chan *sf_pdma_of_xlate(struct of_phandle_args *dma_spec, static int sf_pdma_probe(struct platform_device *pdev) { + const struct sf_pdma_driver_platdata *ddata; struct sf_pdma *pdma; int ret, n_chans; const enum dma_slave_buswidth widths = @@ -545,6 +548,14 @@ static int sf_pdma_probe(struct platform_device *pdev) pdma->n_chans = n_chans; + pdma->transfer_type = PDMA_FULL_SPEED | PDMA_STRICT_ORDERING; + + ddata = device_get_match_data(&pdev->dev); + if (ddata) { + if (ddata->quirks & PDMA_QUIRK_NO_STRICT_ORDERING) + pdma->transfer_type &= ~(PDMA_STRICT_ORDERING) ; + } + pdma->membase = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(pdma->membase)) return PTR_ERR(pdma->membase); @@ -632,9 +643,19 @@ static int sf_pdma_remove(struct platform_device *pdev) return 0; } +static const struct sf_pdma_driver_platdata mpfs_pdma = { + .quirks = PDMA_QUIRK_NO_STRICT_ORDERING, +}; + static const struct of_device_id sf_pdma_dt_ids[] = { - { .compatible = "sifive,fu540-c000-pdma" }, - { .compatible = "sifive,pdma0" }, + { + .compatible = "sifive,fu540-c000-pdma", + }, { + .compatible = "sifive,pdma0", + }, { + .compatible = "microchip,mpfs-pdma", + .data = &mpfs_pdma, + }, {}, }; MODULE_DEVICE_TABLE(of, sf_pdma_dt_ids); diff --git a/drivers/dma/sf-pdma/sf-pdma.h b/drivers/dma/sf-pdma/sf-pdma.h index 5c398a83b491..267e79a5e0a5 100644 --- a/drivers/dma/sf-pdma/sf-pdma.h +++ b/drivers/dma/sf-pdma/sf-pdma.h @@ -48,7 +48,8 @@ #define PDMA_ERR_STATUS_MASK GENMASK(31, 31) /* Transfer Type */ -#define PDMA_FULL_SPEED 0xFF000008 +#define PDMA_FULL_SPEED 0xFF000000 +#define PDMA_STRICT_ORDERING BIT(3) /* Error Recovery */ #define MAX_RETRY 1 @@ -112,8 +113,13 @@ struct sf_pdma { struct dma_device dma_dev; void __iomem *membase; void __iomem *mappedbase; + u32 transfer_type; u32 n_chans; struct sf_pdma_chan chans[]; }; +struct sf_pdma_driver_platdata { + u32 quirks; +}; + #endif /* _SF_PDMA_H */ From patchwork Wed Oct 25 10:22:51 2023 Content-Type: text/plain; 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[2620:137:e000::3:7]) by mx.google.com with ESMTPS id z185-20020a8165c2000000b005a7b1d9a1f8si9922788ywb.553.2023.10.25.03.22.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Oct 2023 03:22:48 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=aZFaagPG; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=microchip.com Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id E648280E06AD; Wed, 25 Oct 2023 03:22:47 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234749AbjJYKWk (ORCPT + 26 others); Wed, 25 Oct 2023 06:22:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34956 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234705AbjJYKWi (ORCPT ); Wed, 25 Oct 2023 06:22:38 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 90F20123; Wed, 25 Oct 2023 03:22:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1698229355; x=1729765355; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ub36EsnDsZ4Pe9+1Jc9C5yZxVaCIMgDzhRw3P0KEHx8=; b=aZFaagPGLdt/hjnoy1S3UXvM3PwTq6+OW6DFmKPHN9Nk2OVVMMvP/Guh pd1YsQf8aC4JXHPDXARnJD1H8uODP6vL1QoRpoU9XNxmqeL9X6EDCqJ3T xtsKUyFDoZk9X6CkhUdRH8KinB6/kf84P9SKOjglZfvrPXPhO+lnVmtPE ryraka04PoBJAsLNgtWhYiUGE2uTMfbTMhSGrz7Gu0xN+iNqtPyhxmUXc MXSdIJeVjA13wlIhO2upGddo4WZlsvCKk2FNa0w+CtQNZtapov4lNrL9v WnzQU/5xwi8XufGcKUviO7CknD1815oz0zgOzqZ4K7OGZYaXPbw+bNUC2 Q==; X-CSE-ConnectionGUID: /1Fh5rPuRU6c46pvXDlHLA== X-CSE-MsgGUID: /6oeDPW+RKiaEqgYvVPuFg== X-ThreatScanner-Verdict: Negative X-IronPort-AV: E=Sophos;i="6.03,250,1694761200"; d="scan'208";a="177735248" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 25 Oct 2023 03:22:34 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Wed, 25 Oct 2023 03:22:14 -0700 Received: from microchip1-OptiPlex-9020.microchip.com (10.10.85.11) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Wed, 25 Oct 2023 03:22:09 -0700 From: shravan chippa To: , , , , , , CC: , , , , , , Subject: [PATCH v3 4/4] riscv: dts: microchip: add specific compatible for mpfs' pdma Date: Wed, 25 Oct 2023 15:52:51 +0530 Message-ID: <20231025102251.3369472-5-shravan.chippa@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231025102251.3369472-1-shravan.chippa@microchip.com> References: <20231025102251.3369472-1-shravan.chippa@microchip.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF, RCVD_IN_DNSWL_BLOCKED,RCVD_IN_MSPIKE_H5,RCVD_IN_MSPIKE_WL, SPF_HELO_PASS,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 25 Oct 2023 03:22:48 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780722559007298654 X-GMAIL-MSGID: 1780722559007298654 From: Shravan Chippa Add specific compatible for PolarFire SoC for The SiFive PDMA driver Signed-off-by: Shravan Chippa Reviewed-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 104504352e99..f43486e9a090 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -221,7 +221,7 @@ plic: interrupt-controller@c000000 { }; pdma: dma-controller@3000000 { - compatible = "sifive,fu540-c000-pdma", "sifive,pdma0"; + compatible = "microchip,mpfs-pdma", "sifive,pdma0"; reg = <0x0 0x3000000 0x0 0x8000>; interrupt-parent = <&plic>; interrupts = <5 6>, <7 8>, <9 10>, <11 12>;