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Mon, 23 Oct 2023 15:14:05 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, tsbogend@alpha.franken.de, gregory.clement@bootlin.com, vladimir.kondratiev@intel.com, Jiaxun Yang Subject: [PATCH 1/5] MIPS: Export higher/highest relocation functions in uasm Date: Mon, 23 Oct 2023 20:13:56 +0100 Message-Id: <20231023191400.170052-2-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023191400.170052-1-jiaxun.yang@flygoat.com> References: <20231023191400.170052-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Mon, 23 Oct 2023 12:14:49 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780574838149858453 X-GMAIL-MSGID: 1780574838149858453 Export uasm_rel_{higher,highest} functions. Those functions can be helpful in dealing with 64bit immediates. Signed-off-by: Jiaxun Yang --- arch/mips/include/asm/uasm.h | 2 ++ arch/mips/mm/uasm.c | 6 ++++-- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h index 296bcf31abb5..12db6d2fca07 100644 --- a/arch/mips/include/asm/uasm.h +++ b/arch/mips/include/asm/uasm.h @@ -196,6 +196,8 @@ void uasm_build_label(struct uasm_label **lab, u32 *addr, #ifdef CONFIG_64BIT int uasm_in_compat_space_p(long addr); #endif +int uasm_rel_highest(long val); +int uasm_rel_higher(long val); int uasm_rel_hi(long val); int uasm_rel_lo(long val); void UASM_i_LA_mostly(u32 **buf, unsigned int rs, long addr); diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c index 125140979d62..6846bf2084c5 100644 --- a/arch/mips/mm/uasm.c +++ b/arch/mips/mm/uasm.c @@ -425,7 +425,7 @@ int uasm_in_compat_space_p(long addr) } UASM_EXPORT_SYMBOL(uasm_in_compat_space_p); -static int uasm_rel_highest(long val) +int uasm_rel_highest(long val) { #ifdef CONFIG_64BIT return ((((val + 0x800080008000L) >> 48) & 0xffff) ^ 0x8000) - 0x8000; @@ -433,8 +433,9 @@ static int uasm_rel_highest(long val) return 0; #endif } +UASM_EXPORT_SYMBOL(uasm_rel_highest); -static int uasm_rel_higher(long val) +int uasm_rel_higher(long val) { #ifdef CONFIG_64BIT return ((((val + 0x80008000L) >> 32) & 0xffff) ^ 0x8000) - 0x8000; @@ -442,6 +443,7 @@ static int uasm_rel_higher(long val) return 0; #endif } +UASM_EXPORT_SYMBOL(uasm_rel_higher); int uasm_rel_hi(long val) { From patchwork Mon Oct 23 19:13:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 157041 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:ce89:0:b0:403:3b70:6f57 with SMTP id p9csp1500291vqx; Mon, 23 Oct 2023 12:14:38 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFlq9HhGOZlsbfkVDTwjspWcHBswBlGlGdshCsfAo8EqKcPB6vyanVYkH7jhEiqRL0A+TNO X-Received: by 2002:a05:6a00:1402:b0:6b6:1216:d8fe with SMTP id l2-20020a056a00140200b006b61216d8femr8054340pfu.27.1698088478045; Mon, 23 Oct 2023 12:14:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698088478; cv=none; d=google.com; s=arc-20160816; b=vICHbUyM+103gU0eKZv6eSzfqymJoEv8z4zSpjsU+eaWCbFEXuMAhUWTjXXX47+h0G qdFBxulpY43f2T/DCZnyNUTcvfDCwpJAuBqjZJiKs6gE/auaz5BJbVJIx8V+uOGKBQ8K IqaJ/bGTqodWoUTNSQStz9HfuACR6KQW7eN7cjogusvoKa1997/PfA4KHWkeRXzhzbi/ 216VBnT6ZU9C3E1x7YX5O0gF1zEtsnQwQ2PfLbVsjxU5CQMbceFeZf4/qEInDVv++4C5 5NlsRC7QKApho6D3mrq5NXm40fIY19PD8MS/2zp8Pg6oClERD+lxddiDSTB0Qp0OkHNL Bqrw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :feedback-id:dkim-signature:dkim-signature; bh=JcLDvuqq+aysWCP3Ln7wvhxjBzjiN4xGl+qlurq8eWo=; fh=34VXqKbbbRVUWYKB0XlF9D4jmhXxe51P2+smd1zcTfU=; b=aFCiMFt7QBy9sbyBuA170J7Ysf2omrSJ5QTh7slqsHW/Uo4nrAY3FXP0z8Z9AVG4+m u23GW9rCuL6T/UGCNXEEbZesVXQssYKlicNr1eiGlcpZ2IerLvcO3C2jNUfricAFhHxF YExRnzfTN8WPo2nt3R0WUj8/0LymrF84fSx2wK5JZ/XfS1nd312Yz2qPQjQn0G78zard 3GB0n8kTbrLHoXp86+1xzev5MxjYt4cJd8d3q5KY4fqPlMftrZybscYHFEEU/reyyy4J SvE0qeGWK6uDG3U6Xdys4Ucivnk4fPB82TOKeXzaDjyvXeNivZiH3ON3kMQ+XzLZlBaz kitg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@flygoat.com header.s=fm1 header.b=Ix0p+2hK; dkim=pass header.i=@messagingengine.com header.s=fm3 header.b=BzlIWe1p; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=flygoat.com Received: from agentk.vger.email (agentk.vger.email. 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Mon, 23 Oct 2023 15:14:07 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, tsbogend@alpha.franken.de, gregory.clement@bootlin.com, vladimir.kondratiev@intel.com, Jiaxun Yang Subject: [PATCH 2/5] MIPS: genex: Fix except_vec_vi for kernel in XKPHYS Date: Mon, 23 Oct 2023 20:13:57 +0100 Message-Id: <20231023191400.170052-3-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023191400.170052-1-jiaxun.yang@flygoat.com> References: <20231023191400.170052-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Mon, 23 Oct 2023 12:14:35 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780574824022585305 X-GMAIL-MSGID: 1780574824022585305 Use {highest, higher, hi, lo} immediate loading sequence to load 64 bit jump address for handler when kernel is loaded to XKPHYS. Co-developed-by: Vladimir Kondratiev Signed-off-by: Vladimir Kondratiev Co-developed-by: Gregory CLEMENT Signed-off-by: Gregory CLEMENT Signed-off-by: Jiaxun Yang --- arch/mips/kernel/genex.S | 19 +++++++++++++++---- arch/mips/kernel/traps.c | 34 ++++++++++++++++++++++++---------- 2 files changed, 39 insertions(+), 14 deletions(-) diff --git a/arch/mips/kernel/genex.S b/arch/mips/kernel/genex.S index b6de8e88c1bd..fd765ad9ecac 100644 --- a/arch/mips/kernel/genex.S +++ b/arch/mips/kernel/genex.S @@ -272,11 +272,22 @@ NESTED(except_vec_vi, 0, sp) .set push .set noreorder PTR_LA v1, except_vec_vi_handler -FEXPORT(except_vec_vi_lui) - lui v0, 0 /* Patched */ +#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32) +FEXPORT(except_vec_vi_hi) + lui v0, 0 /* Patched */ +#else +FEXPORT(except_vec_vi_highest) + lui v0, 0 /* Patched */ +FEXPORT(except_vec_vi_higher) + daddiu v0, 0 /* Patched */ + dsll v0, 16 +FEXPORT(except_vec_vi_hi) + daddiu v0, 0 /* Patched */ + dsll v0, 16 +#endif jr v1 -FEXPORT(except_vec_vi_ori) - ori v0, 0 /* Patched */ +FEXPORT(except_vec_vi_lo) + PTR_ADDIU v0, 0 /* Patched */ .set pop END(except_vec_vi) EXPORT(except_vec_vi_end) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 246c6a6b0261..60c513c51684 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -2091,18 +2091,26 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) * If no shadow set is selected then use the default handler * that does normal register saving and standard interrupt exit */ - extern const u8 except_vec_vi[], except_vec_vi_lui[]; - extern const u8 except_vec_vi_ori[], except_vec_vi_end[]; + extern const u8 except_vec_vi[], except_vec_vi_hi[]; + extern const u8 except_vec_vi_lo[], except_vec_vi_end[]; +#if defined(CONFIG_64BIT) && !defined(KBUILD_64BIT_SYM32) + extern const u8 except_vec_vi_highest[], except_vec_vi_higher[]; +#endif extern const u8 rollback_except_vec_vi[]; const u8 *vec_start = using_rollback_handler() ? rollback_except_vec_vi : except_vec_vi; #if defined(CONFIG_CPU_MICROMIPS) || defined(CONFIG_CPU_BIG_ENDIAN) - const int lui_offset = except_vec_vi_lui - vec_start + 2; - const int ori_offset = except_vec_vi_ori - vec_start + 2; + const int imm_offset = 2; #else - const int lui_offset = except_vec_vi_lui - vec_start; - const int ori_offset = except_vec_vi_ori - vec_start; + const int imm_offset = 0; +#endif +#if defined(CONFIG_64BIT) && !defined(KBUILD_64BIT_SYM32) + const int highest_offset = except_vec_vi_highest - vec_start + imm_offset; + const int higher_offset = except_vec_vi_higher - vec_start + imm_offset; #endif + const int hi_offset = except_vec_vi_hi - vec_start + imm_offset; + const int lo_offset = except_vec_vi_lo - vec_start + imm_offset; + const int handler_len = except_vec_vi_end - vec_start; if (handler_len > VECTORSPACING) { @@ -2119,10 +2127,16 @@ static void *set_vi_srs_handler(int n, vi_handler_t addr, int srs) #else handler_len); #endif - h = (u16 *)(b + lui_offset); - *h = (handler >> 16) & 0xffff; - h = (u16 *)(b + ori_offset); - *h = (handler & 0xffff); +#if defined(CONFIG_64BIT) && !defined(KBUILD_64BIT_SYM32) + h = (u16 *)(b + highest_offset); + *h = uasm_rel_highest(handler); + h = (u16 *)(b + higher_offset); + *h = uasm_rel_higher(handler); +#endif + h = (u16 *)(b + hi_offset); + *h = uasm_rel_hi(handler); + h = (u16 *)(b + lo_offset); + *h = uasm_rel_lo(handler); local_flush_icache_range((unsigned long)b, (unsigned long)(b+handler_len)); } From patchwork Mon Oct 23 19:13:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 157043 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:ce89:0:b0:403:3b70:6f57 with SMTP id p9csp1500443vqx; Mon, 23 Oct 2023 12:14:54 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHUDlg6j8RREDYCGcuD5WjlBh+WnmREy5+joQAG+d3AsMFVHQL3nTDgozKbSRuRspeIyCul X-Received: by 2002:a17:903:11cc:b0:1c9:faef:5765 with SMTP id q12-20020a17090311cc00b001c9faef5765mr8533265plh.5.1698088494640; Mon, 23 Oct 2023 12:14:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698088494; cv=none; d=google.com; s=arc-20160816; b=qOXZz3VVGLOwyEJYtQr+bcJa+FSS86M0EVenUBtXcKKiHmwa/LORkj3e+xxFjmYTfP SreC07mdFd9ljU4H1wmg79nAGxpYY2lu9b8JXDIK/9lPNfDBYvtjLiljeYN9E9uoeYCS O0e3GljX3JQMRFB24oPp6ucfRh9yXfCFiATuccp6C6PKTUiLkjjySTN5MJhHF12U/ti7 r11SCZ7CN77gmzgabRcR4oTLWtio7l75VIZEkKvJIFGPah+I6AASUAxKCihgQ5uC/nBX kcI+K9RCE2cFmF5oOjrRfTjP3P2LwdFKcOY7v1XcqsTG9swUdbkItS39AEsnpH04OyeH 60Tg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :feedback-id:dkim-signature:dkim-signature; bh=z1/hT0gfhZcXEOcRfnRggstjECOl2aSsJ7lZKpBlqTw=; fh=34VXqKbbbRVUWYKB0XlF9D4jmhXxe51P2+smd1zcTfU=; b=JOciQTKkwYcJUI1Zk46GJ1f7eO+MbKNywcrtg1/GcXFZI2nG3h8RACmmKloPoHenaG 3eW11mUQMac0OdzwB/uUKfFk3ByA4bxc1BdjjoVxdOJ66iFD8oOWfs2kNSxGPO/0Zzu3 dPInQ/aTvF3Ku2S26GsH4UiPxcysDqUaRgO4lbHaLhcejQ5zxTG5AZXazc+3OZC4TfCt eGQAvZ/TOB7FY+yXekqiTvWbRhxXGcJC6ba+dBgkfyt1eXE/5TFGdXmPZSTEOkKxnpfQ bvNOSuULF+TQQQxZj1mbPJZTFA0EoZcMOX9Gw4r1BK7MUej7IMYCKNGGVyWklDDyZ4cE j7VQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@flygoat.com header.s=fm1 header.b=f9QS4lLR; dkim=pass header.i=@messagingengine.com header.s=fm3 header.b=d2RjKvnM; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=flygoat.com Received: from pete.vger.email (pete.vger.email. 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Mon, 23 Oct 2023 15:14:08 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, tsbogend@alpha.franken.de, gregory.clement@bootlin.com, vladimir.kondratiev@intel.com, Jiaxun Yang Subject: [PATCH 3/5] MIPS: Fix set_uncached_handler for ebase in XKPHYS Date: Mon, 23 Oct 2023 20:13:58 +0100 Message-Id: <20231023191400.170052-4-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023191400.170052-1-jiaxun.yang@flygoat.com> References: <20231023191400.170052-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Mon, 23 Oct 2023 12:14:49 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780574841498779787 X-GMAIL-MSGID: 1780574841498779787 ebase may be in XKPHYS if memblock unable to allocate memory within KSEG0 physical range. To map ebase into uncached space we just convert it back to physical address and then use platform's TO_UNCAC helper to create mapping. Co-developed-by: Vladimir Kondratiev Signed-off-by: Vladimir Kondratiev Co-developed-by: Gregory CLEMENT Signed-off-by: Gregory CLEMENT Signed-off-by: Jiaxun Yang --- arch/mips/kernel/traps.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 60c513c51684..230728d76d11 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -2346,7 +2346,7 @@ static const char panic_null_cerr[] = void set_uncached_handler(unsigned long offset, void *addr, unsigned long size) { - unsigned long uncached_ebase = CKSEG1ADDR(ebase); + unsigned long uncached_ebase = TO_UNCAC(__pa(ebase)); if (!addr) panic(panic_null_cerr); From patchwork Mon Oct 23 19:13:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 157040 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:ce89:0:b0:403:3b70:6f57 with SMTP id p9csp1500271vqx; Mon, 23 Oct 2023 12:14:36 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFp8wMak8IHI8ODBZFx54foYr3acPPaZw1SV8oX064GZ5wWGiqj+3J9NRA3aDjzj/c7hlHI X-Received: by 2002:a05:6a00:1702:b0:6be:7ee:9914 with SMTP id h2-20020a056a00170200b006be07ee9914mr8069385pfc.11.1698088475744; Mon, 23 Oct 2023 12:14:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698088475; cv=none; d=google.com; s=arc-20160816; b=HzOQ9fEhfVY+Uj7SbemKOt7kdm/OCNAWRsMtYzsZNRdgBv/h72vYuHjc68EcagTPp7 0QliZ5uIawjyvj+JBFCxEk0MqGPc3hfAL97X3zmIAjImp3IXfEE8nUS6Ur8sP+VeXyWg ZBOzk6qstzEJYEqb+U1pvZH+vIZoHrV3QgbfM2BUJKpO2IMfrICu23VYWjt1nTQ+nb0h kir0U/LEsKnV7pbp3OYdtEr9ub42hEHR8b4wV8weQDRGCdQkss25j0Gc/uhEGcow36hc 3tBCLxqRXiWQwZzuk7hSMmEf9Heri0adqPERiFNTUpkPSqJ3jw0ZGrQ/KKNVtpKQ+3YO fmvg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :feedback-id:dkim-signature:dkim-signature; bh=axCOXJ1HMSIUr/oFZjhnVtqXrX+b0q0P4G/a7WUwdbo=; fh=34VXqKbbbRVUWYKB0XlF9D4jmhXxe51P2+smd1zcTfU=; b=vxPvwzGjR5BozAOdoE31CniIdR3ZcXhisxqlanczfcytlZC/Rkh3POpivvRmwkFJSr D9I7u5vhSy2TKfOoo/oouAOgcJlDuOIy07CKrL1G9zybS2uwlKkBqbx6ZiMiSC1UbNIU I+JSv1xZOu0iavC9HEC1ZaaV73ANPz27j6lpYSrFjE2iZKPyyNurDFABFWs64BeHjSgJ l73lluIWwvdlXXOjUKx7ti7+TXuaBMWfSj4TnJuenrlwFBA2mcbTaGLyovoTKp1bukUI H8EWKj90T9jbzrSHAbNI4xFvZ0qH1hKDN8Wq8+3NC8VgGl/YE1uiPFHnShIBC68KUaPe bd0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@flygoat.com header.s=fm1 header.b=vsLaEWs9; dkim=pass header.i=@messagingengine.com header.s=fm3 header.b=H1HXqrR9; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.32 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=flygoat.com Received: from agentk.vger.email (agentk.vger.email. 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Mon, 23 Oct 2023 15:14:10 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, tsbogend@alpha.franken.de, gregory.clement@bootlin.com, vladimir.kondratiev@intel.com, Jiaxun Yang Subject: [PATCH 4/5] MIPS: Handle mips_cps_core_entry within lower 4G Date: Mon, 23 Oct 2023 20:13:59 +0100 Message-Id: <20231023191400.170052-5-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023191400.170052-1-jiaxun.yang@flygoat.com> References: <20231023191400.170052-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Mon, 23 Oct 2023 12:14:33 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780574821531243307 X-GMAIL-MSGID: 1780574821531243307 Set CM_GCR_Cx_RESET_BASE_MODE and use XKPHYS base address for core_entry for 64bit CM when mips_cps_core_entry is beyond KSEG1. Also disable SMP and warn user if mips_cps_core_entry is unsuitable as reset vector. Signed-off-by: Jiaxun Yang --- Note: IMO it does not solve the problem of MobileEye, which have mips_cps_core_entry beyond lower 4G, it just enables me to test kernel in XKPHYS on boston. --- arch/mips/include/asm/mips-cm.h | 1 + arch/mips/kernel/smp-cps.c | 27 +++++++++++++++++++++------ 2 files changed, 22 insertions(+), 6 deletions(-) diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h index 23c67c0871b1..15d8d69de455 100644 --- a/arch/mips/include/asm/mips-cm.h +++ b/arch/mips/include/asm/mips-cm.h @@ -311,6 +311,7 @@ GCR_CX_ACCESSOR_RW(32, 0x018, other) /* GCR_Cx_RESET_BASE - Configure where powered up cores will fetch from */ GCR_CX_ACCESSOR_RW(32, 0x020, reset_base) #define CM_GCR_Cx_RESET_BASE_BEVEXCBASE GENMASK(31, 12) +#define CM_GCR_Cx_RESET_BASE_MODE BIT(1) /* GCR_Cx_ID - Identify the current core */ GCR_CX_ACCESSOR_RO(32, 0x028, id) diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index dd55d59b88db..623dfd05585b 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -26,6 +26,7 @@ #include static DECLARE_BITMAP(core_power, NR_CPUS); +static uint32_t core_entry_reg; struct core_boot_config *mips_cps_core_bootcfg; @@ -37,7 +38,6 @@ static unsigned __init core_vpe_count(unsigned int cluster, unsigned core) static void __init cps_smp_setup(void) { unsigned int nclusters, ncores, nvpes, core_vpes; - unsigned long core_entry; int cl, c, v; /* Detect & record VPE topology */ @@ -94,10 +94,20 @@ static void __init cps_smp_setup(void) /* Make core 0 coherent with everything */ write_gcr_cl_coherence(0xff); - if (mips_cm_revision() >= CM_REV_CM3) { - core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry); - write_gcr_bev_base(core_entry); - } + /* + * Set up the core entry address + * If accessible in KSEG1 just use KSEG1 + */ + if (__pa_symbol(mips_cps_core_entry) < SZ_512M) + core_entry_reg = CKSEG1ADDR(__pa_symbol(mips_cps_core_entry)); + + /* If CM is 64bit and with-in low 4G just use XKPHYS */ + if (mips_cm_is64 && __pa_symbol(mips_cps_core_entry) < SZ_4G) + core_entry_reg = __pa_symbol(mips_cps_core_entry) | + CM_GCR_Cx_RESET_BASE_MODE; + + if (core_entry_reg && mips_cm_revision() >= CM_REV_CM3) + write_gcr_bev_base(core_entry_reg); #ifdef CONFIG_MIPS_MT_FPAFF /* If we have an FPU, enroll ourselves in the FPU-full mask */ @@ -114,6 +124,11 @@ static void __init cps_prepare_cpus(unsigned int max_cpus) mips_mt_set_cpuoptions(); + if (!core_entry_reg) { + pr_err("core_entry address unsuitable, disabling smp-cps\n"); + goto err_out; + } + /* Detect whether the CCA is unsuited to multi-core SMP */ cca = read_c0_config() & CONF_CM_CMASK; switch (cca) { @@ -213,7 +228,7 @@ static void boot_core(unsigned int core, unsigned int vpe_id) mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL); /* Set its reset vector */ - write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry)); + write_gcr_co_reset_base(core_entry_reg); /* Ensure its coherency is disabled */ write_gcr_co_coherence(0); From patchwork Mon Oct 23 19:14:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiaxun Yang X-Patchwork-Id: 157044 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:ce89:0:b0:403:3b70:6f57 with SMTP id p9csp1500475vqx; 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Mon, 23 Oct 2023 15:14:11 -0400 (EDT) From: Jiaxun Yang To: linux-mips@vger.kernel.org Cc: linux-kernel@vger.kernel.org, tsbogend@alpha.franken.de, gregory.clement@bootlin.com, vladimir.kondratiev@intel.com, Jiaxun Yang Subject: [PATCH 5/5] MIPS: Allow kernel base to be set from Kconfig for all platforms Date: Mon, 23 Oct 2023 20:14:00 +0100 Message-Id: <20231023191400.170052-6-jiaxun.yang@flygoat.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231023191400.170052-1-jiaxun.yang@flygoat.com> References: <20231023191400.170052-1-jiaxun.yang@flygoat.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Mon, 23 Oct 2023 12:14:56 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780574845619700521 X-GMAIL-MSGID: 1780574845619700521 There are some platforms in wild that generic loading address won't work with them due to memory layout. Allow PHYSICAL_START to be override from Kconfig, introduce PHYSICAL_START_BOOL symbol as powerpc did. Signed-off-by: Jiaxun Yang --- arch/mips/Kconfig | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index bc8421859006..bfedc8b48a81 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -2884,12 +2884,22 @@ config ARCH_SUPPORTS_KEXEC config ARCH_SUPPORTS_CRASH_DUMP def_bool y +config PHYSICAL_START_BOOL + bool "Set physical address where the kernel is loaded" + default y if CRASH_DUMP + help + This gives the CKSEG0, KSEG0 or XKPHYS address where the kernel + is loaded. + + Say N here unless you know what you are doing. + config PHYSICAL_START - hex "Physical address where the kernel is loaded" - default "0xffffffff84000000" - depends on CRASH_DUMP + hex "Physical address where the kernel is loaded" if PHYSICAL_START_BOOL + default "0xffffffff84000000" if CRASH_DUMP + default "0xffffffff80100000" help - This gives the CKSEG0 or KSEG0 address where the kernel is loaded. + This gives the CKSEG0, KSEG0 or XKPHYS address where the kernel + is loaded. If you plan to use kernel for capturing the crash dump change this value to start of the reserved region (the "X" value as specified in the "crashkernel=YM@XM" command line boot parameter