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Mon, 23 Oct 2023 01:29:26 -0700 (PDT) From: Xu Lu To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, tglx@linutronix.de, maz@kernel.org, anup@brainfault.org, atishp@atishpatra.org Cc: dengliang.1214@bytedance.com, liyu.yukiteru@bytedance.com, sunjiadong.lff@bytedance.com, xieyongji@bytedance.com, lihangjing@bytedance.com, chaiwen.cc@bytedance.com, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Xu Lu Subject: [RFC 01/12] riscv: Introduce CONFIG_RISCV_PSEUDO_NMI Date: Mon, 23 Oct 2023 16:29:00 +0800 Message-Id: <20231023082911.23242-2-luxu.kernel@bytedance.com> X-Mailer: git-send-email 2.39.3 (Apple Git-145) In-Reply-To: <20231023082911.23242-1-luxu.kernel@bytedance.com> References: <20231023082911.23242-1-luxu.kernel@bytedance.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Mon, 23 Oct 2023 01:29:41 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780534250946767557 X-GMAIL-MSGID: 1780534250946767557 This commit introduces a new config RISCV_PSEUDO_NMI to control whether enabling the pseudo NMI feature on RISC-V. Signed-off-by: Xu Lu --- arch/riscv/Kconfig | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index d607ab0f7c6d..487e4293f31e 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -669,6 +669,16 @@ config RISCV_BOOT_SPINWAIT If unsure what to do here, say N. +config RISCV_PSEUDO_NMI + bool "Support for NMI-like interrupts" + depends on !RISCV_M_MODE + default n + help + Adds support for mimicking Non-Maskable Interrupts through the use of + CSR_IE register. + + If unsure, say N. + config ARCH_SUPPORTS_KEXEC def_bool MMU From patchwork Mon Oct 23 08:29:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xu Lu X-Patchwork-Id: 156736 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:ce89:0:b0:403:3b70:6f57 with SMTP id p9csp1151242vqx; Mon, 23 Oct 2023 01:31:34 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFLm4nyP6fbnpfrz7Ak5lFduRIespX6XV9GF7LygL2VEQoz4E/E2wMsLG7mlEiTXqwxlrh6 X-Received: by 2002:a17:902:d4c6:b0:1ca:15ad:1c6 with SMTP id o6-20020a170902d4c600b001ca15ad01c6mr6511501plg.33.1698049893756; Mon, 23 Oct 2023 01:31:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698049893; cv=none; d=google.com; s=arc-20160816; b=QsAdEtQdiRJunGhQi2eDtl0nWALgwnGNXjEZfjw/1n1XX24g1BrlnA/ZhG4YrGelrF +HxZRL+I9gOVw9JsX49uLSEjm/Ih0w1y3F+ZmcP0u9G400RGmmSLaD7vtq8lsePjCD0L 3NCtS3O8MFBusJT4ZAQgPDluzP0toOC9psJTwpTCltKUjlorovnhahhC2QwB3ha/lsnJ vFIJ9dw2U/oo2VrKGBwqip3DabAoE4QYs+apSjlN79pO8h90AJHDXALy9pPIWCeTpHWF weVBxQquyiBEdHGfsgKeN44O2WBYvvZZxyXg68yakQljHpCjsyWELLLWufNGGwUPlJDl EvUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=RLEuNYLzmNdpMekkYxMIqBfr7ettCjIz89PT5TQjtwM=; fh=O4eOVhHjKTyaSORSQqoF+Vv6GYDagG+8LotEUwhRqvg=; b=iEFLP2fkCYKRM1OWRz73AMsMVlIpd1nIzT+Az5zGVYYy87AnQF46jPglt5cf1qiZEN H1SI5wbB9TxiGYx/B1WRrc0bO7rXO1AvlWQuYQx3S3W8lH21j5Yodkbko1tz/zqIA4Ow Gi5YeMX1hyT+gnA2djTG0/L6ZkADjFACABstgMdnVOOsyWl1VprE+l+x+iTMENTQ2RM9 fQ8qs3o9EaPwtcLPDSOrTAFucQB4VBB68PsYva/zecG7DToBnz4jPnNNUZDxA67ijxB5 rmQ9sD6N2/3hDAZR5AgZRjMFVyZGNLazGG9Bpq7loGbAIbLoGA8It8jo0cz2FVZat9I3 vdsg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@bytedance.com header.s=google header.b=DfWQ88JR; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=bytedance.com Received: from snail.vger.email (snail.vger.email. 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Mon, 23 Oct 2023 01:29:32 -0700 (PDT) From: Xu Lu To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, tglx@linutronix.de, maz@kernel.org, anup@brainfault.org, atishp@atishpatra.org Cc: dengliang.1214@bytedance.com, liyu.yukiteru@bytedance.com, sunjiadong.lff@bytedance.com, xieyongji@bytedance.com, lihangjing@bytedance.com, chaiwen.cc@bytedance.com, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Xu Lu Subject: [RFC 02/12] riscv: Make CSR_IE register part of context Date: Mon, 23 Oct 2023 16:29:01 +0800 Message-Id: <20231023082911.23242-3-luxu.kernel@bytedance.com> X-Mailer: git-send-email 2.39.3 (Apple Git-145) In-Reply-To: <20231023082911.23242-1-luxu.kernel@bytedance.com> References: <20231023082911.23242-1-luxu.kernel@bytedance.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Mon, 23 Oct 2023 01:30:18 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780534365174682994 X-GMAIL-MSGID: 1780534365174682994 This commit makes CSR_IE register part of thread context. Kernel nowadays saves and restores irq status of each thread via CSR_STATUS register. When a thread traps into kernel, irq status of it is automatically stored in SR_PIE field of CSR_STATUS by hardware. And when kernel returns back, irq status will be automatically restored from CSR_STATUS. Things get different when we switch to CSR_IE masking for irq disabling. Hardware won't save or restore CSR_IE value during traps. In this case, when trapped into kernel, we should save CSR_IE value for previous thread manually and then clear all CSR_IE bits to disable irqs during traps. Also, we should manually restore SIE field of CSR_STATUS as we do not depends on it to disable irqs. When kernel returns back, we manually restore CSR_IE value from previous saved value. Signed-off-by: Xu Lu Signed-off-by: Hangjing Li Reviewed-by: Liang Deng Reviewed-by: Yu Li --- arch/riscv/include/asm/csr.h | 17 +++++++++++++++++ arch/riscv/include/asm/ptrace.h | 3 +++ arch/riscv/kernel/asm-offsets.c | 3 +++ arch/riscv/kernel/entry.S | 13 +++++++++++++ arch/riscv/kernel/process.c | 6 ++++++ arch/riscv/kernel/suspend_entry.S | 1 + drivers/clocksource/timer-clint.c | 4 ++++ drivers/clocksource/timer-riscv.c | 4 ++++ drivers/irqchip/irq-riscv-intc.c | 4 ++++ drivers/perf/riscv_pmu_sbi.c | 4 ++++ 10 files changed, 59 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 777cb8299551..6520bd826d52 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -7,6 +7,7 @@ #define _ASM_RISCV_CSR_H #include +#include #include /* Status register flags */ @@ -451,6 +452,22 @@ #define IE_TIE (_AC(0x1, UL) << RV_IRQ_TIMER) #define IE_EIE (_AC(0x1, UL) << RV_IRQ_EXT) +#ifdef CONFIG_RISCV_PSEUDO_NMI +#define IRQS_ENABLED_IE (IE_SIE | IE_TIE | IE_EIE) +#define irqs_enabled_ie \ +({ \ + unsigned long __v; \ + asm (ALTERNATIVE( \ + "li %0, " __stringify(IRQS_ENABLED_IE) "\n\t" \ + "nop", \ + "li %0, " __stringify(IRQS_ENABLED_IE | SIP_LCOFIP),\ + 0, RISCV_ISA_EXT_SSCOFPMF, \ + CONFIG_RISCV_PSEUDO_NMI) \ + : "=r"(__v) : : ); \ + __v; \ +}) +#endif /* CONFIG_RISCV_PSEUDO_NMI */ + #ifndef __ASSEMBLY__ #define csr_swap(csr, val) \ diff --git a/arch/riscv/include/asm/ptrace.h b/arch/riscv/include/asm/ptrace.h index b5b0adcc85c1..b57d3a6b232f 100644 --- a/arch/riscv/include/asm/ptrace.h +++ b/arch/riscv/include/asm/ptrace.h @@ -47,6 +47,9 @@ struct pt_regs { unsigned long t6; /* Supervisor/Machine CSRs */ unsigned long status; +#ifdef CONFIG_RISCV_PSEUDO_NMI + unsigned long ie; +#endif unsigned long badaddr; unsigned long cause; /* a0 value before the syscall */ diff --git a/arch/riscv/kernel/asm-offsets.c b/arch/riscv/kernel/asm-offsets.c index d6a75aac1d27..165f6f9fc458 100644 --- a/arch/riscv/kernel/asm-offsets.c +++ b/arch/riscv/kernel/asm-offsets.c @@ -112,6 +112,9 @@ void asm_offsets(void) OFFSET(PT_GP, pt_regs, gp); OFFSET(PT_ORIG_A0, pt_regs, orig_a0); OFFSET(PT_STATUS, pt_regs, status); +#ifdef CONFIG_RISCV_PSEUDO_NMI + OFFSET(PT_IE, pt_regs, ie); +#endif OFFSET(PT_BADADDR, pt_regs, badaddr); OFFSET(PT_CAUSE, pt_regs, cause); diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 143a2bb3e697..19ba7c4520b9 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -65,6 +65,10 @@ _save_context: REG_S s3, PT_BADADDR(sp) REG_S s4, PT_CAUSE(sp) REG_S s5, PT_TP(sp) +#ifdef CONFIG_RISCV_PSEUDO_NMI + csrr s0, CSR_IE + REG_S s0, PT_IE(sp) +#endif /* CONFIG_RISCV_PSEUDO_NMI */ /* * Set the scratch register to 0, so that if a recursive exception @@ -153,6 +157,11 @@ SYM_CODE_START_NOALIGN(ret_from_exception) csrw CSR_STATUS, a0 csrw CSR_EPC, a2 +#ifdef CONFIG_RISCV_PSEUDO_NMI + REG_L s0, PT_IE(sp) + csrw CSR_IE, s0 +#endif /* CONFIG_RISCV_PSEUDO_NMI */ + REG_L x1, PT_RA(sp) REG_L x3, PT_GP(sp) REG_L x4, PT_TP(sp) @@ -251,6 +260,10 @@ restore_caller_reg: REG_S s3, PT_BADADDR(sp) REG_S s4, PT_CAUSE(sp) REG_S s5, PT_TP(sp) +#ifdef CONFIG_RISCV_PSEUDO_NMI + csrr s0, CSR_IE + REG_S s0, PT_IE(sp) +#endif /* CONFIG_RISCV_PSEUDO_NMI */ move a0, sp tail handle_bad_stack SYM_CODE_END(handle_kernel_stack_overflow) diff --git a/arch/riscv/kernel/process.c b/arch/riscv/kernel/process.c index e32d737e039f..9663bae23c57 100644 --- a/arch/riscv/kernel/process.c +++ b/arch/riscv/kernel/process.c @@ -115,6 +115,9 @@ void start_thread(struct pt_regs *regs, unsigned long pc, unsigned long sp) { regs->status = SR_PIE; +#ifdef CONFIG_RISCV_PSEUDO_NMI + regs->ie = irqs_enabled_ie; +#endif if (has_fpu()) { regs->status |= SR_FS_INITIAL; /* @@ -189,6 +192,9 @@ int copy_thread(struct task_struct *p, const struct kernel_clone_args *args) childregs->gp = gp_in_global; /* Supervisor/Machine, irqs on: */ childregs->status = SR_PP | SR_PIE; +#ifdef CONFIG_RISCV_PSEUDO_NMI + childregs->ie = irqs_enabled_ie; +#endif p->thread.s[0] = (unsigned long)args->fn; p->thread.s[1] = (unsigned long)args->fn_arg; diff --git a/arch/riscv/kernel/suspend_entry.S b/arch/riscv/kernel/suspend_entry.S index f7960c7c5f9e..6825f4836be4 100644 --- a/arch/riscv/kernel/suspend_entry.S +++ b/arch/riscv/kernel/suspend_entry.S @@ -47,6 +47,7 @@ ENTRY(__cpu_suspend_enter) REG_S t0, (SUSPEND_CONTEXT_REGS + PT_EPC)(a0) csrr t0, CSR_STATUS REG_S t0, (SUSPEND_CONTEXT_REGS + PT_STATUS)(a0) + /* There is no need to save CSR_IE as it is maintained in memory */ csrr t0, CSR_TVAL REG_S t0, (SUSPEND_CONTEXT_REGS + PT_BADADDR)(a0) csrr t0, CSR_CAUSE diff --git a/drivers/clocksource/timer-clint.c b/drivers/clocksource/timer-clint.c index 9a55e733ae99..bdc10be9d3b4 100644 --- a/drivers/clocksource/timer-clint.c +++ b/drivers/clocksource/timer-clint.c @@ -114,7 +114,9 @@ static int clint_clock_next_event(unsigned long delta, void __iomem *r = clint_timer_cmp + cpuid_to_hartid_map(smp_processor_id()); +#ifndef CONFIG_RISCV_PSEUDO_NMI csr_set(CSR_IE, IE_TIE); +#endif writeq_relaxed(clint_get_cycles64() + delta, r); return 0; } @@ -155,7 +157,9 @@ static irqreturn_t clint_timer_interrupt(int irq, void *dev_id) { struct clock_event_device *evdev = this_cpu_ptr(&clint_clock_event); +#ifndef CONFIG_RISCV_PSEUDO_NMI csr_clear(CSR_IE, IE_TIE); +#endif evdev->event_handler(evdev); return IRQ_HANDLED; diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index da3071b387eb..b730e01a7f02 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -36,7 +36,9 @@ static int riscv_clock_next_event(unsigned long delta, { u64 next_tval = get_cycles64() + delta; +#ifndef CONFIG_RISCV_PSEUDO_NMI csr_set(CSR_IE, IE_TIE); +#endif if (static_branch_likely(&riscv_sstc_available)) { #if defined(CONFIG_32BIT) csr_write(CSR_STIMECMP, next_tval & 0xFFFFFFFF); @@ -119,7 +121,9 @@ static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id) { struct clock_event_device *evdev = this_cpu_ptr(&riscv_clock_event); +#ifndef CONFIG_RISCV_PSEUDO_NMI csr_clear(CSR_IE, IE_TIE); +#endif evdev->event_handler(evdev); return IRQ_HANDLED; diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index e8d01b14ccdd..7fad1ba37e5c 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -39,12 +39,16 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *regs) static void riscv_intc_irq_mask(struct irq_data *d) { +#ifndef CONFIG_RISCV_PSEUDO_NMI csr_clear(CSR_IE, BIT(d->hwirq)); +#endif } static void riscv_intc_irq_unmask(struct irq_data *d) { +#ifndef CONFIG_RISCV_PSEUDO_NMI csr_set(CSR_IE, BIT(d->hwirq)); +#endif } static void riscv_intc_irq_eoi(struct irq_data *d) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 96c7f670c8f0..995b501ec721 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -778,7 +778,9 @@ static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node) if (riscv_pmu_use_irq) { cpu_hw_evt->irq = riscv_pmu_irq; csr_clear(CSR_IP, BIT(riscv_pmu_irq_num)); +#ifndef CONFIG_RISCV_PSEUDO_NMI csr_set(CSR_IE, BIT(riscv_pmu_irq_num)); +#endif enable_percpu_irq(riscv_pmu_irq, IRQ_TYPE_NONE); } @@ -789,7 +791,9 @@ static int pmu_sbi_dying_cpu(unsigned int cpu, struct hlist_node *node) { if (riscv_pmu_use_irq) { disable_percpu_irq(riscv_pmu_irq); +#ifndef CONFIG_RISCV_PSEUDO_NMI csr_clear(CSR_IE, BIT(riscv_pmu_irq_num)); +#endif } /* Disable all counters access for user mode now */ From patchwork Mon Oct 23 08:29:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xu Lu X-Patchwork-Id: 156735 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:ce89:0:b0:403:3b70:6f57 with SMTP id p9csp1151239vqx; Mon, 23 Oct 2023 01:31:33 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFltBrOnU7y/mM7un8XvSILVfLOlJpadSyfHCjOltuta/Fs910Sg3ZQYTCavml9bl6U/+QE X-Received: by 2002:a17:902:da8c:b0:1c3:4565:22f with SMTP id j12-20020a170902da8c00b001c34565022fmr9511167plx.21.1698049893625; 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Mon, 23 Oct 2023 01:29:37 -0700 (PDT) From: Xu Lu To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, tglx@linutronix.de, maz@kernel.org, anup@brainfault.org, atishp@atishpatra.org Cc: dengliang.1214@bytedance.com, liyu.yukiteru@bytedance.com, sunjiadong.lff@bytedance.com, xieyongji@bytedance.com, lihangjing@bytedance.com, chaiwen.cc@bytedance.com, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Xu Lu Subject: [RFC 03/12] riscv: Switch to CSR_IE masking when disabling irqs Date: Mon, 23 Oct 2023 16:29:02 +0800 Message-Id: <20231023082911.23242-4-luxu.kernel@bytedance.com> X-Mailer: git-send-email 2.39.3 (Apple Git-145) In-Reply-To: <20231023082911.23242-1-luxu.kernel@bytedance.com> References: <20231023082911.23242-1-luxu.kernel@bytedance.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Mon, 23 Oct 2023 01:30:09 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780534365066802877 X-GMAIL-MSGID: 1780534365066802877 This commit switch the way of disabling irqs to CSR_IE masking. After CSR_IE has been made a part of context, now we can safely switch to CSR_IE masking when disabling irqs. Signed-off-by: Xu Lu Signed-off-by: Hangjing Li Reviewed-by: Liang Deng Reviewed-by: Yu Li --- arch/riscv/include/asm/irqflags.h | 58 +++++++++++++++++++++++++++++++ arch/riscv/include/asm/ptrace.h | 4 +++ arch/riscv/kernel/entry.S | 7 +++- arch/riscv/kernel/head.S | 10 ++++++ 4 files changed, 78 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/irqflags.h b/arch/riscv/include/asm/irqflags.h index 08d4d6a5b7e9..e0ff37315178 100644 --- a/arch/riscv/include/asm/irqflags.h +++ b/arch/riscv/include/asm/irqflags.h @@ -10,6 +10,62 @@ #include #include +#ifdef CONFIG_RISCV_PSEUDO_NMI + +static inline void local_irq_switch_on(void) +{ + csr_set(CSR_STATUS, SR_IE); +} + +static inline void local_irq_switch_off(void) +{ + csr_clear(CSR_STATUS, SR_IE); +} + +/* read interrupt enabled status */ +static inline unsigned long arch_local_save_flags(void) +{ + return csr_read(CSR_IE); +} + +/* unconditionally enable interrupts */ +static inline void arch_local_irq_enable(void) +{ + csr_set(CSR_IE, irqs_enabled_ie); +} + +/* unconditionally disable interrupts */ +static inline void arch_local_irq_disable(void) +{ + csr_clear(CSR_IE, irqs_enabled_ie); +} + +/* get status and disable interrupts */ +static inline unsigned long arch_local_irq_save(void) +{ + return csr_read_clear(CSR_IE, irqs_enabled_ie); +} + +/* test flags */ +static inline int arch_irqs_disabled_flags(unsigned long flags) +{ + return (flags != irqs_enabled_ie); +} + +/* test hardware interrupt enable bit */ +static inline int arch_irqs_disabled(void) +{ + return arch_irqs_disabled_flags(arch_local_save_flags()); +} + +/* set interrupt enabled status */ +static inline void arch_local_irq_restore(unsigned long flags) +{ + csr_write(CSR_IE, flags); +} + +#else /* CONFIG_RISCV_PSEUDO_NMI */ + /* read interrupt enabled status */ static inline unsigned long arch_local_save_flags(void) { @@ -52,4 +108,6 @@ static inline void arch_local_irq_restore(unsigned long flags) csr_set(CSR_STATUS, flags & SR_IE); } +#endif /* !CONFIG_RISCV_PSEUDO_NMI */ + #endif /* _ASM_RISCV_IRQFLAGS_H */ diff --git a/arch/riscv/include/asm/ptrace.h b/arch/riscv/include/asm/ptrace.h index b57d3a6b232f..e552e7fb46f3 100644 --- a/arch/riscv/include/asm/ptrace.h +++ b/arch/riscv/include/asm/ptrace.h @@ -178,7 +178,11 @@ static inline unsigned long regs_get_kernel_argument(struct pt_regs *regs, static inline int regs_irqs_disabled(struct pt_regs *regs) { +#ifdef CONFIG_RISCV_PSEUDO_NMI + return (regs->ie != irqs_enabled_ie); +#else return !(regs->status & SR_PIE); +#endif } #endif /* __ASSEMBLY__ */ diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index 19ba7c4520b9..d1f28dab02f7 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -66,8 +66,13 @@ _save_context: REG_S s4, PT_CAUSE(sp) REG_S s5, PT_TP(sp) #ifdef CONFIG_RISCV_PSEUDO_NMI - csrr s0, CSR_IE + csrrw s0, CSR_IE, x0 REG_S s0, PT_IE(sp) + andi s1, s1, SR_PIE + beqz s1, 1f + li s1, SR_IE + csrs CSR_STATUS, s1 +1: #endif /* CONFIG_RISCV_PSEUDO_NMI */ /* diff --git a/arch/riscv/kernel/head.S b/arch/riscv/kernel/head.S index 3710ea5d160f..4f9446defacd 100644 --- a/arch/riscv/kernel/head.S +++ b/arch/riscv/kernel/head.S @@ -169,6 +169,10 @@ secondary_start_sbi: call relocate_enable_mmu #endif call setup_trap_vector +#ifdef CONFIG_RISCV_PSEUDO_NMI + li t0, SR_IE + csrs CSR_STATUS, t0 +#endif tail smp_callin #endif /* CONFIG_SMP */ @@ -320,6 +324,12 @@ clear_bss_done: #ifdef CONFIG_KASAN call kasan_early_init #endif + +#ifdef CONFIG_RISCV_PSEUDO_NMI + li t0, SR_IE + csrs CSR_STATUS, t0 +#endif + /* Start the kernel */ call soc_early_init tail start_kernel From patchwork Mon Oct 23 08:29:03 2023 Content-Type: text/plain; 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Mon, 23 Oct 2023 01:29:43 -0700 (PDT) From: Xu Lu To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, tglx@linutronix.de, maz@kernel.org, anup@brainfault.org, atishp@atishpatra.org Cc: dengliang.1214@bytedance.com, liyu.yukiteru@bytedance.com, sunjiadong.lff@bytedance.com, xieyongji@bytedance.com, lihangjing@bytedance.com, chaiwen.cc@bytedance.com, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Xu Lu Subject: [RFC 04/12] riscv: Switch back to CSR_STATUS masking when going idle Date: Mon, 23 Oct 2023 16:29:03 +0800 Message-Id: <20231023082911.23242-5-luxu.kernel@bytedance.com> X-Mailer: git-send-email 2.39.3 (Apple Git-145) In-Reply-To: <20231023082911.23242-1-luxu.kernel@bytedance.com> References: <20231023082911.23242-1-luxu.kernel@bytedance.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Mon, 23 Oct 2023 01:30:59 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780534367823033547 X-GMAIL-MSGID: 1780534367823033547 The WFI instruction makes current core stall until interrupt happens. In WFI's implementation, core can only be waken up from interrupt which is both pending in CSR_IP and enabled in CSR_IE. After we switch to CSR_IE masking for irq disabling, WFI instruction can never resume execution if CSR_IE is masked. This commit handles this special case. When WFI instruction is called with CSR_IE masked, we unmask CSR_IE first and disable irqs in traditional CSR_STATUS way instead. Signed-off-by: Xu Lu --- arch/riscv/include/asm/processor.h | 4 ++++ arch/riscv/kernel/irq.c | 17 +++++++++++++++++ 2 files changed, 21 insertions(+) diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/processor.h index 3e23e1786d05..ab9b2b974979 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -111,10 +111,14 @@ extern void start_thread(struct pt_regs *regs, extern unsigned long __get_wchan(struct task_struct *p); +#ifndef CONFIG_RISCV_PSEUDO_NMI static inline void wait_for_interrupt(void) { __asm__ __volatile__ ("wfi"); } +#else +void wait_for_interrupt(void); +#endif struct device_node; int riscv_of_processor_hartid(struct device_node *node, unsigned long *hartid); diff --git a/arch/riscv/kernel/irq.c b/arch/riscv/kernel/irq.c index 9cc0a7669271..e7dfd68e9ca3 100644 --- a/arch/riscv/kernel/irq.c +++ b/arch/riscv/kernel/irq.c @@ -15,6 +15,23 @@ #include #include +#ifdef CONFIG_RISCV_PSEUDO_NMI + +void wait_for_interrupt(void) +{ + if (irqs_disabled()) { + local_irq_switch_off(); + local_irq_enable(); + __asm__ __volatile__ ("wfi"); + local_irq_disable(); + local_irq_switch_on(); + } else { + __asm__ __volatile__ ("wfi"); + } +} + +#endif /* CONFIG_RISCV_PSEUDO_NMI */ + static struct fwnode_handle *(*__get_intc_node)(void); void riscv_set_intc_hwnode_fn(struct fwnode_handle *(*fn)(void)) From patchwork Mon Oct 23 08:29:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xu Lu X-Patchwork-Id: 156745 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:ce89:0:b0:403:3b70:6f57 with SMTP id p9csp1151457vqx; Mon, 23 Oct 2023 01:32:15 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGUPmZ3DHty8kywpZivjK/h8HHr8P4fQQc5jlkfewUy+5y+lwjs6nyjk8wwdrMI032SL8f5 X-Received: by 2002:a17:903:1110:b0:1c8:9832:827f with SMTP id n16-20020a170903111000b001c89832827fmr7042313plh.20.1698049934805; Mon, 23 Oct 2023 01:32:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698049934; cv=none; d=google.com; s=arc-20160816; b=LGmDB1CF//aJlWre1n5oS8zFYKLXlY0/2JqrOzchs1zi1tM0+4ieoEXC7rQOrmSjY9 52eSO5Xr0tVndQO0DnhM06mCTsOMJKzS6HvzAUPsHinjYtlIPHAEaE9p6U55PWWoRAAj n+9NyZA3UfVD/fn2oKpxNTs9MAcqhkre1rqupdXLg4LdNZPxI7fuVHOStoUuyQIefH3u wwafAhqhOIejUgH6ZP7bZNmHhkiXfbEbpvGqFicd2hIjknu4QuvGWUpPDCHfJLNGPtj0 YV6N0M3qsxWuauBVir2ObnuheeX1cdYdW8PZAzgdaBIGc02om7aExjq0BSMDfzc16FgK /wsA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=4WLOSQOA5Tm0Adw6Ut8ujQkn4XXYrNjbdXHKCGaB3LM=; fh=O4eOVhHjKTyaSORSQqoF+Vv6GYDagG+8LotEUwhRqvg=; b=vlHO+GbPhtgQUB1sXXvJyA6d6vpeTkUsuH8Q3Uc7G7FDWoS4TaieyQr8U4o3gzFuIz Yh/NldJJQfR/L+TZSLdNbgJW9p8TfWmmsaoMNRrTaIUy25a6RByciCGRFqiIzRtksDgp PFMkXL1j1+GMdaf2Qik1KS7Ijjj8OcLCQD/tLfWZWOY+CzC2yjiyJESY0mR2F2hq7YhR NhmFAmONxJTSdGsjXvQoMtzLfVPskvPS5cCyaIahAWQb8eglbpoxxQtQDX8n4DweikSH mawa00DGkZoaNMgPOU7UuqDvMvQ/4MpKrdKD5dDH1zj0zAKyD57vKW38sH5AtQMBhQbo liMw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@bytedance.com header.s=google header.b=iLxR9CpP; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=bytedance.com Received: from lipwig.vger.email (lipwig.vger.email. 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Mon, 23 Oct 2023 01:29:49 -0700 (PDT) From: Xu Lu To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, tglx@linutronix.de, maz@kernel.org, anup@brainfault.org, atishp@atishpatra.org Cc: dengliang.1214@bytedance.com, liyu.yukiteru@bytedance.com, sunjiadong.lff@bytedance.com, xieyongji@bytedance.com, lihangjing@bytedance.com, chaiwen.cc@bytedance.com, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Xu Lu Subject: [RFC 05/12] riscv: kvm: Switch back to CSR_STATUS masking when entering guest Date: Mon, 23 Oct 2023 16:29:04 +0800 Message-Id: <20231023082911.23242-6-luxu.kernel@bytedance.com> X-Mailer: git-send-email 2.39.3 (Apple Git-145) In-Reply-To: <20231023082911.23242-1-luxu.kernel@bytedance.com> References: <20231023082911.23242-1-luxu.kernel@bytedance.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Mon, 23 Oct 2023 01:30:12 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780534408366933170 X-GMAIL-MSGID: 1780534408366933170 When kvm enters vcpu, it first disables local irqs before preparing vcpu context and uses SRET instruction to enter guest mode after vcpu context is ready, which automatically restores guest's irq status. However, after we switch to CSR_IE masking for interrupt disabling, the SRET instruction itself can not restore guest's irq status correctly as interrupts are still masked by CSR_IE. This commit handles this special case by switching to traditional CSR_STATUS way to disable irqs before entering guest mode. Signed-off-by: Xu Lu --- arch/riscv/include/asm/irqflags.h | 3 +++ arch/riscv/kvm/vcpu.c | 18 +++++++++++++----- 2 files changed, 16 insertions(+), 5 deletions(-) diff --git a/arch/riscv/include/asm/irqflags.h b/arch/riscv/include/asm/irqflags.h index e0ff37315178..60c19f8b57f0 100644 --- a/arch/riscv/include/asm/irqflags.h +++ b/arch/riscv/include/asm/irqflags.h @@ -64,6 +64,9 @@ static inline void arch_local_irq_restore(unsigned long flags) csr_write(CSR_IE, flags); } +#define local_irq_enable_vcpu_run local_irq_switch_on +#define local_irq_disable_vcpu_run local_irq_switch_off + #else /* CONFIG_RISCV_PSEUDO_NMI */ /* read interrupt enabled status */ diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index 82229db1ce73..233408247da7 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -621,6 +621,14 @@ static void noinstr kvm_riscv_vcpu_enter_exit(struct kvm_vcpu *vcpu) guest_state_exit_irqoff(); } +#ifndef local_irq_enable_vcpu_run +#define local_irq_enable_vcpu_run local_irq_enable +#endif + +#ifndef local_irq_disable_vcpu_run +#define local_irq_disable_vcpu_run local_irq_disable +#endif + int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) { int ret; @@ -685,7 +693,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) continue; } - local_irq_disable(); + local_irq_disable_vcpu_run(); /* * Ensure we set mode to IN_GUEST_MODE after we disable @@ -712,7 +720,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) kvm_request_pending(vcpu) || xfer_to_guest_mode_work_pending()) { vcpu->mode = OUTSIDE_GUEST_MODE; - local_irq_enable(); + local_irq_enable_vcpu_run(); preempt_enable(); kvm_vcpu_srcu_read_lock(vcpu); continue; @@ -757,12 +765,12 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) * recognised, so we just hope that the CPU takes any pending * interrupts between the enable and disable. */ - local_irq_enable(); - local_irq_disable(); + local_irq_enable_vcpu_run(); + local_irq_disable_vcpu_run(); guest_timing_exit_irqoff(); - local_irq_enable(); + local_irq_enable_vcpu_run(); preempt_enable(); From patchwork Mon Oct 23 08:29:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xu Lu X-Patchwork-Id: 156737 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:ce89:0:b0:403:3b70:6f57 with SMTP id p9csp1151244vqx; Mon, 23 Oct 2023 01:31:34 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGsTMXV8rAhVyrxPXox/xYNTI8btrI/2MLlygRXffEVaq7t7lYN39VAJn2IKUOqzlbGRgmQ X-Received: by 2002:a17:90b:2b85:b0:27d:1339:9176 with SMTP id rs5-20020a17090b2b8500b0027d13399176mr6179015pjb.25.1698049893837; Mon, 23 Oct 2023 01:31:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698049893; cv=none; d=google.com; s=arc-20160816; b=Be5dUTPupRwL2jyKZnyT/XYdVhM+bo/udCv2HDFknIiWMTv68SS97QN4ddXRHIb2Yd ctOPSJrS0ohLvoRwEPZjv1OML3c0lxGDBMhJeKrmNJxUkHXLm3es/RTI6kHxVWo0I3oE QKvD6QxiuhokT3pf7csrj/0MYvPHg2duPXlQB3noAJGRr2gnkk1iM8Fs1rbXqNDhZNF0 bV3GDo6hXMfXP2SbWB0FlCr/3kgTpdrz8WSfs3XR2/aqNCDDsuKDdHkGL4MIOTHxGIGZ fiwK47vDAAWI19zpQ3jvbqUTT4P7uQR5jkfX4JfQ45Ja6opunJuytkZ4Cbkg4rAF9UOP fWgw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=AUO1/BVdvM4H5C6LBNItdP0IIJipRGNxmDV7eD7nopg=; fh=O4eOVhHjKTyaSORSQqoF+Vv6GYDagG+8LotEUwhRqvg=; b=cek/fq7M3Pvuoq715KAZpFUmfc31Nlx2q36RbyWIba2mJ7rvpkCVLmtOpsHZfZ6IDE QBi6z7Rc1ItPRFUs8P0Qxb9ZgsFMY5GEvvGwAU/5x7ksj41WkMOrtiJEaBqinRSEv/Td vBPQgGQ9lYdrg48j9Ie/NFRfCKZOF+a086KsCF3tOGz+t/ajYl43hIyDaPhJYrXGx75f 4iff08T6XgaEWVqkRTHw5k/QrzAHDeEjTb2Gre1eXu6kVHkaZqRz52y59juvy2qou2zc CfMaJ+p6OS8ddIYP3RfrhwJUFZzRaFyp8au49bTk+N+FXbGo/zaiRT5vljUPcR7eATQd vr+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@bytedance.com header.s=google header.b=eIYgUBkX; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=bytedance.com Received: from morse.vger.email (morse.vger.email. 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Mon, 23 Oct 2023 01:29:54 -0700 (PDT) From: Xu Lu To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, tglx@linutronix.de, maz@kernel.org, anup@brainfault.org, atishp@atishpatra.org Cc: dengliang.1214@bytedance.com, liyu.yukiteru@bytedance.com, sunjiadong.lff@bytedance.com, xieyongji@bytedance.com, lihangjing@bytedance.com, chaiwen.cc@bytedance.com, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Xu Lu Subject: [RFC 06/12] riscv: Allow requesting irq as pseudo NMI Date: Mon, 23 Oct 2023 16:29:05 +0800 Message-Id: <20231023082911.23242-7-luxu.kernel@bytedance.com> X-Mailer: git-send-email 2.39.3 (Apple Git-145) In-Reply-To: <20231023082911.23242-1-luxu.kernel@bytedance.com> References: <20231023082911.23242-1-luxu.kernel@bytedance.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Mon, 23 Oct 2023 01:30:22 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780534365455877037 X-GMAIL-MSGID: 1780534365455877037 This commit implements pseudo NMI callbacks for riscv_intc_irq chip. We use an immediate macro to denote NMIs of each cpu. Each bit of it represents an irq. Bit 1 means corresponding irq is registered as NMI while bit 0 means not. Signed-off-by: Xu Lu Signed-off-by: Hangjing Li Reviewed-by: Liang Deng Reviewed-by: Yu Li --- arch/riscv/include/asm/irqflags.h | 17 ++++++++++++++ drivers/irqchip/irq-riscv-intc.c | 38 +++++++++++++++++++++++++++++++ 2 files changed, 55 insertions(+) diff --git a/arch/riscv/include/asm/irqflags.h b/arch/riscv/include/asm/irqflags.h index 60c19f8b57f0..9700a17a003a 100644 --- a/arch/riscv/include/asm/irqflags.h +++ b/arch/riscv/include/asm/irqflags.h @@ -12,6 +12,23 @@ #ifdef CONFIG_RISCV_PSEUDO_NMI +#define __ALLOWED_NMI_MASK 0 +#define ALLOWED_NMI_MASK (__ALLOWED_NMI_MASK & irqs_enabled_ie) + +static inline bool nmi_allowed(int irq) +{ + return (BIT(irq) & ALLOWED_NMI_MASK); +} + +static inline bool is_nmi(int irq) +{ + return (BIT(irq) & ALLOWED_NMI_MASK); +} + +static inline void set_nmi(int irq) {} + +static inline void unset_nmi(int irq) {} + static inline void local_irq_switch_on(void) { csr_set(CSR_STATUS, SR_IE); diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index 7fad1ba37e5c..83a0a744fce6 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -67,11 +67,49 @@ static void riscv_intc_irq_eoi(struct irq_data *d) */ } +#ifdef CONFIG_RISCV_PSEUDO_NMI + +static int riscv_intc_irq_nmi_setup(struct irq_data *d) +{ + unsigned int hwirq = d->hwirq; + struct irq_desc *desc = irq_to_desc(d->irq); + + if (WARN_ON((hwirq >= BITS_PER_LONG) || !nmi_allowed(hwirq))) + return -EINVAL; + + desc->handle_irq = handle_percpu_devid_fasteoi_nmi; + set_nmi(hwirq); + + return 0; +} + +static void riscv_intc_irq_nmi_teardown(struct irq_data *d) +{ + unsigned int hwirq = d->hwirq; + struct irq_desc *desc = irq_to_desc(d->irq); + + if (WARN_ON(hwirq >= BITS_PER_LONG)) + return; + + if (WARN_ON(!is_nmi(hwirq))) + return; + + desc->handle_irq = handle_percpu_devid_irq; + unset_nmi(hwirq); +} + +#endif /* CONFIG_RISCV_PSEUDO_NMI */ + static struct irq_chip riscv_intc_chip = { .name = "RISC-V INTC", .irq_mask = riscv_intc_irq_mask, .irq_unmask = riscv_intc_irq_unmask, .irq_eoi = riscv_intc_irq_eoi, +#ifdef CONFIG_RISCV_PSEUDO_NMI + .irq_nmi_setup = riscv_intc_irq_nmi_setup, + .irq_nmi_teardown = riscv_intc_irq_nmi_teardown, + .flags = IRQCHIP_SUPPORTS_NMI, +#endif }; static int riscv_intc_domain_map(struct irq_domain *d, unsigned int irq, From patchwork Mon Oct 23 08:29:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xu Lu X-Patchwork-Id: 156738 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:ce89:0:b0:403:3b70:6f57 with SMTP id p9csp1151248vqx; Mon, 23 Oct 2023 01:31:34 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF1WaGipcmJF0trCqsRegxEqMUB/4yHF4raRwL2yj8nRKWWVy6EoRb0ciwdBPruHJd8Ccn5 X-Received: by 2002:a05:6870:3893:b0:1ea:29a:861e with SMTP id y19-20020a056870389300b001ea029a861emr9078743oan.12.1698049894464; Mon, 23 Oct 2023 01:31:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698049894; cv=none; d=google.com; s=arc-20160816; b=Ks3qksOGkyxIIoWuP/a0QsJrD0M70U1oxtBTNa3/PNIo2KCHUsdSI2hbz9LxJdHmB8 eGD9nXa0QXvyUXtHWpEZDZ1FDRIjKEUOkX0gi0vFNrkx7pC2eNn3Vsr5UthLz3Mo1JQN VpAkqT+7rl4x5sSdVWc9eU7Zdztb7Hr06sI1U5/KZZqgplzHrseWshPv1OW2p8QMZHBh CI9hOgAKIEA7HREu23LiVUTATdQGJarxsB4zh3fv+lpRf86A3WuY04yrz4KhVg/AMt6S IhOcdFGN3+VMOOiFyiQhLxe6Y1E+nt4/83fuGE6XjUkjCxBEZXbwFaodKQ+cWOgEaOgz mKGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=KDj8p8VlOUWmt6ePZtJj52Ju7p2Y1636xaXynBRmH4M=; fh=O4eOVhHjKTyaSORSQqoF+Vv6GYDagG+8LotEUwhRqvg=; b=B96dK7fHG5sESjTcPRsqd+g0YZSxrEMD5Z++WiTBO/8eS6csAQZUbWfSvTVIsadpGl BfdadHdu4XbY1CENrhexow1kwCmLkthdVLviwRx5LAUTUEYHvTh6/XAh2EUuKV1XgrVk nti/mBfuWmzYl6mZrTkzZJ5ljeyN6O6fUhfUTc9I1VubCs/Qvi6olAHD4uJgudvXWbKa WP2uMwB8QO8NlDTsdNw0EfwZxsj/CUZoKfWJpuNSgxJ5Ee/K/dYVA7+IU4b03VjgGNRB LAR6WUoWI86t/BIVUwzcns+HDkXU+89YR0uywsJu42jPZw4PwtW0l6+rV9bP3tcb233D d8bw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@bytedance.com header.s=google header.b=ESLob1Ub; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=bytedance.com Received: from fry.vger.email (fry.vger.email. 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We enter NMI context before handling NMI and keeps all interrupts disabled during NMI handling to avoid interrupt nesting. Signed-off-by: Xu Lu Signed-off-by: Hangjing Li --- drivers/irqchip/irq-riscv-intc.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index 83a0a744fce6..c672c0c64d5d 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -20,6 +20,26 @@ static struct irq_domain *intc_domain; +#ifdef CONFIG_RISCV_PSEUDO_NMI + +static asmlinkage void riscv_intc_irq(struct pt_regs *regs) +{ + unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG; + + if (unlikely(cause >= BITS_PER_LONG)) + panic("unexpected interrupt cause"); + + if (is_nmi(cause)) { + nmi_enter(); + generic_handle_domain_nmi(intc_domain, cause); + nmi_exit(); + } else { + generic_handle_domain_irq(intc_domain, cause); + } +} + +#else /* CONFIG_RISCV_PSEUDO_NMI */ + static asmlinkage void riscv_intc_irq(struct pt_regs *regs) { unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG; @@ -30,6 +50,8 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *regs) generic_handle_domain_irq(intc_domain, cause); } +#endif /* CONFIG_RISCV_PSEUDO_NMI */ + /* * On RISC-V systems local interrupts are masked or unmasked by writing * the SIE (Supervisor Interrupt Enable) CSR. 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Mon, 23 Oct 2023 01:30:06 -0700 (PDT) From: Xu Lu To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, tglx@linutronix.de, maz@kernel.org, anup@brainfault.org, atishp@atishpatra.org Cc: dengliang.1214@bytedance.com, liyu.yukiteru@bytedance.com, sunjiadong.lff@bytedance.com, xieyongji@bytedance.com, lihangjing@bytedance.com, chaiwen.cc@bytedance.com, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Xu Lu Subject: [RFC 08/12] riscv: Enable NMIs during irqs disabled context Date: Mon, 23 Oct 2023 16:29:07 +0800 Message-Id: <20231023082911.23242-9-luxu.kernel@bytedance.com> X-Mailer: git-send-email 2.39.3 (Apple Git-145) In-Reply-To: <20231023082911.23242-1-luxu.kernel@bytedance.com> References: <20231023082911.23242-1-luxu.kernel@bytedance.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Mon, 23 Oct 2023 01:31:07 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780534366866219898 X-GMAIL-MSGID: 1780534366866219898 This commit allows NMIs to happen even when irqs are disabled. When disabling irqs, we mask all normal irqs via clearing corresponding bits in CSR_IE while leaving NMI bits alone. Signed-off-by: Xu Lu --- arch/riscv/include/asm/irqflags.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/include/asm/irqflags.h b/arch/riscv/include/asm/irqflags.h index 9700a17a003a..42f7803582df 100644 --- a/arch/riscv/include/asm/irqflags.h +++ b/arch/riscv/include/asm/irqflags.h @@ -54,13 +54,13 @@ static inline void arch_local_irq_enable(void) /* unconditionally disable interrupts */ static inline void arch_local_irq_disable(void) { - csr_clear(CSR_IE, irqs_enabled_ie); + csr_clear(CSR_IE, ~ALLOWED_NMI_MASK); } /* get status and disable interrupts */ static inline unsigned long arch_local_irq_save(void) { - return csr_read_clear(CSR_IE, irqs_enabled_ie); + return csr_read_clear(CSR_IE, ~ALLOWED_NMI_MASK); } /* test flags */ From patchwork Mon Oct 23 08:29:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xu Lu X-Patchwork-Id: 156744 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:ce89:0:b0:403:3b70:6f57 with SMTP id p9csp1151323vqx; Mon, 23 Oct 2023 01:31:49 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHXtLtBCgkfg3enTpheL5oH8mbweQevDwedi1YECuUl6wAKBBe1U9XN/bWk3RBmmDM7wRkl X-Received: by 2002:a05:6a21:3391:b0:16b:e89b:fb18 with SMTP id yy17-20020a056a21339100b0016be89bfb18mr10438551pzb.26.1698049909029; Mon, 23 Oct 2023 01:31:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698049909; cv=none; d=google.com; s=arc-20160816; b=xiC/TQ32Tu3V6kwinl98FmL4dbTEZvCvbbuneRb/cpkQGcj9Vv5LsQe/2DDuD3mSLe TvtPAaXlScjoICpMJeDpk7M2b6lo8A/GWBDpmsCJRSSNbTcBlGvJ0F8YqNWQaCYUa0RI V2+hoeL+aMTIXCe9z7b7BeaivjA5TVGykf48CnzsPgdvd8nH0PsUX9GBGaBHulhg/1fO l1KHJmw3rCxW5qrSXRuHX+Fhcc1D46AW+Q4mVeVTVp57RUmCxhplEwzKyvzpCcWxD5xJ 5xaxLLftIfvjC5fg5wYhQdxTI0F/8NhuHO6z/ioEeLMPsENJZn1h1qjfm3wuLI6vc4WN Xe3A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=CJ95gw/OAzQTy7Pqa/IxTLGW5cdMj2QHsOf1G6j+k+o=; fh=O4eOVhHjKTyaSORSQqoF+Vv6GYDagG+8LotEUwhRqvg=; b=ygDvUQRW/edn5Tu/aKD+P6k//b3hpMqT3cW4gwPF7bUbhr2zfXh4ajTOwtjBLtyxmP uElquAzC/GwDCjTDh9FiYJ3CjNk1JcSOGV/Z+SSlTgE8N2Y9n4LqBznNW75tjeDWdY5s XH/82nBdg2NeHUcDB6ljhGvEJNqC8aLjQKvu2jHGGsa8y+KlyFcvYzrRPjc/Sa9k2Jrq MupehqN2q2EsvrjdA9JE8FQ4BnRHqoRp5VqgILoNt1vS0BSmtXnuid5MhhkuHWpuHaoL hvKInXENPbQ3k0omrvOmc0vA7G2SCYSMWZvAgQvl1eHkZwDwo9WpciTxWieFmYU/VjzY 6SSg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@bytedance.com header.s=google header.b=S30YYUPe; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=bytedance.com Received: from howler.vger.email (howler.vger.email. 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Mon, 23 Oct 2023 01:30:11 -0700 (PDT) From: Xu Lu To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, tglx@linutronix.de, maz@kernel.org, anup@brainfault.org, atishp@atishpatra.org Cc: dengliang.1214@bytedance.com, liyu.yukiteru@bytedance.com, sunjiadong.lff@bytedance.com, xieyongji@bytedance.com, lihangjing@bytedance.com, chaiwen.cc@bytedance.com, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Xu Lu Subject: [RFC 09/12] riscv: Enable NMIs during exceptions Date: Mon, 23 Oct 2023 16:29:08 +0800 Message-Id: <20231023082911.23242-10-luxu.kernel@bytedance.com> X-Mailer: git-send-email 2.39.3 (Apple Git-145) In-Reply-To: <20231023082911.23242-1-luxu.kernel@bytedance.com> References: <20231023082911.23242-1-luxu.kernel@bytedance.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on howler.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Mon, 23 Oct 2023 01:31:14 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780534381599763361 X-GMAIL-MSGID: 1780534381599763361 We have switched the way of disabling irqs to CSR_IE masking. But hardware still automatically clearing SIE field of CSR_STATUS whenever thread traps into kernel, which disabling all irqs including NMIs. This commit re-enables NMIs and normal irqs during exceptions by setting the SIE field in CSR_STATUS and restoring NMI and irq bits in CSR_IE. Signed-off-by: Xu Lu --- arch/riscv/include/asm/irqflags.h | 13 +++++++++++++ arch/riscv/include/asm/switch_to.h | 7 +++++++ arch/riscv/kernel/traps.c | 10 ++++++++++ 3 files changed, 30 insertions(+) diff --git a/arch/riscv/include/asm/irqflags.h b/arch/riscv/include/asm/irqflags.h index 42f7803582df..6a709e9c69ca 100644 --- a/arch/riscv/include/asm/irqflags.h +++ b/arch/riscv/include/asm/irqflags.h @@ -29,6 +29,16 @@ static inline void set_nmi(int irq) {} static inline void unset_nmi(int irq) {} +static inline void enable_nmis(void) +{ + csr_set(CSR_IE, ALLOWED_NMI_MASK); +} + +static inline void disable_nmis(void) +{ + csr_clear(CSR_IE, ALLOWED_NMI_MASK); +} + static inline void local_irq_switch_on(void) { csr_set(CSR_STATUS, SR_IE); @@ -128,6 +138,9 @@ static inline void arch_local_irq_restore(unsigned long flags) csr_set(CSR_STATUS, flags & SR_IE); } +static inline void enable_nmis(void) {} +static inline void disable_nmis(void) {} + #endif /* !CONFIG_RISCV_PSEUDO_NMI */ #endif /* _ASM_RISCV_IRQFLAGS_H */ diff --git a/arch/riscv/include/asm/switch_to.h b/arch/riscv/include/asm/switch_to.h index a727be723c56..116cffeaa6bf 100644 --- a/arch/riscv/include/asm/switch_to.h +++ b/arch/riscv/include/asm/switch_to.h @@ -84,4 +84,11 @@ do { \ ((last) = __switch_to(__prev, __next)); \ } while (0) +#ifdef CONFIG_RISCV_PSEUDO_NMI + +#define prepare_arch_switch(next) disable_nmis() +#define finish_arch_post_lock_switch() enable_nmis() + +#endif /* CONFIG_RISCV_PSEUDO_NMI */ + #endif /* _ASM_RISCV_SWITCH_TO_H */ diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index fae8f610d867..63d3c1417563 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -135,7 +135,9 @@ asmlinkage __visible __trap_section void name(struct pt_regs *regs) \ { \ if (user_mode(regs)) { \ irqentry_enter_from_user_mode(regs); \ + enable_nmis(); \ do_trap_error(regs, signo, code, regs->epc, "Oops - " str); \ + disable_nmis(); \ irqentry_exit_to_user_mode(regs); \ } else { \ irqentry_state_t state = irqentry_nmi_enter(regs); \ @@ -292,8 +294,12 @@ asmlinkage __visible __trap_section void do_trap_break(struct pt_regs *regs) if (user_mode(regs)) { irqentry_enter_from_user_mode(regs); + enable_nmis(); + handle_break(regs); + disable_nmis(); + irqentry_exit_to_user_mode(regs); } else { irqentry_state_t state = irqentry_nmi_enter(regs); @@ -338,10 +344,14 @@ asmlinkage __visible noinstr void do_page_fault(struct pt_regs *regs) { irqentry_state_t state = irqentry_enter(regs); + enable_nmis(); + handle_page_fault(regs); local_irq_disable(); + disable_nmis(); + irqentry_exit(regs, state); } #endif From patchwork Mon Oct 23 08:29:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xu Lu X-Patchwork-Id: 156741 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:ce89:0:b0:403:3b70:6f57 with SMTP id p9csp1151259vqx; Mon, 23 Oct 2023 01:31:36 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHtgXXdPT9uhZcfEd8XapJOpKeQfaI0MKzyE0esIJB31ayvJAH+g8ztCfAYsgCZba3MtlW5 X-Received: by 2002:a17:903:1210:b0:1c7:245a:7fea with SMTP id l16-20020a170903121000b001c7245a7feamr10724116plh.58.1698049895677; Mon, 23 Oct 2023 01:31:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698049895; cv=none; d=google.com; s=arc-20160816; b=d5BcYCfJDFXagYq5bAwMIlYbKkEwLIUn8V8hd4PosR0wEh/Yi8UjFM7QuqNyF2vqeX 7xiVjJtI5xNdkJdqZteE+S3kpxarffK1Z3ZReyoAGmiN8hHWVJ0Es5plPXCeUr+RLW0E 2tDuhzd5LH8rCSlRaoQDAmSf0QUbyvR2rwzqE+o1P9ic7I1aCEHC+xv//veKYw9++bIK MnopWWc879KglGPLh7pWgazNmP9/7efB4dsSqvmgkduXNXPr98Dny43KIjIST+6Cwx91 5YREnaHzBQ88TGa4YmNOiRoJYZ6s0NabVYSYyPdSw+9T6SDg+zTXgqFUzVcERh+Bo3wJ Gq9g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=+zaYgIQbfD9rezIYpqI9laPzzTdWx+ZAuyZYYGD6lvk=; fh=O4eOVhHjKTyaSORSQqoF+Vv6GYDagG+8LotEUwhRqvg=; b=Ht3YXwQllv6PQvhWOh8/8ai/o9T0hZE6oKuNGsHQRU82mAq/hy9MlsBgDbKljUSj/7 gLmQqv3qs8gKU0ViD9OtBuBLgCkgNY448oHab6KJFlo/xwuv7p4kCoddKfetOiUOzSPQ p2+2BsCDojI1i/F7JKuC1hOkT2LTN6r4xkuIhOieWEhkiKqET5m8srqSrQRrvh/QTa6c Q67G0Auoa3lnrLbgrAi8SdUjnwaJVL44jyluea7OdVTrZKKlbD0AddTSyP5lrAmJEZNc y+KWT13PQy+OqljiPfUWJdFtrmjHOugHc9V6sP/L1fMz01YC4g4kWLL8KYDepSvAq2TI govg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@bytedance.com header.s=google header.b=Kjd3jevJ; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=bytedance.com Received: from snail.vger.email (snail.vger.email. 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Mon, 23 Oct 2023 01:30:17 -0700 (PDT) From: Xu Lu To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, tglx@linutronix.de, maz@kernel.org, anup@brainfault.org, atishp@atishpatra.org Cc: dengliang.1214@bytedance.com, liyu.yukiteru@bytedance.com, sunjiadong.lff@bytedance.com, xieyongji@bytedance.com, lihangjing@bytedance.com, chaiwen.cc@bytedance.com, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Xu Lu Subject: [RFC 10/12] riscv: Enable NMIs during interrupt handling Date: Mon, 23 Oct 2023 16:29:09 +0800 Message-Id: <20231023082911.23242-11-luxu.kernel@bytedance.com> X-Mailer: git-send-email 2.39.3 (Apple Git-145) In-Reply-To: <20231023082911.23242-1-luxu.kernel@bytedance.com> References: <20231023082911.23242-1-luxu.kernel@bytedance.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Mon, 23 Oct 2023 01:31:21 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780534367508529758 X-GMAIL-MSGID: 1780534367508529758 Hardware automatically clearing SIE field of CSR_STATUS whenever thread traps into kernel by interrupt, disabling all irqs including NMIs during interrupt handling. This commit re-enable NMIs during interrupt handling by setting the SIE field in CSR_STATUS and restoring NMIs bits in CSR_IE. Normal interrupts are still disabled during interrupt handling and NMIs are also disabled during NMIs handling to avoid nesting. Signed-off-by: Xu Lu Signed-off-by: Hangjing Li Reviewed-by: Liang Deng Reviewed-by: Yu Li --- arch/riscv/kernel/traps.c | 44 +++++++++++++++++++++++--------- drivers/irqchip/irq-riscv-intc.c | 2 ++ 2 files changed, 34 insertions(+), 12 deletions(-) diff --git a/arch/riscv/kernel/traps.c b/arch/riscv/kernel/traps.c index 63d3c1417563..185743edfa09 100644 --- a/arch/riscv/kernel/traps.c +++ b/arch/riscv/kernel/traps.c @@ -356,20 +356,11 @@ asmlinkage __visible noinstr void do_page_fault(struct pt_regs *regs) } #endif -static void noinstr handle_riscv_irq(struct pt_regs *regs) +static void noinstr do_interrupt(struct pt_regs *regs) { struct pt_regs *old_regs; - irq_enter_rcu(); old_regs = set_irq_regs(regs); - handle_arch_irq(regs); - set_irq_regs(old_regs); - irq_exit_rcu(); -} - -asmlinkage void noinstr do_irq(struct pt_regs *regs) -{ - irqentry_state_t state = irqentry_enter(regs); #ifdef CONFIG_IRQ_STACKS if (on_thread_stack()) { ulong *sp = per_cpu(irq_stack_ptr, smp_processor_id()) @@ -382,7 +373,9 @@ asmlinkage void noinstr do_irq(struct pt_regs *regs) "addi s0, sp, 2*"RISCV_SZPTR "\n" "move sp, %[sp] \n" "move a0, %[regs] \n" - "call handle_riscv_irq \n" + "la t0, handle_arch_irq \n" + REG_L" t1, (t0) \n" + "jalr t1 \n" "addi sp, s0, -2*"RISCV_SZPTR"\n" REG_L" s0, (sp) \n" "addi sp, sp, "RISCV_SZPTR "\n" @@ -398,11 +391,38 @@ asmlinkage void noinstr do_irq(struct pt_regs *regs) "memory"); } else #endif - handle_riscv_irq(regs); + handle_arch_irq(regs); + set_irq_regs(old_regs); +} + +static __always_inline void __do_nmi(struct pt_regs *regs) +{ + irqentry_state_t state = irqentry_nmi_enter(regs); + + do_interrupt(regs); + + irqentry_nmi_exit(regs, state); +} + +static __always_inline void __do_irq(struct pt_regs *regs) +{ + irqentry_state_t state = irqentry_enter(regs); + + irq_enter_rcu(); + do_interrupt(regs); + irq_exit_rcu(); irqentry_exit(regs, state); } +asmlinkage void noinstr do_irq(struct pt_regs *regs) +{ + if (IS_ENABLED(CONFIG_RISCV_PSEUDO_NMI) && regs_irqs_disabled(regs)) + __do_nmi(regs); + else + __do_irq(regs); +} + #ifdef CONFIG_GENERIC_BUG int is_valid_bugaddr(unsigned long pc) { diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index c672c0c64d5d..80ed8606e04d 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -34,7 +34,9 @@ static asmlinkage void riscv_intc_irq(struct pt_regs *regs) generic_handle_domain_nmi(intc_domain, cause); nmi_exit(); } else { + enable_nmis(); generic_handle_domain_irq(intc_domain, cause); + disable_nmis(); } } From patchwork Mon Oct 23 08:29:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xu Lu X-Patchwork-Id: 156743 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:ce89:0:b0:403:3b70:6f57 with SMTP id p9csp1151263vqx; Mon, 23 Oct 2023 01:31:36 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHBHftxLGdZsV4r2owUNl1AC3O2Gp49jXNhSMCwUv946Aqm1x2DuEdZFd9lovZ3LcHlEivO X-Received: by 2002:a05:6a00:854:b0:68a:582b:6b62 with SMTP id q20-20020a056a00085400b0068a582b6b62mr10100927pfk.7.1698049896178; Mon, 23 Oct 2023 01:31:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698049896; cv=none; d=google.com; s=arc-20160816; b=bjuAAEUd7S0eeEmeVLGVmSIm+efYd+z+3xm+CV+onz/RZ/V0UfWR11vhRcHYgsN3+u Q3pkHUeaOEqGimuJvxqz9znRvfi8v41rw0bpz6MVGn6jqc6LWzan9tgfQbHKcN0XWYLN I1rPZBn4jNTE1sJeKxIJXZvUFVwC4NMT/GUEn/5UsD4A00QJKaHnlyRS2l2wvyFVqQhJ znjmcxPugum0glIrLI8hkZ26uslN9X8tNJkFQ+nmngA/vjI+CFMtKKghWVWBx2rOIPLl hkmBLo0wd4wQeTymwUrmFMKOm0F3SUCTaXwFh8xINg3OIXBvI2bJoRn0qbiq2q1Mx/Tk gyNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=0DBuRxeBwydw4BwBQS/PBMNuUJKwvOuK50YBTu/VQqs=; fh=O4eOVhHjKTyaSORSQqoF+Vv6GYDagG+8LotEUwhRqvg=; b=JJLdAm+2NuFjvYN4MFXE+dG2vaG7H14JF4dsHcUOxGB7K5K/v2F2J3YAZa2OHFQWEM 0BkZ5nZo3g2RlRGrFvsLHer0CtVbVGDOrDWzQfJwqjanH3oMUrwlP0v7qxUp/toLIRDO Y/6pf9k7zsaGHt9ymcg/nQh6AJQX/U+XK2Aq16lG09ZGkY6xPyLekrXh+7Wz4y7piiqg roYQ3OPibChS45KCLzTgTPzB55yFScJz0lMHebFRDLgqrixACUiYvVWG2DdDNsrMiVNs xTOF82fr+Q2jY8KqluWRZ4rg+M7Dup6/DvRrvekONUVuVy2dJL6x+Y0z7j8CkGO78xQ/ TIRw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@bytedance.com header.s=google header.b=KxlUY0bd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=bytedance.com Received: from snail.vger.email (snail.vger.email. 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Mon, 23 Oct 2023 01:30:23 -0700 (PDT) From: Xu Lu To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, tglx@linutronix.de, maz@kernel.org, anup@brainfault.org, atishp@atishpatra.org Cc: dengliang.1214@bytedance.com, liyu.yukiteru@bytedance.com, sunjiadong.lff@bytedance.com, xieyongji@bytedance.com, lihangjing@bytedance.com, chaiwen.cc@bytedance.com, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Xu Lu Subject: [RFC 11/12] riscv: Request pmu overflow interrupt as NMI Date: Mon, 23 Oct 2023 16:29:10 +0800 Message-Id: <20231023082911.23242-12-luxu.kernel@bytedance.com> X-Mailer: git-send-email 2.39.3 (Apple Git-145) In-Reply-To: <20231023082911.23242-1-luxu.kernel@bytedance.com> References: <20231023082911.23242-1-luxu.kernel@bytedance.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Mon, 23 Oct 2023 01:31:26 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780534367784151268 X-GMAIL-MSGID: 1780534367784151268 This commit registers pmu overflow interrupt as NMI to improve the accuracy of perf sampling. Signed-off-by: Xu Lu --- arch/riscv/include/asm/irqflags.h | 2 +- drivers/perf/riscv_pmu_sbi.c | 23 +++++++++++++++++++---- 2 files changed, 20 insertions(+), 5 deletions(-) diff --git a/arch/riscv/include/asm/irqflags.h b/arch/riscv/include/asm/irqflags.h index 6a709e9c69ca..be840e297559 100644 --- a/arch/riscv/include/asm/irqflags.h +++ b/arch/riscv/include/asm/irqflags.h @@ -12,7 +12,7 @@ #ifdef CONFIG_RISCV_PSEUDO_NMI -#define __ALLOWED_NMI_MASK 0 +#define __ALLOWED_NMI_MASK BIT(IRQ_PMU_OVF) #define ALLOWED_NMI_MASK (__ALLOWED_NMI_MASK & irqs_enabled_ie) static inline bool nmi_allowed(int irq) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index 995b501ec721..85abb7dd43b9 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -760,6 +760,7 @@ static irqreturn_t pmu_sbi_ovf_handler(int irq, void *dev) static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node) { + int ret = 0; struct riscv_pmu *pmu = hlist_entry_safe(node, struct riscv_pmu, node); struct cpu_hw_events *cpu_hw_evt = this_cpu_ptr(pmu->hw_events); @@ -778,20 +779,30 @@ static int pmu_sbi_starting_cpu(unsigned int cpu, struct hlist_node *node) if (riscv_pmu_use_irq) { cpu_hw_evt->irq = riscv_pmu_irq; csr_clear(CSR_IP, BIT(riscv_pmu_irq_num)); -#ifndef CONFIG_RISCV_PSEUDO_NMI +#ifdef CONFIG_RISCV_PSEUDO_NMI + ret = prepare_percpu_nmi(riscv_pmu_irq); + if (ret != 0) { + pr_err("Failed to prepare percpu nmi:%d\n", ret); + return ret; + } + enable_percpu_nmi(riscv_pmu_irq, IRQ_TYPE_NONE); +#else csr_set(CSR_IE, BIT(riscv_pmu_irq_num)); -#endif enable_percpu_irq(riscv_pmu_irq, IRQ_TYPE_NONE); +#endif } - return 0; + return ret; } static int pmu_sbi_dying_cpu(unsigned int cpu, struct hlist_node *node) { if (riscv_pmu_use_irq) { +#ifdef CONFIG_RISCV_PSEUDO_NMI + disable_percpu_nmi(riscv_pmu_irq); + teardown_percpu_nmi(riscv_pmu_irq); +#else disable_percpu_irq(riscv_pmu_irq); -#ifndef CONFIG_RISCV_PSEUDO_NMI csr_clear(CSR_IE, BIT(riscv_pmu_irq_num)); #endif } @@ -835,7 +846,11 @@ static int pmu_sbi_setup_irqs(struct riscv_pmu *pmu, struct platform_device *pde return -ENODEV; } +#ifdef CONFIG_RISCV_PSEUDO_NMI + ret = request_percpu_nmi(riscv_pmu_irq, pmu_sbi_ovf_handler, "riscv-pmu", hw_events); +#else ret = request_percpu_irq(riscv_pmu_irq, pmu_sbi_ovf_handler, "riscv-pmu", hw_events); +#endif if (ret) { pr_err("registering percpu irq failed [%d]\n", ret); return ret; From patchwork Mon Oct 23 08:29:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xu Lu X-Patchwork-Id: 156739 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a59:ce89:0:b0:403:3b70:6f57 with SMTP id p9csp1151250vqx; Mon, 23 Oct 2023 01:31:34 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFKIEVKoRMzWr3Q8SzRYbRlwQSolIQOe5KDe3HuegCtzf6kP6/ANL420UHHnqEHfIP3DbKy X-Received: by 2002:a17:902:7c95:b0:1c3:3c91:61cc with SMTP id y21-20020a1709027c9500b001c33c9161ccmr5645737pll.13.1698049894622; Mon, 23 Oct 2023 01:31:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1698049894; cv=none; d=google.com; s=arc-20160816; b=RS/4ksIBzeU4/P5sHaIan7luJCIanGmj0YVx2qt3Z6d/uWQmypboBu/xQaRu5FWxW0 12r5Ie2YM/iiS56ncqw7clak290Dk4Og+UuIg9IbX1NfoeorEwP3Ppxsf7Ao63CnFChn mo/zK8qWNvbkzWvu6gp/rTZB9iHXawwvWfC618GysVKi+tKHnggol7e/Zj3s54Ut/R9e y828DFZ4ft93eU0obf78SIA16eKyUAqtUHBQsBaTZD6JxnSVD/+gHp8SsKIjUSMzRq4G XvoObFadFasHyD32ZvVJW+kmORctGUF7+NJs3uln8YK+YcQvRu3izDMRFySz4TSqUGD5 ZBug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=qwqRYcNnh3bL2bnUHbsBXwm7mmQqzZo0pVLQzAgbeF0=; fh=O4eOVhHjKTyaSORSQqoF+Vv6GYDagG+8LotEUwhRqvg=; b=DPX13H+N2ysmcTMvMPuxuV8xkAbuVPM7BEx+vYL2Jd/xKTshtjroyTDPuwQEa7nhak 9GnfD/osxNhZ8vETkHYMolssAc+qKGui+9uioyENPOVFZBRkuKf+5al38YsvD0RSZtLS QL+oOHgw4D1KqbJsXeQWnE8NasLaEqZnlhE3NOFg6HAX1cIS4jdx65VT/M/iMDTZrzzA NaHPNGB2bpziQX916Dewom5n38fxZihOhcmLE2LukkiB2LeMVeZAtJlikm8dgB8eUiTP 0xkJyut5HaqY+87faVQHqb2A1ziuaKrX0aCpY8brnVa2HPSQKe1VH/gDCO1MDU2YBUVo wq6Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@bytedance.com header.s=google header.b=ZIJ3GaaK; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=bytedance.com Received: from groat.vger.email (groat.vger.email. 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Mon, 23 Oct 2023 01:30:28 -0700 (PDT) From: Xu Lu To: paul.walmsley@sifive.com, palmer@dabbelt.com, aou@eecs.berkeley.edu, tglx@linutronix.de, maz@kernel.org, anup@brainfault.org, atishp@atishpatra.org Cc: dengliang.1214@bytedance.com, liyu.yukiteru@bytedance.com, sunjiadong.lff@bytedance.com, xieyongji@bytedance.com, lihangjing@bytedance.com, chaiwen.cc@bytedance.com, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Xu Lu Subject: [RFC 12/12] riscv: Enable CONFIG_RISCV_PSEUDO_NMI in default Date: Mon, 23 Oct 2023 16:29:11 +0800 Message-Id: <20231023082911.23242-13-luxu.kernel@bytedance.com> X-Mailer: git-send-email 2.39.3 (Apple Git-145) In-Reply-To: <20231023082911.23242-1-luxu.kernel@bytedance.com> References: <20231023082911.23242-1-luxu.kernel@bytedance.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Mon, 23 Oct 2023 01:31:32 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780534366362345067 X-GMAIL-MSGID: 1780534366362345067 This commit enables CONFIG_RISCV_PSEUDO_NMI in default. Now pseudo NMI feature is defaultly enabled on RISC-V. Signed-off-by: Xu Lu --- arch/riscv/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 487e4293f31e..ecccdc91563f 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -672,7 +672,7 @@ config RISCV_BOOT_SPINWAIT config RISCV_PSEUDO_NMI bool "Support for NMI-like interrupts" depends on !RISCV_M_MODE - default n + default y help Adds support for mimicking Non-Maskable Interrupts through the use of CSR_IE register.