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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id u16-20020a0ced30000000b0065b1365cf66si4845883qvq.383.2023.10.22.19.18.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Oct 2023 19:18:39 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=lzBsd0Cz; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 1374E3858C39 for ; Mon, 23 Oct 2023 02:18:39 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.65]) by sourceware.org (Postfix) with ESMTPS id 571243858D39 for ; Mon, 23 Oct 2023 02:18:14 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 571243858D39 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 571243858D39 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=134.134.136.65 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698027496; cv=none; b=OS/3a4MmQSMXBFr+gaMwzvJccsuH2YeiU5/ltMZBJf91zr04sfRh0kWlV6Qk4/wZuhJrD+DosNiv8zKuisTPwOCnLEY3sn77jKjMscXS0REzs8CsIAGI6KNVOSx7ucm1S/+64iqh2rYEl7E7NgJlhzFOdyxHL1W6DtjB81gytss= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1698027496; c=relaxed/simple; bh=9wHyq2USjNtWt6uqNxjP2M2vjEU5cDbD8/TPkq48bSk=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=f/5X1s7WZdaahAhwN3Q8uUxC4qcCLpg44aU8VIJynsqx3ku/+ZdWPBBkEUVUe7sMXGd7im9SP9Xn2HAH8Ul7Ni8j6yHZxMdt7P/H8iJdRGEM4KTj9a75eeaSVOQmtwA2Hcg/awEj1Ew+a8bpbWv2OaIg8e6D8iF3SpMRvcJil9I= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1698027494; x=1729563494; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=9wHyq2USjNtWt6uqNxjP2M2vjEU5cDbD8/TPkq48bSk=; b=lzBsd0Czyeyj+lxEl2DUBOYm6KH3qjsHxMB1sAb3L5HKmjrgATS0h3Bl OEybbV/kHy3uxuSpzomwJVzVVdjfokxThm62TJcZ6K6J0RNfzW8sxgZrr XaoCl/IY+wXhRytqqc9j9OTafbmzUWhoKzT6g98z2+wnnnwG9OwcY9jtu dcdG4LyHHiQ72de4/88aoE6Pj3PCDZdhdE1+fBPtsHCi26g1TOMyHyaGX v6KB9eO2eM8oXEVlleXBFl+2aUVyUtNgTUp4SU5ITA0yKcy1z8FN1oUUQ OmQ/tPslvBK1iCFE4Z+KFu+uMf0QY13gMHqOd2Ofa+MyTSf9RFBTzggl+ A==; X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="390638163" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="390638163" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2023 19:18:13 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10871"; a="874532727" X-IronPort-AV: E=Sophos;i="6.03,244,1694761200"; d="scan'208";a="874532727" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga002.fm.intel.com with ESMTP; 22 Oct 2023 19:18:11 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id 7D841100571C; Mon, 23 Oct 2023 10:18:10 +0800 (CST) From: Haochen Jiang To: gcc-patches@gcc.gnu.org Cc: gerald@pfeifer.com, ubizjak@gmail.com, hongtao.liu@intel.com Subject: [gccwwwdocs PATCH] gcc-13/14: Mention Intel new ISA and march support Date: Mon, 23 Oct 2023 10:18:10 +0800 Message-Id: <20231023021810.2134824-1-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780510904029257791 X-GMAIL-MSGID: 1780510904029257791 Hi all, This patch mentions recent update for x86-64 backend, including ISAs enabled update on previous introduced CPU and newly introduced options/ISAs/CPUs. Ok for wwwdocs? Thx, Haochen --- htdocs/gcc-13/changes.html | 8 ++++---- htdocs/gcc-14/changes.html | 19 +++++++++++++++++++ 2 files changed, 23 insertions(+), 4 deletions(-) diff --git a/htdocs/gcc-13/changes.html b/htdocs/gcc-13/changes.html index 10c54689..8ef3d639 100644 --- a/htdocs/gcc-13/changes.html +++ b/htdocs/gcc-13/changes.html @@ -579,13 +579,13 @@ You may also want to check out our
  • GCC now supports the Intel CPU named Sierra Forest through -march=sierraforest. - The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT and - CMPccXADD ISA extensions. + The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, CMPccXADD, + ENQCMD and UINTR ISA extensions.
  • GCC now supports the Intel CPU named Grand Ridge through -march=grandridge. - The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, CMPccXADD - and RAO-INT ISA extensions. + The switch enables the AVX-IFMA, AVX-VNNI-INT8, AVX-NE-CONVERT, CMPccXADD, + ENQCMD, UINTR and RAO-INT ISA extensions.
  • GCC now supports the Intel CPU named Emerald Rapids through -march=emeraldrapids. diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html index c817dde4..4f71061f 100644 --- a/htdocs/gcc-14/changes.html +++ b/htdocs/gcc-14/changes.html @@ -186,6 +186,10 @@ a work-in-progress.

    IA-32/x86-64

      +
    • New compiler option -m[no-]evex512 was added. + The compiler switch enables/disables 512 bit vector and 64 bit mask + register. It will be default on if AVX512F is enabled. +
    • New ISA extension support for Intel AVX-VNNI-INT16 was added. AVX-VNNI-INT16 intrinsics are available via the -mavxvnniint16 compiler switch. @@ -202,6 +206,16 @@ a work-in-progress.

      SM4 intrinsics are available via the -msm4 compiler switch.
      • +
    • New ISA extension support for Intel USER_MSR was added. + USER_MSR intrinsics are available via the -muser_msr + compiler switch. +
      • +
    • GCC now supports the Intel CPU named Clearwater Forest through + -march=clearwaterforest. + Based on Sierra Forest, the switch further enables the AVX-VNNI-INT16, + SHA512, SM3, SM4, USER_MSR and PREFETCHI ISA extensions. + extensions. +
    • GCC now supports the Intel CPU named Arrow Lake through -march=arrowlake. Based on Alder Lake, the switch further enables the AVX-IFMA, @@ -216,6 +230,11 @@ a work-in-progress.

      -march=lunarlake. Lunar Lake is based on Arrow Lake S.
      • +
    • GCC now supports the Intel CPU named Panther Lake through + -march=pantherlake. + Based on Arrow Lake S, the switch further enables the PREFETCHI ISA + extensions. +