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Mon, 7 Nov 2022 11:57:55 -0600 From: Perry Yuan To: , , CC: , , , , , , , , , Perry Yuan Subject: [PATCH v3 1/8] ACPI: CPPC: Add AMD pstate energy performance preference cppc control Date: Tue, 8 Nov 2022 01:56:58 +0800 Message-ID: <20221107175705.2207842-2-Perry.Yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221107175705.2207842-1-Perry.Yuan@amd.com> References: <20221107175705.2207842-1-Perry.Yuan@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT033:EE_|BL3PR12MB6379:EE_ X-MS-Office365-Filtering-Correlation-Id: 20428671-2beb-43cf-3d16-08dac0e99b5c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: AdYbMo3fy7wOwB8g3Aoc1rd95bqLKVJxUMCmcHgQ1KZ59aFd39CVdYbQU1g6tqHGOaldXqa9j+Rk53C7WEy3kpci3wZ0MBIjzNA77ZMT4Kca9LEVBPwRcrEbgVbmrkE+hWQ/yDifkOipmUzl/64HuXjt1Nhqi2p83+nIObNDo0QbGujBQrFQZkdbyzE+Qs2fgMYTFYspOjarLoekaOKOl4xVrS8IJr1WQX/GfU8bWwdFArJKraAoe4ycD3f6Yx2eRE8ZIebH88XZa3EiEGAqKiNeYLJKbqHwttZXpbC8KSoGlaYTV8c0ZWJ1YJjZigpgOlQGKJ3lycvPwdVc2qK0K+5tpPH7lTRTzwwnLUsLvWN6Pcl/txnMX5u8zfPJcEEKia7xB1IAox3uT9T6xfQtL9JIxT7pRl0uKowDDLnxgfTa0+AQfqxjxyULIFBeYGLJj6cDBKk4E/GomnbFrMMRXtYfLPFM6F9R52FGSncliv7LdsiRoM4aMpPgHbH87cCLS0jggnOv/o+k+4C0CfhgymXaD7qKAfbMV0vuA7P1bJbpXxkIxMiRZdsN8+o7sKufAgQPG2bK0SKbswaE/V7zZqSLC54ml1z8YUIp95WgfqORbzUE0fGQf/g6VPhh+waXih7JLHF14d/yF9LZRFhv/gc+6K3u7bt5tzfQyuAjW6ZeL+/du/MSUJ1WEbXB4UpAtALtCA9CU7QDjV+Cx8pl0BFZr6iRk8cVbnN0vBpYYP18qvS5T5OAExffCzI0eJDM2LpCFDn/YDGipb+1VTr112xlenmt8IRQAZCx/dFMsmAatKWdKiLw0MkcZSFEV9nyY1kSwzW4g5zGo99pWOJMiQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(346002)(396003)(376002)(136003)(39860400002)(451199015)(36840700001)(40470700004)(46966006)(36756003)(40480700001)(86362001)(16526019)(81166007)(41300700001)(356005)(110136005)(316002)(8676002)(8936002)(4326008)(70586007)(54906003)(70206006)(36860700001)(5660300002)(40460700003)(82740400003)(478600001)(186003)(336012)(1076003)(83380400001)(7696005)(26005)(82310400005)(2616005)(426003)(47076005)(2906002)(36900700001)(2101003);DIR:OUT;SFP:1101; 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In order to get EPP worked, cppc_get_epp_caps() will query EPP preference value and cppc_set_epp_perf() will set EPP new value. Before the EPP works, pstate driver will use cppc_set_auto_epp() to enable EPP function from firmware firstly. Signed-off-by: Perry Yuan --- drivers/acpi/cppc_acpi.c | 126 +++++++++++++++++++++++++++++++++++++++ include/acpi/cppc_acpi.h | 17 ++++++ 2 files changed, 143 insertions(+) diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c index 093675b1a1ff..d9c38dee1f48 100644 --- a/drivers/acpi/cppc_acpi.c +++ b/drivers/acpi/cppc_acpi.c @@ -1365,6 +1365,132 @@ int cppc_get_perf_ctrs(int cpunum, struct cppc_perf_fb_ctrs *perf_fb_ctrs) } EXPORT_SYMBOL_GPL(cppc_get_perf_ctrs); +/** + * cppc_get_epp_caps - Get the energy preference register value. + * @cpunum: CPU from which to get epp preference level. + * @perf_caps: Return address. + * + * Return: 0 for success, -EIO otherwise. + */ +int cppc_get_epp_caps(int cpunum, struct cppc_perf_caps *perf_caps) +{ + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpunum); + struct cpc_register_resource *energy_perf_reg; + u64 energy_perf; + + if (!cpc_desc) { + pr_warn("No CPC descriptor for CPU:%d\n", cpunum); + return -ENODEV; + } + + energy_perf_reg = &cpc_desc->cpc_regs[ENERGY_PERF]; + + if (!CPC_SUPPORTED(energy_perf_reg)) + pr_warn("energy perf reg update is unsupported!\n"); + + if (CPC_IN_PCC(energy_perf_reg)) { + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpunum); + struct cppc_pcc_data *pcc_ss_data = NULL; + int ret = 0; + + if (pcc_ss_id < 0) + return -ENODEV; + + pcc_ss_data = pcc_data[pcc_ss_id]; + + down_write(&pcc_ss_data->pcc_lock); + + if (send_pcc_cmd(pcc_ss_id, CMD_READ) >= 0) { + cpc_read(cpunum, energy_perf_reg, &energy_perf); + perf_caps->energy_perf = energy_perf; + } else { + ret = -EIO; + } + + up_write(&pcc_ss_data->pcc_lock); + + return ret; + } + + return 0; +} +EXPORT_SYMBOL_GPL(cppc_get_epp_caps); + +int cppc_set_auto_epp(int cpu, bool enable) +{ + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); + struct cpc_register_resource *auto_sel_reg; + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); + struct cppc_pcc_data *pcc_ss_data = NULL; + int ret = -EINVAL; + + if (!cpc_desc) { + pr_warn("No CPC descriptor for CPU:%d\n", cpu); + return -EINVAL; + } + + auto_sel_reg = &cpc_desc->cpc_regs[AUTO_SEL_ENABLE]; + + if (CPC_IN_PCC(auto_sel_reg)) { + if (pcc_ss_id < 0) + return -ENODEV; + + ret = cpc_write(cpu, auto_sel_reg, enable); + if (ret) + return ret; + + pcc_ss_data = pcc_data[pcc_ss_id]; + + down_write(&pcc_ss_data->pcc_lock); + /* after writing CPC, transfer the ownership of PCC to platform */ + ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE); + up_write(&pcc_ss_data->pcc_lock); + return ret; + } + + return cpc_write(cpu, auto_sel_reg, enable); +} +EXPORT_SYMBOL_GPL(cppc_set_auto_epp); + +/* + * Set Energy Performance Preference Register value through + * Performance Controls Interface + */ +int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) +{ + int pcc_ss_id = per_cpu(cpu_pcc_subspace_idx, cpu); + struct cpc_register_resource *epp_set_reg; + struct cpc_desc *cpc_desc = per_cpu(cpc_desc_ptr, cpu); + struct cppc_pcc_data *pcc_ss_data = NULL; + int ret = -EINVAL; + + if (!cpc_desc) { + pr_warn("No CPC descriptor for CPU:%d\n", cpu); + return -EINVAL; + } + + epp_set_reg = &cpc_desc->cpc_regs[ENERGY_PERF]; + + if (CPC_IN_PCC(epp_set_reg)) { + if (pcc_ss_id < 0) + return -ENODEV; + + ret = cpc_write(cpu, epp_set_reg, perf_ctrls->energy_perf); + if (ret) + return ret; + + pcc_ss_data = pcc_data[pcc_ss_id]; + + down_write(&pcc_ss_data->pcc_lock); + /* after writing CPC, transfer the ownership of PCC to platform */ + ret = send_pcc_cmd(pcc_ss_id, CMD_WRITE); + up_write(&pcc_ss_data->pcc_lock); + } + + return ret; +} +EXPORT_SYMBOL_GPL(cppc_set_epp_perf); + /** * cppc_set_enable - Set to enable CPPC on the processor by writing the * Continuous Performance Control package EnableRegister field. diff --git a/include/acpi/cppc_acpi.h b/include/acpi/cppc_acpi.h index c5614444031f..10d91aeedaca 100644 --- a/include/acpi/cppc_acpi.h +++ b/include/acpi/cppc_acpi.h @@ -108,12 +108,14 @@ struct cppc_perf_caps { u32 lowest_nonlinear_perf; u32 lowest_freq; u32 nominal_freq; + u32 energy_perf; }; struct cppc_perf_ctrls { u32 max_perf; u32 min_perf; u32 desired_perf; + u32 energy_perf; }; struct cppc_perf_fb_ctrs { @@ -149,6 +151,9 @@ extern bool cpc_ffh_supported(void); extern bool cpc_supported_by_cpu(void); extern int cpc_read_ffh(int cpunum, struct cpc_reg *reg, u64 *val); extern int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val); +extern int cppc_set_auto_epp(int cpu, bool enable); +extern int cppc_get_epp_caps(int cpunum, struct cppc_perf_caps *perf_caps); +extern int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls); #else /* !CONFIG_ACPI_CPPC_LIB */ static inline int cppc_get_desired_perf(int cpunum, u64 *desired_perf) { @@ -202,6 +207,18 @@ static inline int cpc_write_ffh(int cpunum, struct cpc_reg *reg, u64 val) { return -ENOTSUPP; } +static inline int cppc_set_auto_epp(int cpu, bool enable) +{ + return -ENOTSUPP; +} +static inline int cppc_set_epp_perf(int cpu, struct cppc_perf_ctrls *perf_ctrls) +{ + return -ENOTSUPP; +} +static inline int cppc_get_epp_caps(int cpunum, struct cppc_perf_caps *perf_caps) +{ + return -ENOTSUPP; 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Mon, 7 Nov 2022 11:57:58 -0600 From: Perry Yuan To: , , CC: , , , , , , , , , Perry Yuan Subject: [PATCH v3 2/8] Documentation: amd-pstate: add EPP profiles introduction Date: Tue, 8 Nov 2022 01:56:59 +0800 Message-ID: <20221107175705.2207842-3-Perry.Yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221107175705.2207842-1-Perry.Yuan@amd.com> References: <20221107175705.2207842-1-Perry.Yuan@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT110:EE_|PH0PR12MB5481:EE_ X-MS-Office365-Filtering-Correlation-Id: cc1dbd9e-c792-4ed5-27e4-08dac0e9ae92 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: esiR2yrZcGtTbkX7SARkzP41gWAFjvlMq8ebZDTDYgrQmBhNgoyJwB6Vzt4wQFzICZOPjdWW7XN6Qsx2SOqTeXcEh0m7GJDkEqu2YXWBGEsGuHxLdnXN7Y05gMydpqt3padgxwZgucVqEbZaFm4628ajDAfd16oXOcjIjE5F3wqoWzUFxkPAY5H5bPLBWqyu/2zjL8joDpJzTHVc6Wi6OGtxB1pMsoZffLjrnSMGXhLSzVHexKmd2MpxkUOHiRcIGqNATT3WPPjeg+ov9KVnFVz6ZSuVvnHOpkQjxz82k+XAhVNSL/gRoycAifkfCrRZwGLwcyAH7c8ciJhrGusdOL+NmKNtF036VYNpgJuTX75yKVhDCknQljjqKhc1/r5Kl1wD48aV57pmiwzlf52byUk4iwGvaw8wwXn51zVVwy/OU4l8y4Y2/2cK5I1znVP/EW6nI2nWqVxAo5ZCkUQKsfUZylQP6tJMp0K5JNmfo6i11CcpqaEvGa8xHR4PUYh2eOpNw0Nv9FcoJckH6o+ZdtluRb+v1Wpd5oSP2LmusZbOWLoIN1sUkmcir6Lw03QNR1qvYDg72sDJY/QBuUKLc9FPieDHfvMjSLzYpS6N5ekir7PkFHLHYEow2MEot4jMiU5mc2dj3s7P4DTrOfOEhEHeqKILFvn6UTdDQOKw7lZ3fWKy/hz/gToH0erVzMAkmgeNE+7Knj55YtUV0TbUEvgoK5U/KSFX67CR9sXfrWkrFYtteGfzd/AXwjqy7JpOtxc8yGefec1ey97dqbFSc+0DcLpy/S2xbNMj3Zqp2xMWNH37jNs0xy5hdT96iUdW896MFcIs30v348/zQe5f4w== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(39860400002)(136003)(376002)(346002)(396003)(451199015)(40470700004)(36840700001)(46966006)(36860700001)(7696005)(54906003)(110136005)(316002)(40480700001)(5660300002)(47076005)(2616005)(2906002)(426003)(40460700003)(8936002)(336012)(16526019)(186003)(1076003)(26005)(86362001)(70586007)(36756003)(70206006)(8676002)(4326008)(41300700001)(83380400001)(356005)(81166007)(82740400003)(82310400005)(478600001)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Nov 2022 17:58:31.4447 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cc1dbd9e-c792-4ed5-27e4-08dac0e9ae92 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT110.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB5481 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748861689433383325?= X-GMAIL-MSGID: =?utf-8?q?1748861689433383325?= The patch add AMD pstate EPP feature introduction and what EPP preference supported for AMD processors. User can get supported list from energy_performance_available_preferences attribute file, or update current profile to energy_performance_preference file 1) See all EPP profiles $ sudo cat /sys/devices/system/cpu/cpu0/cpufreq/energy_performance_available_preferences default performance balance_performance balance_power power 2) Check current EPP profile $ sudo cat /sys/devices/system/cpu/cpu0/cpufreq/energy_performance_preference performance 3) Set new EPP profile $ sudo bash -c "echo power > /sys/devices/system/cpu/cpu0/cpufreq/energy_performance_preference" Signed-off-by: Perry Yuan --- Documentation/admin-guide/pm/amd-pstate.rst | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst index 8f3d30c5a0d8..78c6525d5a49 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -262,6 +262,25 @@ lowest non-linear performance in `AMD CPPC Performance Capability `_.) This attribute is read-only. +``energy_performance_available_preferences`` + +All the supported EPP preference could be selected, List of the strings that +can be set to the ``energy_performance_preference`` attribute +those different profiles represent different energy vs efficiency hints provided +to low-level firmware +however, the ``default`` represents the epp value is set by platform firmware +This attribute is read-only. + +``energy_performance_preference`` + +The current energy performance preference can be read from this attribute. +and user can change current preference according to energy or performance needs +Please get all support profiles list from +``energy_performance_available_preferences`` attribute, all the profiles are +integer values defined between 0 to 255 when EPP feature is enabled by platform +firmware, if EPP feature is disabled, driver will ignore the written value +This attribute is read-write. + Other performance and frequency values can be read back from ``/sys/devices/system/cpu/cpuX/acpi_cppc/``, see :ref:`cppc_sysfs`. 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Mon, 7 Nov 2022 11:58:02 -0600 From: Perry Yuan To: , , CC: , , , , , , , , , Perry Yuan Subject: [PATCH v3 3/8] cpufreq: amd-pstate: change driver to be built-in type Date: Tue, 8 Nov 2022 01:57:00 +0800 Message-ID: <20221107175705.2207842-4-Perry.Yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221107175705.2207842-1-Perry.Yuan@amd.com> References: <20221107175705.2207842-1-Perry.Yuan@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT110:EE_|LV2PR12MB5750:EE_ X-MS-Office365-Filtering-Correlation-Id: bf36bd7a-e805-465a-71a3-08dac0e9b027 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: fQGZVuG3DJ3i+uj7XNqGd0MV4bz61tK9+Y8U1rNslxRJVX+A9JMIOPm73F5GjIYixz0WaC1Da+1NspZAafm4XLa3X/pRoC7RGpT2Rusxrmlp6XjcYkhQa6ueAkzGgynYVuduXicAbiy0TbSIH275cFspB6afEaQeStxzNu49Mw3bte+eLMPAPh3bhhJ9HN1YrsGa77AfDV/YU+iXYF5MwppYK7BdCHQ5uHGgNCzgpVuXpUvzMr0P5Y8AdRAw9HPQswxW+Ce76k4ENai5M+hntD7eEHDl7qF9DgwySH+cAiBrFWp8Wau6N3Uvzb3Fz+eH2NqacuJp/4swlg3huuSdgngPD5dfshbWyQyM1///PFO68xOvFQpjvJ1p5k+CKFF9fhDbQyDLzt7P5yezx3JaISJpYswipJGyr2eNzauYuhrkpxfmSFZ/xI+MgOrLoZ90aavwZM13QjyxW3rJAPlWoI/+mAiHToagOEcM5sidx7n6dg/3NtD2WjkPc51V0f2LrvlJWRcy5sM0ONV32cKa1MYVb27QiJ9F0eJU28QupsCJX6fwQ+f7tQ+2q5aZmmYtTXRdxAVbX7zXEfE5mbmzQM++/YdOn0+sBtY3aE752iaejnKT5oLEfF99MkDAFW9ZLSnEj5bmCfST8phkCYmR6IUYmdgIQNyFiJKtetrIolTE3u//ZlbEZBC4rJQY7HrYMIrMUhEv/FX7NGHaHt7ybxpswKq/3/s7ICTG+Zl8tKoPVSLncLB9/SctgvT+k2yOZqS4CEr+GLQPgRDl1IgiyUUMjM4MjlkauqTZVkLx5B25qUs3r/3Nfv9ueQoJsqvl1WWlmQDnLpbU2M70DNaabA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(346002)(136003)(39860400002)(396003)(451199015)(46966006)(36840700001)(40470700004)(478600001)(86362001)(81166007)(40480700001)(82310400005)(7696005)(110136005)(316002)(356005)(54906003)(4326008)(47076005)(40460700003)(8676002)(2906002)(83380400001)(336012)(26005)(82740400003)(36756003)(70586007)(70206006)(5660300002)(426003)(41300700001)(36860700001)(2616005)(186003)(8936002)(1076003)(16526019)(36900700001)(2101003);DIR:OUT;SFP:1101; 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Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index ace7d50cf2ac..14906431dc15 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -59,10 +59,7 @@ * we disable it by default to go acpi-cpufreq on these processors and add a * module parameter to be able to enable it manually for debugging. */ -static bool shared_mem = false; -module_param(shared_mem, bool, 0444); -MODULE_PARM_DESC(shared_mem, - "enable amd-pstate on processors with shared memory solution (false = disabled (default), true = enabled)"); +static bool shared_mem __read_mostly; static struct cpufreq_driver amd_pstate_driver; @@ -653,16 +650,22 @@ static int __init amd_pstate_init(void) return ret; } +device_initcall(amd_pstate_init); -static void __exit amd_pstate_exit(void) +static int __init amd_pstate_param(char *str) { - cpufreq_unregister_driver(&amd_pstate_driver); + if (!str) + return -EINVAL; - amd_pstate_enable(false); -} + /* enable shared memory type CPPC ,if you processor has no MSR, you have to add this + * to your grub to make cppc driver loaded successfully. + */ + if (!strcmp(str, "legacy_cppc")) + shared_mem = true; -module_init(amd_pstate_init); -module_exit(amd_pstate_exit); + return 0; +} +early_param("amd-pstate", amd_pstate_param); MODULE_AUTHOR("Huang Rui "); MODULE_DESCRIPTION("AMD Processor P-state Frequency Driver"); From patchwork Mon Nov 7 17:57:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 16628 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2207615wru; Mon, 7 Nov 2022 10:07:20 -0800 (PST) X-Google-Smtp-Source: AMsMyM5qSSscsgC9SEUdLtkY6Y6AepV346t+deqj7cvH9iyUrcBYDwafgG4WEPWcjEDm4Lnuuxa/ X-Received: by 2002:a63:d60e:0:b0:46f:8979:30ba with SMTP id q14-20020a63d60e000000b0046f897930bamr41566230pgg.332.1667844440491; Mon, 07 Nov 2022 10:07:20 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1667844440; cv=pass; d=google.com; s=arc-20160816; b=qsg+sheujjvhdG1Yq9iAFqd9LXhee0grCm5nsGGiH9m9E+NMeHHlxb/X8hy1L9hQpX lieMjIKRjK632u6ApCgksxgp//liKYTsiZkkHQ9Ea8kqMTvzBeQqmcCQVhK0wVem5C5p CWC7/NkUM8WJ199jFLVfzVu5lFfbCILFi6DwdHLtNA0qbygLGe9XTmVRQIGRg2Cyemy/ OdNlNOJJV/aZtDdYwVnVsWAjbPVhaZEemG8f5jCZUThWFOb/JMHQLPBVmjt6EIVN0qeP xJ3EjlLgtPHlkw+a66PgGZ3s7ccCneHhfbyPp8ojXQ8m7XaB+HChrXA5T1kwvlFEDXll fDMQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=yK8s7ZyFKh+SLhXdMscu+nsk5PvfTFEIpUrnSP6zuI0=; b=IfHtfGQZxP+ucBwPfv9HsCW9Psv+G/mp67vaj7Ei/RNfALPW3AEjrJHlyGNL0N/Jc+ oe3VGN96QGqeGZW8RrLfrDZQW8czPbgLEgIy42ALOcSdO8ymyI0h/peI0JhXMLDurpRz UrMXF76o9spV/elWc9p0nvRsusDdzelXjNzTxC6BZVk6OEhnZO4/hErbdGYrcLw8jtaQ ijeGmTU03eHrGDh4CKZ6OLqbQG1Xuy5AOe2touH1J7r3Fna+cJPM5eHtdstmgstzcaAC L6/22jRr2P76JV5dRr5XL5ckKAA14wl9MDLZ4Ygn6DdyGZ5aqgFiRg8bNuO2hs4/GR0e 08ng== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=gd1HkR3a; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Mon, 7 Nov 2022 11:58:31 -0600 From: Perry Yuan To: , , CC: , , , , , , , , , Perry Yuan Subject: [PATCH v3 4/8] cpufreq: amd_pstate: add AMD Pstate EPP support for the MSR based processors Date: Tue, 8 Nov 2022 01:57:01 +0800 Message-ID: <20221107175705.2207842-5-Perry.Yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221107175705.2207842-1-Perry.Yuan@amd.com> References: <20221107175705.2207842-1-Perry.Yuan@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT110:EE_|PH0PR12MB8125:EE_ X-MS-Office365-Filtering-Correlation-Id: 25c8877c-a6c0-47e8-399b-08dac0e9b137 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 2nRJVzrRGLlw8IIHI952Zl4Ixko7TvD8biBng3ocysAnPaOy0I8VNaNvyp5slXSUUcjjZOE5Uzt0VRhRcC4KJNszQ8Oj9+qHwdxGNSoqntedHs1OvDv9oL8UlzQkx69EYqpg6+7gNdwmjrFUDzpyiaX+kfO+/AA5sAzIvM1AmuF43YrazhBthD0zqYnKddNsULameE/wsEG9hL1Ie0lDClnwp960sn8OLW2Bci/yWi6AAd3azGLv9U4ijNM72UHOgiTDy2zy4WANvbnWmpb8DA4u5TKWi6nmgKyE3Y3yGzkbGIbpQxWGhR6dUxBCtPZmTHCP2jY0v9dM62Y/xUtT2179Pqg2/R+lVuz9QCi8RWZU/liUH4qpiqruBoVkv9XTWg65PwWhQBvWBgFL75bZXRIPyeP9mlYD2sLLFY9Q2cyN2Buzggq0l7m1ymsOzvLn0HDc69KO6zg/60/piO5pfMudTEZeAa3n36Mv6Bpq/AVJQEyfq7AGeOsCM1dvQsAB041rLDN42YX7VC7sihC8PbKLMVPChO4M/FXbEMbzzO5b4EM6YjC9gjM80cG/XjN2X2hqZ5DV/+UUUfxYv/md13zIvDH9LJ1nYiZRP9qpLWfW6V3vrq0+p6ajQdgQ7LMrprYiuZc5VVcdtVyAYTOx7wlHW+nX+cS2TTev/J0xwq6ksA1WOUjj/57bpjddngwRbSSTDi6M0nyiwb0XyC0KQFE3XtfQu++YNY07fkWs8I8YzdvYaCoku856WfnbBWbe4+JXLPhqkZMtSIdtTizVprHNtaJRuqfo3MOj/sOFBZPBS/9D2k2ttLcL5mr2/Abo X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(39860400002)(346002)(136003)(396003)(451199015)(36840700001)(46966006)(40470700004)(8936002)(82310400005)(2906002)(36860700001)(26005)(30864003)(7696005)(356005)(40480700001)(2616005)(81166007)(1076003)(16526019)(186003)(36756003)(47076005)(40460700003)(83380400001)(5660300002)(336012)(426003)(86362001)(478600001)(41300700001)(82740400003)(70206006)(4326008)(8676002)(70586007)(316002)(6666004)(54906003)(110136005)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Nov 2022 17:58:35.8820 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 25c8877c-a6c0-47e8-399b-08dac0e9b137 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT110.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB8125 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748861651829652483?= X-GMAIL-MSGID: =?utf-8?q?1748861651829652483?= Add EPP driver support for those AMD CPUs which has full MSR feature enabled, The EPP is used in the DPM controller to drive the frequency that a core is going to operate during short periods of activity. EPP values will be utilized for different OS profiles (balanced, performance, power savings). cppc performance can be controlled by the user space interface sys attributes for min and max frequency limits, when pstate driver is working under power save policy. EPP scale is 0 - 255, 0 is the max performance and 255 is min level. balance_performance (0x80) can provide best balance performance and watt for most of system, meanwhile user can choose performance policy on needs. $ cat /sys/devices/system/cpu/cpufreq/policy0/energy_performance_available_preferences default performance balance_performance balance_power power $ cat /sys/devices/system/cpu/cpufreq/policy0/energy_performance_preference balance_performance Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 658 ++++++++++++++++++++++++++++++++++- include/linux/amd-pstate.h | 81 +++++ 2 files changed, 734 insertions(+), 5 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 14906431dc15..eb82bc6a7f66 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -60,8 +60,136 @@ * module parameter to be able to enable it manually for debugging. */ static bool shared_mem __read_mostly; +static int cppc_active __read_mostly; +static int disable_pstate_load __initdata; +static int epp_off __initdata; -static struct cpufreq_driver amd_pstate_driver; +static struct cpufreq_driver *default_pstate_driver; +static struct amd_cpudata **all_cpu_data; + +static struct amd_pstate_params global_params; + +static DEFINE_MUTEX(amd_pstate_limits_lock); +static DEFINE_MUTEX(amd_pstate_driver_lock); + +static bool cppc_boost __read_mostly; +struct kobject *amd_pstate_kobj; + +#ifdef CONFIG_ACPI_CPPC_LIB +static s16 amd_pstate_get_epp(struct amd_cpudata *cpudata, u64 cppc_req_cached) +{ + s16 epp; + struct cppc_perf_caps perf_caps; + int ret; + + if (boot_cpu_has(X86_FEATURE_CPPC)) { + if (!cppc_req_cached) { + epp = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, + &cppc_req_cached); + if (epp) + return epp; + } + epp = (cppc_req_cached >> 24) & 0xFF; + } else { + ret = cppc_get_epp_caps(cpudata->cpu, &perf_caps); + if (ret < 0) { + pr_debug("Could not retrieve energy perf value (%d)\n", ret); + return -EIO; + } + epp = (s16) perf_caps.energy_perf; + } + + return epp; +} +#endif + +static int amd_pstate_get_energy_pref_index(struct amd_cpudata *cpudata, int *raw_epp) +{ + s16 epp; + int index = -EINVAL; + + *raw_epp = 0; + epp = amd_pstate_get_epp(cpudata, 0); + if (epp < 0) + return epp; + + switch (epp) { + case AMD_CPPC_EPP_PERFORMANCE: + index = EPP_INDEX_PERFORMANCE; + break; + case AMD_CPPC_EPP_BALANCE_PERFORMANCE: + index = EPP_INDEX_BALANCE_PERFORMANCE; + break; + case AMD_CPPC_EPP_BALANCE_POWERSAVE: + index = EPP_INDEX_BALANCE_POWERSAVE; + break; + case AMD_CPPC_EPP_POWERSAVE: + index = EPP_INDEX_POWERSAVE; + break; + default: + *raw_epp = epp; + index = 0; + } + + return index; +} + +#ifdef CONFIG_ACPI_CPPC_LIB +static int amd_pstate_set_epp(struct amd_cpudata *cpudata, u32 epp) +{ + int ret; + struct cppc_perf_ctrls perf_ctrls; + + if (boot_cpu_has(X86_FEATURE_CPPC)) { + u64 value = READ_ONCE(cpudata->cppc_req_cached); + + value &= ~GENMASK_ULL(31, 24); + value |= (u64)epp << 24; + WRITE_ONCE(cpudata->cppc_req_cached, value); + + ret = wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); + if (!ret) + cpudata->epp_cached = epp; + } else { + perf_ctrls.energy_perf = epp; + ret = cppc_set_epp_perf(cpudata->cpu, &perf_ctrls); + if (ret) { + pr_debug("failed to set energy perf value (%d)\n", ret); + return ret; + } + cpudata->epp_cached = epp; + } + + return ret; +} + +static int amd_pstate_set_energy_pref_index(struct amd_cpudata *cpudata, + int pref_index, bool use_raw, + u32 raw_epp) +{ + int epp = -EINVAL; + int ret; + + if (!pref_index) { + pr_debug("EPP pref_index is invalid\n"); + return -EINVAL; + } + + if (use_raw) + epp = raw_epp; + else if (epp == -EINVAL) + epp = epp_values[pref_index]; + + if (epp > 0 && cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) { + pr_debug("EPP cannot be set under performance policy\n"); + return -EBUSY; + } + + ret = amd_pstate_set_epp(cpudata, epp); + + return ret; +} +#endif static inline int pstate_enable(bool enable) { @@ -71,11 +199,25 @@ static inline int pstate_enable(bool enable) static int cppc_enable(bool enable) { int cpu, ret = 0; + struct cppc_perf_ctrls perf_ctrls; for_each_present_cpu(cpu) { ret = cppc_set_enable(cpu, enable); if (ret) return ret; + + /* Enable autonomous mode for EPP */ + if (!cppc_active) { + ret = cppc_set_auto_epp(cpu, enable); + if (ret) + return ret; + + /* Set desired perf as zero to allow EPP firmware control */ + perf_ctrls.desired_perf = 0; + ret = cppc_set_perf(cpu, &perf_ctrls); + if (ret) + return ret; + } } return ret; @@ -418,7 +560,7 @@ static void amd_pstate_boost_init(struct amd_cpudata *cpudata) return; cpudata->boost_supported = true; - amd_pstate_driver.boost_enabled = true; + default_pstate_driver->boost_enabled = true; } static int amd_pstate_cpu_init(struct cpufreq_policy *policy) @@ -582,10 +724,74 @@ static ssize_t show_amd_pstate_highest_perf(struct cpufreq_policy *policy, return sprintf(&buf[0], "%u\n", perf); } +static ssize_t show_energy_performance_available_preferences( + struct cpufreq_policy *policy, char *buf) +{ + int i = 0; + int ret = 0; + + while (energy_perf_strings[i] != NULL) + ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]); + + ret += sprintf(&buf[ret], "\n"); + + return ret; +} + +static ssize_t store_energy_performance_preference( + struct cpufreq_policy *policy, const char *buf, size_t count) +{ + struct amd_cpudata *cpudata = policy->driver_data; + char str_preference[21]; + bool raw = false; + ssize_t ret; + u32 epp = 0; + + ret = sscanf(buf, "%20s", str_preference); + if (ret != 1) + return -EINVAL; + + ret = match_string(energy_perf_strings, -1, str_preference); + if (ret < 0) { + ret = kstrtouint(buf, 10, &epp); + if (ret) + return ret; + + if ((epp > 255) || (epp < 0)) + return -EINVAL; + + raw = true; + } + + mutex_lock(&amd_pstate_limits_lock); + ret = amd_pstate_set_energy_pref_index(cpudata, ret, raw, epp); + mutex_unlock(&amd_pstate_limits_lock); + + return ret ?: count; +} + +static ssize_t show_energy_performance_preference( + struct cpufreq_policy *policy, char *buf) +{ + struct amd_cpudata *cpudata = policy->driver_data; + int preference, raw_epp; + + preference = amd_pstate_get_energy_pref_index(cpudata, &raw_epp); + if (preference < 0) + return preference; + + if (raw_epp) + return sprintf(buf, "%d\n", raw_epp); + else + return sprintf(buf, "%s\n", energy_perf_strings[preference]); +} + cpufreq_freq_attr_ro(amd_pstate_max_freq); cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); cpufreq_freq_attr_ro(amd_pstate_highest_perf); +cpufreq_freq_attr_rw(energy_performance_preference); +cpufreq_freq_attr_ro(energy_performance_available_preferences); static struct freq_attr *amd_pstate_attr[] = { &amd_pstate_max_freq, @@ -594,6 +800,415 @@ static struct freq_attr *amd_pstate_attr[] = { NULL, }; +static struct freq_attr *amd_pstate_epp_attr[] = { + &amd_pstate_max_freq, + &amd_pstate_lowest_nonlinear_freq, + &amd_pstate_highest_perf, + &energy_performance_preference, + &energy_performance_available_preferences, + NULL, +}; + +static inline void update_boost_state(void) +{ + u64 misc_en; + struct amd_cpudata *cpudata; + + cpudata = all_cpu_data[0]; + rdmsrl(MSR_K7_HWCR, misc_en); + global_params.cppc_boost_disabled = misc_en & BIT_ULL(25); +} + +static int amd_pstate_init_cpu(unsigned int cpunum) +{ + struct amd_cpudata *cpudata; + + cpudata = all_cpu_data[cpunum]; + if (!cpudata) { + cpudata = kzalloc(sizeof(*cpudata), GFP_KERNEL); + if (!cpudata) + return -ENOMEM; + WRITE_ONCE(all_cpu_data[cpunum], cpudata); + + cpudata->cpu = cpunum; + } + cpudata->epp_powersave = -EINVAL; + cpudata->epp_policy = 0; + pr_debug("controlling: cpu %d\n", cpunum); + return 0; +} + +static int __amd_pstate_cpu_init(struct cpufreq_policy *policy) +{ + int min_freq, max_freq, nominal_freq, lowest_nonlinear_freq, ret; + struct amd_cpudata *cpudata; + struct device *dev; + int rc; + u64 value; + + rc = amd_pstate_init_cpu(policy->cpu); + if (rc) + return rc; + + cpudata = all_cpu_data[policy->cpu]; + + dev = get_cpu_device(policy->cpu); + if (!dev) + goto free_cpudata1; + + rc = amd_pstate_init_perf(cpudata); + if (rc) + goto free_cpudata1; + + min_freq = amd_get_min_freq(cpudata); + max_freq = amd_get_max_freq(cpudata); + nominal_freq = amd_get_nominal_freq(cpudata); + lowest_nonlinear_freq = amd_get_lowest_nonlinear_freq(cpudata); + if (min_freq < 0 || max_freq < 0 || min_freq > max_freq) { + dev_err(dev, "min_freq(%d) or max_freq(%d) value is incorrect\n", + min_freq, max_freq); + ret = -EINVAL; + goto free_cpudata1; + } + + policy->min = min_freq; + policy->max = max_freq; + + policy->cpuinfo.min_freq = min_freq; + policy->cpuinfo.max_freq = max_freq; + /* It will be updated by governor */ + policy->cur = policy->cpuinfo.min_freq; + + /* Initial processor data capability frequencies */ + cpudata->max_freq = max_freq; + cpudata->min_freq = min_freq; + cpudata->nominal_freq = nominal_freq; + cpudata->lowest_nonlinear_freq = lowest_nonlinear_freq; + + policy->driver_data = cpudata; + + update_boost_state(); + cpudata->epp_cached = amd_pstate_get_epp(cpudata, value); + + policy->min = policy->cpuinfo.min_freq; + policy->max = policy->cpuinfo.max_freq; + + if (boot_cpu_has(X86_FEATURE_CPPC)) + policy->fast_switch_possible = true; + + if (!shared_mem && boot_cpu_has(X86_FEATURE_CPPC)) { + ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, &value); + if (ret) + return ret; + WRITE_ONCE(cpudata->cppc_req_cached, value); + + ret = rdmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_CAP1, &value); + if (ret) + return ret; + WRITE_ONCE(cpudata->cppc_cap1_cached, value); + } + amd_pstate_boost_init(cpudata); + + return 0; + +free_cpudata1: + kfree(cpudata); + return ret; +} + +static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) +{ + int ret; + + ret = __amd_pstate_cpu_init(policy); + if (ret) + return ret; + /* + * Set the policy to powersave to provide a valid fallback value in case + * the default cpufreq governor is neither powersave nor performance. + */ + policy->policy = CPUFREQ_POLICY_POWERSAVE; + + return 0; +} + +static int amd_pstate_epp_cpu_exit(struct cpufreq_policy *policy) +{ + pr_debug("amd-pstate: CPU %d exiting\n", policy->cpu); + policy->fast_switch_possible = false; + return 0; +} + +static void amd_pstate_update_max_freq(unsigned int cpu) +{ + struct cpufreq_policy *policy = policy = cpufreq_cpu_get(cpu); + + if (!policy) + return; + + refresh_frequency_limits(policy); + cpufreq_cpu_put(policy); +} + +static void amd_pstate_epp_update_limits(unsigned int cpu) +{ + mutex_lock(&amd_pstate_driver_lock); + update_boost_state(); + if (global_params.cppc_boost_disabled) { + for_each_possible_cpu(cpu) + amd_pstate_update_max_freq(cpu); + } else { + cpufreq_update_policy(cpu); + } + mutex_unlock(&amd_pstate_driver_lock); +} + +static int cppc_boost_hold_time_ns = 3 * NSEC_PER_MSEC; + +static inline void amd_pstate_boost_up(struct amd_cpudata *cpudata) +{ + u64 hwp_req = READ_ONCE(cpudata->cppc_req_cached); + u64 hwp_cap = READ_ONCE(cpudata->cppc_cap1_cached); + u32 max_limit = (hwp_req & 0xff); + u32 min_limit = (hwp_req & 0xff00) >> 8; + u32 boost_level1; + + /* If max and min are equal or already at max, nothing to boost */ + if (max_limit == min_limit) + return; + + /* Set boost max and min to initial value */ + if (!cpudata->cppc_boost_min) + cpudata->cppc_boost_min = min_limit; + + boost_level1 = ((AMD_CPPC_NOMINAL_PERF(hwp_cap) + min_limit) >> 1); + + if (cpudata->cppc_boost_min < boost_level1) + cpudata->cppc_boost_min = boost_level1; + else if (cpudata->cppc_boost_min < AMD_CPPC_NOMINAL_PERF(hwp_cap)) + cpudata->cppc_boost_min = AMD_CPPC_NOMINAL_PERF(hwp_cap); + else if (cpudata->cppc_boost_min == AMD_CPPC_NOMINAL_PERF(hwp_cap)) + cpudata->cppc_boost_min = max_limit; + else + return; + + hwp_req &= ~AMD_CPPC_MIN_PERF(~0L); + hwp_req |= AMD_CPPC_MIN_PERF(cpudata->cppc_boost_min); + wrmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, hwp_req); + cpudata->last_update = cpudata->sample.time; +} + +static inline void amd_pstate_boost_down(struct amd_cpudata *cpudata) +{ + bool expired; + + if (cpudata->cppc_boost_min) { + expired = time_after64(cpudata->sample.time, cpudata->last_update + + cppc_boost_hold_time_ns); + + if (expired) { + wrmsrl_safe_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, + cpudata->cppc_req_cached); + cpudata->cppc_boost_min = 0; + } + } + + cpudata->last_update = cpudata->sample.time; +} + +static inline void amd_pstate_boost_update_util(struct amd_cpudata *cpudata, + u64 time) +{ + cpudata->sample.time = time; + if (smp_processor_id() != cpudata->cpu) + return; + + if (cpudata->sched_flags & SCHED_CPUFREQ_IOWAIT) { + bool do_io = false; + + cpudata->sched_flags = 0; + /* + * Set iowait_boost flag and update time. Since IO WAIT flag + * is set all the time, we can't just conclude that there is + * some IO bound activity is scheduled on this CPU with just + * one occurrence. If we receive at least two in two + * consecutive ticks, then we treat as boost candidate. + * This is leveraged from Intel Pstate driver. + */ + if (time_before64(time, cpudata->last_io_update + 2 * TICK_NSEC)) + do_io = true; + + cpudata->last_io_update = time; + + if (do_io) + amd_pstate_boost_up(cpudata); + + } else { + amd_pstate_boost_down(cpudata); + } +} + +static inline void amd_pstate_cppc_update_hook(struct update_util_data *data, + u64 time, unsigned int flags) +{ + struct amd_cpudata *cpudata = container_of(data, + struct amd_cpudata, update_util); + + cpudata->sched_flags |= flags; + + if (smp_processor_id() == cpudata->cpu) + amd_pstate_boost_update_util(cpudata, time); +} + +static void amd_pstate_clear_update_util_hook(unsigned int cpu) +{ + struct amd_cpudata *cpudata = all_cpu_data[cpu]; + + if (!cpudata->update_util_set) + return; + + cpufreq_remove_update_util_hook(cpu); + cpudata->update_util_set = false; + synchronize_rcu(); +} + +static void amd_pstate_set_update_util_hook(unsigned int cpu_num) +{ + struct amd_cpudata *cpudata = all_cpu_data[cpu_num]; + + if (!cppc_boost) { + if (cpudata->update_util_set) + amd_pstate_clear_update_util_hook(cpudata->cpu); + return; + } + + if (cpudata->update_util_set) + return; + + cpudata->sample.time = 0; + cpufreq_add_update_util_hook(cpu_num, &cpudata->update_util, + amd_pstate_cppc_update_hook); + cpudata->update_util_set = true; +} + +static void amd_pstate_epp_init(unsigned int cpu) +{ + struct amd_cpudata *cpudata = all_cpu_data[cpu]; + u32 max_perf, min_perf; + u64 value; + s16 epp; + int ret; + + max_perf = READ_ONCE(cpudata->highest_perf); + min_perf = READ_ONCE(cpudata->lowest_perf); + + value = READ_ONCE(cpudata->cppc_req_cached); + + if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) + min_perf = max_perf; + + /* Initial min/max values for CPPC Performance Controls Register */ + value &= ~AMD_CPPC_MIN_PERF(~0L); + value |= AMD_CPPC_MIN_PERF(min_perf); + + value &= ~AMD_CPPC_MAX_PERF(~0L); + value |= AMD_CPPC_MAX_PERF(max_perf); + + /* CPPC EPP feature require to set zero to the desire perf bit */ + value &= ~AMD_CPPC_DES_PERF(~0L); + value |= AMD_CPPC_DES_PERF(0); + + if (cpudata->epp_policy == cpudata->policy) + goto skip_epp; + + cpudata->epp_policy = cpudata->policy; + + if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) { + epp = amd_pstate_get_epp(cpudata, value); + cpudata->epp_powersave = epp; + if (epp < 0) + goto skip_epp; + /* force the epp value to be zero for performance policy */ + epp = 0; + } else { + if (cpudata->epp_powersave < 0) + goto skip_epp; + /* Get BIOS pre-defined epp value */ + epp = amd_pstate_get_epp(cpudata, value); + if (epp) + goto skip_epp; + epp = cpudata->epp_powersave; + } + /* Set initial EPP value */ + if (boot_cpu_has(X86_FEATURE_CPPC)) { + value &= ~GENMASK_ULL(31, 24); + value |= (u64)epp << 24; + } + +skip_epp: + WRITE_ONCE(cpudata->cppc_req_cached, value); + ret = wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); + if (!ret) + cpudata->epp_cached = epp; +} + +static void amd_pstate_set_max_limits(struct amd_cpudata *cpudata) +{ + u64 hwp_cap = READ_ONCE(cpudata->cppc_cap1_cached); + u64 hwp_req = READ_ONCE(cpudata->cppc_req_cached); + u32 max_limit = (hwp_cap >> 24) & 0xff; + + hwp_req &= ~AMD_CPPC_MIN_PERF(~0L); + hwp_req |= AMD_CPPC_MIN_PERF(max_limit); + wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, hwp_req); +} + +static int amd_pstate_epp_set_policy(struct cpufreq_policy *policy) +{ + struct amd_cpudata *cpudata; + + if (!policy->cpuinfo.max_freq) + return -ENODEV; + + pr_debug("set_policy: cpuinfo.max %u policy->max %u\n", + policy->cpuinfo.max_freq, policy->max); + + cpudata = all_cpu_data[policy->cpu]; + cpudata->policy = policy->policy; + + if (boot_cpu_has(X86_FEATURE_CPPC)) { + mutex_lock(&amd_pstate_limits_lock); + + if (cpudata->policy == CPUFREQ_POLICY_PERFORMANCE) { + amd_pstate_clear_update_util_hook(policy->cpu); + amd_pstate_set_max_limits(cpudata); + } else { + amd_pstate_set_update_util_hook(policy->cpu); + } + + if (boot_cpu_has(X86_FEATURE_CPPC)) + amd_pstate_epp_init(policy->cpu); + + mutex_unlock(&amd_pstate_limits_lock); + } + + return 0; +} + +static void amd_pstate_verify_cpu_policy(struct amd_cpudata *cpudata, + struct cpufreq_policy_data *policy) +{ + update_boost_state(); + cpufreq_verify_within_cpu_limits(policy); +} + +static int amd_pstate_epp_verify_policy(struct cpufreq_policy_data *policy) +{ + amd_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy); + pr_debug("policy_max =%d, policy_min=%d\n", policy->max, policy->min); + return 0; +} + static struct cpufreq_driver amd_pstate_driver = { .flags = CPUFREQ_CONST_LOOPS | CPUFREQ_NEED_UPDATE_LIMITS, .verify = amd_pstate_verify, @@ -607,8 +1222,20 @@ static struct cpufreq_driver amd_pstate_driver = { .attr = amd_pstate_attr, }; +static struct cpufreq_driver amd_pstate_epp_driver = { + .flags = CPUFREQ_CONST_LOOPS, + .verify = amd_pstate_epp_verify_policy, + .setpolicy = amd_pstate_epp_set_policy, + .init = amd_pstate_epp_cpu_init, + .exit = amd_pstate_epp_cpu_exit, + .update_limits = amd_pstate_epp_update_limits, + .name = "amd_pstate_epp", + .attr = amd_pstate_epp_attr, +}; + static int __init amd_pstate_init(void) { + static struct amd_cpudata **cpudata; int ret; if (boot_cpu_data.x86_vendor != X86_VENDOR_AMD) @@ -623,10 +1250,18 @@ static int __init amd_pstate_init(void) if (cpufreq_get_current_driver()) return -EEXIST; + if (!epp_off) { + WRITE_ONCE(cppc_active, 1); + if (!default_pstate_driver) + default_pstate_driver = &amd_pstate_epp_driver; + } + pr_info("AMD CPPC loading with %s driver instance.\n", default_pstate_driver->name); + /* capability check */ if (boot_cpu_has(X86_FEATURE_CPPC)) { + if (!cppc_active) + default_pstate_driver->adjust_perf = amd_pstate_adjust_perf; pr_debug("AMD CPPC MSR based functionality is supported\n"); - amd_pstate_driver.adjust_perf = amd_pstate_adjust_perf; } else if (shared_mem) { static_call_update(amd_pstate_enable, cppc_enable); static_call_update(amd_pstate_init_perf, cppc_init_perf); @@ -636,6 +1271,10 @@ static int __init amd_pstate_init(void) return -ENODEV; } + cpudata = vzalloc(array_size(sizeof(void *), num_possible_cpus())); + if (!cpudata) + return -ENOMEM; + WRITE_ONCE(all_cpu_data, cpudata); /* enable amd pstate feature */ ret = amd_pstate_enable(true); if (ret) { @@ -643,9 +1282,9 @@ static int __init amd_pstate_init(void) return ret; } - ret = cpufreq_register_driver(&amd_pstate_driver); + ret = cpufreq_register_driver(default_pstate_driver); if (ret) - pr_err("failed to register amd_pstate_driver with return %d\n", + pr_err("failed to register amd pstate driver with return %d\n", ret); return ret; @@ -657,6 +1296,15 @@ static int __init amd_pstate_param(char *str) if (!str) return -EINVAL; + if (!strcmp(str, "disable")) + disable_pstate_load = 1; + else if (!strcmp(str, "active")) { + default_pstate_driver = &amd_pstate_epp_driver; + } else if (!strcmp(str, "passive")) { + epp_off = 1; + default_pstate_driver = &amd_pstate_driver; + } + /* enable shared memory type CPPC ,if you processor has no MSR, you have to add this * to your grub to make cppc driver loaded successfully. */ diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h index 1c4b8659f171..7e6e8cab97b3 100644 --- a/include/linux/amd-pstate.h +++ b/include/linux/amd-pstate.h @@ -25,6 +25,7 @@ struct amd_aperf_mperf { u64 aperf; u64 mperf; u64 tsc; + u64 time; }; /** @@ -47,6 +48,18 @@ struct amd_aperf_mperf { * @prev: Last Aperf/Mperf/tsc count value read from register * @freq: current cpu frequency value * @boost_supported: check whether the Processor or SBIOS supports boost mode + * @epp_powersave: Last saved CPPC energy performance preference + when policy switched to performance + * @epp_policy: Last saved policy used to set energy-performance preference + * @epp_cached: Cached CPPC energy-performance preference value + * @policy: Cpufreq policy value + * @sched_flags: Store scheduler flags for possible cross CPU update + * @update_util_set: CPUFreq utility callback is set + * @last_update: Time stamp of the last performance state update + * @cppc_boost_min: Last CPPC boosted min performance state + * @cppc_cap1_cached: Cached value of the last CPPC Capabilities MSR + * @update_util: Cpufreq utility callback information + * @sample: the stored performance sample * * The amd_cpudata is key private data for each CPU thread in AMD P-State, and * represents all the attributes and goals that AMD P-State requests at runtime. @@ -72,6 +85,74 @@ struct amd_cpudata { u64 freq; bool boost_supported; + + /* EPP feature related attributes*/ + s16 epp_powersave; + s16 epp_policy; + s16 epp_cached; + u32 policy; + u32 sched_flags; + bool update_util_set; + u64 last_update; + u64 last_io_update; + u32 cppc_boost_min; + u64 cppc_cap1_cached; + struct update_util_data update_util; + struct amd_aperf_mperf sample; +}; + +/** + * struct amd_pstate_params - global parameters for the performance control + * @ cppc_boost_disabled wheher the core performance boost disabled + */ +struct amd_pstate_params { + bool cppc_boost_disabled; +}; + +#define AMD_CPPC_EPP_PERFORMANCE 0x00 +#define AMD_CPPC_EPP_BALANCE_PERFORMANCE 0x80 +#define AMD_CPPC_EPP_BALANCE_POWERSAVE 0xBF +#define AMD_CPPC_EPP_POWERSAVE 0xFF + +/* + * AMD Energy Preference Performance (EPP) + * The EPP is used in the CCLK DPM controller to drive + * the frequency that a core is going to operate during + * short periods of activity. EPP values will be utilized for + * different OS profiles (balanced, performance, power savings) + * display strings corresponding to EPP index in the + * energy_perf_strings[] + * index String + *------------------------------------- + * 0 default + * 1 performance + * 2 balance_performance + * 3 balance_power + * 4 power + */ +enum energy_perf_value_index { + EPP_INDEX_DEFAULT = 0, + EPP_INDEX_PERFORMANCE, + EPP_INDEX_BALANCE_PERFORMANCE, + EPP_INDEX_BALANCE_POWERSAVE, + EPP_INDEX_POWERSAVE, +}; + +static const char * const energy_perf_strings[] = { + [EPP_INDEX_DEFAULT] = "default", + [EPP_INDEX_PERFORMANCE] = "performance", + [EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance", + [EPP_INDEX_BALANCE_POWERSAVE] = "balance_power", + [EPP_INDEX_POWERSAVE] = "power", + NULL +}; + +static unsigned int epp_values[] = { + [EPP_INDEX_DEFAULT] = 0, + [EPP_INDEX_PERFORMANCE] = AMD_CPPC_EPP_PERFORMANCE, + [EPP_INDEX_BALANCE_PERFORMANCE] = AMD_CPPC_EPP_BALANCE_PERFORMANCE, + [EPP_INDEX_BALANCE_POWERSAVE] = AMD_CPPC_EPP_BALANCE_POWERSAVE, + [EPP_INDEX_POWERSAVE] = AMD_CPPC_EPP_POWERSAVE, }; #endif /* _LINUX_AMD_PSTATE_H */ From patchwork Mon Nov 7 17:57:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 16632 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2207999wru; Mon, 7 Nov 2022 10:08:01 -0800 (PST) X-Google-Smtp-Source: AMsMyM4Fk5TsJKdgSHDV879vubWPJ/5icg6kVpN0G4DjMqcCRP5IDGbYBmWVyLhKyx1MZ3TdL8fR X-Received: by 2002:a17:90b:400e:b0:213:de3a:a20e with SMTP id ie14-20020a17090b400e00b00213de3aa20emr43331903pjb.195.1667844480784; Mon, 07 Nov 2022 10:08:00 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1667844480; cv=pass; d=google.com; s=arc-20160816; b=bjLr+aKZP5r16eDXNo46WQ7w3GZ0VgkuGv0JqDRQzYyBe0ln+QQWi5k4zU+Pb34Mtg WCmBxG+m/wclowSJaRjF2ZleNVF3HAAl8KK2dfGCU4R9i1PltOSK25UsLpVlfrecIGpP jNMoei2bvplvi2pxPljDGWLoNrTOPU6nQUTwYPe2LId2Eeo3c5o3l65+KQSeef9H+47p gGfHUseQdh2QsQgOOs1hNKyf4ob8HB+fBqYQGe/jbKVR48zCfsC5zl43yFA4A0IEx8VM uYyhkb8BZVlMODcNUUKyh06mTVYZx9ie0tLZGyDnUcdo7P2fSRhIdsp1pmhsTts+cKG0 B7vw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=g5XkR+f6hwgRLPic66USNXfjx5kiDB8SwqB2wva+S6o=; b=rVfQhH+Hgo4MXqFdyHoCZbNTHWwXuO+BJWLWkRYGZVWPQ4wUxQOCGxOKKGlRqxLNu0 iBNjXAj5PeX9B6kYllkLS4oL9jIa0HcX3mmwbKZckkI2n/Kt9GEGFkTGt26odmDJoDXX fx+byOQCwsNmASMgjUQdLZ/JAGqJxl0fZybBRfzAxZncPa9dm3gLNp2htWv7UJgkO8Uc eTn4kOhOgSM4u57TW0z5m/TyCaolmEZsv1wbjR8nDTeJu4kBYBszE/W4arpngivgk0gb 5yp0ojVKzIfzUNdAjDpZ/nhQ3zCtzN1q7LA34wi8XeS0HJWXY9+7+mik8aJG/U9HJEyk p2Sg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=iAY6h8Np; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Mon, 7 Nov 2022 11:58:35 -0600 From: Perry Yuan To: , , CC: , , , , , , , , , Perry Yuan Subject: [PATCH v3 5/8] cpufreq: amd_pstate: implement amd pstate cpu online and offline callback Date: Tue, 8 Nov 2022 01:57:02 +0800 Message-ID: <20221107175705.2207842-6-Perry.Yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221107175705.2207842-1-Perry.Yuan@amd.com> References: <20221107175705.2207842-1-Perry.Yuan@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT053:EE_|CY5PR12MB6382:EE_ X-MS-Office365-Filtering-Correlation-Id: 21d6d8a8-6771-4790-aaf2-08dac0e9b32e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: hjMvCS0r3B4awqO2g7vaIO7oswrW1LT848StjxXNyTiW8BJrE3dN1QX/ZZbAlprK/uGgZs+yXJHbeNtkwbVq2pBhnJDERMZgwmyPBC70yDMiE4Q87DBjL5gvbvitc2NbrpnjSQOQfghj+CXsgUl5pz8xOAAdeHAaLTSh8TLpf7UaODCoTzx+WHp4CCJsObeEIfG3g7kbVWJUDmvnhhVn0MBGWwCz+ap5iS7XKrwROaNjjJNdBrKWbU+0EnAnhox0JFzPGTxtN2Zg6hV1a49X+vY9z8SDxgtyuHgk4W70/kO/VziHdrV0Ypdi7383OIsbhE6dBb5TxrTzW/934nkWH15wqkJrSDLZPkpdQ42RnM/4SmFLEv0NZlcYbIxiBejRYw/is9B2mdVhknB1qyErzuCEm2Fbgcx8qEuR1uW7hQiXItA+2E7HBJOAU8pIfh62+ncRjWSEXKt8n1AjxBUIjwbpicmPr0qOjOaP11US3/GebO7Q3Hgxy2s0PrTb30WPTaoDAIEDZRUfz0t5pAeGr2FLraQn4E6QlTebOG8c1/86UxWZpbqCNAVRpOdsaEdQ5Gc5q7j/1E1Qkm9jFEayz+mV+ESagRUB6gG/LV4kLXRkSVcXFJl4iLttY9JE7M+vmRwGhh5c4cV5pprDEO6v3jlXH1gNTLBEg6DlBvsq63oZZyUAGvPtpyQtxlgkpr79KayOGvvaHT8IEy9GregepurZlqFm7U/N7xBsUuOa4oQPiZ7fW3D+B9BncXAwEBxA71qmIM5T25VsCqaQf7WaFoU7PSHzqKTSypUbFOcHaJQQ8KE7iAmthb60uQ9QCkxm4nkILYQN+9tUh+yUwEUWgQ== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(39860400002)(136003)(346002)(396003)(451199015)(36840700001)(40470700004)(46966006)(40480700001)(36756003)(36860700001)(86362001)(5660300002)(356005)(2906002)(81166007)(83380400001)(426003)(2616005)(478600001)(1076003)(186003)(110136005)(316002)(26005)(336012)(82740400003)(54906003)(40460700003)(16526019)(47076005)(8676002)(4326008)(8936002)(41300700001)(70586007)(70206006)(6666004)(82310400005)(7696005)(2101003)(36900700001);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Nov 2022 17:58:39.1814 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 21d6d8a8-6771-4790-aaf2-08dac0e9b32e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT053.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6382 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748861694256781446?= X-GMAIL-MSGID: =?utf-8?q?1748861694256781446?= Adds online and offline driver callback support to allow cpu cores go offline and help to restore the previous working states when core goes back online later for EPP driver mode. Signed-off-by: Perry Yuan Reviewed-by: Mario Limonciello --- drivers/cpufreq/amd-pstate.c | 89 ++++++++++++++++++++++++++++++++++++ include/linux/amd-pstate.h | 1 + 2 files changed, 90 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index eb82bc6a7f66..6ce9fca0a128 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -1195,6 +1195,93 @@ static int amd_pstate_epp_set_policy(struct cpufreq_policy *policy) return 0; } +static void amd_pstate_epp_reenable(struct amd_cpudata *cpudata) +{ + struct cppc_perf_ctrls perf_ctrls; + u64 value, max_perf; + int ret; + + ret = amd_pstate_enable(true); + if (ret) + pr_err("failed to enable amd pstate during resume, return %d\n", ret); + + value = READ_ONCE(cpudata->cppc_req_cached); + max_perf = READ_ONCE(cpudata->highest_perf); + + if (boot_cpu_has(X86_FEATURE_CPPC)) { + wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); + } else { + perf_ctrls.max_perf = max_perf; + perf_ctrls.energy_perf = AMD_CPPC_ENERGY_PERF_PREF(cpudata->epp_cached); + cppc_set_perf(cpudata->cpu, &perf_ctrls); + } +} + +static int amd_pstate_epp_cpu_online(struct cpufreq_policy *policy) +{ + struct amd_cpudata *cpudata = all_cpu_data[policy->cpu]; + + pr_debug("AMD CPU Core %d going online\n", cpudata->cpu); + + if (cppc_active) { + amd_pstate_epp_reenable(cpudata); + cpudata->suspended = false; + } + + return 0; +} + +static void amd_pstate_epp_offline(struct cpufreq_policy *policy) +{ + struct amd_cpudata *cpudata = all_cpu_data[policy->cpu]; + struct cppc_perf_ctrls perf_ctrls; + int min_perf; + u64 value; + + min_perf = READ_ONCE(cpudata->lowest_perf); + value = READ_ONCE(cpudata->cppc_req_cached); + + mutex_lock(&amd_pstate_limits_lock); + if (boot_cpu_has(X86_FEATURE_CPPC)) { + cpudata->epp_policy = CPUFREQ_POLICY_UNKNOWN; + + /* Set max perf same as min perf */ + value &= ~AMD_CPPC_MAX_PERF(~0L); + value |= AMD_CPPC_MAX_PERF(min_perf); + value &= ~AMD_CPPC_MIN_PERF(~0L); + value |= AMD_CPPC_MIN_PERF(min_perf); + wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); + } else { + perf_ctrls.desired_perf = 0; + perf_ctrls.max_perf = min_perf; + perf_ctrls.energy_perf = AMD_CPPC_ENERGY_PERF_PREF(AMD_CPPC_EPP_POWERSAVE); + cppc_set_perf(cpudata->cpu, &perf_ctrls); + } + mutex_unlock(&amd_pstate_limits_lock); +} + +static int amd_pstate_cpu_offline(struct cpufreq_policy *policy) +{ + struct amd_cpudata *cpudata = all_cpu_data[policy->cpu]; + + pr_debug("AMD CPU Core %d going offline\n", cpudata->cpu); + + if (cpudata->suspended) + return 0; + + if (cppc_active) + amd_pstate_epp_offline(policy); + + return 0; +} + +static int amd_pstate_epp_cpu_offline(struct cpufreq_policy *policy) +{ + amd_pstate_clear_update_util_hook(policy->cpu); + + return amd_pstate_cpu_offline(policy); +} + static void amd_pstate_verify_cpu_policy(struct amd_cpudata *cpudata, struct cpufreq_policy_data *policy) { @@ -1229,6 +1316,8 @@ static struct cpufreq_driver amd_pstate_epp_driver = { .init = amd_pstate_epp_cpu_init, .exit = amd_pstate_epp_cpu_exit, .update_limits = amd_pstate_epp_update_limits, + .offline = amd_pstate_epp_cpu_offline, + .online = amd_pstate_epp_cpu_online, .name = "amd_pstate_epp", .attr = amd_pstate_epp_attr, }; diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h index 7e6e8cab97b3..c0ad7eedcae3 100644 --- a/include/linux/amd-pstate.h +++ b/include/linux/amd-pstate.h @@ -99,6 +99,7 @@ struct amd_cpudata { u64 cppc_cap1_cached; struct update_util_data update_util; struct amd_aperf_mperf sample; + bool suspended; }; /** From patchwork Mon Nov 7 17:57:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 16624 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2207302wru; Mon, 7 Nov 2022 10:06:43 -0800 (PST) X-Google-Smtp-Source: AMsMyM68rDrkwZwdFmZoQj9N34xUHGNfJUvZYtCXqDVkzreS0zt0mUsOTOS/N8pTdhIbAKEweTWJ X-Received: by 2002:a05:6402:1d4e:b0:461:c7bd:7d9c with SMTP id dz14-20020a0564021d4e00b00461c7bd7d9cmr51255335edb.284.1667844402877; Mon, 07 Nov 2022 10:06:42 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1667844402; cv=pass; d=google.com; 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Mon, 7 Nov 2022 11:58:38 -0600 From: Perry Yuan To: , , CC: , , , , , , , , , Perry Yuan Subject: [PATCH v3 6/8] cpufreq: amd-pstate: implement suspend and resume callbacks Date: Tue, 8 Nov 2022 01:57:03 +0800 Message-ID: <20221107175705.2207842-7-Perry.Yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221107175705.2207842-1-Perry.Yuan@amd.com> References: <20221107175705.2207842-1-Perry.Yuan@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT067:EE_|DS7PR12MB5982:EE_ X-MS-Office365-Filtering-Correlation-Id: c0f9c833-c55d-4ce0-7f39-08dac0e9b570 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: D+wv+tANqBayn4aogKEA2bFMm2sSBMwBeq+jq46KrXxIJZeFeYhn/Yb948B0Nr4tzbLYdJFyu+qIK9pTVDKjZ833EH/n06ZYRdl1QqbPgrxjNSE/urn/U27b2QEr7l5dVlIJ3IH5r3ohQy1M5GVPxpPp0IFMP0sRiyzzqOMGstbbxTODM1ZhIKD30+Sgx72iAHpd0t8YPXom589YzJBxVDG4RoYw69Dj7E0jgnmyrQZr+6sc3KL/7Dixx7Bi4e0+C99PsuIP6lyYDxbfJOWIC2pIX9NXsVLSu7GmPtbo8lr/sKsvmhdS3o6JRtl/XeqQUF7tpAp1uD1M4j2cM8dxvieno0Pp7Z87yDxdeNWOdqh9EMNSCxhi8MD284kF8BwSqn3ty/pSvoLoFalmkGezfsMgi+vF2rBi3YH8IPP8HEgSA/i6V1fiDioCZ7PMUJoIVEOZETRzYHJPga3AFzfUZgcfg68CBFiU5UPylmrfaBDL11aGdxd6CDqKbcUuEwMFYPgzmbiBVVhX+z3eqW/jZ9ugCY1kDYOSHY5R3JwAusP28KV17MV+Fd+OrUtFuPoPGb+AFDbzDfkrSVwtpL7cmWOTQ/YaHu4/khdGbr/9/6y3sXHKps14UfmqcC2G3Ky16HdB/gOUWrPZHs/HcMpCtKP3bya/dPrzAcSP0oXek5A8TrHdAAtiQEryd90kDp4xr+niV6GIK7IPtVfT3px2F9AgHFq6O3j5pcxfKIharSBOum4blXOUu0O3iuotc/DY3If2uVN29K2D8eK4k66PFrP+slJf3XFWPDXaw/6GOARJgNLLE5yusIymRLR3JrkZDcKepKeRLS2xpyjMQwgsYw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(346002)(39860400002)(376002)(136003)(396003)(451199015)(36840700001)(40470700004)(46966006)(316002)(110136005)(8676002)(54906003)(40460700003)(4326008)(2906002)(478600001)(36756003)(70586007)(70206006)(86362001)(82310400005)(356005)(36860700001)(83380400001)(426003)(47076005)(1076003)(82740400003)(81166007)(40480700001)(7696005)(6666004)(26005)(2616005)(336012)(16526019)(186003)(8936002)(5660300002)(41300700001)(15650500001)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Nov 2022 17:58:42.9370 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c0f9c833-c55d-4ce0-7f39-08dac0e9b570 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT067.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5982 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748861612564714873?= X-GMAIL-MSGID: =?utf-8?q?1748861612564714873?= add suspend and resume support for the AMD processors by amd_pstate_epp driver instance. When the CPPC is suspended, EPP driver will set EPP profile to 'power' profile and set max/min perf to lowest perf value. When resume happens, it will restore the MSR registers with previous cached value. Signed-off-by: Perry Yuan Reviewed-by: Mario Limonciello --- drivers/cpufreq/amd-pstate.c | 40 ++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 6ce9fca0a128..841b1e2383b8 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -1282,6 +1282,44 @@ static int amd_pstate_epp_cpu_offline(struct cpufreq_policy *policy) return amd_pstate_cpu_offline(policy); } +static int amd_pstate_epp_suspend(struct cpufreq_policy *policy) +{ + struct amd_cpudata *cpudata = all_cpu_data[policy->cpu]; + int ret; + + /* avoid suspending when EPP is not enabled */ + if (!cppc_active) + return 0; + + /* set this flag to avoid setting core offline*/ + cpudata->suspended = true; + + /* disable CPPC in lowlevel firmware */ + ret = amd_pstate_enable(false); + if (ret) + pr_err("failed to suspend, return %d\n", ret); + + return 0; +} + +static int amd_pstate_epp_resume(struct cpufreq_policy *policy) +{ + struct amd_cpudata *cpudata = all_cpu_data[policy->cpu]; + + if (cpudata->suspended) { + mutex_lock(&amd_pstate_limits_lock); + + /* enable amd pstate from suspend state*/ + amd_pstate_epp_reenable(cpudata); + + mutex_unlock(&amd_pstate_limits_lock); + + cpudata->suspended = false; + } + + return 0; +} + static void amd_pstate_verify_cpu_policy(struct amd_cpudata *cpudata, struct cpufreq_policy_data *policy) { @@ -1318,6 +1356,8 @@ static struct cpufreq_driver amd_pstate_epp_driver = { .update_limits = amd_pstate_epp_update_limits, .offline = amd_pstate_epp_cpu_offline, .online = amd_pstate_epp_cpu_online, + .suspend = amd_pstate_epp_suspend, + .resume = amd_pstate_epp_resume, .name = "amd_pstate_epp", .attr = amd_pstate_epp_attr, }; From patchwork Mon Nov 7 17:57:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 16625 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2207362wru; Mon, 7 Nov 2022 10:06:48 -0800 (PST) X-Google-Smtp-Source: AMsMyM5NJLrMoXs7zKlxXNyJhOGMhZuUafd8gu7X6/+mTYGdCMg3sJzpn6E8NmUg2pp4e4WdxVo4 X-Received: by 2002:a05:6402:5250:b0:461:e870:850f with SMTP id t16-20020a056402525000b00461e870850fmr51399395edd.404.1667844408215; Mon, 07 Nov 2022 10:06:48 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1667844408; cv=pass; d=google.com; s=arc-20160816; b=V67u1pO3cxrWa9FrZx3BeXUm327WDsObtatwW7gXc0oWP1hbJtEbZQG4fUMJ+ubK/r rgJR5Zkewxy3fBUOr29c1ud3cLONA/X6JEnHpQa2zyXEsrMHsPvJK3Q4uZ+xYwKi3JNL ese9SSFNFPYo7/uN3eEFEbEYeDeCB9RX2NAsiyb3zGo+4c7jIkzAXUArXofzLB7DAR14 m45SKzh5kKD7mmy00G3Sb/NLBpbTBCChUsN+zy5l19ILpLs39em8U/UzTMpRgos9hjUV pqEhbuN6pAYD2P1pq4n+CgsIlhsleAzcsp7PgJYjoGv9EPvr3s5RdU6rez/8STKyR1kx 0SSA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=g1Nf18yDHNox+tTcvp4PQMEAJuGUnh+8c5j9n7dq4B8=; b=Hb4N1rig6zpMhtVtau8b/rSu760iK3JuWp/dQ8B445/RAELDK4XQEtbP6R3EfT6JNS Haa/Is8+tDW9a1IAJiBvy0oaxtP27Srbf5guqx5aTe5gbVkqfGS+m2Ykp1ifg+NmApvP B83U6K2rQHhkv5yYJA6FLKtAHe7MGDTByn3o9rSn0Osx/aLDB8Hx9QekldaQLSF20PFK qeWF+7UF72a2/LxihjD52ovel4ewAeQQsfwQl7K8hAG0p7bcseF8ZFl1CxkVueRf5clN F3IEwHYhmH8rBKe6kqWzdV9qa1sP44A+RXnMVk+gDyx726rmGQCzBE0HUGOpn9tmssct ypVg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b="Q6lQrOL/"; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Mon, 7 Nov 2022 11:58:42 -0600 From: Perry Yuan To: , , CC: , , , , , , , , , Perry Yuan Subject: [PATCH v3 7/8] cpufreq: amd-pstate: add frequency dynamic boost sysfs control Date: Tue, 8 Nov 2022 01:57:04 +0800 Message-ID: <20221107175705.2207842-8-Perry.Yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221107175705.2207842-1-Perry.Yuan@amd.com> References: <20221107175705.2207842-1-Perry.Yuan@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT037:EE_|PH7PR12MB6907:EE_ X-MS-Office365-Filtering-Correlation-Id: 1c598324-b526-45a6-b465-08dac0e9bed3 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: g+nC3y0X7czgDXKJl+5yZHSPbvxcp5Pj5c7WEoYpIkkQL70XqUUJfo04sr7cZ31zNcnw6af5recbdpEaV0SUsVvCbDJNcFgVfhy+zptaWH9v4DeIMe7R37DFnr+XvWUtpE0T34IwFIo2lwRGSggjU5YAFVphO5pXIzUciPxab2VI3H0nHIedWzAVyGB87TPWYYMuflSTombL7mjpoJ9r6kAYcWOkg9ixyta/0HF1gUBD3/okL0/Ahmyq/tyTwzsTUZIfoqMcdrOKNsRD0GdD1WLYzmo+HVDiq8q8nk926F7QXq1Pk0Uuao7LYeFioOgJQ1X1sdv4DUtXgQz+3oVuY9d2VI33cWx9ufdczBDPwJeSV53iHPELn299juxQRAygkrp3hMxy3MDRXtjwkVuwEhz955Oq7fQN3HtD0qDnMoYSqoczVNdPtenlX6ywJ4IfoxG58nQvhozFQIHGpBAbDd0Xabxs2wSURMdXuwN9Pg3NMb/nBCdCD2DtLfoCI4360NL1hezC9NJ5RQO9FSrBRzpw+/lof1a96PpS/3b27C+SDWTfxDydv34DrePGyf8LWz6MqZLsQkQ/PYjreCVJARdaKKN50AQRilXG2KxV4Pp523Y+wH4RpGOG2BoJwxPv+I4kOB/qg0UbWPE/PmTrQpX3eEgc1L2aSuR0kicZMgQTjJW1sPxI3joeS+UtHxMhrvCH/8WAv+NJEXgskI2KlcBsad2fpVHUw3K5gYBhNpMb78OAkohwyVTHI/SxksAcZAzPTf66EAy3EfDzlpT+ZXyAEPir2O4MZ+iaKSJGIjFJhwRTqcqhRhHiFNP4HZwbrKVv/Hipd8eilMfI+1wjY71cizh87EnLtUG8a8qeVcA= X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(376002)(396003)(39860400002)(136003)(346002)(451199015)(46966006)(40470700004)(36840700001)(82310400005)(36756003)(7696005)(82740400003)(41300700001)(2906002)(6666004)(5660300002)(40480700001)(36860700001)(70206006)(4326008)(70586007)(8676002)(316002)(54906003)(110136005)(8936002)(356005)(86362001)(81166007)(336012)(40460700003)(26005)(83380400001)(16526019)(186003)(1076003)(2616005)(478600001)(47076005)(426003)(2101003)(36900700001)(309714004);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Nov 2022 17:58:58.7023 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1c598324-b526-45a6-b465-08dac0e9bed3 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT037.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6907 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748861618274426447?= X-GMAIL-MSGID: =?utf-8?q?1748861618274426447?= Add one sysfs entry to control the CPU cores frequency boost state The attribute file can allow user to set max performance boosted or keeping at normal perf level. Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 53 ++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 841b1e2383b8..6958c5fd9e1c 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -786,12 +786,46 @@ static ssize_t show_energy_performance_preference( return sprintf(buf, "%s\n", energy_perf_strings[preference]); } +static void amd_pstate_update_policies(void) +{ + int cpu; + + for_each_possible_cpu(cpu) + cpufreq_update_policy(cpu); +} + +static ssize_t show_pstate_dynamic_boost(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + return sprintf(buf, "%u\n", cppc_boost); +} + +static ssize_t store_pstate_dynamic_boost(struct kobject *a, + struct kobj_attribute *b, + const char *buf, size_t count) +{ + unsigned int input; + int ret; + + ret = kstrtouint(buf, 10, &input); + if (ret) + return ret; + + mutex_lock(&amd_pstate_driver_lock); + cppc_boost = !!input; + amd_pstate_update_policies(); + mutex_unlock(&amd_pstate_driver_lock); + + return count; +} + cpufreq_freq_attr_ro(amd_pstate_max_freq); cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); cpufreq_freq_attr_ro(amd_pstate_highest_perf); cpufreq_freq_attr_rw(energy_performance_preference); cpufreq_freq_attr_ro(energy_performance_available_preferences); +define_one_global_rw(pstate_dynamic_boost); static struct freq_attr *amd_pstate_attr[] = { &amd_pstate_max_freq, @@ -809,6 +843,15 @@ static struct freq_attr *amd_pstate_epp_attr[] = { NULL, }; +static struct attribute *pstate_global_attributes[] = { + &pstate_dynamic_boost.attr, + NULL +}; + +static const struct attribute_group amd_pstate_global_attr_group = { + .attrs = pstate_global_attributes, +}; + static inline void update_boost_state(void) { u64 misc_en; @@ -1416,6 +1459,16 @@ static int __init amd_pstate_init(void) pr_err("failed to register amd pstate driver with return %d\n", ret); + amd_pstate_kobj = kobject_create_and_add("amd-pstate", &cpu_subsys.dev_root->kobj); + if (!amd_pstate_kobj) + pr_err("amd-pstate: Global sysfs registration failed.\n"); + + ret = sysfs_create_group(amd_pstate_kobj, &amd_pstate_global_attr_group); + if (ret) { + pr_err("amd-pstate: Sysfs attribute export failed with error %d.\n", + ret); + } + return ret; } device_initcall(amd_pstate_init); From patchwork Mon Nov 7 17:57:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 16623 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2207274wru; Mon, 7 Nov 2022 10:06:40 -0800 (PST) X-Google-Smtp-Source: AMsMyM4r5ETU/G/mbJNXJuG1Q7Sg60Jzx3eu+qTbBPErvZtW8dWgHpqCp77MGPaDh2DC+KE81zOr X-Received: by 2002:a17:90b:1212:b0:213:a3a4:4d97 with SMTP id gl18-20020a17090b121200b00213a3a44d97mr51366686pjb.225.1667844400214; Mon, 07 Nov 2022 10:06:40 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1667844400; cv=pass; d=google.com; s=arc-20160816; b=lARnLfdDV2g1TaR3+sioQ7x/sIdEbjpcz7S9Pg9g31+5/eHw4+dYpCtDdRGP+9ggH6 FPitHfTf9/PtzDJHziYuX6Wit9kjIlk0hztXMPrXVNO8PgoK36HOdip3Cqqs9ojaQJmJ D8a9jhhhjYI+Yry6EgLJfmdMtrBaHgOFBvnyE7JuBZNw+iPqfQoiK46FGzEYXLk9SAPA IqqBxAGexSmhN3eTEqC1nIRWw8Zc+RAOl7YUbjJk/o+BFJ7V5ypIUIgOv1PjwYO2mn0O 6N1sz7VOGoWK/E6DNT0fkrTobPo/GDi5dHPl2npIDiW2BulQxkjXUShOIzxo3H6WrDck B8wQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=PmzqqzhXAXpmhecmtyRLBCcvFOxG/63OQKgqSl/Y+LI=; b=I5cseZEhOEfErLRSSK/ouXsGw08zkvMbDDxs20/rGlQW47IBIOrdJTPFFyiO3qnVgD R/BYMjBJwPXnQ3B16EZiVHXifbu+cCgB24endDJNLypTZEXwT4ba9/LrCTdiPGt/IYRy UR/aB8FxoHw3c0hkCr+ckuiWyJY2R1JPV9V2a4UYtmi4NoAq4lZaoTFChrPzCPvnzqB1 0x4uaSxkX4/6eU6pUxIsmy6xP5Hj/E5AXpPIRvKcKHOzG8SFsfqLWqV7HTk3r9CV0MU9 ye+f2Z4TjC155ghl8Ms3sOvGO01jygDh1/tQhvUmd+hKN8wf7ERftepwTgE2rcUTIcap +Wbw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=lnjFE51y; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from out1.vger.email (out1.vger.email. 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Mon, 7 Nov 2022 11:58:58 -0600 From: Perry Yuan To: , , CC: , , , , , , , , , Perry Yuan Subject: [PATCH v3 8/8] cpufreq: amd_pstate: add driver working mode status sysfs entry Date: Tue, 8 Nov 2022 01:57:05 +0800 Message-ID: <20221107175705.2207842-9-Perry.Yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20221107175705.2207842-1-Perry.Yuan@amd.com> References: <20221107175705.2207842-1-Perry.Yuan@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT037:EE_|SN7PR12MB7228:EE_ X-MS-Office365-Filtering-Correlation-Id: b37856f2-a699-4666-6ba5-08dac0e9c0db X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Bt/99VUEizP4XoQzqrRNTHUpSnuY5zyVjXwf3TpzSo/9JGVt+1OSLkZ6LQfbHWIs4oT6hefE8wRmXKsisEmuDUk7cG228HbctJ+1z1rYewW1VZn1tLaFQPUSEKQQU7vXlYMpOKpbjHnpMwfqCB/ayQfsae6JjrfR38tS7R1qfwu7rDLl9JmcLJl3hsz1o5ERqftsTT1WFatybuBuFufWnCQ6g9NJqAk1YewL8ONdh5vz9zrGDXS42zysGeXErTxnCn6G3sl5isvduniWNJYRSssIDhf4StiSd0hCPANM4ydZRndYyuCIy+KDTVPRFJPmjJ3Axv2nbywCOC6gHAItGNoqQx5kEmPqiZbQuQHSjmxrihF7c+QG22LsntdrUnqmo58ctxEIiwHgE3nJZN3ob6nJloCshapUMKKDJR1H9vJ8OaYnDjQ+QYQk2JttZQ+0laIc6+3LtJs7V/Be+r+lOQc2MEEI8uBzl5jIoCpyz4jxWjqJECD30ppDz6myacZU2vPvBOYiHjsEHgQjMfiafTJTzA7JsdZRYEEFb3L5ArPzxDRBBhCuHiv1HUN7Ib8uPFIexz3WlzhbvtYdF5b8WEngUrR8+ATXJr/xmkq7ik6mqvyQbBaZQonhAy8pe3bvOFX3wiUs3HOjvW5wrsMVLduJ8UdTDENTzS+qFSkk+etCATZBsBT79pbCqNyJ1afuJhY2pI2Z2Yhhlzupi6xNYbxgY+RVUQAQo6uTbN4Kw4U1sMV9rtRltK1ICjDGr/QM0y+Yq9fr5KZ+IIxSUvpbCfz5DBiYHKfqjJB2pgOXBqa0JZ9zrNZvk8/6FtZkUMaN X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:SATLEXMB04.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230022)(4636009)(136003)(376002)(346002)(396003)(39860400002)(451199015)(40470700004)(36840700001)(46966006)(47076005)(426003)(7696005)(356005)(6666004)(110136005)(1076003)(2616005)(186003)(26005)(16526019)(336012)(36860700001)(83380400001)(5660300002)(2906002)(40480700001)(40460700003)(82310400005)(54906003)(478600001)(316002)(41300700001)(8936002)(8676002)(4326008)(70586007)(70206006)(36756003)(81166007)(82740400003)(86362001)(36900700001)(2101003);DIR:OUT;SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Nov 2022 17:59:02.1083 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b37856f2-a699-4666-6ba5-08dac0e9c0db X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT037.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7228 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748861610042786353?= X-GMAIL-MSGID: =?utf-8?q?1748861610042786353?= While amd-pstate driver was loaded with specific driver mode, it will need to check which mode is enabled for the pstate driver,add this sysfs entry to show the current status $ cat /sys/devices/system/cpu/amd-pstate/status active Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 44 ++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 6958c5fd9e1c..eadcc9d61d39 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -65,6 +65,8 @@ static int disable_pstate_load __initdata; static int epp_off __initdata; static struct cpufreq_driver *default_pstate_driver; +static struct cpufreq_driver amd_pstate_epp_driver; +static struct cpufreq_driver amd_pstate_driver; static struct amd_cpudata **all_cpu_data; static struct amd_pstate_params global_params; @@ -819,6 +821,46 @@ static ssize_t store_pstate_dynamic_boost(struct kobject *a, return count; } +static ssize_t amd_pstate_show_status(char *buf) +{ + if (!default_pstate_driver) + return sprintf(buf, "off\n"); + + return sprintf(buf, "%s\n", default_pstate_driver == &amd_pstate_epp_driver ? + "active" : "passive"); +} + +static int amd_pstate_update_status(const char *buf, size_t size) +{ + /* FIXME: add driver dynamic switching code */ + return 0; +} + +static ssize_t show_status(struct kobject *kobj, + struct kobj_attribute *attr, char *buf) +{ + ssize_t ret; + + mutex_lock(&amd_pstate_driver_lock); + ret = amd_pstate_show_status(buf); + mutex_unlock(&amd_pstate_driver_lock); + + return ret; +} + +static ssize_t store_status(struct kobject *a, struct kobj_attribute *b, + const char *buf, size_t count) +{ + char *p = memchr(buf, '\n', count); + int ret; + + mutex_lock(&amd_pstate_driver_lock); + ret = amd_pstate_update_status(buf, p ? p - buf : count); + mutex_unlock(&amd_pstate_driver_lock); + + return ret < 0 ? ret : count; +} + cpufreq_freq_attr_ro(amd_pstate_max_freq); cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); @@ -826,6 +868,7 @@ cpufreq_freq_attr_ro(amd_pstate_highest_perf); cpufreq_freq_attr_rw(energy_performance_preference); cpufreq_freq_attr_ro(energy_performance_available_preferences); define_one_global_rw(pstate_dynamic_boost); +define_one_global_rw(status); static struct freq_attr *amd_pstate_attr[] = { &amd_pstate_max_freq, @@ -845,6 +888,7 @@ static struct freq_attr *amd_pstate_epp_attr[] = { static struct attribute *pstate_global_attributes[] = { &pstate_dynamic_boost.attr, + &status.attr, NULL };