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Fri, 20 Oct 2023 04:34:25 -0700 (PDT) From: =?utf-8?q?Alvin_=C5=A0ipraga?= Date: Fri, 20 Oct 2023 13:34:14 +0200 Subject: [PATCH v5 1/3] dt-bindings: clock: si5351: convert to yaml MIME-Version: 1.0 Message-Id: <20231020-alvin-clk-si5351-no-pll-reset-v5-1-f0c1ba537f88@bang-olufsen.dk> References: <20231020-alvin-clk-si5351-no-pll-reset-v5-0-f0c1ba537f88@bang-olufsen.dk> In-Reply-To: <20231020-alvin-clk-si5351-no-pll-reset-v5-0-f0c1ba537f88@bang-olufsen.dk> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Alvin_=C5=A0ipraga?= Cc: Sebastian Hesselbarth , Rabeeh Khoury , Jacob Siverskog , Sergej Sawazki , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.12.3 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Fri, 20 Oct 2023 04:35:07 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780274126350759622 X-GMAIL-MSGID: 1780274126350759622 From: Alvin Šipraga The following additional properties are described: - clock-names - clock-frequency of the clkout child nodes In order to suppress warnings from the DT schema validator, the clkout child nodes are prescribed names clkout@[0-7] rather than clkout[0-7]. The example is refined as follows: - correct the usage of property pll-master -> silabs,pll-master - give an example of how the silabs,pll-reset property can be used I made myself maintainer of the file as I cannot presume that anybody else wants the responsibility. Cc: Sebastian Hesselbarth Cc: Rabeeh Khoury Signed-off-by: Alvin Šipraga Reviewed-by: Rob Herring --- .../devicetree/bindings/clock/silabs,si5351.txt | 126 ----------- .../devicetree/bindings/clock/silabs,si5351.yaml | 241 +++++++++++++++++++++ 2 files changed, 241 insertions(+), 126 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/silabs,si5351.txt b/Documentation/devicetree/bindings/clock/silabs,si5351.txt deleted file mode 100644 index bfda6af76bee..000000000000 --- a/Documentation/devicetree/bindings/clock/silabs,si5351.txt +++ /dev/null @@ -1,126 +0,0 @@ -Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator. - -Reference -[1] Si5351A/B/C Data Sheet - https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf - -The Si5351a/b/c are programmable i2c clock generators with up to 8 output -clocks. Si5351a also has a reduced pin-count package (MSOP10) where only -3 output clocks are accessible. The internal structure of the clock -generators can be found in [1]. - -==I2C device node== - -Required properties: -- compatible: shall be one of the following: - "silabs,si5351a" - Si5351a, QFN20 package - "silabs,si5351a-msop" - Si5351a, MSOP10 package - "silabs,si5351b" - Si5351b, QFN20 package - "silabs,si5351c" - Si5351c, QFN20 package -- reg: i2c device address, shall be 0x60 or 0x61. -- #clock-cells: from common clock binding; shall be set to 1. -- clocks: from common clock binding; list of parent clock - handles, shall be xtal reference clock or xtal and clkin for - si5351c only. Corresponding clock input names are "xtal" and - "clkin" respectively. -- #address-cells: shall be set to 1. -- #size-cells: shall be set to 0. - -Optional properties: -- silabs,pll-source: pair of (number, source) for each pll. Allows - to overwrite clock source of pll A (number=0) or B (number=1). - -==Child nodes== - -Each of the clock outputs can be overwritten individually by -using a child node to the I2C device node. If a child node for a clock -output is not set, the eeprom configuration is not overwritten. - -Required child node properties: -- reg: number of clock output. - -Optional child node properties: -- silabs,clock-source: source clock of the output divider stage N, shall be - 0 = multisynth N - 1 = multisynth 0 for output clocks 0-3, else multisynth4 - 2 = xtal - 3 = clkin (si5351c only) -- silabs,drive-strength: output drive strength in mA, shall be one of {2,4,6,8}. -- silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth - divider. -- silabs,pll-master: boolean, multisynth can change pll frequency. -- silabs,pll-reset: boolean, clock output can reset its pll. -- silabs,disable-state : clock output disable state, shall be - 0 = clock output is driven LOW when disabled - 1 = clock output is driven HIGH when disabled - 2 = clock output is FLOATING (HIGH-Z) when disabled - 3 = clock output is NEVER disabled - -==Example== - -/* 25MHz reference crystal */ -ref25: ref25M { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <25000000>; -}; - -i2c-master-node { - - /* Si5351a msop10 i2c clock generator */ - si5351a: clock-generator@60 { - compatible = "silabs,si5351a-msop"; - reg = <0x60>; - #address-cells = <1>; - #size-cells = <0>; - #clock-cells = <1>; - - /* connect xtal input to 25MHz reference */ - clocks = <&ref25>; - clock-names = "xtal"; - - /* connect xtal input as source of pll0 and pll1 */ - silabs,pll-source = <0 0>, <1 0>; - - /* - * overwrite clkout0 configuration with: - * - 8mA output drive strength - * - pll0 as clock source of multisynth0 - * - multisynth0 as clock source of output divider - * - multisynth0 can change pll0 - * - set initial clock frequency of 74.25MHz - */ - clkout0 { - reg = <0>; - silabs,drive-strength = <8>; - silabs,multisynth-source = <0>; - silabs,clock-source = <0>; - silabs,pll-master; - clock-frequency = <74250000>; - }; - - /* - * overwrite clkout1 configuration with: - * - 4mA output drive strength - * - pll1 as clock source of multisynth1 - * - multisynth1 as clock source of output divider - * - multisynth1 can change pll1 - */ - clkout1 { - reg = <1>; - silabs,drive-strength = <4>; - silabs,multisynth-source = <1>; - silabs,clock-source = <0>; - pll-master; - }; - - /* - * overwrite clkout2 configuration with: - * - xtal as clock source of output divider - */ - clkout2 { - reg = <2>; - silabs,clock-source = <2>; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/clock/silabs,si5351.yaml b/Documentation/devicetree/bindings/clock/silabs,si5351.yaml new file mode 100644 index 000000000000..494fa49a0c1b --- /dev/null +++ b/Documentation/devicetree/bindings/clock/silabs,si5351.yaml @@ -0,0 +1,241 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/silabs,si5351.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Silicon Labs Si5351A/B/C programmable I2C clock generators + +description: | + The Silicon Labs Si5351A/B/C are programmable I2C clock generators with up to + 8 outputs. Si5351A also has a reduced pin-count package (10-MSOP) where only 3 + output clocks are accessible. The internal structure of the clock generators + can be found in [1]. + + [1] Si5351A/B/C Data Sheet + https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf + +maintainers: + - Alvin Šipraga + +properties: + compatible: + enum: + - silabs,si5351a # Si5351A, 20-QFN package + - silabs,si5351a-msop # Si5351A, 10-MSOP package + - silabs,si5351b # Si5351B, 20-QFN package + - silabs,si5351c # Si5351C, 20-QFN package + + reg: + enum: + - 0x60 + - 0x61 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + "#clock-cells": + const: 1 + + clocks: + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: xtal + - const: clkin + + silabs,pll-source: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: | + A list of cell pairs containing a PLL index and its source. Allows to + overwrite clock source of the internal PLLs. + items: + items: + - description: PLL A (0) or PLL B (1) + enum: [ 0, 1 ] + - description: PLL source, XTAL (0) or CLKIN (1, Si5351C only). + enum: [ 0, 1 ] + +patternProperties: + "^clkout@[0-7]$": + type: object + + additionalProperties: false + + properties: + reg: + description: Clock output number. + + clock-frequency: true + + silabs,clock-source: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Source clock of the this output's divider stage. + + 0 - use multisynth N for this output, where N is the output number + 1 - use either multisynth 0 (if output number is 0-3) or multisynth 4 + (otherwise) for this output + 2 - use XTAL for this output + 3 - use CLKIN for this output (Si5351C only) + + silabs,drive-strength: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 2, 4, 6, 8 ] + description: Output drive strength in mA. + + silabs,multisynth-source: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1 ] + description: + Source PLL A (0) or B (1) for the corresponding multisynth divider. + + silabs,pll-master: + type: boolean + description: | + The frequency of the source PLL is allowed to be changed by the + multisynth when setting the rate of this clock output. + + silabs,pll-reset: + type: boolean + description: Reset the source PLL when enabling this clock output. + + silabs,disable-state: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [ 0, 1, 2, 3 ] + description: | + Clock output disable state. The state can be one of: + + 0 - clock output is driven LOW when disabled + 1 - clock output is driven HIGH when disabled + 2 - clock output is FLOATING (HIGH-Z) when disabled + 3 - clock output is never disabled + + allOf: + - if: + properties: + compatible: + contains: + const: silabs,si5351a-msop + then: + properties: + reg: + maximum: 2 + else: + properties: + reg: + maximum: 7 + + - if: + properties: + compatible: + contains: + const: silabs,si5351c + then: + properties: + silabs,clock-source: + enum: [ 0, 1, 2, 3 ] + else: + properties: + silabs,clock-source: + enum: [ 0, 1, 2 ] + + required: + - reg + +allOf: + - if: + properties: + compatible: + contains: + enum: + - silabs,si5351a + - silabs,si5351a-msop + - silabs,si5351b + then: + properties: + clocks: + maxItems: 1 + clock-names: + maxItems: 1 + +required: + - reg + - "#address-cells" + - "#size-cells" + - "#clock-cells" + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + clock-generator@60 { + compatible = "silabs,si5351a-msop"; + reg = <0x60>; + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + + /* Connect XTAL input to 25MHz reference */ + clocks = <&ref25>; + clock-names = "xtal"; + + /* Use XTAL input as source of PLL0 and PLL1 */ + silabs,pll-source = <0 0>, <1 0>; + + /* + * Overwrite CLK0 configuration with: + * - 8 mA output drive strength + * - PLL0 as clock source of multisynth 0 + * - Multisynth 0 as clock source of output divider + * - Multisynth 0 can change PLL0 + * - Set initial clock frequency of 74.25MHz + */ + clkout@0 { + reg = <0>; + silabs,drive-strength = <8>; + silabs,multisynth-source = <0>; + silabs,clock-source = <0>; + silabs,pll-master; + clock-frequency = <74250000>; + }; + + /* + * Overwrite CLK1 configuration with: + * - 4 mA output drive strength + * - PLL1 as clock source of multisynth 1 + * - Multisynth 1 as clock source of output divider + * - Multisynth 1 can change PLL1 + * - Reset PLL1 when enabling this clock output + */ + clkout@1 { + reg = <1>; + silabs,drive-strength = <4>; + silabs,multisynth-source = <1>; + silabs,clock-source = <0>; + silabs,pll-master; + silabs,pll-reset; + }; + + /* + * Overwrite CLK2 configuration with: + * - XTAL as clock source of output divider + */ + clkout@2 { + reg = <2>; + silabs,clock-source = <2>; + }; + }; + }; From patchwork Fri Oct 20 11:34:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alvin_=C5=A0ipraga?= X-Patchwork-Id: 156017 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2010:b0:403:3b70:6f57 with SMTP id fe16csp988814vqb; Fri, 20 Oct 2023 04:34:48 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGZljzevRPbNGArObRn31gVoqVJpqKlUU3vulGa8hCXPt+6aScfSVmAakm++Y9+P2a4YWMp X-Received: by 2002:a05:6a21:35c9:b0:12c:2dc7:74bc with SMTP id ba9-20020a056a2135c900b0012c2dc774bcmr1419059pzc.46.1697801688339; Fri, 20 Oct 2023 04:34:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697801688; cv=none; d=google.com; s=arc-20160816; b=dD6zdwmjDm5L12Ib5YxNOYgOLP0VsRawmrPIJJo3PrbpPB6Ntq0VYPfw1ile05zO8N UbkV64KVnNWnK+GZA37sr1CnmYWhH7BTu2XS+FRQJfHUOuGHTki0eGignjm0bBKHH3Yh 9OPF3H70OdnuJ2Ww7AKLp7tKupqUscxkSogHrOYk8dkvOkxQkrwiJpH7Hq3qqq5LAPqN Bpt/Y+mCdisZI3Azd8hFVg0d5rxiFiIdQDttX78adcDrhfsilQegB7OO7SlzU9MDRvL6 sHq4t8VdXm4eutaR/1zTttND5R2Ly9gwAPvJyb7AcrSXmviVQs+JDeRkuFIF2KzY6YMN ZsMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=qxGWL09T/U8ViEdhIaJ8zHze/hctW85nUnnCuD7crpg=; fh=cmShaaKDM89fu74c5NvQ6BtZelLx90jo5mGjUZMX0tM=; b=RVdhWFaBfn4GU/YFoX2zWcV8oVK/hTa7CTlCcpZ/S9/bFOBt0ikYghfJuXHn0g4dPR TgBRMwKzysKQ3qF7UnDR3QwzzBJAtVgTDremW/SMQbglkfc0NVMVrBbURQbeWrUFYGWU wbGfJvIy9GnSH2Qr/f4o0Sfg98Y3r0Gw9jrgLuUxPM3BUasYMgoYZtjqIdYrdGW5JaQv ELov/q9HgVcR9Z6MWxnySUUYVCya80bDUVwDfgvDB2t3PHqTjtPjDrqXPwTFccGTqJQg pETXzUgWyhlmh7LZ5pj1Y4bd/JcXK1mJWl/2QQU0NJN+4GWcYA741u5aiqXBITOrdR0c kY8w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@pqrs.dk header.s=google header.b=OlAcPWgL; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from morse.vger.email (morse.vger.email. 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It can be used to specify whether or not the PLL should be reset after adjustment. Resetting is known to cause glitches. For compatibility with older device trees, it must be assumed that the default PLL reset mode is to unconditionally reset after adjustment. Cc: Sebastian Hesselbarth Cc: Rabeeh Khoury Cc: Jacob Siverskog Cc: Sergej Sawazki Signed-off-by: Alvin Šipraga Reviewed-by: Rob Herring --- .../devicetree/bindings/clock/silabs,si5351.yaml | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/silabs,si5351.yaml b/Documentation/devicetree/bindings/clock/silabs,si5351.yaml index 494fa49a0c1b..d3e0ec29993b 100644 --- a/Documentation/devicetree/bindings/clock/silabs,si5351.yaml +++ b/Documentation/devicetree/bindings/clock/silabs,si5351.yaml @@ -62,6 +62,27 @@ properties: - description: PLL source, XTAL (0) or CLKIN (1, Si5351C only). enum: [ 0, 1 ] + silabs,pll-reset-mode: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + minItems: 1 + maxItems: 2 + description: A list of cell pairs containing a PLL index and its reset mode. + items: + items: + - description: PLL A (0) or PLL B (1) + enum: [ 0, 1 ] + - description: | + Reset mode for the PLL. Mode can be one of: + + 0 - reset whenever PLL rate is adjusted (default mode) + 1 - do not reset when PLL rate is adjusted + + In mode 1, the PLL is only reset if the silabs,pll-reset is + specified in one of the clock output child nodes that also sources + the PLL. This mode may be preferable if output clocks are expected + to be adjusted without glitches. + enum: [ 0, 1 ] + patternProperties: "^clkout@[0-7]$": type: object @@ -195,6 +216,9 @@ examples: /* Use XTAL input as source of PLL0 and PLL1 */ silabs,pll-source = <0 0>, <1 0>; + /* Don't reset PLL1 on rate adjustment */ + silabs,pll-reset-mode = <1 1>; + /* * Overwrite CLK0 configuration with: * - 8 mA output drive strength From patchwork Fri Oct 20 11:34:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alvin_=C5=A0ipraga?= X-Patchwork-Id: 156016 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2010:b0:403:3b70:6f57 with SMTP id fe16csp988733vqb; Fri, 20 Oct 2023 04:34:39 -0700 (PDT) X-Google-Smtp-Source: AGHT+IER6l+Xszcm7TtZg9vFsuxSbf9GGo/gmgYFLz7SCPD81OpXZT7y2/v+HjIWkXrH6XDbE3+Z X-Received: by 2002:a05:6358:91a:b0:14b:86a3:b3f0 with SMTP id r26-20020a056358091a00b0014b86a3b3f0mr1750778rwi.5.1697801679374; Fri, 20 Oct 2023 04:34:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697801679; cv=none; d=google.com; s=arc-20160816; b=Z2jpVnfUMgsBekrBrD1oqT1MnPaPSg8sRFrA5aMA9TuZFSZm3+dYc6cI+eDKoF4Vdp AMXxcvZqHzdoa1UJUwVKMA7Y7/QDUcesNS2F8Xb8NcTa1v2f04QYKn2LNQH4ibeqE8dD wHwC1cBr7JDP7ZqC5D9CBMUFfBdsJrp+2CstNndRxlsLXr1U4gfXA1XbG0gd3hDtsYww N1TSSz1UXNag8HeUtzbgStxtUhL/ymEeTxSmOZNop+aOXTnD3xTDngJgIvI3tQJUSpy0 yUT7EpTuO2oeIXOi1QSt2vktHNWC6LT38irUKJSEaOCzRRhfqDoXrGnokKUrLStynEbF tXyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=fXvJpV0gpvSkUrAaGppJnbjeNlJABP+T2f/Ne1XnKTw=; fh=cmShaaKDM89fu74c5NvQ6BtZelLx90jo5mGjUZMX0tM=; b=twtp6/XWKWf2ZkRb10+wki1Ij29p43o1l3JWTugPDAMhq1MSqmUjWWsFlA/KKwYd7j 8iMfx0PBuvUu7IOXXIpJum0SwKlsv1Nse6CLxZ2cxICsvYstgsDx1SC0nS/pzvc0KBaZ hiJFVnRZhe3glnWFfy6Fx1ZC2+z7+xiZ+6YSaj5NhIwdVuOIGsLiVpl585TwEmHnBEFU qaRuZjHqFwSt7ccU/4iy35i7y3BrZPcUkA6wrJ6CvnT7A1ZNK+T+JxCCtL96/YqFbuax W0PDo0z1hUZQein5fo9RktHZPyxw/wfRWZIkbr7ve7NfFDipjqvhv5tS+BiowovktE0z i52g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@pqrs.dk header.s=google header.b=QkYBgQhm; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from snail.vger.email (snail.vger.email. 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The mode can be configured through platform data or device tree. Since commit 6dc669a22c77 ("clk: si5351: Add PLL soft reset"), the driver unconditionally resets a PLL whenever its rate is adjusted. The rationale was that a PLL reset was required to get three outputs working at the same time. Before this change, the driver never reset the PLLs. Commit b26ff127c52c ("clk: si5351: Apply PLL soft reset before enabling the outputs") subsequently introduced an option to reset the PLL when enabling a clock output that sourced it. Here, the rationale was that this is required to get a deterministic phase relationship between multiple output clocks. This clearly shows that it is useful to reset the PLLs in applications where multiple clock outputs are used. However, the Si5351 also allows for glitch-free rate adjustment of its PLLs if one avoids resetting the PLL. In our audio application where a single Si5351 clock output is used to supply a runtime adjustable bit clock, this unconditional PLL reset behaviour introduces unwanted glitches in the clock output. It would appear that the problem being solved in the former commit may be solved by using the optional device tree property introduced in the latter commit, obviating the need for an unconditional PLL reset after rate adjustment. But it's not OK to break the default behaviour of the driver, and it cannot be assumed that all device trees are using the property introduced in the latter commit. Hence, the new behaviour is made opt-in. Cc: Sebastian Hesselbarth Cc: Rabeeh Khoury Cc: Jacob Siverskog Cc: Sergej Sawazki Signed-off-by: Alvin Šipraga Acked-by: Sebastian Hesselbarth --- drivers/clk/clk-si5351.c | 47 +++++++++++++++++++++++++++++++++--- include/linux/platform_data/si5351.h | 2 ++ 2 files changed, 46 insertions(+), 3 deletions(-) diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c index cbf7cde01157..bed0fe3bfa08 100644 --- a/drivers/clk/clk-si5351.c +++ b/drivers/clk/clk-si5351.c @@ -506,6 +506,8 @@ static int si5351_pll_set_rate(struct clk_hw *hw, unsigned long rate, { struct si5351_hw_data *hwdata = container_of(hw, struct si5351_hw_data, hw); + struct si5351_platform_data *pdata = + hwdata->drvdata->client->dev.platform_data; u8 reg = (hwdata->num == 0) ? SI5351_PLLA_PARAMETERS : SI5351_PLLB_PARAMETERS; @@ -518,9 +520,10 @@ static int si5351_pll_set_rate(struct clk_hw *hw, unsigned long rate, (hwdata->params.p2 == 0) ? SI5351_CLK_INTEGER_MODE : 0); /* Do a pll soft reset on the affected pll */ - si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET, - hwdata->num == 0 ? SI5351_PLL_RESET_A : - SI5351_PLL_RESET_B); + if (pdata->pll_reset[hwdata->num]) + si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET, + hwdata->num == 0 ? SI5351_PLL_RESET_A : + SI5351_PLL_RESET_B); dev_dbg(&hwdata->drvdata->client->dev, "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n", @@ -1222,6 +1225,44 @@ static int si5351_dt_parse(struct i2c_client *client, } } + /* + * Parse PLL reset mode. For compatibility with older device trees, the + * default is to always reset a PLL after setting its rate. + */ + pdata->pll_reset[0] = true; + pdata->pll_reset[1] = true; + + of_property_for_each_u32(np, "silabs,pll-reset-mode", prop, p, num) { + if (num >= 2) { + dev_err(&client->dev, + "invalid pll %d on pll-reset-mode prop\n", num); + return -EINVAL; + } + + p = of_prop_next_u32(prop, p, &val); + if (!p) { + dev_err(&client->dev, + "missing pll-reset-mode for pll %d\n", num); + return -EINVAL; + } + + switch (val) { + case 0: + /* Reset PLL whenever its rate is adjusted */ + pdata->pll_reset[num] = true; + break; + case 1: + /* Don't reset PLL whenever its rate is adjusted */ + pdata->pll_reset[num] = false; + break; + default: + dev_err(&client->dev, + "invalid pll-reset-mode %d for pll %d\n", val, + num); + return -EINVAL; + } + } + /* per clkout properties */ for_each_child_of_node(np, child) { if (of_property_read_u32(child, "reg", &num)) { diff --git a/include/linux/platform_data/si5351.h b/include/linux/platform_data/si5351.h index c71a2dd66143..5f412a615532 100644 --- a/include/linux/platform_data/si5351.h +++ b/include/linux/platform_data/si5351.h @@ -105,10 +105,12 @@ struct si5351_clkout_config { * @clk_xtal: xtal input clock * @clk_clkin: clkin input clock * @pll_src: array of pll source clock setting + * @pll_reset: array indicating if plls should be reset after setting the rate * @clkout: array of clkout configuration */ struct si5351_platform_data { enum si5351_pll_src pll_src[2]; + bool pll_reset[2]; struct si5351_clkout_config clkout[8]; };