From patchwork Fri Oct 20 10:37:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Qiu X-Patchwork-Id: 155975 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2010:b0:403:3b70:6f57 with SMTP id fe16csp960649vqb; Fri, 20 Oct 2023 03:38:25 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGppcyAjB7/yr4x8XsbzfuuWqjw5/wsvcWrYa7oqsd7vhUMFRlM0kVzpR8KM36CInXzkfpO X-Received: by 2002:a17:90a:ba15:b0:27d:1a75:5b98 with SMTP id s21-20020a17090aba1500b0027d1a755b98mr6946496pjr.12.1697798305133; Fri, 20 Oct 2023 03:38:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697798305; cv=none; d=google.com; s=arc-20160816; b=itAj4ZLbVxHZ/XlRznaUQKP2YceAhadvxaAYKNUny1sp0y0m5B7Xp4kOZ/Kq+KV6mj NH67Re6cxPbtel9Zmhy1zOrmvNprbCJPhhVNp3JT5thacEDvgLYltbiy9tET8/9o0VvK hEa6gzKBY6LzgRO0is7eRWpAPqRPilTu+GviFB+T8poL0MYIzUSyn9R9IclU0UfShKdN 50dKcP+tBZGyo2LyfbufPj6RHiznECoctP6ohUhFZX09cY7zXFZjNwQ8CQelWvFnpfFa /CoZvYIq9b7ccaXsRteh+UbYu7m51o/JhKt1M+ZJcYOhgE8nCSQAWfQfs1ogg+p4ghQi eeNA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=4Dg2H2NE7Z8Go0tJV2Rj0PmKbQ3MMIvgTqq5HtUjzek=; fh=T4gzk7+hgrXGjSNvKGZTlbuKXCiuDaGkxvCBgfgONjs=; b=uYVWMpZWTM8WV892Xuk7h6d4cUWz128BJsawZVRzYc2aCc6Z46YXAeYjvgaQjFptCs /5xIVqGNVkW2uK6uBGJ7B3NU9nv91IGiN56lLu8NUkRiWSXvDoSO6iP7U037EkxjcRvj /nzCL/uk0DJ12Egui9LfNGEb352850AMPdFJayHbaqIZRlKtmwytz8HJPIfH4bxxpAdq UK82VzaMEjhfqa3mpfQW4P76z5Gjzkr502GT8W3nxARXH9SH3aYM5bvATbJ9UlrgYGdh oymmdevUFTR9zeB90TJsEdxriS0cMOcnul13nsXyT16Y9687DcJI3MtyFC2K02GwTdEL QMXg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from lipwig.vger.email (lipwig.vger.email. [23.128.96.33]) by mx.google.com with ESMTPS id my18-20020a17090b4c9200b002774d978e19si1740969pjb.175.2023.10.20.03.38.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 03:38:25 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) client-ip=23.128.96.33; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id 8FF6882A3F43; Fri, 20 Oct 2023 03:38:22 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376930AbjJTKhu convert rfc822-to-8bit (ORCPT + 25 others); Fri, 20 Oct 2023 06:37:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34718 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1376775AbjJTKht (ORCPT ); Fri, 20 Oct 2023 06:37:49 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 479EED5A; Fri, 20 Oct 2023 03:37:46 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 92D2224E13F; Fri, 20 Oct 2023 18:37:44 +0800 (CST) Received: from EXMBX168.cuchost.com (172.16.6.78) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 20 Oct 2023 18:37:44 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX168.cuchost.com (172.16.6.78) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 20 Oct 2023 18:37:43 +0800 From: William Qiu To: , , , CC: Emil Renner Berthing , Rob Herring , Thierry Reding , Philipp Zabel , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , "Hal Feng" , Paul Walmsley , Palmer Dabbelt , Albert Ou , William Qiu Subject: [PATCH v6 1/4] dt-bindings: pwm: Add OpenCores PWM module Date: Fri, 20 Oct 2023 18:37:38 +0800 Message-ID: <20231020103741.557735-2-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020103741.557735-1-william.qiu@starfivetech.com> References: <20231020103741.557735-1-william.qiu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX168.cuchost.com (172.16.6.78) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Fri, 20 Oct 2023 03:38:22 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780270555458899487 X-GMAIL-MSGID: 1780270555458899487 Add documentation to describe OpenCores Pulse Width Modulation controller driver. Signed-off-by: William Qiu Reviewed-by: Krzysztof Kozlowski Reviewed-by: Hal Feng --- .../bindings/pwm/opencores,pwm-ocores.yaml | 53 +++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 Documentation/devicetree/bindings/pwm/opencores,pwm-ocores.yaml diff --git a/Documentation/devicetree/bindings/pwm/opencores,pwm-ocores.yaml b/Documentation/devicetree/bindings/pwm/opencores,pwm-ocores.yaml new file mode 100644 index 000000000000..0f6a3434f155 --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/opencores,pwm-ocores.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/opencores,pwm-ocores.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: OpenCores PWM controller + +maintainers: + - William Qiu + +description: + OpenCores PTC ip core contains a PWM controller. When operating in PWM mode, the PTC core + generates binary signal with user-programmable low and high periods. All PTC counters and + registers are 32-bit. + +allOf: + - $ref: pwm.yaml# + +properties: + compatible: + enum: + - opencores,pwm-ocores + - starfive,jh71x0-pwm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + "#pwm-cells": + const: 3 + +required: + - compatible + - reg + - clocks + +additionalProperties: false + +examples: + - | + pwm@12490000 { + compatible = "opencores,pwm-ocores"; + reg = <0x12490000 0x10000>; + clocks = <&clkgen 181>; + resets = <&rstgen 109>; + #pwm-cells = <3>; + }; From patchwork Fri Oct 20 10:37:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Qiu X-Patchwork-Id: 155976 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2010:b0:403:3b70:6f57 with SMTP id fe16csp960689vqb; Fri, 20 Oct 2023 03:38:31 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHVVsw5ASuYs7SCRREzREBfAVBJzp+fE5tJTc/NO8RXo/UzibcjbhumM0XHoP+PtJRL2RET X-Received: by 2002:a05:6358:528f:b0:166:dace:c5c with SMTP id g15-20020a056358528f00b00166dace0c5cmr1682789rwa.24.1697798311239; Fri, 20 Oct 2023 03:38:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697798311; cv=none; d=google.com; s=arc-20160816; b=DK40Q7YaRtPlOavzZTpQ5lrow4jv4sVOXqPfx4ssWhFLK62Vz42e5vY+lqkrFroU5b XRi6b2zTADcCrlJ2tRGFKgkxS3Sez/qEPHgfMG5hzMvF4I2rQ5IRrfTwSCoriqcWXjm9 6WRAqHuBjXNpOqme7R/Bs5qR7cyBhomHGmgXDT4SrR7nix5M0n4dpDvDQ/PQzbmKuA0b FD8IyJuhd7Ai5IRjbtB9l0Gslke2I3C7ebyYQnsTuHSFmnqdVfs7dS5L9amlyITf78SX hClx1FyN8WKxRc9PQs+lD1ISMLKTf0X2ZR6TqNPlZtHU/z/0R4azdGt7MHpXR6QIBGcJ 7HiA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=qkBMY8WiF4OszI4RCyrfPSIu/YKE4hdJmre++zGv4LM=; fh=T4gzk7+hgrXGjSNvKGZTlbuKXCiuDaGkxvCBgfgONjs=; b=vtoWgJFaYytQKT1S2tKOowoK+ZMoN5Dc/cBj9+l9awmIDVs09EooDLfgQUw2ex+cEv Uf5wue5w2a5BF6uIJCPpu75Hh4bCzfejwyqUXGwqATbFPuztcqgHJ1anmyU6qcuLyJZp DBNNd9cJHNDkXiGUgJGxCD4x9S14/NIUrS5FxjWsklXsjWEOv4K2LEb+jx9iXF0J+P2v jFAwvq8k8clzkuBeEkwOglTWDFHkMEpwfK5V1erb+x2cUO25kpcEGUrWU7YAmNgBv3A3 R6tzxx/p5YRX1mHhkbBmDuR+M0EmoXqCAkU7Q34Ul6QGUzaJXzjIGJAgWp5gUkomb/Zy Sm2w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from fry.vger.email (fry.vger.email. [2620:137:e000::3:8]) by mx.google.com with ESMTPS id i18-20020aa796f2000000b0068fd7cb5864si1584531pfq.263.2023.10.20.03.38.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 03:38:31 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) client-ip=2620:137:e000::3:8; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by fry.vger.email (Postfix) with ESMTP id 36A2E82D997D; Fri, 20 Oct 2023 03:38:28 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at fry.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376984AbjJTKh6 convert rfc822-to-8bit (ORCPT + 25 others); Fri, 20 Oct 2023 06:37:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34770 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1376932AbjJTKhu (ORCPT ); Fri, 20 Oct 2023 06:37:50 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 286EBD46; Fri, 20 Oct 2023 03:37:47 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 6BC9D24E346; Fri, 20 Oct 2023 18:37:45 +0800 (CST) Received: from EXMBX168.cuchost.com (172.16.6.78) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 20 Oct 2023 18:37:45 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX168.cuchost.com (172.16.6.78) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 20 Oct 2023 18:37:44 +0800 From: William Qiu To: , , , CC: Emil Renner Berthing , Rob Herring , Thierry Reding , Philipp Zabel , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , "Hal Feng" , Paul Walmsley , Palmer Dabbelt , Albert Ou , William Qiu Subject: [PATCH v6 2/4] pwm: opencores: Add PWM driver support Date: Fri, 20 Oct 2023 18:37:39 +0800 Message-ID: <20231020103741.557735-3-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020103741.557735-1-william.qiu@starfivetech.com> References: <20231020103741.557735-1-william.qiu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX168.cuchost.com (172.16.6.78) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Fri, 20 Oct 2023 03:38:28 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780270561741379636 X-GMAIL-MSGID: 1780270561741379636 Add Pulse Width Modulation driver support for OpenCores. Co-developed-by: Hal Feng Signed-off-by: Hal Feng Signed-off-by: William Qiu --- MAINTAINERS | 7 ++ drivers/pwm/Kconfig | 11 ++ drivers/pwm/Makefile | 1 + drivers/pwm/pwm-ocores.c | 211 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 230 insertions(+) create mode 100644 drivers/pwm/pwm-ocores.c diff --git a/MAINTAINERS b/MAINTAINERS index 6c4cce45a09d..321af8fa7aad 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -16003,6 +16003,13 @@ F: Documentation/i2c/busses/i2c-ocores.rst F: drivers/i2c/busses/i2c-ocores.c F: include/linux/platform_data/i2c-ocores.h +OPENCORES PWM DRIVER +M: William Qiu +M: Hal Feng +S: Supported +F: Documentation/devicetree/bindings/pwm/opencores,pwm-ocores.yaml +F: drivers/pwm/pwm-ocores.c + OPENRISC ARCHITECTURE M: Jonas Bonn M: Stefan Kristiansson diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 8ebcddf91f7b..cbfbf227d957 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -434,6 +434,17 @@ config PWM_NTXEC controller found in certain e-book readers designed by the original design manufacturer Netronix. +config PWM_OCORES + tristate "Opencores PWM support" + depends on HAS_IOMEM && OF + depends on COMMON_CLK && RESET_CONTROLLER + help + If you say yes to this option, support will be included for the + OpenCores PWM. For details see https://opencores.org/projects/ptc. + + To compile this driver as a module, choose M here: the module + will be called pwm-ocores. + config PWM_OMAP_DMTIMER tristate "OMAP Dual-Mode Timer PWM support" depends on OF diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index c822389c2a24..542b98202153 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -39,6 +39,7 @@ obj-$(CONFIG_PWM_MICROCHIP_CORE) += pwm-microchip-core.o obj-$(CONFIG_PWM_MTK_DISP) += pwm-mtk-disp.o obj-$(CONFIG_PWM_MXS) += pwm-mxs.o obj-$(CONFIG_PWM_NTXEC) += pwm-ntxec.o +obj-$(CONFIG_PWM_OCORES) += pwm-ocores.o obj-$(CONFIG_PWM_OMAP_DMTIMER) += pwm-omap-dmtimer.o obj-$(CONFIG_PWM_PCA9685) += pwm-pca9685.o obj-$(CONFIG_PWM_PXA) += pwm-pxa.o diff --git a/drivers/pwm/pwm-ocores.c b/drivers/pwm/pwm-ocores.c new file mode 100644 index 000000000000..7a510de4e063 --- /dev/null +++ b/drivers/pwm/pwm-ocores.c @@ -0,0 +1,211 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * OpenCores PWM Driver + * + * https://opencores.org/projects/ptc + * + * Copyright (C) 2018-2023 StarFive Technology Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define REG_OCPWM_CNTR(base) ((base)) +#define REG_OCPWM_HRC(base) ((base) + 0x4) +#define REG_OCPWM_LRC(base) ((base) + 0x8) +#define REG_OCPWM_CTRL(base) ((base) + 0xC) + +/* OCPWM_CTRL register bits*/ +#define OCPWM_EN BIT(0) +#define OCPWM_ECLK BIT(1) +#define OCPWM_NEC BIT(2) +#define OCPWM_OE BIT(3) +#define OCPWM_SIGNLE BIT(4) +#define OCPWM_INTE BIT(5) +#define OCPWM_INT BIT(6) +#define OCPWM_CNTRRST BIT(7) +#define OCPWM_CAPTE BIT(8) + +struct ocores_pwm_device { + struct pwm_chip chip; + struct clk *clk; + struct reset_control *rst; + const struct ocores_pwm_data *data; + void __iomem *regs; + u32 clk_rate; /* PWM APB clock frequency */ +}; + +struct ocores_pwm_data { + void __iomem *(*get_ch_base)(void __iomem *base, unsigned int channel); +}; + +static inline struct ocores_pwm_device * +chip_to_ocores(struct pwm_chip *chip) + +{ + return container_of(chip, struct ocores_pwm_device, chip); +} + +void __iomem *starfive_jh71x0_get_ch_base(void __iomem *base, + unsigned int channel) +{ + return base + (channel > 3 ? channel % 4 * 0x10 + (1 << 15) : channel * 0x10); +} + +static int ocores_pwm_get_state(struct pwm_chip *chip, + struct pwm_device *dev, + struct pwm_state *state) +{ + struct ocores_pwm_device *pwm = chip_to_ocores(chip); + void __iomem *base = pwm->data->get_ch_base ? + pwm->data->get_ch_base(pwm->regs, dev->hwpwm) : pwm->regs; + u32 period_data, duty_data, ctrl_data; + + period_data = readl(REG_OCPWM_LRC(base)); + duty_data = readl(REG_OCPWM_HRC(base)); + ctrl_data = readl(REG_OCPWM_CTRL(base)); + + state->period = DIV_ROUND_CLOSEST_ULL((u64)period_data * NSEC_PER_SEC, pwm->clk_rate); + state->duty_cycle = DIV_ROUND_CLOSEST_ULL((u64)duty_data * NSEC_PER_SEC, pwm->clk_rate); + state->polarity = PWM_POLARITY_INVERSED; + state->enabled = (ctrl_data & OCPWM_EN) ? true : false; + + return 0; +} + +static int ocores_pwm_apply(struct pwm_chip *chip, + struct pwm_device *dev, + const struct pwm_state *state) +{ + struct ocores_pwm_device *pwm = chip_to_ocores(chip); + void __iomem *base = pwm->data->get_ch_base ? + pwm->data->get_ch_base(pwm->regs, dev->hwpwm) : pwm->regs; + u32 period_data, duty_data, ctrl_data = 0; + + if (state->polarity != PWM_POLARITY_INVERSED) + return -EINVAL; + + period_data = DIV_ROUND_CLOSEST_ULL(state->period * pwm->clk_rate, + NSEC_PER_SEC); + duty_data = DIV_ROUND_CLOSEST_ULL(state->duty_cycle * pwm->clk_rate, + NSEC_PER_SEC); + + writel(period_data, REG_OCPWM_LRC(base)); + writel(duty_data, REG_OCPWM_HRC(base)); + writel(0, REG_OCPWM_CNTR(base)); + + ctrl_data = readl(REG_OCPWM_CTRL(base)); + if (state->enabled) + writel(ctrl_data | OCPWM_EN | OCPWM_OE, REG_OCPWM_CTRL(base)); + else + writel(ctrl_data & ~(OCPWM_EN | OCPWM_OE), REG_OCPWM_CTRL(base)); + + return 0; +} + +static const struct pwm_ops ocores_pwm_ops = { + .get_state = ocores_pwm_get_state, + .apply = ocores_pwm_apply, + .owner = THIS_MODULE, +}; + +static const struct ocores_pwm_data jh71x0_pwm_data = { + .get_ch_base = starfive_jh71x0_get_ch_base, +}; + +static const struct of_device_id ocores_pwm_of_match[] = { + { .compatible = "opencores,pwm-ocores" }, + { .compatible = "starfive,jh71x0-pwm", .data = &jh71x0_pwm_data}, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, ocores_pwm_of_match); + +static int ocores_pwm_probe(struct platform_device *pdev) +{ + const struct of_device_id *id; + struct device *dev = &pdev->dev; + struct ocores_pwm_device *pwm; + struct pwm_chip *chip; + int ret; + + id = of_match_device(ocores_pwm_of_match, dev); + if (!id) + return -EINVAL; + + pwm = devm_kzalloc(dev, sizeof(*pwm), GFP_KERNEL); + if (!pwm) + return -ENOMEM; + + pwm->data = id->data; + chip = &pwm->chip; + chip->dev = dev; + chip->ops = &ocores_pwm_ops; + chip->npwm = 8; + chip->of_pwm_n_cells = 3; + + pwm->regs = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pwm->regs)) + return dev_err_probe(dev, PTR_ERR(pwm->regs), + "Unable to map IO resources\n"); + + pwm->clk = devm_clk_get_enabled(dev, NULL); + if (IS_ERR(pwm->clk)) + return dev_err_probe(dev, PTR_ERR(pwm->clk), + "Unable to get pwm's clock\n"); + + pwm->rst = devm_reset_control_get_optional_exclusive(dev, NULL); + reset_control_deassert(pwm->rst); + + pwm->clk_rate = clk_get_rate(pwm->clk); + if (pwm->clk_rate <= 0) { + dev_warn(dev, "Failed to get APB clock rate\n"); + return -EINVAL; + } + + ret = devm_pwmchip_add(dev, chip); + if (ret < 0) { + dev_err(dev, "Cannot register PTC: %d\n", ret); + clk_disable_unprepare(pwm->clk); + reset_control_assert(pwm->rst); + return ret; + } + + platform_set_drvdata(pdev, pwm); + + return 0; +} + +static int ocores_pwm_remove(struct platform_device *dev) +{ + struct ocores_pwm_device *pwm = platform_get_drvdata(dev); + + reset_control_assert(pwm->rst); + clk_disable_unprepare(pwm->clk); + + return 0; +} + +static struct platform_driver ocores_pwm_driver = { + .probe = ocores_pwm_probe, + .remove = ocores_pwm_remove, + .driver = { + .name = "ocores-pwm", + .of_match_table = ocores_pwm_of_match, + }, +}; +module_platform_driver(ocores_pwm_driver); + +MODULE_AUTHOR("Jieqin Chen"); +MODULE_AUTHOR("Hal Feng "); +MODULE_DESCRIPTION("OpenCores PWM PTC driver"); +MODULE_LICENSE("GPL"); -- 2.34.1 From patchwork Fri Oct 20 10:37:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Qiu X-Patchwork-Id: 155973 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2010:b0:403:3b70:6f57 with SMTP id fe16csp960581vqb; Fri, 20 Oct 2023 03:38:13 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHouZzIcS2DQ/6UyeiIbnMoxsX71sYrAgOkWfGx2FiSH1ozo26vbR20ANsIdVL0TmoVe+EV X-Received: by 2002:a17:902:e80c:b0:1c9:e774:58d0 with SMTP id u12-20020a170902e80c00b001c9e77458d0mr1798119plg.34.1697798293162; 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[23.128.96.36]) by mx.google.com with ESMTPS id z18-20020a170903019200b001c5e0672f53si1636334plg.466.2023.10.20.03.38.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 03:38:13 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) client-ip=23.128.96.36; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by pete.vger.email (Postfix) with ESMTP id A230981A32B8; Fri, 20 Oct 2023 03:38:10 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at pete.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376955AbjJTKhv convert rfc822-to-8bit (ORCPT + 25 others); Fri, 20 Oct 2023 06:37:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34752 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1376842AbjJTKht (ORCPT ); Fri, 20 Oct 2023 06:37:49 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7C481D55; Fri, 20 Oct 2023 03:37:47 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 560D124E35A; Fri, 20 Oct 2023 18:37:46 +0800 (CST) Received: from EXMBX168.cuchost.com (172.16.6.78) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 20 Oct 2023 18:37:46 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX168.cuchost.com (172.16.6.78) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Fri, 20 Oct 2023 18:37:45 +0800 From: William Qiu To: , , , CC: Emil Renner Berthing , Rob Herring , Thierry Reding , Philipp Zabel , Krzysztof Kozlowski , Conor Dooley , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , "Hal Feng" , Paul Walmsley , Palmer Dabbelt , Albert Ou , William Qiu Subject: [PATCH v6 3/4] riscv: dts: starfive: jh7110: Add PWM node and pins configuration Date: Fri, 20 Oct 2023 18:37:40 +0800 Message-ID: <20231020103741.557735-4-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020103741.557735-1-william.qiu@starfivetech.com> References: <20231020103741.557735-1-william.qiu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS064.cuchost.com (172.16.6.24) To EXMBX168.cuchost.com (172.16.6.78) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Fri, 20 Oct 2023 03:38:10 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780270543274831689 X-GMAIL-MSGID: 1780270543274831689 Add OpenCores PWM controller node and add PWM pins configuration on VisionFive 2 board. Signed-off-by: William Qiu Reviewed-by: Hal Feng --- .../jh7110-starfive-visionfive-2.dtsi | 22 +++++++++++++++++++ arch/riscv/boot/dts/starfive/jh7110.dtsi | 9 ++++++++ 2 files changed, 31 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index 12ebe9792356..63d16a6a4e12 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -268,6 +268,12 @@ reserved-data@600000 { }; }; +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + &spi0 { pinctrl-names = "default"; pinctrl-0 = <&spi0_pins>; @@ -402,6 +408,22 @@ GPOEN_SYS_SDIO1_DATA3, }; }; + pwm_pins: pwm-0 { + pwm-pins { + pinmux = , + ; + bias-disable; + drive-strength = <12>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + spi0_pins: spi0-0 { mosi-pins { pinmux = ; + clocks = <&syscrg JH7110_SYSCLK_PWM_APB>; + resets = <&syscrg JH7110_SYSRST_PWM_APB>; + #pwm-cells = <3>; + status = "disabled"; + }; + sfctemp: temperature-sensor@120e0000 { compatible = "starfive,jh7110-temp"; reg = <0x0 0x120e0000 0x0 0x10000>; From patchwork Fri Oct 20 10:37:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Qiu X-Patchwork-Id: 155974 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2010:b0:403:3b70:6f57 with SMTP id fe16csp960618vqb; Fri, 20 Oct 2023 03:38:19 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGUx1bUhTG5birZY9fNAEFgey7pRymF/P4fVsxYFuY5n5utzmp1F5ECZwqBzyu02B8xd7Yt X-Received: by 2002:a05:6871:4f13:b0:1e9:8782:f948 with SMTP id zu19-20020a0568714f1300b001e98782f948mr1206085oab.58.1697798299646; Fri, 20 Oct 2023 03:38:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697798299; cv=none; d=google.com; s=arc-20160816; b=0ZPpReOy5dVsHDO61zfGanv9IWEOolA1BRvx0alTfQDmhpzKPnj2iV8efUCMZQYm+J SNiuQscojfzOH00E4+ZKsLC4SEBn6WuXHAsVoqukTXh69ZtZmoEo6/AwIlvCwdJkKvwa QtPtAaz3jxsyhG8FI3rKmQUdk+p1ULUDHy23FSar9PnLknjJxr7E88LhN+agLxYataxm 9ZAoMirGK68lAaegVSz/NxYGg8Za6PfkjJii6rQiX52Fx9iRZHT5dA0yZT7b3Iu7QTZl VUaQmyf1Fr6UVXPhgNhUnM7iCPoN0dgLO+YjR0iHvhUPi3Nu0KZOk+3Nuj8RtIwRpCSG P1Zw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=QmJ2fWlQ3bjI6T6QI0OOPjLwF1outNv2z3KoDzbiRg4=; fh=T4gzk7+hgrXGjSNvKGZTlbuKXCiuDaGkxvCBgfgONjs=; b=KNHnTUEsDkzF/mCabmLaJ0SN54xwNGvNfUfhOIwBVNuTH7yMNEQiT9qZxQJTLI8gef dPkFyvI7tpXuKOGpK+p8gZktdGKN7R5O/GDTaSfXNOZWpE80r+WJlkWv0m0UPhs5nz3O SatqUD2Kh/Vx8wPPXCn1bDsyPA72hClVvsjaUzAWSwVh/z0PKkTHMz57AvrW3pW0Mr7b ELv2kZZi1sB/+F+A3rbyCjoh4KgucXBVq7rfk34aeLPnpZ6uTUqd99PHXqHOC/0M0xXv ohtHTjReZ4nnbufsiK3iCieyyg+45kcJ4OetGGYE1jZPSBge7s/tjPHqjR68UTDRKSJV pDZQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from groat.vger.email (groat.vger.email. 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Signed-off-by: William Qiu Reviewed-by: Hal Feng --- .../boot/dts/starfive/jh7100-common.dtsi | 24 +++++++++++++++++++ arch/riscv/boot/dts/starfive/jh7100.dtsi | 9 +++++++ 2 files changed, 33 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi index b93ce351a90f..11876906cc05 100644 --- a/arch/riscv/boot/dts/starfive/jh7100-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100-common.dtsi @@ -84,6 +84,24 @@ GPO_I2C2_PAD_SDA_OEN, }; }; + pwm_pins: pwm-0 { + pwm-pins { + pinmux = , + ; + bias-disable; + drive-strength = <35>; + input-disable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + uart3_pins: uart3-0 { rx-pins { pinmux = ; }; +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + &uart3 { pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>; diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi index 35ab54fb235f..0bb9e2e5ae68 100644 --- a/arch/riscv/boot/dts/starfive/jh7100.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi @@ -274,6 +274,15 @@ watchdog@12480000 { <&rstgen JH7100_RSTN_WDT>; }; + pwm: pwm@12490000 { + compatible = "starfive,jh71x0-pwm"; + reg = <0x0 0x12490000 0x0 0x10000>; + clocks = <&clkgen JH7100_CLK_PWM_APB>; + resets = <&rstgen JH7100_RSTN_PWM_APB>; + #pwm-cells = <3>; + status = "disabled"; + }; + sfctemp: temperature-sensor@124a0000 { compatible = "starfive,jh7100-temp"; reg = <0x0 0x124a0000 0x0 0x10000>;