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[23.128.96.35]) by mx.google.com with ESMTPS id g19-20020a170902869300b001be025f8407si1190839plo.37.2023.10.20.00.22.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 00:22:20 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) client-ip=23.128.96.35; Authentication-Results: mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=cb8kwDbf; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by groat.vger.email (Postfix) with ESMTP id 2AA79826A058; Fri, 20 Oct 2023 00:22:15 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at groat.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376408AbjJTHV7 (ORCPT + 25 others); Fri, 20 Oct 2023 03:21:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41476 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1376403AbjJTHV4 (ORCPT ); Fri, 20 Oct 2023 03:21:56 -0400 Received: from mail-oi1-x22e.google.com (mail-oi1-x22e.google.com [IPv6:2607:f8b0:4864:20::22e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 468AB1A3 for ; Fri, 20 Oct 2023 00:21:55 -0700 (PDT) Received: by mail-oi1-x22e.google.com with SMTP id 5614622812f47-3af6bd48093so311529b6e.3 for ; Fri, 20 Oct 2023 00:21:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1697786514; x=1698391314; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vFjlFx01Ut+IIk7lMz+iwDuvVBUbWHCR3u/gBbk/FU0=; b=cb8kwDbfcMYKuSbeSM4vmK4dk5HzH6+UGU9Z4Cm9buYLbisAywChN7kMLnISn5KVCX 4iEg08DokJN7xvb1BkDT73ttxPDnbStGLtP/6xk0fZaF1syrUmO1QYmkRXv8jbLIqPGI 7g8Fv5F/gIwBBHj59qwC3zPpZC5m9kKpl6dNSQpenDmKNCFPLr0RMNrcAX4wXpCNBrvW eqk79GYyEO9VH4V8sC52dBFkZr60OL+mAUu7j9ytcxNFJF7NHpm9yIMJO7aiWPZwAHkv q45YENrxvOIK0hLlEQSOwLCkrqjqbKDiBokIL35OGLchAHkXvgTwUgqFi5BI9UU6NkIV 74UQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697786514; x=1698391314; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vFjlFx01Ut+IIk7lMz+iwDuvVBUbWHCR3u/gBbk/FU0=; b=G6rSjhstIF5YfzxecRE3Sos1QSO2reuOFKUHC4gb059JHQQPNnRjiS40j8e/yJNbnI 1kbkGMxYalOmWEdp0sfmiNxPXt7WnLxZzcszSrQc+9Z/F9RE8ccIVJTyRMfM8OzUORiW pdhj6Pc2USDD1T1GehEnHggbo0RkyosWOq0tjkMqYnz+DEakHJ3sEw3hg/O6l54mxMzC xVRFktMFuvqCbF7E/IrFr6wTmulMUAeEhHphAl1/U+wmRPSlm/I58NsdqVduyOQk/WI+ QOAtqwUdR/QdsbfgPCdE1bgS8l3URL0C6bQT9Mcvd3RgcxpJr2YaX1TMs3lA2vZYk3LY szgw== X-Gm-Message-State: AOJu0YzvCTxfenxNWSSOvZeSJ8oJXpqPZnqRLTa696N6EEnvCMFKBGHG 5A15LVLQpoNqyad+NTHuNNLS0Q== X-Received: by 2002:a05:6808:15a3:b0:3ad:ffa4:dfee with SMTP id t35-20020a05680815a300b003adffa4dfeemr1187937oiw.51.1697786514419; Fri, 20 Oct 2023 00:21:54 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.83.81]) by smtp.gmail.com with ESMTPSA id v12-20020a63f20c000000b005b32d6b4f2fsm828204pgh.81.2023.10.20.00.21.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 00:21:54 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Greg Kroah-Hartman , Jiri Slaby Cc: Conor Dooley , Andrew Jones , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v3 1/9] RISC-V: Add defines for SBI debug console extension Date: Fri, 20 Oct 2023 12:51:32 +0530 Message-Id: <20231020072140.900967-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020072140.900967-1-apatel@ventanamicro.com> References: <20231020072140.900967-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Fri, 20 Oct 2023 00:22:15 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780258219860243718 X-GMAIL-MSGID: 1780258219860243718 We add SBI debug console extension related defines/enum to the asm/sbi.h header. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- arch/riscv/include/asm/sbi.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 5b4a1bf5f439..12dfda6bb924 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -30,6 +30,7 @@ enum sbi_ext_id { SBI_EXT_HSM = 0x48534D, SBI_EXT_SRST = 0x53525354, SBI_EXT_PMU = 0x504D55, + SBI_EXT_DBCN = 0x4442434E, /* Experimentals extensions must lie within this range */ SBI_EXT_EXPERIMENTAL_START = 0x08000000, @@ -236,6 +237,12 @@ enum sbi_pmu_ctr_type { /* Flags defined for counter stop function */ #define SBI_PMU_STOP_FLAG_RESET (1 << 0) +enum sbi_ext_dbcn_fid { + SBI_EXT_DBCN_CONSOLE_WRITE = 0, + SBI_EXT_DBCN_CONSOLE_READ = 1, + SBI_EXT_DBCN_CONSOLE_WRITE_BYTE = 2, +}; + #define SBI_SPEC_VERSION_DEFAULT 0x1 #define SBI_SPEC_VERSION_MAJOR_SHIFT 24 #define SBI_SPEC_VERSION_MAJOR_MASK 0x7f From patchwork Fri Oct 20 07:21:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 155852 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2010:b0:403:3b70:6f57 with SMTP id fe16csp881268vqb; Fri, 20 Oct 2023 00:22:19 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFvCMrCyWNpwSLAZaU9s6zae+YLekneXfFswxoSWLrCm7dAykU9fMvnLfh30VsLAEDVn1nE X-Received: by 2002:a05:6a00:939a:b0:68a:586a:f62 with SMTP id ka26-20020a056a00939a00b0068a586a0f62mr1111847pfb.4.1697786538801; Fri, 20 Oct 2023 00:22:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697786538; cv=none; d=google.com; s=arc-20160816; b=uyooI3cJAx6Kk9xkUmRgHFG223+Cl7HieYkZ3jHvylBhzOVsdwJnchvPcCngluoGbE 5zz6HXYagaCTNW+jbSDfcncaFjTGAGBl4cZhS3MxmkJWI3zQb4J42mH/VQxIadmzZEJp eZFWVw9vnBIIFfhxZknOR6079pZSKeTcFU5eMWVlcLTTdMFF5jEqrjluYJNnYvdX/6lw YHox65Rne86aOgbS5idsGHFSADeTfEoVJrw75YUZ8W6z39egR+K8L7EAZEE6vbrcYAGm QUZmSWgHLE4MepwjJ2N1NndBDCsQUJ195JNyRa2BouNjWxyc0CFrpE0nqB8Q5o8SU+pu 5q0A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=eeCDV01Cfgp2ua0LgBWyAWr2dv9+xpkaYGG6VewjHJM=; fh=7GYORjoWw1oF4BCDuq40hd+MOEKRwzNqXwnZ/K2vS9Q=; b=PBte4aSKn5/I86cQbDN14D6kcns+Lgfk+Xd72sZ53aXy4El2gEYevc3gqY5C8Av28n 42dXAd99KMFwqXNLGAmVkbEB3d1Vy+f+35mDDKuf7pgj33z6eeN+xoq3RO8Cn6osNWwh 5x1EthrGEM1KF/MFI+KOtUpNfDpaAEDh7lGjE+lySqgUZBzO/DSagqXoksSToFq8MXB8 vkTPrk7jwd6yE40t3sYd1E4rExf0OB8euMv2vYINSppqzn+xAF421P6kDwBCxJRWfRHe p2HEd+F7nJlMseK4obYRIHbMmF4j43Cl3lUuNVHciQTKNwaPBR58nSQ++CbpRYAgzXNw LpvQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=YIVl7jqh; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from lipwig.vger.email (lipwig.vger.email. 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Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- arch/riscv/include/asm/kvm_vcpu_sbi.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm/kvm_vcpu_sbi.h index cdcf0ff07be7..8d6d4dce8a5e 100644 --- a/arch/riscv/include/asm/kvm_vcpu_sbi.h +++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h @@ -11,7 +11,7 @@ #define KVM_SBI_IMPID 3 -#define KVM_SBI_VERSION_MAJOR 1 +#define KVM_SBI_VERSION_MAJOR 2 #define KVM_SBI_VERSION_MINOR 0 enum kvm_riscv_sbi_ext_status { From patchwork Fri Oct 20 07:21:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 155854 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2010:b0:403:3b70:6f57 with SMTP id fe16csp881309vqb; Fri, 20 Oct 2023 00:22:25 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEPA0QxPXpTf7r/ABA1wlhD7KkzjtT9tYge7UfEshdMsDq7bvru6vFiFQcM7+XYc2tEkVz4 X-Received: by 2002:a17:90b:1204:b0:27c:eb59:e9c7 with SMTP id gl4-20020a17090b120400b0027ceb59e9c7mr1110392pjb.36.1697786545413; Fri, 20 Oct 2023 00:22:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697786545; cv=none; d=google.com; s=arc-20160816; b=i7BWVMkKYRgRNQi47lFSknp9HqAr/lQnGHGL4gf8JpmtJvuKlMLM3Mx5p8SIMdi/az Lea1TRCxjObgslzKni8vTYXZhoUnLQyEVTihQblaQUmsuW7Uz6UKdyG+AGbUy/X4/H4f 4xMuYNc1wzerQarebbpi5mK0XwTUimpy4Jll6b5iOgLHSOuk3a80UfM7Wk1YfZtxBDp9 GPw93rCQFtTrL7h4zX/HYWGff3XL3+amcQn9mrEu8K7IavqaZAD7ZgJkT8qmdH2xiEz4 5AfCVW1262zZ7SXe1RXtTlDS5sA3Dc651Mtr6xD0AwHoZCKi6TkgXX8JcQN3/AfO2uRV pq2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=m3zCDz3wNvDFZIfhQp3mdMMGRfliX9zzX2s9SoD5fk8=; fh=7GYORjoWw1oF4BCDuq40hd+MOEKRwzNqXwnZ/K2vS9Q=; b=KnH8ePYRefF2v1Uk+mJXQl5IolorW7PGSBRBOUReQF8A8b9H+FKV0N0Vp5gzqhNsxv wZWo5ZWmSzmBtzoIFCbfAr1p/r7Z2iRZ3LGxPT2NBAa1Gzr4DSjDsVsDBiegw0trDyFk xgfEx9ORBQVIFukS0l4ZUurX+32vaV4M2Qh/9c3DJcVNpCYdaaA0xougGT6uLAUlwcmm LqgG2wyGL+/gvpFmI4dfAaOVWzYs4nFRMR6OWPg5HV70Twm7MQNpUU7rA36irCsPwETy bXQrZ/OCELNGv3o7HbuDmZCeRVm6w+ibarNKSuZDlm28Cm6EUpWxJyUXdxkveGwZlStO 5s4w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=eWZlqXMT; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from agentk.vger.email (agentk.vger.email. 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Fri, 20 Oct 2023 00:22:03 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Greg Kroah-Hartman , Jiri Slaby Cc: Conor Dooley , Andrew Jones , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v3 3/9] RISC-V: KVM: Allow some SBI extensions to be disabled by default Date: Fri, 20 Oct 2023 12:51:34 +0530 Message-Id: <20231020072140.900967-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020072140.900967-1-apatel@ventanamicro.com> References: <20231020072140.900967-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Fri, 20 Oct 2023 00:22:23 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780258224393742138 X-GMAIL-MSGID: 1780258224393742138 Currently, all SBI extensions are enabled by default which is problematic for SBI extensions (such as DBCN) which are forwarded to the KVM user-space because we might have an older KVM user-space which is not aware/ready to handle newer SBI extensions. Ideally, the SBI extensions forwarded to the KVM user-space must be disabled by default. To address above, we allow certain SBI extensions to be disabled by default so that KVM user-space must explicitly enable such SBI extensions to receive forwarded calls from Guest VCPU. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- arch/riscv/include/asm/kvm_vcpu_sbi.h | 4 ++ arch/riscv/kvm/vcpu.c | 6 +++ arch/riscv/kvm/vcpu_sbi.c | 57 +++++++++++++-------------- 3 files changed, 38 insertions(+), 29 deletions(-) diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm/kvm_vcpu_sbi.h index 8d6d4dce8a5e..c02bda5559d7 100644 --- a/arch/riscv/include/asm/kvm_vcpu_sbi.h +++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h @@ -35,6 +35,9 @@ struct kvm_vcpu_sbi_return { struct kvm_vcpu_sbi_extension { unsigned long extid_start; unsigned long extid_end; + + bool default_unavail; + /** * SBI extension handler. It can be defined for a given extension or group of * extension. But it should always return linux error codes rather than SBI @@ -59,6 +62,7 @@ int kvm_riscv_vcpu_get_reg_sbi_ext(struct kvm_vcpu *vcpu, const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext( struct kvm_vcpu *vcpu, unsigned long extid); int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run); +void kvm_riscv_vcpu_sbi_init(struct kvm_vcpu *vcpu); #ifdef CONFIG_RISCV_SBI_V01 extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_v01; diff --git a/arch/riscv/kvm/vcpu.c b/arch/riscv/kvm/vcpu.c index c061a1c5fe98..e087c809073c 100644 --- a/arch/riscv/kvm/vcpu.c +++ b/arch/riscv/kvm/vcpu.c @@ -141,6 +141,12 @@ int kvm_arch_vcpu_create(struct kvm_vcpu *vcpu) if (rc) return rc; + /* + * Setup SBI extensions + * NOTE: This must be the last thing to be initialized. + */ + kvm_riscv_vcpu_sbi_init(vcpu); + /* Reset VCPU */ kvm_riscv_reset_vcpu(vcpu); diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c index 9cd97091c723..bda8b0b33343 100644 --- a/arch/riscv/kvm/vcpu_sbi.c +++ b/arch/riscv/kvm/vcpu_sbi.c @@ -155,14 +155,8 @@ static int riscv_vcpu_set_sbi_ext_single(struct kvm_vcpu *vcpu, if (!sext) return -ENOENT; - /* - * We can't set the extension status to available here, since it may - * have a probe() function which needs to confirm availability first, - * but it may be too early to call that here. We can set the status to - * unavailable, though. - */ - if (!reg_val) - scontext->ext_status[sext->ext_idx] = + scontext->ext_status[sext->ext_idx] = (reg_val) ? + KVM_RISCV_SBI_EXT_AVAILABLE : KVM_RISCV_SBI_EXT_UNAVAILABLE; return 0; @@ -188,16 +182,8 @@ static int riscv_vcpu_get_sbi_ext_single(struct kvm_vcpu *vcpu, if (!sext) return -ENOENT; - /* - * If the extension status is still uninitialized, then we should probe - * to determine if it's available, but it may be too early to do that - * here. The best we can do is report that the extension has not been - * disabled, i.e. we return 1 when the extension is available and also - * when it only may be available. - */ - *reg_val = scontext->ext_status[sext->ext_idx] != - KVM_RISCV_SBI_EXT_UNAVAILABLE; - + *reg_val = scontext->ext_status[sext->ext_idx] == + KVM_RISCV_SBI_EXT_AVAILABLE; return 0; } @@ -337,18 +323,8 @@ const struct kvm_vcpu_sbi_extension *kvm_vcpu_sbi_find_ext( scontext->ext_status[entry->ext_idx] == KVM_RISCV_SBI_EXT_AVAILABLE) return ext; - if (scontext->ext_status[entry->ext_idx] == - KVM_RISCV_SBI_EXT_UNAVAILABLE) - return NULL; - if (ext->probe && !ext->probe(vcpu)) { - scontext->ext_status[entry->ext_idx] = - KVM_RISCV_SBI_EXT_UNAVAILABLE; - return NULL; - } - scontext->ext_status[entry->ext_idx] = - KVM_RISCV_SBI_EXT_AVAILABLE; - return ext; + return NULL; } } @@ -419,3 +395,26 @@ int kvm_riscv_vcpu_sbi_ecall(struct kvm_vcpu *vcpu, struct kvm_run *run) return ret; } + +void kvm_riscv_vcpu_sbi_init(struct kvm_vcpu *vcpu) +{ + struct kvm_vcpu_sbi_context *scontext = &vcpu->arch.sbi_context; + const struct kvm_riscv_sbi_extension_entry *entry; + const struct kvm_vcpu_sbi_extension *ext; + int i; + + for (i = 0; i < ARRAY_SIZE(sbi_ext); i++) { + entry = &sbi_ext[i]; + ext = entry->ext_ptr; + + if (ext->probe && !ext->probe(vcpu)) { + scontext->ext_status[entry->ext_idx] = + KVM_RISCV_SBI_EXT_UNAVAILABLE; + continue; + } + + scontext->ext_status[entry->ext_idx] = ext->default_unavail ? + KVM_RISCV_SBI_EXT_UNAVAILABLE : + KVM_RISCV_SBI_EXT_AVAILABLE; + } +} From patchwork Fri Oct 20 07:21:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 155855 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2010:b0:403:3b70:6f57 with SMTP id fe16csp881464vqb; Fri, 20 Oct 2023 00:22:52 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGTeodyyPH0C0uKKNLH0IcLwCdOOh4aSDemNYYfiluKwPfqWaZex7r/CU5LEw5FVwtnUcG/ X-Received: by 2002:a05:6a21:3b4a:b0:14c:d494:77c3 with SMTP id zy10-20020a056a213b4a00b0014cd49477c3mr962462pzb.33.1697786571755; Fri, 20 Oct 2023 00:22:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697786571; cv=none; d=google.com; s=arc-20160816; b=lJCC7sJcbrYttbvlMsRhuq4pa+7T4JsmPOdZPKmy3WWavy+qy0jHxrRAxFppSkxGE/ F1el2vYVXOtLe/Pn6rx96UVZYu5RBi+PnTFdIT1vjAvdKg5nA+k8ibNOwvFWsjOiU3Pq stns5UsaSdTe8K/rdwR9vJI61ukXMRveh8JOgKzlMZUOAw/4efb09ZSid0weXpv1dYt4 Hy2d5w5LARtZffOtI+4XqhPWLJAGNzQCIV2L9dPk2NfIEBP/1lMc+IUcC/l9o3xDfUvS GOU9ma7x9HBP/X6t+G3x2tM9RpUn8BGfFaUa+G0fB1y7XhXG8zrOAP1YMgDmkMu3VA+B 86BQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=hO8QQxSKIIq22xFRYvu7Gu8eaqjv2hPcSOTMD/z9e94=; fh=7GYORjoWw1oF4BCDuq40hd+MOEKRwzNqXwnZ/K2vS9Q=; b=GaD5JFnEh1ii3rTncZDCW8BzxBxwtMjX41XS8UedneVVc/7xpXtWvps2Fczn32iQnl J2sgdqpHNv4ZuvEAXgN8hma0RMZmaBwG3lzC/jxtohIFyLtu2VLYcjGkMCn7+PP2Rnf7 uKE5eUpDBwDpSYbXL9FEhA8HOB6RRMIEDyksFtUiQApiQW4r5fH2aDuPKOh39QZgoHRA 7k9M/JEGnqstx6My6tb432mDqT0EGHDRZLTWTQrWGf6LxgGEZ76t6u+go4VqSFH9/Z6x VaBX0aJDyMP0Uq0F/r9cEJZWAS9GUSVtD4IPfcyocxI5Y2PnA6Fpxs8NGezEanWlqX2x s3Aw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=NF++K+IH; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from agentk.vger.email (agentk.vger.email. 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Fri, 20 Oct 2023 00:22:07 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Greg Kroah-Hartman , Jiri Slaby Cc: Conor Dooley , Andrew Jones , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v3 4/9] RISC-V: KVM: Forward SBI DBCN extension to user-space Date: Fri, 20 Oct 2023 12:51:35 +0530 Message-Id: <20231020072140.900967-5-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020072140.900967-1-apatel@ventanamicro.com> References: <20231020072140.900967-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Fri, 20 Oct 2023 00:22:29 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780258251916328942 X-GMAIL-MSGID: 1780258251916328942 The frozen SBI v2.0 specification defines the SBI debug console (DBCN) extension which replaces the legacy SBI v0.1 console functions namely sbi_console_getchar() and sbi_console_putchar(). The SBI DBCN extension needs to be emulated in the KVM user-space (i.e. QEMU-KVM or KVMTOOL) so we forward SBI DBCN calls from KVM guest to the KVM user-space which can then redirect the console input/output to wherever it wants (e.g. telnet, file, stdio, etc). The SBI debug console is simply a early console available to KVM guest for early prints and it does not intend to replace the proper console devices such as 8250, VirtIO console, etc. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- arch/riscv/include/asm/kvm_vcpu_sbi.h | 1 + arch/riscv/include/uapi/asm/kvm.h | 1 + arch/riscv/kvm/vcpu_sbi.c | 4 ++++ arch/riscv/kvm/vcpu_sbi_replace.c | 32 +++++++++++++++++++++++++++ 4 files changed, 38 insertions(+) diff --git a/arch/riscv/include/asm/kvm_vcpu_sbi.h b/arch/riscv/include/asm/kvm_vcpu_sbi.h index c02bda5559d7..6a453f7f8b56 100644 --- a/arch/riscv/include/asm/kvm_vcpu_sbi.h +++ b/arch/riscv/include/asm/kvm_vcpu_sbi.h @@ -73,6 +73,7 @@ extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_ipi; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_rfence; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_srst; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_hsm; +extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_dbcn; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_experimental; extern const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_vendor; diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h index 917d8cc2489e..60d3b21dead7 100644 --- a/arch/riscv/include/uapi/asm/kvm.h +++ b/arch/riscv/include/uapi/asm/kvm.h @@ -156,6 +156,7 @@ enum KVM_RISCV_SBI_EXT_ID { KVM_RISCV_SBI_EXT_PMU, KVM_RISCV_SBI_EXT_EXPERIMENTAL, KVM_RISCV_SBI_EXT_VENDOR, + KVM_RISCV_SBI_EXT_DBCN, KVM_RISCV_SBI_EXT_MAX, }; diff --git a/arch/riscv/kvm/vcpu_sbi.c b/arch/riscv/kvm/vcpu_sbi.c index bda8b0b33343..a04ff98085d9 100644 --- a/arch/riscv/kvm/vcpu_sbi.c +++ b/arch/riscv/kvm/vcpu_sbi.c @@ -66,6 +66,10 @@ static const struct kvm_riscv_sbi_extension_entry sbi_ext[] = { .ext_idx = KVM_RISCV_SBI_EXT_PMU, .ext_ptr = &vcpu_sbi_ext_pmu, }, + { + .ext_idx = KVM_RISCV_SBI_EXT_DBCN, + .ext_ptr = &vcpu_sbi_ext_dbcn, + }, { .ext_idx = KVM_RISCV_SBI_EXT_EXPERIMENTAL, .ext_ptr = &vcpu_sbi_ext_experimental, diff --git a/arch/riscv/kvm/vcpu_sbi_replace.c b/arch/riscv/kvm/vcpu_sbi_replace.c index 7c4d5d38a339..23b57c931b15 100644 --- a/arch/riscv/kvm/vcpu_sbi_replace.c +++ b/arch/riscv/kvm/vcpu_sbi_replace.c @@ -175,3 +175,35 @@ const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_srst = { .extid_end = SBI_EXT_SRST, .handler = kvm_sbi_ext_srst_handler, }; + +static int kvm_sbi_ext_dbcn_handler(struct kvm_vcpu *vcpu, + struct kvm_run *run, + struct kvm_vcpu_sbi_return *retdata) +{ + struct kvm_cpu_context *cp = &vcpu->arch.guest_context; + unsigned long funcid = cp->a6; + + switch (funcid) { + case SBI_EXT_DBCN_CONSOLE_WRITE: + case SBI_EXT_DBCN_CONSOLE_READ: + case SBI_EXT_DBCN_CONSOLE_WRITE_BYTE: + /* + * The SBI debug console functions are unconditionally + * forwarded to the userspace. + */ + kvm_riscv_vcpu_sbi_forward(vcpu, run); + retdata->uexit = true; + break; + default: + retdata->err_val = SBI_ERR_NOT_SUPPORTED; + } + + return 0; +} + +const struct kvm_vcpu_sbi_extension vcpu_sbi_ext_dbcn = { + .extid_start = SBI_EXT_DBCN, + .extid_end = SBI_EXT_DBCN, + .default_unavail = true, + .handler = kvm_sbi_ext_dbcn_handler, +}; From patchwork Fri Oct 20 07:21:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 155860 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2010:b0:403:3b70:6f57 with SMTP id fe16csp881712vqb; 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[2620:137:e000::3:1]) by mx.google.com with ESMTPS id mi18-20020a17090b4b5200b0027cf3fd376bsi4324291pjb.28.2023.10.20.00.23.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 00:23:35 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) client-ip=2620:137:e000::3:1; Authentication-Results: mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=EjP9DRi8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by morse.vger.email (Postfix) with ESMTP id 3AAA6809DE64; Fri, 20 Oct 2023 00:22:42 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at morse.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376448AbjJTHW3 (ORCPT + 25 others); Fri, 20 Oct 2023 03:22:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42140 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1376480AbjJTHWS (ORCPT ); Fri, 20 Oct 2023 03:22:18 -0400 Received: from mail-oi1-x22d.google.com (mail-oi1-x22d.google.com [IPv6:2607:f8b0:4864:20::22d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BAFC810EA for ; Fri, 20 Oct 2023 00:22:13 -0700 (PDT) Received: by mail-oi1-x22d.google.com with SMTP id 5614622812f47-3b3e13fc1f7so391941b6e.0 for ; Fri, 20 Oct 2023 00:22:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1697786533; x=1698391333; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7XKdexmGCdd2bnnrJTDfux86dDbyR62+1G32W+zioUE=; b=EjP9DRi80NBbQp34j86KtekV/1R8/ysD99DAJ1ahh1zuXn2EF6ZDCA+xF7G2qde/8e Q3xE/3ma96e0D08dCGGxxHeLN46I3BjRv/7v7mUdlyp90j2QNttZ9+/JCndp9lzL+45H VRM+JLD0tu6p1g5qQotPFfJEuLQq9CCGbX2mgv/kdZ0ibWUSE+Jx5haQM73rEOcrHe+Y pG/FNIBmWaUstQzVw8KuSa0sdrUpIGNP8Nh+6nX5YOqi3ZeK4HuXhu/iLeGLDK6u9xLo W7iLlPWZNnVnseCacK4+5vrgBLZmKZ5S/iuLqQ+XcLWhK5olpyJ+FJ614Al3f1K/HSi8 s50Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697786533; x=1698391333; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7XKdexmGCdd2bnnrJTDfux86dDbyR62+1G32W+zioUE=; b=EdPxtClp/qbztt5MfefeYQdk5xg2wZRfkzod2g/pXknolnV7GCk4EP75goO+tTikbc CzcLvNfp06zWCb9a2ETrNODLJVlEYbGxNQ/XUMdRQEz4lbwbq7s0PKExU+ynH6HK8M2Y R7BFsbZr40bza1sAq+veaOawdi3RP+aorTNJjNfsEq2aoJD6GQpunynW9qVJdPSkiRFS Q8JJlZxSB6rP0Cd4Nfu5z50FuYOe8WAZA/oSSEDu5+fi6cQBEiG4GrBl0ASJNlLPUdJO Ndh5GTax4Dqd6KWdw8gHMEy2yAPVGRo9e4mk2ZjWM40yhM9EJu8XZIDHLnLQPdii1ece DQUQ== X-Gm-Message-State: AOJu0YxQT1k+c5Wb3+rHpQeXAfOcMVjcEoDS0wsHXQuoXx6AMFGVEl2K zqNlhUl9zVZGivJOP5HWd/kjiA== X-Received: by 2002:a05:6808:144d:b0:3b2:dcff:9e54 with SMTP id x13-20020a056808144d00b003b2dcff9e54mr1358519oiv.24.1697786532716; Fri, 20 Oct 2023 00:22:12 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.83.81]) by smtp.gmail.com with ESMTPSA id v12-20020a63f20c000000b005b32d6b4f2fsm828204pgh.81.2023.10.20.00.22.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 00:22:12 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Greg Kroah-Hartman , Jiri Slaby Cc: Conor Dooley , Andrew Jones , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v3 5/9] KVM: riscv: selftests: Add SBI DBCN extension to get-reg-list test Date: Fri, 20 Oct 2023 12:51:36 +0530 Message-Id: <20231020072140.900967-6-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020072140.900967-1-apatel@ventanamicro.com> References: <20231020072140.900967-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.1 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,UPPERCASE_50_75 autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Fri, 20 Oct 2023 00:22:42 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780258297815576443 X-GMAIL-MSGID: 1780258297815576443 We have a new SBI debug console (DBCN) extension supported by in-kernel KVM so let us add this extension to get-reg-list test. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- tools/testing/selftests/kvm/riscv/get-reg-list.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c index 234006d035c9..6bedaea95395 100644 --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c @@ -394,6 +394,7 @@ static const char *sbi_ext_single_id_to_str(__u64 reg_off) KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_PMU), KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_EXPERIMENTAL), KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_VENDOR), + KVM_SBI_EXT_ARR(KVM_RISCV_SBI_EXT_DBCN), }; if (reg_off >= ARRAY_SIZE(kvm_sbi_ext_reg_name)) @@ -567,6 +568,7 @@ static __u64 base_regs[] = { KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_PMU, KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_EXPERIMENTAL, KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_VENDOR, + KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_SINGLE | KVM_RISCV_SBI_EXT_DBCN, KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_MULTI_EN | 0, KVM_REG_RISCV | KVM_REG_SIZE_ULONG | KVM_REG_RISCV_SBI_EXT | KVM_REG_RISCV_SBI_MULTI_DIS | 0, }; From patchwork Fri Oct 20 07:21:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 155857 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2010:b0:403:3b70:6f57 with SMTP id fe16csp881633vqb; Fri, 20 Oct 2023 00:23:18 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFbiORmmglVCNfKxMdi71FU2Rp6tGU5clvba58w4/erpSmr+MlhbdkLBhcFEEr1w25XdPnP X-Received: by 2002:a17:90b:288e:b0:27d:7f1b:1bec with SMTP id qc14-20020a17090b288e00b0027d7f1b1becmr1017615pjb.35.1697786598457; Fri, 20 Oct 2023 00:23:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697786598; cv=none; d=google.com; s=arc-20160816; b=yseGftm7OxdkAn9nTAaBVhO6f9nvX2AeXzRdEr88yfN8ao9VzY4pRX0pVtKakqpimD d8WSS2ukTrMhrn2EwjrQahLSSdmKd62sxJFQ/K8iMOJuiDXM5NDb8DcJXe5N8pgP/86b kTt2vyWOuEum/n0Hye+xUuX5MK9gbCb1/qKVSbWo2SzDGx0EOCsbAALoDZy8Nvz60sfD 3StCnEL+wWYijFJnTUE89gusSJtueCKaKYgGvplOc7DgxG+5w0B8wCyRsdps7vtQvpo1 lPyk/5+j100Zt1oC/rOTdstZIT5dL14HzZuxhcMDsZm/0Z2ziNpCkOQVA3YVozKz1251 tlMQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=MwlyMPcz0zqeFoKpmeSvnyAhcAgahoPS/k2EPhyd9Ww=; fh=7GYORjoWw1oF4BCDuq40hd+MOEKRwzNqXwnZ/K2vS9Q=; b=UZlLA0B94WzEbIO8wkYZAL0Go6psQ+LfsgLSQzjmxUXP8YUV48g9pvUlEQ0stkQL2S SEmW9foaw2FL8ySb5LMTNDyGnjzBQU8YZU1oT6YF2Dd4pAhaGNb0aEGZHAL50IBGq30g 01L1FJrYg/9vF+BNXyECfuTp3VLw4J2tpODH2jUYNJnDPooxDGQhtrY9YlURC2Z3FvB1 npB/h+/ejcOSJkeGIkg8+XjfKBbaPC9mxigu0tOS1XIiEZxV6y5xqgLN/xV6QL0w5u/W /VjZvQY7hE3lS8xkr+jx1DBtmxMi08JDn4wuKWjEN09vYJrWnQjPor9NYQGGnvu/DTYU TnyQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=JvsWy9tI; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from fry.vger.email (fry.vger.email. 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Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- arch/riscv/include/asm/sbi.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index 12dfda6bb924..cbcefa344417 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -271,8 +271,13 @@ struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, unsigned long arg3, unsigned long arg4, unsigned long arg5); +#ifdef CONFIG_RISCV_SBI_V01 void sbi_console_putchar(int ch); int sbi_console_getchar(void); +#else +static inline void sbi_console_putchar(int ch) { } +static inline int sbi_console_getchar(void) { return -1; } +#endif long sbi_get_mvendorid(void); long sbi_get_marchid(void); long sbi_get_mimpid(void); From patchwork Fri Oct 20 07:21:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 155856 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2010:b0:403:3b70:6f57 with SMTP id fe16csp881562vqb; Fri, 20 Oct 2023 00:23:08 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGQaDrD6ddoItY7NYwzcY+++cJxI2Y+E3c2WEYjHiAmuRTXu6mD8mifOkJjgsG3RYYrz+xf X-Received: by 2002:a05:6830:3145:b0:6bd:b879:c313 with SMTP id c5-20020a056830314500b006bdb879c313mr1439900ots.10.1697786588582; Fri, 20 Oct 2023 00:23:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697786588; cv=none; d=google.com; s=arc-20160816; b=kLqxOFlmiYMscjOwWbYTuf75+00Zcq4JEoGwamqpyKZvGN6dW7kZ2OdMYaILVSn6kK A92rOG4xnkd8QXtpDQfiuZaqZEiNVvKUr+BT0hGbRuagCnFE8AJBP41/2vSLxU0N6JzB 4CGgCm5jaFxGiNTqh0HH+gDtbvOyi2UpPLPk25w351pt7zUbU9ks4vA48aUTm3HAtKqQ hnJbAiXgn9Fj5jFHZhEkM32xuaIq2vkf81RddyjFWGuHDRQo0mys59TndWMuj1x14yJi Fu3TFgiqTBEsGzO7KZ2VZfV9tkLHrwxl1l7ahH6bllHWsFqTThPjC3NVU4xaGknRduiB mNhA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=y40VDpa5tFn1F2iuJCGX0eAdf56bF4H2v7CDU5J7JlM=; fh=7GYORjoWw1oF4BCDuq40hd+MOEKRwzNqXwnZ/K2vS9Q=; b=ssVQP/3teGx/TVwrnuDNSjhYyCQFsZYThPyWDZGHg2HMVYPpo1T7uRW0nRJnYIxyJY ooMsqouFN5eVUSkxtCLPijyInHTIZIAp2qtdaBH6p+nQ4I9cs0niE4dHs9HU2vN9ZVkx H4Hq48vwH+S8Z8RCr6gHTxnvZzFgerGTcIuQK2S7LJWTJxz5MvFBpCyRgUoMFG7goLRJ Kml4xK8Qg09IrSs9UG7cgO3mslhztWXGogyBpeE/gfFKZYPm1uJflM8ZINlrS1XbLJ1o ck9KoV0DubRE2U0eYCqQ5pJpkL96KgRtJFmSlM/JvdsjyXlCotNpGjE9f4D5mgvyh5vQ CIzw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b="Y/dSv7M8"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from agentk.vger.email (agentk.vger.email. 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Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- drivers/tty/serial/Kconfig | 2 +- drivers/tty/serial/earlycon-riscv-sbi.c | 32 +++++++++++++++++++++---- 2 files changed, 29 insertions(+), 5 deletions(-) diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index bdc568a4ab66..cec46091a716 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -87,7 +87,7 @@ config SERIAL_EARLYCON_SEMIHOST config SERIAL_EARLYCON_RISCV_SBI bool "Early console using RISC-V SBI" - depends on RISCV_SBI_V01 + depends on RISCV_SBI select SERIAL_CORE select SERIAL_CORE_CONSOLE select SERIAL_EARLYCON diff --git a/drivers/tty/serial/earlycon-riscv-sbi.c b/drivers/tty/serial/earlycon-riscv-sbi.c index 27afb0b74ea7..c21cdef254e7 100644 --- a/drivers/tty/serial/earlycon-riscv-sbi.c +++ b/drivers/tty/serial/earlycon-riscv-sbi.c @@ -15,17 +15,41 @@ static void sbi_putc(struct uart_port *port, unsigned char c) sbi_console_putchar(c); } -static void sbi_console_write(struct console *con, - const char *s, unsigned n) +static void sbi_0_1_console_write(struct console *con, + const char *s, unsigned int n) { struct earlycon_device *dev = con->data; uart_console_write(&dev->port, s, n, sbi_putc); } +static void sbi_dbcn_console_write(struct console *con, + const char *s, unsigned int n) +{ + phys_addr_t pa = __pa(s); + + if (IS_ENABLED(CONFIG_32BIT)) + sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE, + n, lower_32_bits(pa), upper_32_bits(pa), 0, 0, 0); + else + sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE, + n, pa, 0, 0, 0, 0); +} + static int __init early_sbi_setup(struct earlycon_device *device, const char *opt) { - device->con->write = sbi_console_write; - return 0; + int ret = 0; + + if ((sbi_spec_version >= sbi_mk_version(2, 0)) && + (sbi_probe_extension(SBI_EXT_DBCN) > 0)) { + device->con->write = sbi_dbcn_console_write; + } else { + if (IS_ENABLED(CONFIG_RISCV_SBI_V01)) + device->con->write = sbi_0_1_console_write; + else + ret = -ENODEV; + } + + return ret; } EARLYCON_DECLARE(sbi, early_sbi_setup); From patchwork Fri Oct 20 07:21:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 155861 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2010:b0:403:3b70:6f57 with SMTP id fe16csp881725vqb; Fri, 20 Oct 2023 00:23:38 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEscwNZXdtJN0hPKKMISAB/FBx7RVZBIIH3CJ7W9EDZDvotKL0dcsFG29/pgaxdCIiivP0I X-Received: by 2002:a05:6808:f13:b0:3ae:126b:8c2b with SMTP id m19-20020a0568080f1300b003ae126b8c2bmr1245112oiw.30.1697786618121; Fri, 20 Oct 2023 00:23:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697786618; cv=none; d=google.com; s=arc-20160816; b=VGT7TVsHINYHsJZySfO59UvFf6+8mFWud/28te5CDvT66VPyQJkXT7/d8NI5WEk2/f UQHGvb4f8MwlVl7fBlhTaxZtsC/ree05VQ3jGsqyw7ddbukpqyNnuAJWHYQk/6TkZt3N MR4xUBoze+wmmhq3sD9R+bmne6fa6BYbTVTJd0+z2ayN7yxOfF5gvZcigafW5zWeeYOr tOc75DG/VjjbaAXMHtXoEeVXfkpFpVt02gviUDAuIqfnfRNzueo777ToyEPS+oB6CcVV Jukc79sUWsz112ZRoelvtdN1elTJvPYykAQGTIf+hSHvyANSWYLMtJ8Gh2Ieq6Nwr7nK w8gg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=jRerAerNbb8Gix3xbbzThpKCfwsEd5HQVNj+VzWX/14=; fh=OfNDhWBTBAuUy+hoy8Y3XMW7PkzxeKRBsc+xFswuT9E=; b=novPHN+rxMtpvQQJpwq/Kka4U/NaOwNT4MqiVl3W0f6pI80UnxOYVJJcfxdMBqBGVm 4SU9oSsh0jT1z1NNYkMAJEYDSzQYuBqB4xHpyEobAEP8g9nvW0F35vmZD1XqCEto41Sh UjMrIogZHsPXUt5MHREIogBoTW+gwXlJfocS2nYNhHLR3EtF4pXD2YSH4XxpRlcKUB4u KeEOW2qSmD2EN6kxuW3rdssoM7M7bVNQFvvz6pAE1QhSVhVyo/tScmB/xOGKz3ksYrdz 1gc5jjzNrs3csPCOmZVP5xt0RTO63da6YqXEeG65OFOPMii5mde8JeAYPi45ks5Y/w6F sopA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=KjrGLpp1; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from morse.vger.email (morse.vger.email. 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Extend the HVC SBI driver to support it. Signed-off-by: Atish Patra Signed-off-by: Anup Patel --- drivers/tty/hvc/Kconfig | 2 +- drivers/tty/hvc/hvc_riscv_sbi.c | 82 ++++++++++++++++++++++++++++++--- 2 files changed, 76 insertions(+), 8 deletions(-) diff --git a/drivers/tty/hvc/Kconfig b/drivers/tty/hvc/Kconfig index 4f9264d005c0..6e05c5c7bca1 100644 --- a/drivers/tty/hvc/Kconfig +++ b/drivers/tty/hvc/Kconfig @@ -108,7 +108,7 @@ config HVC_DCC_SERIALIZE_SMP config HVC_RISCV_SBI bool "RISC-V SBI console support" - depends on RISCV_SBI_V01 + depends on RISCV_SBI select HVC_DRIVER help This enables support for console output via RISC-V SBI calls, which diff --git a/drivers/tty/hvc/hvc_riscv_sbi.c b/drivers/tty/hvc/hvc_riscv_sbi.c index 31f53fa77e4a..56da1a4b5aca 100644 --- a/drivers/tty/hvc/hvc_riscv_sbi.c +++ b/drivers/tty/hvc/hvc_riscv_sbi.c @@ -39,21 +39,89 @@ static int hvc_sbi_tty_get(uint32_t vtermno, char *buf, int count) return i; } -static const struct hv_ops hvc_sbi_ops = { +static const struct hv_ops hvc_sbi_v01_ops = { .get_chars = hvc_sbi_tty_get, .put_chars = hvc_sbi_tty_put, }; -static int __init hvc_sbi_init(void) +static int hvc_sbi_dbcn_tty_put(uint32_t vtermno, const char *buf, int count) { - return PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_ops, 16)); + phys_addr_t pa; + struct sbiret ret; + + if (is_vmalloc_addr(buf)) { + pa = page_to_phys(vmalloc_to_page(buf)) + offset_in_page(buf); + if (PAGE_SIZE < (offset_in_page(buf) + count)) + count = PAGE_SIZE - offset_in_page(buf); + } else { + pa = __pa(buf); + } + + if (IS_ENABLED(CONFIG_32BIT)) + ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE, + count, lower_32_bits(pa), upper_32_bits(pa), + 0, 0, 0); + else + ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE, + count, pa, 0, 0, 0, 0); + if (ret.error) + return 0; + + return count; } -device_initcall(hvc_sbi_init); -static int __init hvc_sbi_console_init(void) +static int hvc_sbi_dbcn_tty_get(uint32_t vtermno, char *buf, int count) { - hvc_instantiate(0, 0, &hvc_sbi_ops); + phys_addr_t pa; + struct sbiret ret; + + if (is_vmalloc_addr(buf)) { + pa = page_to_phys(vmalloc_to_page(buf)) + offset_in_page(buf); + if (PAGE_SIZE < (offset_in_page(buf) + count)) + count = PAGE_SIZE - offset_in_page(buf); + } else { + pa = __pa(buf); + } + + if (IS_ENABLED(CONFIG_32BIT)) + ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_READ, + count, lower_32_bits(pa), upper_32_bits(pa), + 0, 0, 0); + else + ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_READ, + count, pa, 0, 0, 0, 0); + if (ret.error) + return 0; + + return ret.value; +} + +static const struct hv_ops hvc_sbi_dbcn_ops = { + .put_chars = hvc_sbi_dbcn_tty_put, + .get_chars = hvc_sbi_dbcn_tty_get, +}; + +static int __init hvc_sbi_init(void) +{ + int err; + + if ((sbi_spec_version >= sbi_mk_version(2, 0)) && + (sbi_probe_extension(SBI_EXT_DBCN) > 0)) { + err = PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_dbcn_ops, 16)); + if (err) + return err; + hvc_instantiate(0, 0, &hvc_sbi_dbcn_ops); + } else { + if (IS_ENABLED(CONFIG_RISCV_SBI_V01)) { + err = PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_v01_ops, 16)); + if (err) + return err; + hvc_instantiate(0, 0, &hvc_sbi_v01_ops); + } else { + return -ENODEV; + } + } return 0; } -console_initcall(hvc_sbi_console_init); +device_initcall(hvc_sbi_init); From patchwork Fri Oct 20 07:21:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 155859 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2010:b0:403:3b70:6f57 with SMTP id fe16csp881702vqb; Fri, 20 Oct 2023 00:23:33 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEBcK+l6KQpV8MwNDiLfH8skKqBidHxr1lJ49azSgmpG2VLOr343d8QluAm6HNxBSAa8jtR X-Received: by 2002:a05:6a20:6a04:b0:161:28e0:9abd with SMTP id p4-20020a056a206a0400b0016128e09abdmr1026458pzk.16.1697786613648; Fri, 20 Oct 2023 00:23:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697786613; cv=none; d=google.com; s=arc-20160816; b=Z/ly4cUtcjFMlGw/EI8nwqpqtt3YaVvedtYt4O4IGnYln3rlQe/D9RHYLL1mLzpQvC vNB6FgpZVNNCev4ktIkhUVH67fnrBoB8/31EbhSw8LaW+D/uSfif/mle54YhMZzbSvG2 GUo37r6meh1hdzsDpWxpuzZpS9tD1OmH6SEyMNfShFYcXGOE1/8Wbk+mENpRL1hEKASr V77Ibv8IQMLZNhks3R2eyIc/8HtrU7Vanlp23c9cFzpl4yjNa1Q11WWKS7EGzyg1Vy4/ tL0fgIESsS8TlqMMbhiWq4Czphg8C95M9Xu+RyTsl5+DKyyQUICoVHZeFCZgv6bZSML7 sF0Q== ARC-Message-Signature: i=1; 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[23.128.96.38]) by mx.google.com with ESMTPS id 15-20020a17090a000f00b00276945c92c1si1338912pja.36.2023.10.20.00.23.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 00:23:33 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) client-ip=23.128.96.38; Authentication-Results: mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b="Jb/OhA2L"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by fry.vger.email (Postfix) with ESMTP id 9E79A8107F00; Fri, 20 Oct 2023 00:23:31 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at fry.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1376497AbjJTHXO (ORCPT + 25 others); Fri, 20 Oct 2023 03:23:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42206 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1376499AbjJTHWp (ORCPT ); Fri, 20 Oct 2023 03:22:45 -0400 Received: from mail-oo1-xc2e.google.com (mail-oo1-xc2e.google.com [IPv6:2607:f8b0:4864:20::c2e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AA22C199A for ; Fri, 20 Oct 2023 00:22:32 -0700 (PDT) Received: by mail-oo1-xc2e.google.com with SMTP id 006d021491bc7-584042e7f73so292255eaf.2 for ; Fri, 20 Oct 2023 00:22:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1697786551; x=1698391351; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DQOTSMVYEAXB96lPNmfxUETXmF1nmywj/hDtdToDI6M=; b=Jb/OhA2L1vep8syvG8Ez0j19Zv4UJmFoTgTdokFmzHBwZ4335kx3ycYFl9tkj49v7A SrUVu0Yc5/p72SSDT8YEr2PnSMuCl1nyHZHLEstID6BlZ0u70WTwbmrt/7UcqgzTOO6e +dWWMmXA3qn9iSH47TlsGEyidwCYBBFSAH8RRhJE/Coq9M/mwunuX1rWpNyXgrttUWMf K4IKq7j3n5G6Kj+ZKnUUMfbAUodR7mVgPfnL6tT29PIsDC9qWxw5TMgY5t2hqnsgMGWB P2kOWbRUvHXaDqHm/nal0EmKzjiA+TF32CNinC5qTl5F0m2c2DQV6udtjFn8PRq/ZOS2 JuWg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1697786551; x=1698391351; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DQOTSMVYEAXB96lPNmfxUETXmF1nmywj/hDtdToDI6M=; b=EKcT/B92JcUe6M6jvRWBRKYaq1OhMZwu69BlNTXDxGmwZwmqpyTdw7qIJjq/ZntJiK 39tHS6L7mKEj11khUK9/85+1U+SD9HrZ3ZV+FY00QUtsT/nZg7+0+CeR4fSMiFZzyvcE TU9REa7fLF24780F4JmcF+ZVUyGjP7YJhKmknzXSQZjRNfFovDtCc+fDq8vU/gqVNk9T rjSBfo/yt3b1M/P+TAprM3QVjcV2WTnpUXIc5YCWvaDrhvRl/BRwyCvkijd+DhMesL0+ 3bffebovKM8pGbTWDRpt4oQhObmzgTybG8aIqbyoV1J3Hrg0g+7V+dPe5fD7F3ZLN3YR NS2g== X-Gm-Message-State: AOJu0YzvkRHtFvbHfP0TljgjDnNTf3y/QKWaXFUbx80/lQpfs80pIdMo h4rWyuK5ISQ/2dnuPOl37IoVYA== X-Received: by 2002:a05:6871:3316:b0:1e9:9215:3987 with SMTP id nf22-20020a056871331600b001e992153987mr1427367oac.16.1697786550612; Fri, 20 Oct 2023 00:22:30 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.83.81]) by smtp.gmail.com with ESMTPSA id v12-20020a63f20c000000b005b32d6b4f2fsm828204pgh.81.2023.10.20.00.22.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Oct 2023 00:22:30 -0700 (PDT) From: Anup Patel To: Paolo Bonzini , Atish Patra , Palmer Dabbelt , Paul Walmsley , Greg Kroah-Hartman , Jiri Slaby Cc: Conor Dooley , Andrew Jones , kvm@vger.kernel.org, kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v3 9/9] RISC-V: Enable SBI based earlycon support Date: Fri, 20 Oct 2023 12:51:40 +0530 Message-Id: <20231020072140.900967-10-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020072140.900967-1-apatel@ventanamicro.com> References: <20231020072140.900967-1-apatel@ventanamicro.com> MIME-Version: 1.0 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Fri, 20 Oct 2023 00:23:31 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780258295998064692 X-GMAIL-MSGID: 1780258295998064692 Let us enable SBI based earlycon support in defconfigs for both RV32 and RV64 so that "earlycon=sbi" can be used again. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- arch/riscv/configs/defconfig | 1 + arch/riscv/configs/rv32_defconfig | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index ab86ec3b9eab..f82700da0056 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -132,6 +132,7 @@ CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_DW=y CONFIG_SERIAL_OF_PLATFORM=y CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_EARLYCON_RISCV_SBI=y CONFIG_VIRTIO_CONSOLE=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_VIRTIO=y diff --git a/arch/riscv/configs/rv32_defconfig b/arch/riscv/configs/rv32_defconfig index 89b601e253a6..5721af39afd1 100644 --- a/arch/riscv/configs/rv32_defconfig +++ b/arch/riscv/configs/rv32_defconfig @@ -66,6 +66,7 @@ CONFIG_INPUT_MOUSEDEV=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_EARLYCON_RISCV_SBI=y CONFIG_VIRTIO_CONSOLE=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_VIRTIO=y