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Thu, 19 Oct 2023 23:28:59 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780254865013333005 X-GMAIL-MSGID: 1780254865013333005 Add acpi machine id for ACP6.3 version based platform and configure driver data to enable SOF sound card support on newer boards. Signed-off-by: Vijendar Mukunda --- sound/soc/amd/acp-config.c | 12 ++++++++++++ sound/soc/amd/mach-config.h | 1 + 2 files changed, 13 insertions(+) diff --git a/sound/soc/amd/acp-config.c b/sound/soc/amd/acp-config.c index a58d646d28f6..20cee7104c2b 100644 --- a/sound/soc/amd/acp-config.c +++ b/sound/soc/amd/acp-config.c @@ -263,4 +263,16 @@ struct snd_soc_acpi_mach snd_soc_acpi_amd_rmb_sof_machines[] = { }; EXPORT_SYMBOL(snd_soc_acpi_amd_rmb_sof_machines); +struct snd_soc_acpi_mach snd_soc_acpi_amd_acp63_sof_machines[] = { + { + .id = "AMDI1019", + .drv_name = "acp63-dsp", + .pdata = &acp_quirk_data, + .fw_filename = "sof-acp_6_3.ri", + .sof_tplg_filename = "sof-acp_6_3.tplg", + }, + {}, +}; +EXPORT_SYMBOL(snd_soc_acpi_amd_acp63_sof_machines); + MODULE_LICENSE("Dual BSD/GPL"); diff --git a/sound/soc/amd/mach-config.h b/sound/soc/amd/mach-config.h index d392e6d6e6e1..ce5d77639086 100644 --- a/sound/soc/amd/mach-config.h +++ b/sound/soc/amd/mach-config.h @@ -21,6 +21,7 @@ extern struct snd_soc_acpi_mach snd_soc_acpi_amd_sof_machines[]; extern struct snd_soc_acpi_mach snd_soc_acpi_amd_rmb_sof_machines[]; extern struct snd_soc_acpi_mach snd_soc_acpi_amd_vangogh_sof_machines[]; +extern struct snd_soc_acpi_mach snd_soc_acpi_amd_acp63_sof_machines[]; struct config_entry { u32 flags; From patchwork Fri Oct 20 06:28:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mukunda,Vijendar" X-Patchwork-Id: 155833 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2010:b0:403:3b70:6f57 with SMTP id fe16csp860741vqb; Thu, 19 Oct 2023 23:29:29 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEd8+QWyBvR+Gy2Pb+xSOXS47hIn3yfUZySyv2uAIvNaykjWRv63HcepwOHBKzrGbNCHORE X-Received: by 2002:a05:6a00:21ca:b0:6be:43f8:4e0b with SMTP id t10-20020a056a0021ca00b006be43f84e0bmr885179pfj.24.1697783368917; Thu, 19 Oct 2023 23:29:28 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1697783368; cv=pass; d=google.com; s=arc-20160816; b=Se4S2e4Y2Ad5mh8FtzKccsfPXY/mivYlwq8Hj6S4hXW0KpZM26YDsQejdP3cF6itIZ fNhg3jYwYgAEukEU2ybMv4eS/+n5EAhpSUHC3qjR17aMu6uTAMGx6lEDK88513f6vwfW nfKvJXolC12iNwYPxfNbGLDs/pPj/8AFRlemb2Ozk8rAa8DKkiDyDv7rui9Alu52tO70 jC3YCEWNEbBKcRcdPHlkC3fj7Uxt0ClnYhTxbtgET/hv2vC/+NHwxy+DSWEAhqLfGChi vJG8pXWrSwrAfzh8vxq5HVW2+vVR/X14KhwYOZbFPLC5GMwM5Uv4Ujn+CBueXLMrROtm Cvcw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=XDCXCiZoqnjUxCvpDcsRrOWumgzb76V6UiN2QRKdBaY=; fh=v7BzzCE5/2iy0yiUispqtNxF8gaM9zC6/wSGJOLJHsQ=; b=fDzZqp8/e+z4ZLhjgqw5ArEmeED23wKB+IoICtyaG3YZNG+81JZmhMTNzm3Gf8gv7F e5MWTkFND7RpsTI+omWpVVQYwDRct7VyHAk0x5Z3wpNZ0lf1cw78qqrMvhqEdgDRRaHx oMnxrvEkRYr4PLr1AU085qZPxeBPm+aX9m3Br+O8/anKdLN3if+zqcvSQVUJlGtO4iCH 3fLNeRarDtkwUTyI+mDemuMbDsiAqRkd2Q3aQz6+Mf2S+Jfc6/FF/ggixJND9BN6AP7F LT1CykwiCWBb262zMJ/vHfNB5yP0DEXUPl5dNeJt4Pug/5PSZh8M6mFVMQfYrRcTWW05 KuxQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=tI7bn0u3; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from morse.vger.email (morse.vger.email. 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Thu, 19 Oct 2023 23:29:26 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780254894091465751 X-GMAIL-MSGID: 1780254894091465751 Add SOF support for ACP6.3 version based platform Signed-off-by: Vijendar Mukunda --- sound/soc/sof/amd/Kconfig | 9 +++ sound/soc/sof/amd/Makefile | 2 + sound/soc/sof/amd/acp.h | 4 + sound/soc/sof/amd/acp63.c | 146 ++++++++++++++++++++++++++++++++++ sound/soc/sof/amd/pci-acp63.c | 106 ++++++++++++++++++++++++ 5 files changed, 267 insertions(+) create mode 100644 sound/soc/sof/amd/acp63.c create mode 100644 sound/soc/sof/amd/pci-acp63.c diff --git a/sound/soc/sof/amd/Kconfig b/sound/soc/sof/amd/Kconfig index f2faa08f0c0e..19c5e27a193f 100644 --- a/sound/soc/sof/amd/Kconfig +++ b/sound/soc/sof/amd/Kconfig @@ -60,4 +60,13 @@ config SND_SOC_SOF_ACP_PROBES This option is not user-selectable but automatically handled by 'select' statements at a higher level +config SND_SOC_SOF_AMD_ACP63 + tristate "SOF support for ACP6.3 platform" + depends on SND_SOC_SOF_PCI + select SND_SOC_SOF_AMD_COMMON + help + Select this option for SOF support on + AMD ACP6.3 version based platforms. + Say Y if you want to enable SOF on ACP6.3 based platform. + If unsure select "N". endif diff --git a/sound/soc/sof/amd/Makefile b/sound/soc/sof/amd/Makefile index f3b375e67a6f..ad25f4206177 100644 --- a/sound/soc/sof/amd/Makefile +++ b/sound/soc/sof/amd/Makefile @@ -9,8 +9,10 @@ snd-sof-amd-acp-$(CONFIG_SND_SOC_SOF_ACP_PROBES) = acp-probes.o snd-sof-amd-renoir-objs := pci-rn.o renoir.o snd-sof-amd-rembrandt-objs := pci-rmb.o rembrandt.o snd-sof-amd-vangogh-objs := pci-vangogh.o vangogh.o +snd-sof-amd-acp63-objs := pci-acp63.o acp63.o obj-$(CONFIG_SND_SOC_SOF_AMD_COMMON) += snd-sof-amd-acp.o obj-$(CONFIG_SND_SOC_SOF_AMD_RENOIR) +=snd-sof-amd-renoir.o obj-$(CONFIG_SND_SOC_SOF_AMD_REMBRANDT) +=snd-sof-amd-rembrandt.o obj-$(CONFIG_SND_SOC_SOF_AMD_VANGOGH) +=snd-sof-amd-vangogh.o +obj-$(CONFIG_SND_SOC_SOF_AMD_ACP63) +=snd-sof-amd-acp63.o diff --git a/sound/soc/sof/amd/acp.h b/sound/soc/sof/amd/acp.h index 6814f2051104..3d2c5f07ed44 100644 --- a/sound/soc/sof/amd/acp.h +++ b/sound/soc/sof/amd/acp.h @@ -62,10 +62,12 @@ #define ACP_RN_PCI_ID 0x01 #define ACP_VANGOGH_PCI_ID 0x50 #define ACP_RMB_PCI_ID 0x6F +#define ACP63_PCI_ID 0x63 #define HOST_BRIDGE_CZN 0x1630 #define HOST_BRIDGE_VGH 0x1645 #define HOST_BRIDGE_RMB 0x14B5 +#define HOST_BRIDGE_ACP63 0x14E8 #define ACP_SHA_STAT 0x8000 #define ACP_PSP_TIMEOUT_US 1000000 #define ACP_EXT_INTR_ERROR_STAT 0x20000000 @@ -273,6 +275,8 @@ extern struct snd_sof_dsp_ops sof_vangogh_ops; int sof_vangogh_ops_init(struct snd_sof_dev *sdev); extern struct snd_sof_dsp_ops sof_rembrandt_ops; int sof_rembrandt_ops_init(struct snd_sof_dev *sdev); +extern struct snd_sof_dsp_ops sof_acp63_ops; +int sof_acp63_ops_init(struct snd_sof_dev *sdev); struct snd_soc_acpi_mach *amd_sof_machine_select(struct snd_sof_dev *sdev); /* Machine configuration */ diff --git a/sound/soc/sof/amd/acp63.c b/sound/soc/sof/amd/acp63.c new file mode 100644 index 000000000000..9fb645079c3a --- /dev/null +++ b/sound/soc/sof/amd/acp63.c @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +// +// This file is provided under a dual BSD/GPLv2 license. When using or +// redistributing this file, you may do so under either license. +// +// Copyright(c) 2023 Advanced Micro Devices, Inc. +// +// Authors: Vijendar Mukunda + +/* + * Hardware interface for Audio DSP on ACP6.3 version based platform + */ + +#include +#include + +#include "../ops.h" +#include "../sof-audio.h" +#include "acp.h" +#include "acp-dsp-offset.h" + +#define I2S_HS_INSTANCE 0 +#define I2S_BT_INSTANCE 1 +#define I2S_SP_INSTANCE 2 +#define PDM_DMIC_INSTANCE 3 +#define I2S_HS_VIRTUAL_INSTANCE 4 + +static struct snd_soc_dai_driver acp63_sof_dai[] = { + [I2S_HS_INSTANCE] = { + .id = I2S_HS_INSTANCE, + .name = "acp-sof-hs", + .playback = { + .rates = SNDRV_PCM_RATE_8000_96000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 | + SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE, + .channels_min = 2, + .channels_max = 8, + .rate_min = 8000, + .rate_max = 96000, + }, + .capture = { + .rates = SNDRV_PCM_RATE_8000_48000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 | + SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE, + /* Supporting only stereo for I2S HS controller capture */ + .channels_min = 2, + .channels_max = 2, + .rate_min = 8000, + .rate_max = 48000, + }, + }, + + [I2S_BT_INSTANCE] = { + .id = I2S_BT_INSTANCE, + .name = "acp-sof-bt", + .playback = { + .rates = SNDRV_PCM_RATE_8000_96000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 | + SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE, + .channels_min = 2, + .channels_max = 8, + .rate_min = 8000, + .rate_max = 96000, + }, + .capture = { + .rates = SNDRV_PCM_RATE_8000_48000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 | + SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE, + /* Supporting only stereo for I2S BT controller capture */ + .channels_min = 2, + .channels_max = 2, + .rate_min = 8000, + .rate_max = 48000, + }, + }, + + [I2S_SP_INSTANCE] = { + .id = I2S_SP_INSTANCE, + .name = "acp-sof-sp", + .playback = { + .rates = SNDRV_PCM_RATE_8000_96000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 | + SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE, + .channels_min = 2, + .channels_max = 8, + .rate_min = 8000, + .rate_max = 96000, + }, + .capture = { + .rates = SNDRV_PCM_RATE_8000_48000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 | + SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE, + /* Supporting only stereo for I2S SP controller capture */ + .channels_min = 2, + .channels_max = 2, + .rate_min = 8000, + .rate_max = 48000, + }, + }, + + [PDM_DMIC_INSTANCE] = { + .id = PDM_DMIC_INSTANCE, + .name = "acp-sof-dmic", + .capture = { + .rates = SNDRV_PCM_RATE_8000_48000, + .formats = SNDRV_PCM_FMTBIT_S32_LE, + .channels_min = 2, + .channels_max = 4, + .rate_min = 8000, + .rate_max = 48000, + }, + }, + + [I2S_HS_VIRTUAL_INSTANCE] = { + .id = I2S_HS_VIRTUAL_INSTANCE, + .name = "acp-sof-hs-virtual", + .playback = { + .rates = SNDRV_PCM_RATE_8000_96000, + .formats = SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S8 | + SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S32_LE, + .channels_min = 2, + .channels_max = 8, + .rate_min = 8000, + .rate_max = 96000, + }, + }, +}; + +/* Phoenix ops */ +struct snd_sof_dsp_ops sof_acp63_ops; +EXPORT_SYMBOL_NS(sof_acp63_ops, SND_SOC_SOF_AMD_COMMON); + +int sof_acp63_ops_init(struct snd_sof_dev *sdev) +{ + /* common defaults */ + memcpy(&sof_acp63_ops, &sof_acp_common_ops, sizeof(struct snd_sof_dsp_ops)); + + sof_acp63_ops.drv = acp63_sof_dai; + sof_acp63_ops.num_drv = ARRAY_SIZE(acp63_sof_dai); + + return 0; +} + +MODULE_IMPORT_NS(SND_SOC_SOF_AMD_COMMON); +MODULE_DESCRIPTION("ACP63 SOF Driver"); +MODULE_LICENSE("Dual BSD/GPL"); diff --git a/sound/soc/sof/amd/pci-acp63.c b/sound/soc/sof/amd/pci-acp63.c new file mode 100644 index 000000000000..bceb94ac80a9 --- /dev/null +++ b/sound/soc/sof/amd/pci-acp63.c @@ -0,0 +1,106 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +// +// This file is provided under a dual BSD/GPLv2 license. When using or +// redistributing this file, you may do so under either license. +// +// Copyright(c) 2023 Advanced Micro Devices, Inc. All rights reserved. +// +// Authors: Vijendar Mukunda + +/*. + * PCI interface for ACP6.3 device + */ + +#include +#include +#include +#include +#include + +#include "../ops.h" +#include "../sof-pci-dev.h" +#include "../../amd/mach-config.h" +#include "acp.h" +#include "acp-dsp-offset.h" + +#define ACP6X_FUTURE_REG_ACLK_0 0x1854 +#define ACP6x_REG_START 0x1240000 +#define ACP6x_REG_END 0x125C000 + +static const struct sof_amd_acp_desc acp63_chip_info = { + .rev = 6, + .host_bridge_id = HOST_BRIDGE_ACP63, + .pgfsm_base = ACP6X_PGFSM_BASE, + .ext_intr_stat = ACP6X_EXT_INTR_STAT, + .dsp_intr_base = ACP6X_DSP_SW_INTR_BASE, + .sram_pte_offset = ACP6X_SRAM_PTE_OFFSET, + .hw_semaphore_offset = ACP6X_AXI2DAGB_SEM_0, + .fusion_dsp_offset = ACP6X_DSP_FUSION_RUNSTALL, + .probe_reg_offset = ACP6X_FUTURE_REG_ACLK_0, +}; + +static const struct sof_dev_desc acp63_desc = { + .machines = snd_soc_acpi_amd_acp63_sof_machines, + .resindex_lpe_base = 0, + .resindex_pcicfg_base = -1, + .resindex_imr_base = -1, + .irqindex_host_ipc = -1, + .chip_info = &acp63_chip_info, + .ipc_supported_mask = BIT(SOF_IPC_TYPE_3), + .ipc_default = SOF_IPC_TYPE_3, + .default_fw_path = { + [SOF_IPC_TYPE_3] = "amd/sof", + }, + .default_tplg_path = { + [SOF_IPC_TYPE_3] = "amd/sof-tplg", + }, + .default_fw_filename = { + [SOF_IPC_TYPE_3] = "sof-acp_6_3.ri", + }, + .nocodec_tplg_filename = "sof-acp.tplg", + .ops = &sof_acp63_ops, + .ops_init = sof_acp63_ops_init, +}; + +static int acp63_pci_probe(struct pci_dev *pci, const struct pci_device_id *pci_id) +{ + unsigned int flag; + + if (pci->revision != ACP63_PCI_ID) + return -ENODEV; + + flag = snd_amd_acp_find_config(pci); + if (flag != FLAG_AMD_SOF && flag != FLAG_AMD_SOF_ONLY_DMIC) + return -ENODEV; + + return sof_pci_probe(pci, pci_id); +}; + +static void acp63_pci_remove(struct pci_dev *pci) +{ + sof_pci_remove(pci); +} + +/* PCI IDs */ +static const struct pci_device_id acp63_pci_ids[] = { + { PCI_DEVICE(PCI_VENDOR_ID_AMD, ACP_PCI_DEV_ID), + .driver_data = (unsigned long)&acp63_desc}, + { 0, } +}; +MODULE_DEVICE_TABLE(pci, acp63_pci_ids); + +/* pci_driver definition */ +static struct pci_driver snd_sof_pci_amd_acp63_driver = { + .name = KBUILD_MODNAME, + .id_table = acp63_pci_ids, + .probe = acp63_pci_probe, + .remove = acp63_pci_remove, + .driver = { + .pm = &sof_pci_pm, + }, +}; +module_pci_driver(snd_sof_pci_amd_acp63_driver); + +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_IMPORT_NS(SND_SOC_SOF_AMD_COMMON); +MODULE_IMPORT_NS(SND_SOC_SOF_PCI_DEV); From patchwork Fri Oct 20 06:28:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mukunda,Vijendar" X-Patchwork-Id: 155834 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2010:b0:403:3b70:6f57 with SMTP id fe16csp860883vqb; Thu, 19 Oct 2023 23:29:50 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHJwEOmHnsyxSIFNKRLiQZ/gYi5I63KN98nhHH1uRXEKutAXwbJlKsRA+O9qbPnrZtOvSPU X-Received: by 2002:a17:903:23c2:b0:1ca:6abe:cb37 with SMTP id o2-20020a17090323c200b001ca6abecb37mr1029748plh.9.1697783390276; Thu, 19 Oct 2023 23:29:50 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1697783390; cv=pass; d=google.com; s=arc-20160816; b=dax2HEeS7GEVx3cg6OeFsHTmXOIy3sxYmE79mrPADdAd5ZRIJZqfJyiNdqiHhMiCPb 93vEixiEi9+1v1hOGLpQNEKd2Cbsf9blkgLnY6rn6U1dR4VSmuimT6k+1LC7vNbjpBQV /qngp1+7jFQxXS5LEZRo2TsaGPGcppQUoNpFVwqZk+TmPu39INfbEJ26g6EsPksJHq18 Vw4/0U5qq1WdIv1wkteQUpQKJnAmMCCP/MFQzPwr2PXXaWBrOne5H+aCi/jdGCwoTelv Xbu8hOQyZSB1uC1y7WhkElwhgztpqobgUL7mNqvbdkqAbNCEpLRql2CtATWCQOiFzfJN Q4CQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=DF3l17Y46tjLzoMfH6AT5Qo1MljznJ7mBGk/VDlhtDM=; fh=a0FgBtUkvpfB1/8TKPyDnnFenTMa0jucjmrS493xJys=; b=Jr+sKjGFGVhhCti4eQ/WMfBFcihkMNuoSsBWSF/JEtVd30vSTZ6B6iTuDVwtqrnWrK RwZffnw2l2LDvui8tlPtlXBatQfQmeIUtE+W1MSUFdJfhxfjBhZ5tjGe8AqED2MWFPsw qSWoLHL3l0fK8llU9G5D7Igv/KGSY0EdlP0iXT9GztZMKyNWmIf+cPpES8iMNgt8IdSe /1HLmUouIBrkn/jVn2xoQN+/DrRVqJ56SmHWKAgh9NnUqJWpj+0MM7jQNdj09iwitlZ/ Lj676IUxS4+qGaIbqZ2N9OWEU2htqWQKVgXVECLAkpmfRNdkSVw7LMChQVq1a8B9Khfi 0/Fw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b="u8pWQ/Hh"; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from lipwig.vger.email (lipwig.vger.email. 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Thu, 19 Oct 2023 23:29:48 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780254916575128328 X-GMAIL-MSGID: 1780254916575128328 Increase DSP cache window range to 2.5MB to align with ACP memory. Signed-off-by: Vijendar Mukunda --- sound/soc/sof/amd/acp.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sound/soc/sof/amd/acp.h b/sound/soc/sof/amd/acp.h index 3d2c5f07ed44..205b434f0872 100644 --- a/sound/soc/sof/amd/acp.h +++ b/sound/soc/sof/amd/acp.h @@ -84,7 +84,7 @@ #define EXCEPT_MAX_HDR_SIZE 0x400 #define AMD_STACK_DUMP_SIZE 32 -#define SRAM1_SIZE 0x13A000 +#define SRAM1_SIZE 0x280000 #define PROBE_STATUS_BIT BIT(31) #define ACP_FIRMWARE_SIGNATURE 0x100 From patchwork Fri Oct 20 06:28:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mukunda,Vijendar" X-Patchwork-Id: 155836 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2010:b0:403:3b70:6f57 with SMTP id fe16csp861012vqb; Thu, 19 Oct 2023 23:30:09 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEbyYGKozfAAfKii1SdlhWoMZB77coUQPj62zCWovTmwRpw5CJ59IQCEztViYpdMm+SPDxZ X-Received: by 2002:a17:902:e751:b0:1b5:674d:2aa5 with SMTP id p17-20020a170902e75100b001b5674d2aa5mr1612318plf.13.1697783409651; Thu, 19 Oct 2023 23:30:09 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1697783409; cv=pass; d=google.com; s=arc-20160816; b=JroOVcIig8KZMxiaTLIGDS5oFscMeoa63gHee+lCJLd3x4Xa7wPTKG9nqUfkF4G+Dm VYIQPm1Wth/bDuIqwQyyFeqO0NyP4DAsCVdMfukMGSDyLdgv4BosLePCi5drrGpuu0a3 BHNzFI3TU7d20IRn9x/7YQFjz0mbXerfGtiQeXnwaod2VN836wXfz8W+3nc+SoE0YqBc BgyfdAQYnepyPGugDyVqQGGJte0WmGS7a4L1a/G6+RIS9/RWFE0y0/PMPJu5zSQda9Sy 4dEkohkM9IM24VSs88mcjHlu7NL7tOjFydk/laKoo1fmxNqbQ520MKf3oBgfDkrxwX5B gbHQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=64IlTLk9U7H3EHFVzimSbXahkhzsdMO0mNXW/M+XRUw=; fh=1GByvCkzBapUeLM7o+fE+v76Q6oHwgqIePrnJJnbOww=; b=ck3G+MGpvW0TzWgt/lJN1jQQVGTypz/rsMJiILaKejGg/HVU6WH6YAiPJ6plQA8o/5 5IRlT0GtYfVSILFOzedd7iSoQChtXADt8wZNh8LxYZe+TY9qcRWsygPl+cw6g3hoLs1H 1kcz8klPO35p5X1c38HWC0RC7/CPCkiKE4owW/BbtKNyY6uPv2zSvjYvmzUBkT4Q0BCK KePWGqZ/y2vpnxG5oXP33GH56eiA962AlPp9xq9Hch2W6SlVMDBgkCwRQy7EKqV6CBt3 WG9Kag2I0A0L3UOQOVPTlc8kSzJ1P7PEpWCUMYWQ70KxUPxujXhzjP+m5Zh6GK+aJLUW v2zw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@amd.com header.s=selector1 header.b=xZMqOro9; arc=pass (i=1 spf=pass spfdomain=amd.com dmarc=pass fromdomain=amd.com); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=amd.com Received: from pete.vger.email (pete.vger.email. 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Thu, 19 Oct 2023 23:30:07 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780254936473044413 X-GMAIL-MSGID: 1780254936473044413 DSP data bin can be loaded in to ACP DRAM or ACP SRAM. Add conditional check for ACP DRAM usage for data bin loading. Rename DRAM base address macro to have symmetry. Signed-off-by: Vijendar Mukunda --- sound/soc/sof/amd/acp-loader.c | 36 +++++++++++++++++++--------------- sound/soc/sof/amd/acp.h | 3 ++- 2 files changed, 22 insertions(+), 17 deletions(-) diff --git a/sound/soc/sof/amd/acp-loader.c b/sound/soc/sof/amd/acp-loader.c index a427673cfb03..d35d47d7e311 100644 --- a/sound/soc/sof/amd/acp-loader.c +++ b/sound/soc/sof/amd/acp-loader.c @@ -83,6 +83,7 @@ int acp_dsp_block_write(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_t } dest = adata->data_buf + offset; adata->fw_data_bin_size = size + offset; + adata->is_dram_in_use = true; break; case SOF_FW_BLK_TYPE_SRAM: offset = offset - desc->sram_pte_offset; @@ -153,7 +154,7 @@ int acp_dsp_pre_fw_run(struct snd_sof_dev *sdev) struct pci_dev *pci = to_pci_dev(sdev->dev); const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); struct acp_dev_data *adata; - unsigned int src_addr, size_fw; + unsigned int src_addr, size_fw, dest_addr; u32 page_count, dma_size; int ret; @@ -174,20 +175,21 @@ int acp_dsp_pre_fw_run(struct snd_sof_dev *sdev) dev_err(sdev->dev, "SHA DMA transfer failed status: %d\n", ret); return ret; } - configure_pte_for_fw_loading(FW_DATA_BIN, ACP_DRAM_PAGE_COUNT, adata); - - src_addr = ACP_SYSTEM_MEMORY_WINDOW + page_count * ACP_PAGE_SIZE; - ret = configure_and_run_dma(adata, src_addr, ACP_DATA_RAM_BASE_ADDRESS, - adata->fw_data_bin_size); - if (ret < 0) { - dev_err(sdev->dev, "acp dma configuration failed: %d\n", ret); - return ret; + if (adata->is_dram_in_use) { + configure_pte_for_fw_loading(FW_DATA_BIN, ACP_DRAM_PAGE_COUNT, adata); + src_addr = ACP_SYSTEM_MEMORY_WINDOW + (page_count * ACP_PAGE_SIZE); + dest_addr = ACP_DRAM_BASE_ADDRESS; + + ret = configure_and_run_dma(adata, src_addr, dest_addr, adata->fw_data_bin_size); + if (ret < 0) { + dev_err(sdev->dev, "acp dma configuration failed: %d\n", ret); + return ret; + } + ret = acp_dma_status(adata, 0); + if (ret < 0) + dev_err(sdev->dev, "acp dma transfer status: %d\n", ret); } - ret = acp_dma_status(adata, 0); - if (ret < 0) - dev_err(sdev->dev, "acp dma transfer status: %d\n", ret); - if (desc->rev > 3) { /* Cache Window enable */ snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_DSP0_CACHE_OFFSET0, desc->sram_pte_offset); @@ -197,10 +199,12 @@ int acp_dsp_pre_fw_run(struct snd_sof_dev *sdev) /* Free memory once DMA is complete */ dma_size = (PAGE_ALIGN(sdev->basefw.fw->size) >> PAGE_SHIFT) * ACP_PAGE_SIZE; dma_free_coherent(&pci->dev, dma_size, adata->bin_buf, adata->sha_dma_addr); - dma_free_coherent(&pci->dev, ACP_DEFAULT_DRAM_LENGTH, adata->data_buf, adata->dma_addr); adata->bin_buf = NULL; - adata->data_buf = NULL; - + if (adata->is_dram_in_use) { + dma_free_coherent(&pci->dev, ACP_DEFAULT_DRAM_LENGTH, adata->data_buf, + adata->dma_addr); + adata->data_buf = NULL; + } return ret; } EXPORT_SYMBOL_NS(acp_dsp_pre_fw_run, SND_SOC_SOF_AMD_COMMON); diff --git a/sound/soc/sof/amd/acp.h b/sound/soc/sof/amd/acp.h index 205b434f0872..2d1f57e1365a 100644 --- a/sound/soc/sof/amd/acp.h +++ b/sound/soc/sof/amd/acp.h @@ -54,7 +54,7 @@ #define ACP3X_SCRATCH_MEMORY_ADDRESS 0x02050000 #define ACP_SYSTEM_MEMORY_WINDOW 0x4000000 #define ACP_IRAM_BASE_ADDRESS 0x000000 -#define ACP_DATA_RAM_BASE_ADDRESS 0x01000000 +#define ACP_DRAM_BASE_ADDRESS 0x01000000 #define ACP_DRAM_PAGE_COUNT 128 #define ACP_DSP_TO_HOST_IRQ 0x04 @@ -208,6 +208,7 @@ struct acp_dev_data { struct pci_dev *smn_dev; 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Fri, 20 Oct 2023 01:29:28 -0500 From: Vijendar Mukunda To: CC: , , , Vijendar Mukunda , Pierre-Louis Bossart , Liam Girdwood , Peter Ujfalusi , "Bard Liao" , Ranjani Sridharan , Daniel Baluta , Kai Vehmanen , Jaroslav Kysela , Takashi Iwai , Chao Song , Venkata Prasad Potturu , V sujith kumar Reddy , Mastan Katragadda , "moderated list:SOUND - SOUND OPEN FIRMWARE (SOF) DRIVERS" , open list Subject: [PATCH 5/5] ASoC: SOF: amd: add option to use sram for data bin loading Date: Fri, 20 Oct 2023 11:58:15 +0530 Message-ID: <20231020062822.3913760-5-Vijendar.Mukunda@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20231020062822.3913760-1-Vijendar.Mukunda@amd.com> References: <20231020062822.3913760-1-Vijendar.Mukunda@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00001506:EE_|PH7PR12MB5617:EE_ X-MS-Office365-Filtering-Correlation-Id: ce8e0cf2-bd17-4976-9b4b-08dbd135eda7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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Thu, 19 Oct 2023 23:30:05 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780254935067509873 X-GMAIL-MSGID: 1780254935067509873 Provide an option to load DSP data bin to ACP SRAM. Signed-off-by: Vijendar Mukunda --- sound/soc/sof/amd/acp-loader.c | 46 +++++++++++++++++++++++++++++----- sound/soc/sof/amd/acp.h | 10 +++++++- 2 files changed, 49 insertions(+), 7 deletions(-) diff --git a/sound/soc/sof/amd/acp-loader.c b/sound/soc/sof/amd/acp-loader.c index d35d47d7e311..e05eb7a86dd4 100644 --- a/sound/soc/sof/amd/acp-loader.c +++ b/sound/soc/sof/amd/acp-loader.c @@ -19,8 +19,9 @@ #include "acp-dsp-offset.h" #include "acp.h" -#define FW_BIN 0 -#define FW_DATA_BIN 1 +#define FW_BIN 0 +#define FW_DATA_BIN 1 +#define FW_SRAM_DATA_BIN 2 #define FW_BIN_PTE_OFFSET 0x00 #define FW_DATA_BIN_PTE_OFFSET 0x08 @@ -49,7 +50,6 @@ int acp_dsp_block_write(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_t u32 offset, void *src, size_t size) { struct pci_dev *pci = to_pci_dev(sdev->dev); - const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata); struct acp_dev_data *adata; void *dest; u32 dma_size, page_count; @@ -86,9 +86,18 @@ int acp_dsp_block_write(struct snd_sof_dev *sdev, enum snd_sof_fw_blk_type blk_t adata->is_dram_in_use = true; break; case SOF_FW_BLK_TYPE_SRAM: - offset = offset - desc->sram_pte_offset; - memcpy_to_scratch(sdev, offset, src, size); - return 0; + if (!adata->sram_data_buf) { + adata->sram_data_buf = dma_alloc_coherent(&pci->dev, + ACP_DEFAULT_SRAM_LENGTH, + &adata->sram_dma_addr, + GFP_ATOMIC); + if (!adata->sram_data_buf) + return -ENOMEM; + } + adata->fw_sram_data_bin_size = size + offset; + dest = adata->sram_data_buf + offset; + adata->is_sram_in_use = true; + break; default: dev_err(sdev->dev, "bad blk type 0x%x\n", blk_type); return -EINVAL; @@ -123,6 +132,10 @@ static void configure_pte_for_fw_loading(int type, int num_pages, struct acp_dev offset = adata->fw_bin_page_count * 8; addr = adata->dma_addr; break; + case FW_SRAM_DATA_BIN: + offset = (adata->fw_bin_page_count + ACP_DRAM_PAGE_COUNT) * 8; + addr = adata->sram_dma_addr; + break; default: dev_err(sdev->dev, "Invalid data type %x\n", type); return; @@ -189,6 +202,22 @@ int acp_dsp_pre_fw_run(struct snd_sof_dev *sdev) if (ret < 0) dev_err(sdev->dev, "acp dma transfer status: %d\n", ret); } + if (adata->is_sram_in_use) { + configure_pte_for_fw_loading(FW_SRAM_DATA_BIN, ACP_SRAM_PAGE_COUNT, adata); + src_addr = ACP_SYSTEM_MEMORY_WINDOW + ACP_DEFAULT_SRAM_LENGTH + + (page_count * ACP_PAGE_SIZE); + dest_addr = ACP_SRAM_BASE_ADDRESS; + + ret = configure_and_run_dma(adata, src_addr, dest_addr, + adata->fw_sram_data_bin_size); + if (ret < 0) { + dev_err(sdev->dev, "acp dma configuration failed: %d\n", ret); + return ret; + } + ret = acp_dma_status(adata, 0); + if (ret < 0) + dev_err(sdev->dev, "acp dma transfer status: %d\n", ret); + } if (desc->rev > 3) { /* Cache Window enable */ @@ -205,6 +234,11 @@ int acp_dsp_pre_fw_run(struct snd_sof_dev *sdev) adata->dma_addr); adata->data_buf = NULL; } + if (adata->is_sram_in_use) { + dma_free_coherent(&pci->dev, ACP_DEFAULT_SRAM_LENGTH, adata->sram_data_buf, + adata->sram_dma_addr); + adata->sram_data_buf = NULL; + } return ret; } EXPORT_SYMBOL_NS(acp_dsp_pre_fw_run, SND_SOC_SOF_AMD_COMMON); diff --git a/sound/soc/sof/amd/acp.h b/sound/soc/sof/amd/acp.h index 2d1f57e1365a..c536cfde0e44 100644 --- a/sound/soc/sof/amd/acp.h +++ b/sound/soc/sof/amd/acp.h @@ -56,7 +56,7 @@ #define ACP_IRAM_BASE_ADDRESS 0x000000 #define ACP_DRAM_BASE_ADDRESS 0x01000000 #define ACP_DRAM_PAGE_COUNT 128 - +#define ACP_SRAM_BASE_ADDRESS 0x3806000 #define ACP_DSP_TO_HOST_IRQ 0x04 #define ACP_RN_PCI_ID 0x01 @@ -88,6 +88,8 @@ #define PROBE_STATUS_BIT BIT(31) #define ACP_FIRMWARE_SIGNATURE 0x100 +#define ACP_DEFAULT_SRAM_LENGTH 0x00080000 +#define ACP_SRAM_PAGE_COUNT 128 enum clock_source { ACP_CLOCK_96M = 0, @@ -194,13 +196,18 @@ struct acp_dev_data { struct platform_device *dmic_dev; unsigned int fw_bin_size; unsigned int fw_data_bin_size; + unsigned int fw_sram_data_bin_size; const char *fw_code_bin; const char *fw_data_bin; + const char *fw_sram_data_bin; u32 fw_bin_page_count; + u32 fw_data_bin_page_count; dma_addr_t sha_dma_addr; u8 *bin_buf; dma_addr_t dma_addr; u8 *data_buf; + dma_addr_t sram_dma_addr; + u8 *sram_data_buf; bool signed_fw_image; struct dma_descriptor dscr_info[ACP_MAX_DESC]; struct acp_dsp_stream stream_buf[ACP_MAX_STREAM]; @@ -209,6 +216,7 @@ struct acp_dev_data { struct acp_dsp_stream *probe_stream; bool enable_fw_debug; bool is_dram_in_use; + bool is_sram_in_use; }; void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes);