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[8.43.85.97]) by mx.google.com with ESMTPS id x16-20020ac85f10000000b00419845c7a91si850521qta.377.2023.10.19.23.21.23 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Oct 2023 23:21:23 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=en5R4AOk; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 71F8D385840A for ; Fri, 20 Oct 2023 06:21:23 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) by sourceware.org (Postfix) with ESMTPS id 075BD3858D35 for ; Fri, 20 Oct 2023 06:20:54 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 075BD3858D35 Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 075BD3858D35 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=192.198.163.7 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1697782858; cv=none; b=nnZScXfYqhFmmGDkRzJsfOuCMJNw98x/fROU0HDQQXIeZ/I78cIx8kea0dVN0cSADIOv0V3M7WoCVwCa9+S97GhruB/7CMLtVm0+TI/eOFtm/c11TtqRDgF7N9SY4Adxpq+H60AIVy22mBH9hjTLJOBO+RXRtG7FJMWmY5yAYf4= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1697782858; c=relaxed/simple; bh=Q7pXIKLQw4EZGE52LBN1XH7f138f9OR+piOBhg6YG+Y=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=LGhTb/Hh9KJGRaQ9XM4UtxWUcOIPcpZ5sNxgobXCGaRKoDUuv+b8G1iwUVtleVmj5rOpGSrTL/YbcrbMPz96PvbVClTbAhLvTGg2Ou2OMujWD0zR36MA5dTwtHZYGeOVY0uvkQB19XaRfuinOZQ3ivBspGpE71CQimIC64gpcy0= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1697782855; x=1729318855; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=Q7pXIKLQw4EZGE52LBN1XH7f138f9OR+piOBhg6YG+Y=; b=en5R4AOkHn2BjQPel77mzGNILVo0Ob8lpQWCM+cnMs+PXm2Xfa3/Ix05 mirxrF6hYoTkmfavb11cLpsxMvt/ZurrzXpixyXFNw/GhY/PkPtywJK3B tFRUn992B1WtQfbITZxWvQjAbfPCF2x4o9gzJafmWauCKHbl1dxmEk+QL HTqVkB4HFeSzeFDSVnZv1uVVgMRlKFmckRsdyXd9j9xN+mvI9pO0EhWqY u3m0k/JvLHETovrK4qa2Qjq1nwFASUu3gATYshoxe3ju996KiaULSWpxU tLyYH6copVS4JidKdiOA2//ZTW+6WH27K/BzucgZ6zaVbW0GJ0pwveuMB w==; X-IronPort-AV: E=McAfee;i="6600,9927,10868"; a="8002020" X-IronPort-AV: E=Sophos;i="6.03,238,1694761200"; d="scan'208";a="8002020" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Oct 2023 23:20:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10868"; a="901051463" X-IronPort-AV: E=Sophos;i="6.03,238,1694761200"; d="scan'208";a="901051463" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by fmsmga001.fm.intel.com with ESMTP; 19 Oct 2023 23:18:43 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id C0E76100571E; Fri, 20 Oct 2023 14:20:50 +0800 (CST) From: Haochen Jiang To: gcc-patches@gcc.gnu.org Cc: ubizjak@gmail.com, hongtao.liu@intel.com Subject: [PATCH] i386: Prevent splitting to xmm16+ when !TARGET_AVX512VL Date: Fri, 20 Oct 2023 14:20:50 +0800 Message-Id: <20231020062050.971264-1-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780254384997884328 X-GMAIL-MSGID: 1780254384997884328 Hi all, Currently, there will be a chance in split to use x/ymm16+ w/o AVX512VL, which finally leads to an ICE as pr111753 does. This patch aims to fix that. Regtested on x86_64-pc-linux-gnu. Ok for trunk? Thx, Haochen gcc/ChangeLog: PR target/111753 * config/i386/i386.cc (ix86_standard_x87sse_constant_load_p): Do not split to xmm16+ when !TARGET_AVX512VL. gcc/testsuite/ChangeLog: PR target/111753 * gcc.target/i386/pr111753.c: New test. --- gcc/config/i386/i386.cc | 3 ++ gcc/testsuite/gcc.target/i386/pr111753.c | 69 ++++++++++++++++++++++++ 2 files changed, 72 insertions(+) create mode 100644 gcc/testsuite/gcc.target/i386/pr111753.c diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc index 641e7680335..5f8c5eb98a2 100644 --- a/gcc/config/i386/i386.cc +++ b/gcc/config/i386/i386.cc @@ -5481,6 +5481,9 @@ ix86_standard_x87sse_constant_load_p (const rtx_insn *insn, rtx dst) if (src == NULL || (SSE_REGNO_P (REGNO (dst)) && standard_sse_constant_p (src, GET_MODE (dst)) != 1) + || (!TARGET_AVX512VL + && EXT_REX_SSE_REGNO_P (REGNO (dst)) + && standard_sse_constant_p (src, GET_MODE (dst)) == 1) || (STACK_REGNO_P (REGNO (dst)) && standard_80387_constant_p (src) < 1)) return false; diff --git a/gcc/testsuite/gcc.target/i386/pr111753.c b/gcc/testsuite/gcc.target/i386/pr111753.c new file mode 100644 index 00000000000..16ceca6ddc6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr111753.c @@ -0,0 +1,69 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -mavx512bw -fno-tree-ter -Wno-div-by-zero" } */ + +typedef int __attribute__((__vector_size__ (8))) v64u8; +typedef char __attribute__((__vector_size__ (16))) v128u8; +typedef int __attribute__((__vector_size__ (16))) v128u32; +typedef int __attribute__((__vector_size__ (32))) v256u8; +typedef int __attribute__((__vector_size__ (64))) v512u8; +typedef short __attribute__((__vector_size__ (4))) v32s16; +typedef short __attribute__((__vector_size__ (16))) v128s16; +typedef short __attribute__((__vector_size__ (32))) v256s16; +typedef _Float16 __attribute__((__vector_size__ (16))) f16; +typedef _Float32 f32; +typedef double __attribute__((__vector_size__ (64))) v512f64; +typedef _Decimal32 d32; +typedef _Decimal64 __attribute__((__vector_size__ (32))) v256d64; +typedef _Decimal64 __attribute__((__vector_size__ (64))) v512d64; +d32 foo0_d32_0, foo0_ret; +v256d64 foo0_v256d64_0; +v128s16 foo0_v128s16_0; +int foo0_v256d128_0; + +extern void bar(int); + +void +foo (v64u8, v128u8 v128u8_0, v128u8 v128s8_0, + v256u8 v256u8_0, int v256s8_0, v512u8 v512u8_0, int v512s8_0, + v256s16 v256s16_0, + v512u8 v512s16_0, + v128u32 v128u64_0, + v128u32 v128s64_0, + int, int, __int128 v128u128_0, __int128 v128s128_0, v128u32 v128f64_0) +{ + v512d64 v512d64_0; + v256u8 v256f32_0, v256d64_1 = foo0_v256d64_0 == foo0_d32_0; + f32 f32_0; + f16 v128f16_0; + f32_0 /= 0; + v128u8 v128u8_1 = v128u8_0 != 0; + int v256d32_1; + v256f32_0 /= 0; + v32s16 v32s16_1 = __builtin_shufflevector ((v128s16) { }, v256s16_0, 5, 10); + v512f64 v512f64_1 = __builtin_convertvector (v512d64_0, v512f64); + v512u8 v512d128_1 = v512s16_0; + v128s16 v128s16_2 = + __builtin_shufflevector ((v32s16) { }, v32s16_1, 0, 3, 2, 1, + 0, 0, 0, 3), v128s16_3 = foo0_v128s16_0 > 0; + v128f16_0 /= 0; + __int128 v128s128_1 = 0 == v128s128_0; + v512u8 v512u8_r = v512u8_0 + v512s8_0 + (v512u8) v512f64_1 + v512s16_0; + v256u8 v256u8_r = ((union { + v512u8 a; + v256u8 b;}) v512u8_r).b + + v256u8_0 + v256s8_0 + v256f32_0 + v256d32_1 + + (v256u8) v256d64_1 + foo0_v256d128_0; + v128u8 v128u8_r = ((union { + v256u8 a; + v128u8 b;}) v256u8_r).b + + v128u8_0 + v128u8_1 + v128s8_0 + (v128u8) v128s16_2 + + (v128u8) v128s16_3 + (v128u8) v128u64_0 + (v128u8) v128s64_0 + + (v128u8) v128u128_0 + (v128u8) v128s128_1 + + (v128u8) v128f16_0 + (v128u8) v128f64_0; + bar (f32_0 + (int) foo0_d32_0); + foo0_ret = ((union { + v64u8 a; + int b;}) ((union { + v128u8 a; + v64u8 b;}) v128u8_r).b).b; +}