From patchwork Thu Oct 19 05:34:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xingyu Wu X-Patchwork-Id: 155282 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2010:b0:403:3b70:6f57 with SMTP id fe16csp174490vqb; Wed, 18 Oct 2023 22:36:04 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHrTf54lQfCOQG180Jugwf/yC58/oJucqLNHKYl77Tff68hA8YBTS50kR288UXvW1ZyHioe X-Received: by 2002:a17:903:84c:b0:1c6:2b9d:56ce with SMTP id ks12-20020a170903084c00b001c62b9d56cemr1268176plb.21.1697693764702; Wed, 18 Oct 2023 22:36:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697693764; cv=none; d=google.com; s=arc-20160816; b=TldPyx9RdK1b+JN3yynCHHc1R83766L3fww8R6lT0A3Dlf4W162F6sOG/22ppK9KkZ nnCfSNzXi17uf9isKHxD8Rb6onZ8XL2IMWpEUkTxd0CRSWEogaXCxbrQWgEdRtQRLVdf q7r9aIrEUe1ZOpfaIQneomHpwfyDP37RbPJAfWDtqsv5/WL5oBR0JpdP4uS9JO5lDJp4 PZfDvW8SZ6vK+3nQmJJ5Owon+TI15bS3Xd8Y3yaB72rTuKxEmrCtyTMF5dw8cUkWAl6l EJzd3Qsf5Rt+hUP399wYWbZUharFwonqAjZ/ai8LNhCnocJt0sfOmo4/nSNsyPorpCm+ /bnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=vNmpNAVj9Eje1F42IE0e85PayPa1YskFbQ8fI10DX/Y=; fh=U35VaI2VhNr3pPNfgjXZzjzNImn7EzZodFPICcSprcI=; b=VJtf0IAb6oI4cTLdPRmzWPrFpGjVzA9LJi/5L+SJtDU7E/phNFWjJnDNgJGoGdD0hS 6WdLSB5CqN+swmMNoBl8z/o3cd3hMF8hG81Diz8F3n6OrzfNnAAYmFpPvO6ZZ8fjeGXz xK1aXI5+u99qrgLa8Wg6NikqwFrPwqLdjmCuXdaShJ0Yo3EGo4z0PDryTzAC5FWIsjpH kyjjWxqjBOrL+gwn0ftuD6q+jNS+0zeWgvZVb/xHbQuD1/bwwEZYbLi8voKs+pEikp9B nQrvlM+TmoBHBa2tVlziCg5s/6vkiFS8zCIDY0VlZ2WEHz35ndu5OHNmtysr3RL66lu3 zoFQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id j6-20020a170902da8600b001c612f42c78si1550588plx.513.2023.10.18.22.36.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 22:36:04 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 380128217EEF; Wed, 18 Oct 2023 22:35:46 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232670AbjJSFf3 convert rfc822-to-8bit (ORCPT + 24 others); Thu, 19 Oct 2023 01:35:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46746 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232614AbjJSFfT (ORCPT ); Thu, 19 Oct 2023 01:35:19 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E2F96132; Wed, 18 Oct 2023 22:35:15 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id C624E24E13F; Thu, 19 Oct 2023 13:35:04 +0800 (CST) Received: from EXMBX061.cuchost.com (172.16.6.61) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 19 Oct 2023 13:35:04 +0800 Received: from localhost.localdomain (183.27.99.123) by EXMBX061.cuchost.com (172.16.6.61) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 19 Oct 2023 13:35:03 +0800 From: Xingyu Wu To: Daniel Lezcano , Thomas Gleixner , Emil Renner Berthing , Christophe JAILLET CC: , , "Rob Herring" , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Walker Chen , Xingyu Wu , "Samin Guo" , , "Conor Dooley" Subject: [PATCH v7 1/3] dt-bindings: timer: Add timer for StarFive JH7110 SoC Date: Thu, 19 Oct 2023 13:34:59 +0800 Message-ID: <20231019053501.46899-2-xingyu.wu@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231019053501.46899-1-xingyu.wu@starfivetech.com> References: <20231019053501.46899-1-xingyu.wu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.99.123] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX061.cuchost.com (172.16.6.61) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_PASS,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Wed, 18 Oct 2023 22:35:46 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780160937024759266 X-GMAIL-MSGID: 1780160937024759266 Add bindings for the timer on the JH7110 RISC-V SoC by StarFive Technology Ltd. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Xingyu Wu --- .../bindings/timer/starfive,jh7110-timer.yaml | 96 +++++++++++++++++++ 1 file changed, 96 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml diff --git a/Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml b/Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml new file mode 100644 index 000000000000..9a2dac11eb06 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/starfive,jh7110-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 Timer + +maintainers: + - Xingyu Wu + - Samin Guo + +description: + This timer has four free-running 32 bit counters in StarFive JH7110 SoC. + And each channel(counter) triggers an interrupt when timeout. They support + one-shot mode and continuous-run mode. + +properties: + compatible: + const: starfive,jh7110-timer + + reg: + maxItems: 1 + + interrupts: + items: + - description: channel 0 + - description: channel 1 + - description: channel 2 + - description: channel 3 + + clocks: + items: + - description: timer APB + - description: channel 0 + - description: channel 1 + - description: channel 2 + - description: channel 3 + + clock-names: + items: + - const: apb + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 + + resets: + items: + - description: timer APB + - description: channel 0 + - description: channel 1 + - description: channel 2 + - description: channel 3 + + reset-names: + items: + - const: apb + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - resets + - reset-names + +additionalProperties: false + +examples: + - | + timer@13050000 { + compatible = "starfive,jh7110-timer"; + reg = <0x13050000 0x10000>; + interrupts = <69>, <70>, <71> ,<72>; + clocks = <&clk 124>, + <&clk 125>, + <&clk 126>, + <&clk 127>, + <&clk 128>; + clock-names = "apb", "ch0", "ch1", + "ch2", "ch3"; + resets = <&rst 117>, + <&rst 118>, + <&rst 119>, + <&rst 120>, + <&rst 121>; + reset-names = "apb", "ch0", "ch1", + "ch2", "ch3"; + }; + From patchwork Thu Oct 19 05:35:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xingyu Wu X-Patchwork-Id: 155284 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2010:b0:403:3b70:6f57 with SMTP id fe16csp174665vqb; Wed, 18 Oct 2023 22:36:39 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGRB4Kh6ndnacNstzECDG219xKJpq53hHUq1D8YTVqE2uSiYf6HoHa3hDEe4ojDwH+U7C4z X-Received: by 2002:a05:6359:308b:b0:166:d637:a2db with SMTP id rg11-20020a056359308b00b00166d637a2dbmr950983rwb.9.1697693799451; Wed, 18 Oct 2023 22:36:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697693799; cv=none; d=google.com; s=arc-20160816; b=fwEvSEp7NcLhhrKjG+QGmI/jVgpVrFTbwUNHSMeD9JNDs6DgGErZJ7mIaIUbo57Zxg /KFmzQClDMDUF153V0Z14QM/s1iie0Pa4Bl3QUWEr/XzsT9tCe1zetom9L3uwXw5zkHo /KXzYul0cdP2vj3VvMPMOpq/FGdRR4sgic4xRqzmgCcbvLTivgkGeaFOQflFRrlFz3bX 7OI/zu4Se9eSxLb5CGSgxRW2xXvo/kNO8IQDg8Rk6wli47p+UMIa2qVbUhGLfZasqzL/ +O18gfCRUGwDZURIpcyRlYi2Jfjjyun0OnumrBi2PssULCDHYwqdm1SIz0NgvpmVknGu oqig== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from; bh=QPZ4IvkKSbr2keRSGVMvNxoZBQNTxtLKMZtVzZYc0Kk=; fh=U35VaI2VhNr3pPNfgjXZzjzNImn7EzZodFPICcSprcI=; b=pE1TBCGA8HFqFNYN9n30KJNRfohJHOjFBkmujZVBgFqriVF3ILkuGtF6F5RfNuqMoq Bs5RFz8V1Epzv9K87rW3sNQTPax2ph6iaALIEU21FV4hT+jHK5oNyHrlxjcFhCuqYrcr Skl0GyKEUOq5p5zxLuSqd2qEegX4nBWsDuU1b9IVAKFXo0PHhON1ObLDz9B0G153x3ih 72EKGG9tDgSC1Jif9lZiyj5ynBeGh/HoxxlYvMvsB5UrDR8K92nP3Y/lYw/H+jXJPQOy IGe3eQ2yHg8MtpdBgPwy4ZUa0skHsfWT0uObq8iLe/Y0NWChAjcMz4Fs07FJ+LdFoyAJ 1k0A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from morse.vger.email (morse.vger.email. [23.128.96.31]) by mx.google.com with ESMTPS id s6-20020a625e06000000b006b7f2d74121si5234357pfb.212.2023.10.18.22.36.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 22:36:39 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) client-ip=23.128.96.31; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by morse.vger.email (Postfix) with ESMTP id E25028095F46; Wed, 18 Oct 2023 22:35:35 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at morse.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232632AbjJSFfP convert rfc822-to-8bit (ORCPT + 24 others); Thu, 19 Oct 2023 01:35:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53544 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232614AbjJSFfO (ORCPT ); Thu, 19 Oct 2023 01:35:14 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E12B113A; Wed, 18 Oct 2023 22:35:07 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id 34F3824E1AB; Thu, 19 Oct 2023 13:35:05 +0800 (CST) Received: from EXMBX061.cuchost.com (172.16.6.61) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 19 Oct 2023 13:35:05 +0800 Received: from localhost.localdomain (183.27.99.123) by EXMBX061.cuchost.com (172.16.6.61) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 19 Oct 2023 13:35:04 +0800 From: Xingyu Wu To: Daniel Lezcano , Thomas Gleixner , Emil Renner Berthing , Christophe JAILLET CC: , , "Rob Herring" , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Walker Chen , Xingyu Wu , "Samin Guo" , , "Conor Dooley" Subject: [PATCH v7 2/3] clocksource: Add JH7110 timer driver Date: Thu, 19 Oct 2023 13:35:00 +0800 Message-ID: <20231019053501.46899-3-xingyu.wu@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231019053501.46899-1-xingyu.wu@starfivetech.com> References: <20231019053501.46899-1-xingyu.wu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.99.123] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX061.cuchost.com (172.16.6.61) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Wed, 18 Oct 2023 22:35:35 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780160973079363006 X-GMAIL-MSGID: 1780160973079363006 Add timer driver for the StarFive JH7110 SoC. Signed-off-by: Xingyu Wu --- MAINTAINERS | 7 + drivers/clocksource/Kconfig | 11 + drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-jh7110.c | 380 +++++++++++++++++++++++++++++ 4 files changed, 399 insertions(+) create mode 100644 drivers/clocksource/timer-jh7110.c diff --git a/MAINTAINERS b/MAINTAINERS index 7a7bd8bd80e9..91c09b399131 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20473,6 +20473,13 @@ S: Maintained F: Documentation/devicetree/bindings/sound/starfive,jh7110-tdm.yaml F: sound/soc/starfive/jh7110_tdm.c +STARFIVE JH7110 TIMER DRIVER +M: Samin Guo +M: Xingyu Wu +S: Supported +F: Documentation/devicetree/bindings/timer/starfive,jh7110-timer.yaml +F: drivers/clocksource/timer-jh7110.c + STARFIVE JH71X0 CLOCK DRIVERS M: Emil Renner Berthing M: Hal Feng diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 0ba0dc4ecf06..821abcc1e517 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -641,6 +641,17 @@ config RISCV_TIMER is accessed via both the SBI and the rdcycle instruction. This is required for all RISC-V systems. +config STARFIVE_JH7110_TIMER + bool "Timer for the STARFIVE JH7110 SoC" + depends on ARCH_STARFIVE || COMPILE_TEST + select TIMER_OF + select CLKSRC_MMIO + default ARCH_STARFIVE + help + This enables the timer for StarFive JH7110 SoC. On RISC-V platform, + the system has started RISCV_TIMER, but you can also use this timer + which can provide four channels to do a lot more things on JH7110 SoC. + config CLINT_TIMER bool "CLINT Timer for the RISC-V platform" if COMPILE_TEST depends on GENERIC_SCHED_CLOCK && RISCV diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 368c3461dab8..b66ac05ec086 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -80,6 +80,7 @@ obj-$(CONFIG_INGENIC_TIMER) += ingenic-timer.o obj-$(CONFIG_CLKSRC_ST_LPC) += clksrc_st_lpc.o obj-$(CONFIG_X86_NUMACHIP) += numachip.o obj-$(CONFIG_RISCV_TIMER) += timer-riscv.o +obj-$(CONFIG_STARFIVE_JH7110_TIMER) += timer-jh7110.o obj-$(CONFIG_CLINT_TIMER) += timer-clint.o obj-$(CONFIG_CSKY_MP_TIMER) += timer-mp-csky.o obj-$(CONFIG_GX6605S_TIMER) += timer-gx6605s.o diff --git a/drivers/clocksource/timer-jh7110.c b/drivers/clocksource/timer-jh7110.c new file mode 100644 index 000000000000..71de29a3ec91 --- /dev/null +++ b/drivers/clocksource/timer-jh7110.c @@ -0,0 +1,380 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Starfive JH7110 Timer driver + * + * Copyright (C) 2022-2023 StarFive Technology Co., Ltd. + * + * Author: + * Xingyu Wu + * Samin Guo + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* Bias: Ch0-0x0, Ch1-0x40, Ch2-0x80, and so on. */ +#define JH7110_TIMER_CH_LEN 0x40 +#define JH7110_TIMER_CH_BASE(x) ((x) * JH7110_TIMER_CH_LEN) +#define JH7110_TIMER_CH_MAX 4 + +#define JH7110_CLOCK_SOURCE_RATING 200 +#define JH7110_VALID_BITS 32 +#define JH7110_DELAY_US 0 +#define JH7110_TIMEOUT_US 10000 +#define JH7110_CLOCKEVENT_RATING 300 +#define JH7110_TIMER_MAX_TICKS 0xffffffff +#define JH7110_TIMER_MIN_TICKS 0xf +#define JH7110_TIMER_RELOAD_VALUE 0 + +#define JH7110_TIMER_INT_STATUS 0x00 /* RO[0:4]: Interrupt Status for channel0~4 */ +#define JH7110_TIMER_CTL 0x04 /* RW[0]: 0-continuous run, 1-single run */ +#define JH7110_TIMER_LOAD 0x08 /* RW: load value to counter */ +#define JH7110_TIMER_ENABLE 0x10 /* RW[0]: timer enable register */ +#define JH7110_TIMER_RELOAD 0x14 /* RW: write 1 or 0 both reload counter */ +#define JH7110_TIMER_VALUE 0x18 /* RO: timer value register */ +#define JH7110_TIMER_INT_CLR 0x20 /* RW: timer interrupt clear register */ +#define JH7110_TIMER_INT_MASK 0x24 /* RW[0]: timer interrupt mask register */ + +#define JH7110_TIMER_INT_CLR_ENA BIT(0) +#define JH7110_TIMER_INT_CLR_AVA_MASK BIT(1) + +struct jh7110_clkevt { + struct clock_event_device evt; + struct clocksource cs; + bool cs_is_valid; + struct clk *clk; + struct reset_control *rst; + u32 rate; + u32 reload_val; + void __iomem *base; + char name[sizeof("jh7110-timer.chX")]; +}; + +struct jh7110_timer_priv { + struct clk *pclk; + struct reset_control *prst; + struct jh7110_clkevt clkevt[JH7110_TIMER_CH_MAX]; +}; + +/* 0:continuous-run mode, 1:single-run mode */ +enum jh7110_timer_mode { + JH7110_TIMER_MODE_CONTIN, + JH7110_TIMER_MODE_SINGLE, +}; + +/* Interrupt Mask, 0:Unmask, 1:Mask */ +enum jh7110_timer_int_mask { + JH7110_TIMER_INT_ENA, + JH7110_TIMER_INT_DIS, +}; + +enum jh7110_timer_enable { + JH7110_TIMER_DIS, + JH7110_TIMER_ENA, +}; + +static inline struct jh7110_clkevt *to_jh7110_clkevt(struct clock_event_device *evt) +{ + return container_of(evt, struct jh7110_clkevt, evt); +} + +/* + * BIT(0): Read value represent channel int status. + * Write 1 to this bit to clear interrupt. Write 0 has no effects. + * BIT(1): "1" means that it is clearing interrupt. BIT(0) can not be written. + */ +static inline int jh7110_timer_int_clear(struct jh7110_clkevt *clkevt) +{ + u32 value; + int ret; + + /* Waiting interrupt can be cleared */ + ret = readl_poll_timeout_atomic(clkevt->base + JH7110_TIMER_INT_CLR, value, + !(value & JH7110_TIMER_INT_CLR_AVA_MASK), + JH7110_DELAY_US, JH7110_TIMEOUT_US); + if (!ret) + writel(JH7110_TIMER_INT_CLR_ENA, clkevt->base + JH7110_TIMER_INT_CLR); + + return ret; +} + +static int jh7110_timer_start(struct jh7110_clkevt *clkevt) +{ + int ret; + + /* Disable and clear interrupt first */ + writel(JH7110_TIMER_INT_DIS, clkevt->base + JH7110_TIMER_INT_MASK); + ret = jh7110_timer_int_clear(clkevt); + if (ret) + return ret; + + writel(JH7110_TIMER_INT_ENA, clkevt->base + JH7110_TIMER_INT_MASK); + writel(JH7110_TIMER_ENA, clkevt->base + JH7110_TIMER_ENABLE); + + return 0; +} + +static int jh7110_timer_shutdown(struct clock_event_device *evt) +{ + struct jh7110_clkevt *clkevt = to_jh7110_clkevt(evt); + + writel(JH7110_TIMER_DIS, clkevt->base + JH7110_TIMER_ENABLE); + return jh7110_timer_int_clear(clkevt); +} + +static void jh7110_timer_suspend(struct clock_event_device *evt) +{ + struct jh7110_clkevt *clkevt = to_jh7110_clkevt(evt); + + clkevt->reload_val = readl(clkevt->base + JH7110_TIMER_LOAD); + jh7110_timer_shutdown(evt); +} + +static void jh7110_timer_resume(struct clock_event_device *evt) +{ + struct jh7110_clkevt *clkevt = to_jh7110_clkevt(evt); + + writel(clkevt->reload_val, clkevt->base + JH7110_TIMER_LOAD); + writel(JH7110_TIMER_RELOAD_VALUE, clkevt->base + JH7110_TIMER_RELOAD); + jh7110_timer_start(clkevt); +} + +static int jh7110_timer_tick_resume(struct clock_event_device *evt) +{ + jh7110_timer_resume(evt); + + return 0; +} + +/* IRQ handler for the timer */ +static irqreturn_t jh7110_timer_interrupt(int irq, void *priv) +{ + struct clock_event_device *evt = (struct clock_event_device *)priv; + struct jh7110_clkevt *clkevt = to_jh7110_clkevt(evt); + + if (jh7110_timer_int_clear(clkevt)) + return IRQ_NONE; + + if (evt->event_handler) + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static int jh7110_timer_set_periodic(struct clock_event_device *evt) +{ + struct jh7110_clkevt *clkevt = to_jh7110_clkevt(evt); + u32 periodic = DIV_ROUND_CLOSEST(clkevt->rate, HZ); + + writel(JH7110_TIMER_MODE_CONTIN, clkevt->base + JH7110_TIMER_CTL); + writel(periodic, clkevt->base + JH7110_TIMER_LOAD); + + return jh7110_timer_start(clkevt); +} + +static int jh7110_timer_set_oneshot(struct clock_event_device *evt) +{ + struct jh7110_clkevt *clkevt = to_jh7110_clkevt(evt); + + writel(JH7110_TIMER_MODE_SINGLE, clkevt->base + JH7110_TIMER_CTL); + writel(JH7110_TIMER_MAX_TICKS, clkevt->base + JH7110_TIMER_LOAD); + + return jh7110_timer_start(clkevt); +} + +static int jh7110_timer_set_next_event(unsigned long next, + struct clock_event_device *evt) +{ + struct jh7110_clkevt *clkevt = to_jh7110_clkevt(evt); + + writel(JH7110_TIMER_MODE_SINGLE, clkevt->base + JH7110_TIMER_CTL); + writel(next, clkevt->base + JH7110_TIMER_LOAD); + + return jh7110_timer_start(clkevt); +} + +static void jh7110_set_clockevent(struct clock_event_device *evt) +{ + evt->features = CLOCK_EVT_FEAT_PERIODIC | + CLOCK_EVT_FEAT_ONESHOT | + CLOCK_EVT_FEAT_DYNIRQ; + evt->set_state_shutdown = jh7110_timer_shutdown; + evt->set_state_periodic = jh7110_timer_set_periodic; + evt->set_state_oneshot = jh7110_timer_set_oneshot; + evt->set_state_oneshot_stopped = jh7110_timer_shutdown; + evt->tick_resume = jh7110_timer_tick_resume; + evt->set_next_event = jh7110_timer_set_next_event; + evt->suspend = jh7110_timer_suspend; + evt->resume = jh7110_timer_resume; + evt->rating = JH7110_CLOCKEVENT_RATING; +} + +static u64 jh7110_timer_clocksource_read(struct clocksource *cs) +{ + struct jh7110_clkevt *clkevt = container_of(cs, struct jh7110_clkevt, cs); + + return (u64)readl(clkevt->base + JH7110_TIMER_VALUE); +} + +static int jh7110_clocksource_init(struct jh7110_clkevt *clkevt) +{ + int ret; + + clkevt->cs.name = clkevt->name; + clkevt->cs.rating = JH7110_CLOCK_SOURCE_RATING; + clkevt->cs.read = jh7110_timer_clocksource_read; + clkevt->cs.mask = CLOCKSOURCE_MASK(JH7110_VALID_BITS); + clkevt->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS; + + ret = clocksource_register_hz(&clkevt->cs, clkevt->rate); + if (ret) + return ret; + + clkevt->cs_is_valid = true; /* clocksource register done */ + writel(JH7110_TIMER_MODE_CONTIN, clkevt->base + JH7110_TIMER_CTL); + writel(JH7110_TIMER_MAX_TICKS, clkevt->base + JH7110_TIMER_LOAD); + + return jh7110_timer_start(clkevt); +} + +static void jh7110_clockevents_register(struct jh7110_clkevt *clkevt) +{ + clkevt->rate = clk_get_rate(clkevt->clk); + + jh7110_set_clockevent(&clkevt->evt); + clkevt->evt.name = clkevt->name; + clkevt->evt.cpumask = cpu_possible_mask; + + clockevents_config_and_register(&clkevt->evt, clkevt->rate, + JH7110_TIMER_MIN_TICKS, JH7110_TIMER_MAX_TICKS); +} + +static void jh7110_timer_release(void *data) +{ + struct jh7110_timer_priv *priv = data; + int i; + + for (i = 0; i < JH7110_TIMER_CH_MAX; i++) { + /* Disable each channel of timer */ + if (priv->clkevt[i].base) + writel(JH7110_TIMER_DIS, priv->clkevt[i].base + JH7110_TIMER_ENABLE); + + /* Avoid no initialization in the loop of the probe */ + if (!IS_ERR_OR_NULL(priv->clkevt[i].rst)) + reset_control_assert(priv->clkevt[i].rst); + + if (priv->clkevt[i].cs_is_valid) + clocksource_unregister(&priv->clkevt[i].cs); + } + + reset_control_assert(priv->prst); +} + +static int jh7110_timer_probe(struct platform_device *pdev) +{ + struct jh7110_timer_priv *priv; + struct jh7110_clkevt *clkevt; + char name[sizeof("chX")]; + int ch; + int ret; + void __iomem *base; + + priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return dev_err_probe(&pdev->dev, PTR_ERR(base), + "failed to map registers\n"); + + priv->prst = devm_reset_control_get_exclusive(&pdev->dev, "apb"); + if (IS_ERR(priv->prst)) + return dev_err_probe(&pdev->dev, PTR_ERR(priv->prst), + "failed to get apb reset\n"); + + priv->pclk = devm_clk_get_enabled(&pdev->dev, "apb"); + if (IS_ERR(priv->pclk)) + return dev_err_probe(&pdev->dev, PTR_ERR(priv->pclk), + "failed to get & enable apb clock\n"); + + ret = reset_control_deassert(priv->prst); + if (ret) + return dev_err_probe(&pdev->dev, ret, "failed to deassert apb reset\n"); + + ret = devm_add_action_or_reset(&pdev->dev, jh7110_timer_release, priv); + if (ret) + return ret; + + for (ch = 0; ch < JH7110_TIMER_CH_MAX; ch++) { + clkevt = &priv->clkevt[ch]; + snprintf(name, sizeof(name), "ch%d", ch); + + clkevt->base = base + JH7110_TIMER_CH_BASE(ch); + /* Ensure timer is disabled */ + writel(JH7110_TIMER_DIS, clkevt->base + JH7110_TIMER_ENABLE); + + clkevt->rst = devm_reset_control_get_exclusive(&pdev->dev, name); + if (IS_ERR(clkevt->rst)) + return PTR_ERR(clkevt->rst); + + clkevt->clk = devm_clk_get_enabled(&pdev->dev, name); + if (IS_ERR(clkevt->clk)) + return PTR_ERR(clkevt->clk); + + ret = reset_control_deassert(clkevt->rst); + if (ret) + return ret; + + clkevt->evt.irq = platform_get_irq(pdev, ch); + if (clkevt->evt.irq < 0) + return clkevt->evt.irq; + + snprintf(clkevt->name, sizeof(clkevt->name), "jh7110-timer.ch%d", ch); + jh7110_clockevents_register(clkevt); + + ret = devm_request_irq(&pdev->dev, clkevt->evt.irq, jh7110_timer_interrupt, + IRQF_TIMER | IRQF_IRQPOLL, + clkevt->name, &clkevt->evt); + if (ret) + return ret; + + ret = jh7110_clocksource_init(clkevt); + if (ret) + return ret; + } + + return 0; +} + +static const struct of_device_id jh7110_timer_match[] = { + { .compatible = "starfive,jh7110-timer", }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, jh7110_timer_match); + +static struct platform_driver jh7110_timer_driver = { + .probe = jh7110_timer_probe, + .driver = { + .name = "jh7110-timer", + .of_match_table = jh7110_timer_match, + }, +}; +module_platform_driver(jh7110_timer_driver); + +MODULE_AUTHOR("Xingyu Wu "); +MODULE_DESCRIPTION("StarFive JH7110 timer driver"); +MODULE_LICENSE("GPL"); From patchwork Thu Oct 19 05:35:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xingyu Wu X-Patchwork-Id: 155283 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2010:b0:403:3b70:6f57 with SMTP id fe16csp174573vqb; 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[2620:137:e000::3:5]) by mx.google.com with ESMTPS id b22-20020a639316000000b00589ab0ae2edsi2466609pge.649.2023.10.18.22.36.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 22:36:21 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) client-ip=2620:137:e000::3:5; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:5 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by groat.vger.email (Postfix) with ESMTP id 8B3318108BC2; Wed, 18 Oct 2023 22:36:17 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at groat.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232601AbjJSFfp convert rfc822-to-8bit (ORCPT + 24 others); Thu, 19 Oct 2023 01:35:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46838 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232690AbjJSFfY (ORCPT ); Thu, 19 Oct 2023 01:35:24 -0400 Received: from ex01.ufhost.com (ex01.ufhost.com [61.152.239.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3E3E713A; Wed, 18 Oct 2023 22:35:21 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by ex01.ufhost.com (Postfix) with ESMTP id F075F24E202; Thu, 19 Oct 2023 13:35:05 +0800 (CST) Received: from EXMBX061.cuchost.com (172.16.6.61) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 19 Oct 2023 13:35:05 +0800 Received: from localhost.localdomain (183.27.99.123) by EXMBX061.cuchost.com (172.16.6.61) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Thu, 19 Oct 2023 13:35:04 +0800 From: Xingyu Wu To: Daniel Lezcano , Thomas Gleixner , Emil Renner Berthing , Christophe JAILLET CC: , , "Rob Herring" , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Philipp Zabel , Walker Chen , Xingyu Wu , "Samin Guo" , , "Conor Dooley" Subject: [PATCH v7 3/3] riscv: dts: jh7110: starfive: Add timer node Date: Thu, 19 Oct 2023 13:35:01 +0800 Message-ID: <20231019053501.46899-4-xingyu.wu@starfivetech.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20231019053501.46899-1-xingyu.wu@starfivetech.com> References: <20231019053501.46899-1-xingyu.wu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [183.27.99.123] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX061.cuchost.com (172.16.6.61) X-YovoleRuleAgent: yovoleflag X-Spam-Status: No, score=-0.8 required=5.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Wed, 18 Oct 2023 22:36:17 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780160954887300855 X-GMAIL-MSGID: 1780160954887300855 Add the timer node for the Starfive JH7110 SoC. Reviewed-by: Emil Renner Berthing Reviewed-by: Walker Chen Signed-off-by: Xingyu Wu --- arch/riscv/boot/dts/starfive/jh7110.dtsi | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index e85464c328d0..76062130d26e 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -811,6 +811,26 @@ sysgpio: pinctrl@13040000 { #gpio-cells = <2>; }; + timer@13050000 { + compatible = "starfive,jh7110-timer"; + reg = <0x0 0x13050000 0x0 0x10000>; + interrupts = <69>, <70>, <71>, <72>; + clocks = <&syscrg JH7110_SYSCLK_TIMER_APB>, + <&syscrg JH7110_SYSCLK_TIMER0>, + <&syscrg JH7110_SYSCLK_TIMER1>, + <&syscrg JH7110_SYSCLK_TIMER2>, + <&syscrg JH7110_SYSCLK_TIMER3>; + clock-names = "apb", "ch0", "ch1", + "ch2", "ch3"; + resets = <&syscrg JH7110_SYSRST_TIMER_APB>, + <&syscrg JH7110_SYSRST_TIMER0>, + <&syscrg JH7110_SYSRST_TIMER1>, + <&syscrg JH7110_SYSRST_TIMER2>, + <&syscrg JH7110_SYSRST_TIMER3>; + reset-names = "apb", "ch0", "ch1", + "ch2", "ch3"; + }; + watchdog@13070000 { compatible = "starfive,jh7110-wdt"; reg = <0x0 0x13070000 0x0 0x10000>;