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Signed-off-by: Inochi Amaoto Acked-by: Krzysztof Kozlowski Reviewed-by: Jisheng Zhang --- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 + 1 file changed, 1 insertion(+) -- 2.42.0 diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index 0c07e8dda445..709b2211276b 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -66,6 +66,7 @@ properties: - enum: - allwinner,sun20i-d1-plic - sophgo,cv1800b-plic + - sophgo,cv1812h-plic - sophgo,sg2042-plic - thead,th1520-plic - const: thead,c900-plic From patchwork Wed Oct 18 23:18:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Inochi Amaoto X-Patchwork-Id: 155226 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2010:b0:403:3b70:6f57 with SMTP id fe16csp53015vqb; Wed, 18 Oct 2023 16:20:21 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEr0MDnIK3AvTv2FQbhqL7QDZGivgAKNA2tjlU+6dTAZuajS+tJ9pcuLeev+TjftYGh+dDF X-Received: by 2002:a05:6a00:2d86:b0:68e:2c2a:5172 with SMTP id fb6-20020a056a002d8600b0068e2c2a5172mr424093pfb.6.1697671220878; Wed, 18 Oct 2023 16:20:20 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1697671220; cv=pass; d=google.com; s=arc-20160816; b=iWS9mZ5YEH9WAUHgrFgLF3Ug0l+Zg8XB5wV70SyPeaWqGOYk4yJCLS3bqipYi1Iiwk ZxQA6kmo9fGnmzvmnDci0YkcU69aTbBnJGOLPp6sWbTA0yt+3D1Jryo/Oafkc9FHAMZf iYUrarzuLurjkUFyaFe4KB3v8fGOoqzois9HCBpQ0bUWLb1Q7DmkGNaiblyw76PvbKF5 VMrkEafIvGtY/igt55ptYfPjAwZgc9mp86YTyqvmA3wuFSRw5kXD7WBhTkjMcNZLgj/f tclNrFq6Kz1kkz977oJ2Wj5pVCni31x6XTMLqBc7zsFUP5E+9yyQkZ3TypeHcLPvVCvS PedA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:content-transfer-encoding :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=uRHRodl38TgXozx4mNNUVZhGvvZTDSwVmIIt8xnJlBc=; fh=TOYRKfFdMWmuuRQZLsHz4AMUohL9vbqDwviKQHwrGy0=; b=zBNKNJQ4h2cpWWd4ZZobDXGfJTiPwVC0/mchqanqFH+cfnkCA+Jek6TKZstrE6T5Xj LNwM9jwxVzn21qyi18nuIOVy0x2eNKXa/20bw8jjVi5QgHPXTn3vnknsjCHWmX2XNG7S uccyw8qw/3PKHzaXZ8IysTrjNkJqHMCU4QFhI/rgOfA/GkKOzPOpENyypYGPTjQ3La5k +JInZaG7Ac87SvPodqJG+RbYmpIMZQ1EycNmmL5wzj0QjP0jmHrYXSHGg3DbhcJATNXR dzFRmjQ5ikgUK11dOkJVHfoGX3vZH9KgOVOzqfRafs2webcX3/VyQ69MjpbTpom4oyrU 4WNA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@outlook.com header.s=selector1 header.b=JQgrNSxO; arc=pass (i=1); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=outlook.com Received: from pete.vger.email (pete.vger.email. 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Signed-off-by: Inochi Amaoto Acked-by: Krzysztof Kozlowski Reviewed-by: Jisheng Zhang --- Documentation/devicetree/bindings/timer/sifive,clint.yaml | 1 + 1 file changed, 1 insertion(+) -- 2.42.0 diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index e8be6c470364..4b6c20fc8194 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -38,6 +38,7 @@ properties: - enum: - allwinner,sun20i-d1-clint - sophgo,cv1800b-clint + - sophgo,cv1812h-clint - thead,th1520-clint - const: thead,c900-clint - items: From patchwork Wed Oct 18 23:18:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Inochi Amaoto X-Patchwork-Id: 155230 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2010:b0:403:3b70:6f57 with SMTP id fe16csp53712vqb; Wed, 18 Oct 2023 16:22:06 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEVQIqa5TBzQZRpKDF8xXkqpHfpvdVEgI9vpqU7dCSHfZU9NBzCNJvKD7UdCjeDAMOPwmy9 X-Received: by 2002:a17:902:f54d:b0:1ca:42b:f625 with SMTP id h13-20020a170902f54d00b001ca042bf625mr494178plf.3.1697671325783; Wed, 18 Oct 2023 16:22:05 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1697671325; cv=pass; d=google.com; s=arc-20160816; b=ShYQhAAZ3qP5YKLEvdxwC+5FKmS7qDouEgn0HZvRcbnI5f7X38iLiNfK84ZkS3u8rh Th4qGQqIjMXVynybEfCtfEUOmGPMR2DUz2ByV2Yw/Ybqx36pEuwjVgCsGjBjfp0oLZQN zXtxzj4VTSJDulYD+JL9q7WBkKOgVX+4v4ZoCre7JunDd/7TxnSLU08mKtT5V6OEKJ2c YX4PCwPdioLRNlwnjyKpAFvNugCsgTFHeCzSWpEnIM7knc9VZVQPgXyVvATv0BIeTW2B jEq0hcEhHuj/EXP+DicxxOVA62J34k4GcPtm2q0Ia/QUnYZeRPFCxMSm4iUDjHvxD4UI NqHg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:content-transfer-encoding :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=XeYWlTYaJOGIiEWkZu5rFXcX7Q/TSa/S03ztRgroNyI=; fh=TFCuo3H0p15go8eBjf4wMXGadIOTKJuSg78Jlhs/YnE=; b=C6ILB1IS/Ne1wIKxancQ69NfraE01vZ6mLBIhUSCdvGfh/KpryKnwZCqs/QM71MAJU +HoA+lWzxuJW0OHujT6oJXwSyIzryjpcwLmkd+UcMPId5yVt0Mr+GMn9NCCj5Hu19v02 p+ZWhXasaF+WWWQLNs3l4tn7zNUujFBSsPOkQdwtRntIBQIukX6ZlfeA5b/5bIpGDiLA rewowdeFR8+jXfb0Twstw1lX/yTE9hxBVkYTJ9t0DdMV3+pmBscPaKDAUaO0DSovZMAg jUejjphAZG3Y5+8fr71k0qa5STngATM4HIMYRoUge6JzpSsNH0nqTW+khG+PSVdt2gF2 62Dg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@outlook.com header.s=selector1 header.b=CW8XLf9M; arc=pass (i=1); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:6 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=outlook.com Received: from pete.vger.email (pete.vger.email. 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Wed, 18 Oct 2023 16:22:00 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780137408233249196 X-GMAIL-MSGID: 1780137408233249196 Document the compatible strings for the SOPHGO Huashan Pi board which uses the SOPHGO CV1812H SoC. Signed-off-by: Inochi Amaoto Link: https://en.sophgo.com/product/introduce/huashan.html Link: https://en.sophgo.com/product/introduce/cv181xH.html Acked-by: Chen Wang Acked-by: Krzysztof Kozlowski Reviewed-by: Jisheng Zhang --- Documentation/devicetree/bindings/riscv/sophgo.yaml | 4 ++++ 1 file changed, 4 insertions(+) -- 2.42.0 diff --git a/Documentation/devicetree/bindings/riscv/sophgo.yaml b/Documentation/devicetree/bindings/riscv/sophgo.yaml index 86748c5390be..9bc813dad098 100644 --- a/Documentation/devicetree/bindings/riscv/sophgo.yaml +++ b/Documentation/devicetree/bindings/riscv/sophgo.yaml @@ -22,6 +22,10 @@ properties: - enum: - milkv,duo - const: sophgo,cv1800b + - items: + - enum: + - sophgo,huashan-pi + - const: sophgo,cv1812h - items: - enum: - milkv,pioneer From patchwork Wed Oct 18 23:18:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Inochi Amaoto X-Patchwork-Id: 155228 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2010:b0:403:3b70:6f57 with SMTP id fe16csp53475vqb; Wed, 18 Oct 2023 16:21:27 -0700 (PDT) X-Google-Smtp-Source: AGHT+IE64mZkQPDWKZi36iNuIvHpJta0q4wYVCgPWY2IfUlGDFIFUeECzw/U3a1hClzRmkBT7Y2M X-Received: by 2002:a17:903:228c:b0:1ca:296d:8ff6 with SMTP id b12-20020a170903228c00b001ca296d8ff6mr1046105plh.38.1697671287206; Wed, 18 Oct 2023 16:21:27 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1697671287; cv=pass; d=google.com; s=arc-20160816; b=EkQrz4lGVz2DeNqSDpRScV2Axr91QkeLzOO9b332cF7h3JH/IdWNL2dcxOS9xRoIC8 k8U3xw6jYG0Ws/EXKNr0TEDmvtSNbpASv3UgWkx9oYdwSEPOPg33jg6aMSN+y4zaLDw2 PgBtI2iR9dE9auxg8wYEDFIZHeKF3VnZrlYHFfOa5jQGDiLBbwqEvoO9w2GwGHQssK2x Tw4xoxW/5aqwR5bVxBOCYdaxCmAFNyo8Z/LxpbJdqxxQUqa7q+w5eDyRgkEC2y4cZh4s YBPsV9Ye6ptoa72ykRlJ/HgklboIWO6BIVH482tS+w+tOWFysUO6BZqmMhtwn4kuL02X UXQw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:content-transfer-encoding :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Ndkk0zNLuRzhXI9J7ATcjm1Eti7mSm6Qk3vViwryehk=; fh=OGvOkw3MWgiYZScLOy2UnDebf3bUtwJu/JxyM869cd4=; b=C3/igb1O8Am7suEaYEeA1+zr4sBUTQ1wrDb/qLzBMvI/02oNThqRjUxtJCoYYRhLYa 9NLrPucXiPsaI9TNQMoaGAgvauBvQom1ks0b788QO7gRkHbv7vG5DZA9QabRu81WRg49 +a5Nk25WJEDsdaLuTO3kylhyGVNzIOVfwl4cym2ziS3cEKZnk7/abNErXpSC6oAGWIqu 8hKftHQ/PnCTUATv+f/6s7N3JrqPrQoQjLM3G9LPRf1iM07OWb6+6kaYb6MJT/Iy2hLx koTR6dcJ+9UFUeyGj2Xs4RwbzvfbcyBG3UvR0siZU/fyppEXXOsZcp430byiTE2bd6ZV FbnA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@outlook.com header.s=selector1 header.b=kxQMq33o; arc=pass (i=1); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.34 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=outlook.com Received: from howler.vger.email (howler.vger.email. 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Wed, 18 Oct 2023 16:21:15 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780137367556302626 X-GMAIL-MSGID: 1780137367556302626 As CV180x and CV181x have the identical layouts, it is OK to use the cv1800b basic device tree for the whole series. For CV1800B soc specific compatible, just move them out of the common file. Signed-off-by: Inochi Amaoto Acked-by: Chen Wang --- arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 119 ++--------------------- arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 120 ++++++++++++++++++++++++ 2 files changed, 127 insertions(+), 112 deletions(-) create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx.dtsi -- 2.42.0 diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi index df40e87ee063..165e9e320a8c 100644 --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi @@ -3,121 +3,16 @@ * Copyright (C) 2023 Jisheng Zhang */ -#include +#include "cv18xx.dtsi" / { compatible = "sophgo,cv1800b"; - #address-cells = <1>; - #size-cells = <1>; - - cpus: cpus { - #address-cells = <1>; - #size-cells = <0>; - timebase-frequency = <25000000>; - - cpu0: cpu@0 { - compatible = "thead,c906", "riscv"; - device_type = "cpu"; - reg = <0>; - d-cache-block-size = <64>; - d-cache-sets = <512>; - d-cache-size = <65536>; - i-cache-block-size = <64>; - i-cache-sets = <128>; - i-cache-size = <32768>; - mmu-type = "riscv,sv39"; - riscv,isa = "rv64imafdc"; - riscv,isa-base = "rv64i"; - riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", - "zifencei", "zihpm"; - - cpu0_intc: interrupt-controller { - compatible = "riscv,cpu-intc"; - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <1>; - }; - }; - }; - - osc: oscillator { - compatible = "fixed-clock"; - clock-output-names = "osc_25m"; - #clock-cells = <0>; - }; - - soc { - compatible = "simple-bus"; - interrupt-parent = <&plic>; - #address-cells = <1>; - #size-cells = <1>; - dma-noncoherent; - ranges; - - uart0: serial@4140000 { - compatible = "snps,dw-apb-uart"; - reg = <0x04140000 0x100>; - interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart1: serial@4150000 { - compatible = "snps,dw-apb-uart"; - reg = <0x04150000 0x100>; - interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart2: serial@4160000 { - compatible = "snps,dw-apb-uart"; - reg = <0x04160000 0x100>; - interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart3: serial@4170000 { - compatible = "snps,dw-apb-uart"; - reg = <0x04170000 0x100>; - interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; - - uart4: serial@41c0000 { - compatible = "snps,dw-apb-uart"; - reg = <0x041c0000 0x100>; - interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&osc>; - reg-shift = <2>; - reg-io-width = <4>; - status = "disabled"; - }; +}; - plic: interrupt-controller@70000000 { - compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; - reg = <0x70000000 0x4000000>; - interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; - interrupt-controller; - #address-cells = <0>; - #interrupt-cells = <2>; - riscv,ndev = <101>; - }; +&plic { + compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; +}; - clint: timer@74000000 { - compatible = "sophgo,cv1800b-clint", "thead,c900-clint"; - reg = <0x74000000 0x10000>; - interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>; - }; - }; +&clint { + compatible = "sophgo,cv1800b-clint", "thead,c900-clint"; }; diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi new file mode 100644 index 000000000000..55d4bc84faa0 --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 Jisheng Zhang + */ + +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <25000000>; + + cpu0: cpu@0 { + compatible = "thead,c906", "riscv"; + device_type = "cpu"; + reg = <0>; + d-cache-block-size = <64>; + d-cache-sets = <512>; + d-cache-size = <65536>; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <32768>; + mmu-type = "riscv,sv39"; + riscv,isa = "rv64imafdc"; + riscv,isa-base = "rv64i"; + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", + "zifencei", "zihpm"; + + cpu0_intc: interrupt-controller { + compatible = "riscv,cpu-intc"; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + }; + }; + + osc: oscillator { + compatible = "fixed-clock"; + clock-output-names = "osc_25m"; + #clock-cells = <0>; + }; + + soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; + #address-cells = <1>; + #size-cells = <1>; + dma-noncoherent; + ranges; + + uart0: serial@4140000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04140000 0x100>; + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart1: serial@4150000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04150000 0x100>; + interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart2: serial@4160000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04160000 0x100>; + interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial@4170000 { + compatible = "snps,dw-apb-uart"; + reg = <0x04170000 0x100>; + interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart4: serial@41c0000 { + compatible = "snps,dw-apb-uart"; + reg = <0x041c0000 0x100>; + interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&osc>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + plic: interrupt-controller@70000000 { + reg = <0x70000000 0x4000000>; + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <2>; + riscv,ndev = <101>; + }; + + clint: timer@74000000 { + reg = <0x74000000 0x10000>; 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Wed, 18 Oct 2023 16:21:30 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780137388589340681 X-GMAIL-MSGID: 1780137388589340681 Add common GPIO devices for the CV180x and CV181x soc. Signed-off-by: Inochi Amaoto Reviewed-by: Jisheng Zhang Acked-by: Chen Wang --- arch/riscv/boot/dts/sophgo/cv18xx.dtsi | 73 ++++++++++++++++++++++++++ 1 file changed, 73 insertions(+) -- 2.42.0 diff --git a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi index 55d4bc84faa0..d415cc758def 100644 --- a/arch/riscv/boot/dts/sophgo/cv18xx.dtsi +++ b/arch/riscv/boot/dts/sophgo/cv18xx.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: (GPL-2.0 OR MIT) /* * Copyright (C) 2023 Jisheng Zhang + * Copyright (C) 2023 Inochi Amaoto */ #include @@ -53,6 +54,78 @@ soc { dma-noncoherent; ranges; + gpio0: gpio@3020000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x3020000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + porta: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <60 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gpio1: gpio@3021000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x3021000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + portb: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <61 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gpio2: gpio@3022000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x3022000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + portc: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <62 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + gpio3: gpio@3023000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x3023000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + + portd: gpio-controller@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; + ngpios = <32>; + reg = <0>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <63 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + uart0: serial@4140000 { compatible = "snps,dw-apb-uart"; reg = <0x04140000 0x100>; From patchwork Wed Oct 18 23:18:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Inochi Amaoto X-Patchwork-Id: 155231 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2010:b0:403:3b70:6f57 with SMTP id fe16csp53838vqb; Wed, 18 Oct 2023 16:22:29 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGQWoIsZyKpL2rbt8VbIwqX7mPuXbPub/MNHF8BMn91yD1NTRZ27KtcHIVsptOWHvfH0Zdv X-Received: by 2002:a17:903:6cd:b0:1c8:91d8:d5c5 with SMTP id kj13-20020a17090306cd00b001c891d8d5c5mr810710plb.55.1697671349540; Wed, 18 Oct 2023 16:22:29 -0700 (PDT) ARC-Seal: i=2; a=rsa-sha256; t=1697671349; cv=pass; d=google.com; s=arc-20160816; b=wajwz3aMUD8JEUNEYCpUuMuHgle/Uk4kn766LH/o1Sw5PVlcvMPmg4HRSOHFUJNuIK JExx8xuoECiTuJxhbbvDkXgBVZiF2d0e1z05Gu0kFj+d+SC9Lq1XPIwmK/gF+G1xtKvH RFBXSrj7ALHJZsjiEZaLgUbcNvnl4tkHQPmwBjEUk4687Sg3k9dcrZ89doqbUdB54aF6 ZjGX0tGSnP+112dJ5T9nuM9P9IGKrdGwD8NFWIjcwPOfS0AZFGilJg6C91ocSbUVDeUC 1qymIexMz8IgcM3X8Ag5KlZKE5HK3zzItzeoptRSdx3tQu2wU9syqTMaQZarmhZu2sZh ICgQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:mime-version:content-transfer-encoding :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=wxdFQHva1tIfHsLwtonuuEUHgRqniT4rOOd7FVoCvqE=; fh=OGvOkw3MWgiYZScLOy2UnDebf3bUtwJu/JxyM869cd4=; b=OtQHl35xM5FqXOk+qU14midbOyLX5ZF7XSuQQ4hAja2+IxpeADEApmwlKKk9o5xIoW AeEI0majEhrXV1EbKmkajJjnORmBqs8xB92R5PaA5IzslA08TccJMCfFMTFxTYFc0p5J jASK1CpFm+6pGWSS5KgHsV5guH9XkyU6wjW648lm5/nops/BVf4xG9RYUlTTjS4SSOc/ bq8hxTDqJxIjCtFOs/3FpyelqzoC/DyataOG7MzPNcYZEv6Ew+nYM6eEB8MmEsiZQJR2 kzrAPFnCK8jETKqJZMh2QpcFbZt+ycMrAcdq5cbgQlhSwiTLAAiM1EPl1J47sH6A8Uxg mDpA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@outlook.com header.s=selector1 header.b="svR9+i3/"; arc=pass (i=1); spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=outlook.com Received: from agentk.vger.email (agentk.vger.email. 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Wed, 18 Oct 2023 16:22:22 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780137432867501285 X-GMAIL-MSGID: 1780137432867501285 Add initial device tree files for the Huashan Pi board. Note: The boot of CV1812H chip needs a rtos firmware for coprocessor to function properly. To make the soc happy, reserved the last 2M memory for the rtos firmware. Signed-off-by: Inochi Amaoto Link: https://en.sophgo.com/product/introduce/huashan.html Link: https://en.sophgo.com/product/introduce/cv181xH.html Link: https://github.com/milkv-duo/duo-buildroot-sdk/blob/develop/build/boards/cv181x/cv1812h_wevb_0007a_emmc_huashan/memmap.py#L15 Reviewed-by: Jisheng Zhang Acked-by: Chen Wang --- arch/riscv/boot/dts/sophgo/Makefile | 1 + .../boot/dts/sophgo/cv1812h-huashan-pi.dts | 48 +++++++++++++++++++ 2 files changed, 49 insertions(+) create mode 100644 arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts -- 2.42.0 diff --git a/arch/riscv/boot/dts/sophgo/Makefile b/arch/riscv/boot/dts/sophgo/Makefile index 3fb65512c631..57ad82a61ea6 100644 --- a/arch/riscv/boot/dts/sophgo/Makefile +++ b/arch/riscv/boot/dts/sophgo/Makefile @@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_ARCH_SOPHGO) += cv1800b-milkv-duo.dtb +dtb-$(CONFIG_ARCH_SOPHGO) += cv1812h-huashan-pi.dtb dtb-$(CONFIG_ARCH_SOPHGO) += sg2042-milkv-pioneer.dtb diff --git a/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts b/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts new file mode 100644 index 000000000000..aa361f3a86bb --- /dev/null +++ b/arch/riscv/boot/dts/sophgo/cv1812h-huashan-pi.dts @@ -0,0 +1,48 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 Inochi Amaoto + */ + +/dts-v1/; + +#include "cv1812h.dtsi" + +/ { + model = "Huashan Pi"; + compatible = "sophgo,huashan-pi", "sophgo,cv1812h"; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + serial4 = &uart4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + coprocessor_rtos: region@8fe00000 { + reg = <0x8fe00000 0x200000>; + no-map; + }; + }; +}; + +&osc { + clock-frequency = <25000000>; +}; + +&uart0 { + status = "okay"; +};