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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id i3-20020a37c203000000b00776b91c0b1esi2329875qkm.23.2023.10.18.01.10.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Oct 2023 01:10:55 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=lkwy1XcD; arc=pass (i=1); spf=pass (google.com: domain of gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 864D9385B513 for ; Wed, 18 Oct 2023 08:10:55 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.24]) by sourceware.org (Postfix) with ESMTPS id C83143858CDB for ; Wed, 18 Oct 2023 08:10:24 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org C83143858CDB Authentication-Results: sourceware.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=intel.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org C83143858CDB Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=134.134.136.24 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1697616628; cv=none; b=m2tncjvVw9sgSo8hq0XkvMYvHZL7L4aQ1L7FKHAx+2+KUp23ojUgonWk9kxx9kQpJfiB5p4ensKwJtmjAy9WFiSneImN1PrOCLnCbDfIJdpGE91H4XXO5a5o88gw5fO7lEWwHHfmnrYCY8n+OAqip09xWjlKaVwcmU4NAsPhIkA= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1697616628; c=relaxed/simple; bh=YsDrpQe8PiAJ1tUmB5Ze7KZ/bgizxaSeN4Ds5KVAelw=; h=DKIM-Signature:From:To:Subject:Date:Message-Id:MIME-Version; b=pBElCv5vWoTPldTPQ3Eu51kcqXDuhbV4xLdqZ5KDvO2Qbo/W0pGv8vIrA8/47Ti9POUnKgBCXi08roDHnz8vhXAxl26n2fyFZ248GSg2JLyxIq+6adYn32oEolLKRFdK4n7WHqzw42jWNlriwqsfF1eKN2Z8rIIcwXosEkzHfM4= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1697616624; x=1729152624; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=YsDrpQe8PiAJ1tUmB5Ze7KZ/bgizxaSeN4Ds5KVAelw=; b=lkwy1XcDLd3zyt1XqYUpiw2r/ZVxZo9zqIb6GF1RkHnXjEFcAz3A2evX GzwkwEPLeVJ3+VEnT3dXzdUwRwQiK4sErg7V7Q5IFbElZmTltIA8ZvXjZ gOqkugYpTlmxldj+UaM5KaAMVgNptyv/drAlpS6ojY4sBArkp7ZCIWtQc Fv6UBk/4SUkcwFXzZEJBlNeU3S0MTvQl1uiH7I/Qs8AVKU9fmTQ3Fx7Tq XfUNQd26QLa+uYPvW9IwQjcRExVylh2M+Xve7j1ldkaXddgyopExPwaok lMS2Cepe4JTzWrq/1iI68ubwQSwCojwRAW3vpTkb0H5k2KDENgezJcZRS Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10866"; a="388827746" X-IronPort-AV: E=Sophos;i="6.03,234,1694761200"; d="scan'208";a="388827746" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Oct 2023 01:10:23 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10866"; a="706342182" X-IronPort-AV: E=Sophos;i="6.03,234,1694761200"; d="scan'208";a="706342182" Received: from shvmail03.sh.intel.com ([10.239.245.20]) by orsmga003.jf.intel.com with ESMTP; 18 Oct 2023 01:10:21 -0700 Received: from shliclel4217.sh.intel.com (shliclel4217.sh.intel.com [10.239.240.127]) by shvmail03.sh.intel.com (Postfix) with ESMTP id C93111005706; Wed, 18 Oct 2023 16:10:20 +0800 (CST) From: Haochen Jiang To: gcc-patches@gcc.gnu.org Cc: ubizjak@gmail.com, hongtao.liu@intel.com Subject: [PATCH] x86: Correct ISA enabled for clients since Arrow Lake Date: Wed, 18 Oct 2023 16:10:20 +0800 Message-Id: <20231018081020.1919314-1-haochen.jiang@intel.com> X-Mailer: git-send-email 2.31.1 MIME-Version: 1.0 X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP, UPPERCASE_50_75 autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780080082484369094 X-GMAIL-MSGID: 1780080082484369094 Hi all, I just found that since ISAs enabled on Sierra Forest changed, clients since Arrow Lake will wrongly enable ENQCMD according to the current code. To avoid messing up again in the future, I changed the dependency on how ISAs are enabled currently by making clients depending on clients and Atom servers depending on Atom servers, which makes no functionality difference on Clearwater Forest. Also, revise the current out of date documentation in texi file. Regtested on x86_64-pc-linux-gnu. Ok for trunk? Thx, Haochen gcc/ChangeLog: * config/i386/i386.h: Correct the ISA enabled for Arrow Lake. Also make Clearwater Forest depends on Sierra Forest. * doc/invoke.texi: Correct documentation. --- gcc/config/i386/i386.h | 7 ++++--- gcc/doc/invoke.texi | 15 ++++++++------- 2 files changed, 12 insertions(+), 10 deletions(-) diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index abfe1672c41..92a7982c87f 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -2401,11 +2401,12 @@ constexpr wide_int_bitmask PTA_GRANITERAPIDS = PTA_SAPPHIRERAPIDS | PTA_AMX_FP16 constexpr wide_int_bitmask PTA_GRANITERAPIDS_D = PTA_GRANITERAPIDS | PTA_AMX_COMPLEX; constexpr wide_int_bitmask PTA_GRANDRIDGE = PTA_SIERRAFOREST | PTA_RAOINT; -constexpr wide_int_bitmask PTA_ARROWLAKE = PTA_SIERRAFOREST; +constexpr wide_int_bitmask PTA_ARROWLAKE = PTA_ALDERLAKE | PTA_AVXIFMA + | PTA_AVXVNNIINT8 | PTA_AVXNECONVERT | PTA_CMPCCXADD | PTA_UINTR; constexpr wide_int_bitmask PTA_ARROWLAKE_S = PTA_ARROWLAKE | PTA_AVXVNNIINT16 | PTA_SHA512 | PTA_SM3 | PTA_SM4; -constexpr wide_int_bitmask PTA_CLEARWATERFOREST = PTA_ARROWLAKE_S | PTA_PREFETCHI - | PTA_USER_MSR; +constexpr wide_int_bitmask PTA_CLEARWATERFOREST = PTA_SIERRAFOREST | PTA_AVXVNNIINT16 + | PTA_SHA512 | PTA_SM3 | PTA_SM4 | PTA_USER_MSR | PTA_PREFETCHI; constexpr wide_int_bitmask PTA_PANTHERLAKE = PTA_ARROWLAKE_S | PTA_PREFETCHI; constexpr wide_int_bitmask PTA_KNM = PTA_KNL | PTA_AVX5124VNNIW | PTA_AVX5124FMAPS | PTA_AVX512VPOPCNTDQ; diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index a0da7f9d5ac..69809db9f1b 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -32845,7 +32845,8 @@ SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI, MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT, PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI, -AVXIFMA, AVXVNNIINT8, AVXNECONVERT and CMPCCXADD instruction set support. +UINTR, AVXIFMA, AVXVNNIINT8, AVXNECONVERT and CMPCCXADD instruction set +support. @item arrowlake-s Intel Arrow Lake S CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, @@ -32853,8 +32854,8 @@ SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI, MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT, PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI, -AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512, SM3 -and SM4 instruction set support. +UINTR, AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512, +SM3 and SM4 instruction set support. @item clearwaterforest Intel Clearwater Forest CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, @@ -32862,8 +32863,8 @@ SSE3, SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI, MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT, PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI, -AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512, SM3, SM4, -USER_MSR and PREFETCHI instruction set support. +ENQCMD, UINTR, AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, +SHA512, SM3, SM4, USER_MSR and PREFETCHI instruction set support. @item pantherlake Intel Panther Lake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, @@ -32871,8 +32872,8 @@ SSSE3, SSE4.1, SSE4.2, POPCNT, AES, PREFETCHW, PCLMUL, RDRND, XSAVE, XSAVEC, XSAVES, XSAVEOPT, FSGSBASE, PTWRITE, RDPID, SGX, GFNI-SSE, CLWB, MOVDIRI, MOVDIR64B, CLDEMOTE, WAITPKG, ADCX, AVX, AVX2, BMI, BMI2, F16C, FMA, LZCNT, PCONFIG, PKU, VAES, VPCLMULQDQ, SERIALIZE, HRESET, KL, WIDEKL, AVX-VNNI, -AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512, SM3, SM4 -and PREFETCHI instruction set support. +UINTR, AVXIFMA, AVXVNNIINT8, AVXNECONVERT, CMPCCXADD, AVXVNNIINT16, SHA512, +SM3, SM4 and PREFETCHI instruction set support. @item knl Intel Knight's Landing CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,