From patchwork Tue Oct 17 21:23:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 154540 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp4406083vqb; Tue, 17 Oct 2023 14:23:52 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFGxWYn2CrkVvLQw6IOkclZ+n9kJXQ9vESJdcZ08PTuIwNHSa1cjFwODd8R/GV13hSXTyc2 X-Received: by 2002:a05:6a00:1c92:b0:690:d0d4:6fb0 with SMTP id y18-20020a056a001c9200b00690d0d46fb0mr3508471pfw.3.1697577832535; Tue, 17 Oct 2023 14:23:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697577832; cv=none; d=google.com; s=arc-20160816; b=VSdBIHPB4mE1OCDyeLU6IWfHc6aq8Lt6zVhdCKErFNeFgKcIW5AP1yD3wokuaQ4Ny2 JaRkE/gz93BhC9swU6BtkmFxvJPAOpv0YcBluIegkQnZdCnpZ5Pf5IS14oqvUKANvjYC CHKww9lYEjNYk7g0Vr2PfBBkSATp++8Z3pV6iJssW6NxrYMMZ0J81OXwbJr+QcAOuufi TDFTV/cWV1K52ZAkoSlZ0NxtoCSpUB0NSL/w0MkchCJz9581/y10L93WesflFi/uSfkR OtOK9b2IeQMG+ilymVjFV1jVA3/iZcU+k6jhKf5erPWgc2FcsJzETjVeFW2c1aZi3XhI whfQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=n70P7VXoQvos+tvoARg8YdC357P9bzhzxWof3PMYpTE=; fh=8iy+GLBXZdpcs/hIddJ7mbUapYjefwP9Gb111pAzFms=; b=NBQsWwyG8md2ZNaSYL/KZb1WgmKSiKJpQPXhATktAx3xVUuYk5G5ps1OAA5sSn2zOB Z/VTdrGeL+++cNIytyojZ71R/Jtdl77O5L+SVtxwLXaTbDoWxF7afYiXNYooAH4vfrWo De+zRYUP1XWi5CmCNllXWr+yAVq53yBWZOL5c7hN9MJsi3+wxuzAiTOz5/aquMtkWDud QA9RnDjvm9cFnWeUcH+Xy69QR2NnWRMrK/fKQE4FMFagx308uqt54taD56Z6sFc2A1D3 jnWT/O28o8V1lEfgkCFAtbi8oiGEJi7ij8JOIVBmdc2ZDmiqVxGrG8hEyFXU1RgX2Dsk o8/w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="SMiNeiQ/"; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=DjuZ02Uu; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from morse.vger.email (morse.vger.email. [2620:137:e000::3:1]) by mx.google.com with ESMTPS id f24-20020a635558000000b0057795cb4f16si584214pgm.684.2023.10.17.14.23.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 14:23:52 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) client-ip=2620:137:e000::3:1; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="SMiNeiQ/"; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=DjuZ02Uu; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by morse.vger.email (Postfix) with ESMTP id 56FA9801B7BC; Tue, 17 Oct 2023 14:23:47 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at morse.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232770AbjJQVX2 (ORCPT + 21 others); Tue, 17 Oct 2023 17:23:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32906 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229459AbjJQVX1 (ORCPT ); Tue, 17 Oct 2023 17:23:27 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F120BC6 for ; Tue, 17 Oct 2023 14:23:25 -0700 (PDT) Message-ID: <20231017211721.990580849@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1697577804; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=n70P7VXoQvos+tvoARg8YdC357P9bzhzxWof3PMYpTE=; b=SMiNeiQ/s5oDUwUUum5Ddfk05cPTUzZ9hQ0/GGHgxHg7XNiRULFTZZLx/UV1T/mkXRg3+a l6Bt4nphPW74/KaLOmlzYQvOS7yxpwjCegmYO1qalPNi4z664GPqqWz8rTdRYrtsk3MxmE BYVpYCAiL0CSri49W/gtolPX/uCsPkpRL8uSFddlp9/rXjePhfv/g6cM0elfbIo3e1o9r2 imh7keXzYplj9O7BUU8G+tr8FSc5afnMDi+EJ3o05IyVgqK1ScRHmzF5zYGFDXFqbTo8yP jdmY03p5K8VMRlgM7wwSo9zHjXpU1qo55yKI0nzmMSh/Sp8FiRAgthJwzqo+9Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1697577804; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=n70P7VXoQvos+tvoARg8YdC357P9bzhzxWof3PMYpTE=; b=DjuZ02UuiZWrwZnoPFeH+9FGXmbZYNkaFE2Sak5Pub59YwvW8sTdMA1ZK2Ij+vmtekXVo+ 2a45mX6csMbvd7AQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov Subject: [patch V5 01/39] x86/boot/32: Disable stackprotector and tracing for mk_early_pgtbl_32() References: <20231017200758.877560658@linutronix.de> MIME-Version: 1.0 Date: Tue, 17 Oct 2023 23:23:24 +0200 (CEST) X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Tue, 17 Oct 2023 14:23:47 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780039373304008645 X-GMAIL-MSGID: 1780039373304008645 From: Thomas Gleixner Stackprotector cannot work before paging is enabled. The read from the per CPU variable __stack_chk_guard is always accessing the virtual address either directly on UP or via FS on SMP. In physical address mode this results in an access to memory above 3GB. So this works by chance as the hardware returns the same value when there is no RAM at this physical address. When there is RAM populated above 3G then the read is by chance the same as nothing changes that memory during the very early boot stage. Stop relying on pure luck and disable the stack protector for the only C function which is called during early boot before paging is enabled. Remove function tracing from the whole source file as there is no way to trace this at all, but in case of CONFIG_DYNAMIC_FTRACE=n mk_early_pgtbl_32() would access global function tracer variables in physical address mode which again might work by chance. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/Makefile | 1 + arch/x86/kernel/head32.c | 3 ++- 2 files changed, 3 insertions(+), 1 deletion(-) --- --- a/arch/x86/kernel/Makefile +++ b/arch/x86/kernel/Makefile @@ -16,6 +16,7 @@ CFLAGS_REMOVE_kvmclock.o = -pg CFLAGS_REMOVE_ftrace.o = -pg CFLAGS_REMOVE_early_printk.o = -pg CFLAGS_REMOVE_head64.o = -pg +CFLAGS_REMOVE_head32.o = -pg CFLAGS_REMOVE_sev.o = -pg CFLAGS_REMOVE_rethook.o = -pg endif --- a/arch/x86/kernel/head32.c +++ b/arch/x86/kernel/head32.c @@ -70,7 +70,8 @@ asmlinkage __visible void __init __noret * always zero at this stage. */ void __init mk_early_pgtbl_32(void); -void __init mk_early_pgtbl_32(void) + +void __init __no_stack_protector mk_early_pgtbl_32(void) { #ifdef __pa #undef __pa From patchwork Tue Oct 17 21:23:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 154538 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp4405974vqb; Tue, 17 Oct 2023 14:23:39 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEp/Ka88OLDz0AtwSBa+wO6RZ8uUiQsUov3DWEwf8jkaUV4MNoA6CO/OvzP8q7kOG0SyebZ X-Received: by 2002:a05:6a00:180f:b0:68f:c8b3:3077 with SMTP id y15-20020a056a00180f00b0068fc8b33077mr3486822pfa.1.1697577819240; Tue, 17 Oct 2023 14:23:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697577819; cv=none; d=google.com; s=arc-20160816; b=R2hcdk2CXibTJSZEKIQ4+g9DuJY82q222UUbb13ls4ugFCU9iUe1Ui10UOFHz45JkA h2NBtM/Me1qwZP8hUOydNqqehwSsfPJDZNnfuTeu9Usw/7sjhzTntG03SPY/MFBP9whl XCwf63RlRqgYSwY925ffzDjCBX37MN8IggeCl7kkGeLuYDP0KjMobPzlS1QDt3GZdFge jL8rj0VdzktW6+02wErzLqk2Df7ZlBe0GnT3LzeFGQR1V3134Jeb++tbSAvfZkleKRm6 y56FhrLTuVlSaIpocpsM9gZfkj4S8QR3NhlrPfjVyUrvHEV9zEIsEktelU4V+hAfVq/m lFXw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=lbJOYYfEHtT/va9V68vAJRypxMhoPgp+vUtRehmb5+s=; fh=8iy+GLBXZdpcs/hIddJ7mbUapYjefwP9Gb111pAzFms=; b=AlCEDIBBvvkmqfZu0t2UOixNDgan3S495CyAsQKLi+UFfZZj2OKwBD/fyaSonhMVvY aBktR2B51lXouFTqikH74ZTbmA0lYZuBSwRgoSQD3+cbpXReYjR6Ib2EheJWVXC1gq56 sQiKR0QHleykC4fdsWMVXguYnzFcf08o5TDCcc5n3m0KgEhg01SMDZPC8YlG8TVj/f0a EMl0Ct/+DOUTXTZk8/F7opv9rVrBZ9Ag3JMosMlGLqDbqAtceukLDI3QQFGEx02uTFav ZmP2AgL2BWD95Tbwc6Y9mYN8oJtaVVP+QklpuzA0i2KpEN84WxtLsTxDYrX3xm4/tRO9 9RYw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=EQh3GyX9; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id s9-20020a656449000000b0057776b67494si594034pgv.887.2023.10.17.14.23.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 14:23:39 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=EQh3GyX9; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 6121E80DF269; Tue, 17 Oct 2023 14:23:38 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344000AbjJQVXc (ORCPT + 21 others); Tue, 17 Oct 2023 17:23:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32914 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232068AbjJQVX2 (ORCPT ); Tue, 17 Oct 2023 17:23:28 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3448CC4 for ; Tue, 17 Oct 2023 14:23:27 -0700 (PDT) Message-ID: <20231017211722.051625827@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1697577805; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=lbJOYYfEHtT/va9V68vAJRypxMhoPgp+vUtRehmb5+s=; b=EQh3GyX9g7Y8vF1WVmwq4aQgerLtDVxxz/+4S2qGYSj2DsH/T2UtPZc2fGFYOF96J9aaTA eTAZ1H+lI+z29H/KrUegQa1EHm6TCqs0wcFTdRdAJJ8xiQa6wdYi0eEnwzVErQrkkpUo0L SUArvNPviOJYtQuHlFYg8NcLTvr9oCActlvj6Os3aUwaz7PVF5/KSkEn5z6WMWCKy9ItiR mabn7a0cvkdySD6lj0CvTXxkVEVjdfOP2Ajutu4Qv+F2mRP8ORAE7QXp9H3ghx3PYKXczg Ye7Mlqk2Xs+vb6XhV+BJhLvLX6aWquHNPuSjgyLxnVkuvHpazP8RxI3Ch83Wyg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1697577805; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=lbJOYYfEHtT/va9V68vAJRypxMhoPgp+vUtRehmb5+s=; b=67HZHtdltjEhaIOOD9sxR+Wliq7Q+U+4SYN5vz0MHpLwaJTks1GZqalBKv0Na+rTvPHy31 +KwwSiOD53zr1tAQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov Subject: [patch V5 02/39] x86/boot: Use __pa_nodebug() in mk_early_pgtbl_32() References: <20231017200758.877560658@linutronix.de> MIME-Version: 1.0 Date: Tue, 17 Oct 2023 23:23:25 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 17 Oct 2023 14:23:38 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780039359288026168 X-GMAIL-MSGID: 1780039359288026168 From: Thomas Gleixner Use the existing macro instead of undefining and redefining __pa(). No functional change. Signed-off-by: Thomas Gleixner --- V5: New patch --- arch/x86/kernel/head32.c | 16 ++++++---------- 1 file changed, 6 insertions(+), 10 deletions(-) --- --- a/arch/x86/kernel/head32.c +++ b/arch/x86/kernel/head32.c @@ -73,25 +73,21 @@ void __init mk_early_pgtbl_32(void); void __init __no_stack_protector mk_early_pgtbl_32(void) { -#ifdef __pa -#undef __pa -#endif -#define __pa(x) ((unsigned long)(x) - PAGE_OFFSET) pte_t pte, *ptep; int i; unsigned long *ptr; /* Enough space to fit pagetables for the low memory linear map */ - const unsigned long limit = __pa(_end) + + const unsigned long limit = __pa_nodebug(_end) + (PAGE_TABLE_SIZE(LOWMEM_PAGES) << PAGE_SHIFT); #ifdef CONFIG_X86_PAE - pmd_t pl2, *pl2p = (pmd_t *)__pa(initial_pg_pmd); + pmd_t pl2, *pl2p = (pmd_t *)__pa_nodebug(initial_pg_pmd); #define SET_PL2(pl2, val) { (pl2).pmd = (val); } #else - pgd_t pl2, *pl2p = (pgd_t *)__pa(initial_page_table); + pgd_t pl2, *pl2p = (pgd_t *)__pa_nodebug(initial_page_table); #define SET_PL2(pl2, val) { (pl2).pgd = (val); } #endif - ptep = (pte_t *)__pa(__brk_base); + ptep = (pte_t *)__pa_nodebug(__brk_base); pte.pte = PTE_IDENT_ATTR; while ((pte.pte & PTE_PFN_MASK) < limit) { @@ -111,11 +107,11 @@ void __init __no_stack_protector mk_earl pl2p++; } - ptr = (unsigned long *)__pa(&max_pfn_mapped); + ptr = (unsigned long *)__pa_nodebug(&max_pfn_mapped); /* Can't use pte_pfn() since it's a call with CONFIG_PARAVIRT */ *ptr = (pte.pte & PTE_PFN_MASK) >> PAGE_SHIFT; - ptr = (unsigned long *)__pa(&_brk_end); + ptr = (unsigned long *)__pa_nodebug(&_brk_end); *ptr = (unsigned long)ptep + PAGE_OFFSET; } From patchwork Tue Oct 17 21:23:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 154542 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp4406132vqb; Tue, 17 Oct 2023 14:24:00 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFomFldBAn59sr6IxIEIzI6K34g8UXWKcO0nUgKcclio7f1p2Xl4acbMOtkpeHT8DgMp9f7 X-Received: by 2002:a05:6359:8001:b0:166:db65:af9a with SMTP id rc1-20020a056359800100b00166db65af9amr2945072rwb.2.1697577840170; Tue, 17 Oct 2023 14:24:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697577840; cv=none; d=google.com; s=arc-20160816; b=uHdjdCKfZens03M7PMxX0xttaLwtzJh3tJDLFqaK1quhzgXFEKttI8R+5Dk5erdF+t LJQ76J2N1Eg/4Q8dACDIOjKhkIKS80AVLymh7xPRf3SOy4Ic5m3+h3I/WRrrMN383sHl vvjVGApoALZUhn9VPECcCzI0Qoi4QSbt100TfR83PSTOBzLvhAkziWBryDHRBmCf2Kg+ 5Xb6YXfxBd/P0E74FSr6MOLxR7HO9kE4fh5s0fJlx0HEunWkCje0SrSEdJA/Ibm0lNNM djK7QguJN6oztrqHwNrE1ClPFT/y1ZtHDdV5dmZFgdNh3zIKXl0npLTp5ASRlfxlWr/4 Q51g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=cOWd3mA0/NpSnoGliA9lY2CUL6yFVz+hcd1BXCQ4PjQ=; fh=8iy+GLBXZdpcs/hIddJ7mbUapYjefwP9Gb111pAzFms=; b=tvqIMxTcJmkCWfphx3fy1kl4jnwfn28mfAZOVAhFDMW/bcUuNfkyrUE08oSwcQFTSr k8OBy2k/3linodiN36G1yE1+hAMJ/C1yUudYKMxa1E16ke8qsp4oNYYvvN0qyjnBoLBQ TyqQTEd2puaxCXE6cumRmZg/v9wGWRe35K6EYVMJX6Hsh0mgE5HZezpmgh4U06UI9a46 mmmFRZ260tcjPIFgz8WTEMoKie+9HAU4A67KFOvWPGaQfquGzHfF3ScwcAKClfSq9w1Z Xt52JrWvUmn6ggVkIccv6/1VADYVRX0VE2Gb0OUZu9hNalvU5Dkzzzx5A6hoSKIc6wtM PhLw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=4z2f2xNc; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=fV85nwip; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from howler.vger.email (howler.vger.email. [2620:137:e000::3:4]) by mx.google.com with ESMTPS id d17-20020a056a00245100b006be02784405si2542099pfj.275.2023.10.17.14.23.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 14:24:00 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) client-ip=2620:137:e000::3:4; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=4z2f2xNc; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=fV85nwip; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by howler.vger.email (Postfix) with ESMTP id 8E56D802D0D1; Tue, 17 Oct 2023 14:23:54 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at howler.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343885AbjJQVXf (ORCPT + 21 others); Tue, 17 Oct 2023 17:23:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32926 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343824AbjJQVX3 (ORCPT ); Tue, 17 Oct 2023 17:23:29 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8B02CC4 for ; Tue, 17 Oct 2023 14:23:28 -0700 (PDT) Message-ID: <20231017211722.111059491@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1697577807; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=cOWd3mA0/NpSnoGliA9lY2CUL6yFVz+hcd1BXCQ4PjQ=; b=4z2f2xNcj3NtihmzLmZArpBNxGNWvuTEf+iUyBSxKFKld0Nn5qeupZNDk6+ZU/YNVW8J+U 9gnP2DRtZ9OKuS0NQsH7rVOeVn/ZksL5a0ApewfCOxM5NwrLTManyci63DRkbILZlCbXm9 VRNltETVhr89O08E3VE7vELk7jts29azYlGe973X8KDZOn333hcvTL9fG8yrOiPA4N0GJY kScdibz5iP+3R1LtOF9FEjxhVgvwXqIxIg9uL5mCHCpr3jy03vYTC4Nq80e/EK4j9XhSFJ dXA2psJKmZ1HeAWCEjBhl0sactAG6IHgZRsI5TZOkquAr6vGvvzLRYP54Ylwbw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1697577807; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=cOWd3mA0/NpSnoGliA9lY2CUL6yFVz+hcd1BXCQ4PjQ=; b=fV85nwipkJR6owvvmejqZlePAbTYJ4adrIAS/INqHoVmWOk0q6D5uZ3CRvFEWpg+hj2L6i LoNVAnivz+6Jd3CA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov Subject: [patch V5 03/39] x86/boot/32: De-uglify the 2/3 level paging difference in mk_early_pgtbl_32() References: <20231017200758.877560658@linutronix.de> MIME-Version: 1.0 Date: Tue, 17 Oct 2023 23:23:26 +0200 (CEST) X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on howler.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Tue, 17 Oct 2023 14:23:54 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780039381668819082 X-GMAIL-MSGID: 1780039381668819082 Move the ifdeffery out of the function and use proper typedefs to make it work for both 2 and 3 level paging. No functional change. Signed-off-by: Thomas Gleixner Signed-off-by: Thomas Gleixner Signed-off-by: Borislav Petkov (AMD) --- V5: New patch --- arch/x86/kernel/head32.c | 38 +++++++++++++++++++++----------------- 1 file changed, 21 insertions(+), 17 deletions(-) --- a/arch/x86/kernel/head32.c +++ b/arch/x86/kernel/head32.c @@ -71,39 +71,43 @@ asmlinkage __visible void __init __noret */ void __init mk_early_pgtbl_32(void); +#ifdef CONFIG_X86_PAE +typedef pmd_t pl2_t; +#define pl2_base initial_pg_pmd +#define SET_PL2(val) { .pmd = (val), } +#else +typedef pgd_t pl2_t; +#define pl2_base initial_page_table +#define SET_PL2(val) { .pgd = (val), } +#endif + void __init __no_stack_protector mk_early_pgtbl_32(void) { - pte_t pte, *ptep; - int i; - unsigned long *ptr; /* Enough space to fit pagetables for the low memory linear map */ const unsigned long limit = __pa_nodebug(_end) + (PAGE_TABLE_SIZE(LOWMEM_PAGES) << PAGE_SHIFT); -#ifdef CONFIG_X86_PAE - pmd_t pl2, *pl2p = (pmd_t *)__pa_nodebug(initial_pg_pmd); -#define SET_PL2(pl2, val) { (pl2).pmd = (val); } -#else - pgd_t pl2, *pl2p = (pgd_t *)__pa_nodebug(initial_page_table); -#define SET_PL2(pl2, val) { (pl2).pgd = (val); } -#endif + pte_t pte, *ptep = (pte_t *)__pa_nodebug(__brk_base); + pl2_t *pl2p = (pl2_t *)__pa_nodebug(pl2_base); + unsigned long *ptr; + int i; - ptep = (pte_t *)__pa_nodebug(__brk_base); pte.pte = PTE_IDENT_ATTR; while ((pte.pte & PTE_PFN_MASK) < limit) { + pl2_t pl2 = SET_PL2((unsigned long)ptep | PDE_IDENT_ATTR); - SET_PL2(pl2, (unsigned long)ptep | PDE_IDENT_ATTR); *pl2p = pl2; -#ifndef CONFIG_X86_PAE - /* Kernel PDE entry */ - *(pl2p + ((PAGE_OFFSET >> PGDIR_SHIFT))) = pl2; -#endif + + if (!IS_ENABLED(CONFIG_X86_PAE)) { + /* Kernel PDE entry */ + *(pl2p + ((PAGE_OFFSET >> PGDIR_SHIFT))) = pl2; + } + for (i = 0; i < PTRS_PER_PTE; i++) { *ptep = pte; pte.pte += PAGE_SIZE; ptep++; } - pl2p++; } From patchwork Tue Oct 17 21:23:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 154539 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp4406045vqb; Tue, 17 Oct 2023 14:23:49 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFsTrKUYJBF3WlqUT2s/ayz6oc8rYHcPPXrrkZa3mEaLL8/EHF6s3g8hS0vzo266/v8ZIXZ X-Received: by 2002:a17:902:fb45:b0:1bb:83ec:832 with SMTP id lf5-20020a170902fb4500b001bb83ec0832mr3382867plb.2.1697577828930; Tue, 17 Oct 2023 14:23:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697577828; cv=none; d=google.com; s=arc-20160816; b=VV9m4V6Fy2/MmPHtW8M9XZJwzX0uDZLjqFQiBSR/3zxPqrxNDbjqoYPb75/DQx2Ed7 aiI80Ellt73T4pTtrcfJvkb7HSllyqm4fvkQTXCmWsa+nsQgkzyKbicv9X6ov6sf6+RC 1Qbm9xcBXCbpO9liUq1i2x/Z/jvLdY7OWPhI5J0ljuCjyjZoliPzMqviT4osbarsY6+7 ckKriCRF0FrJRrGl2XZMvLDyUVKQ2Kciz4+HA4Kchzx9GT5fydHeogBVARaOnDrTxDtl mQ5HgN2s0jbk1rpTAVWkwUnW0Bra33ZNsDDKykJvhfgdWsnt2t5zVpZB8Ho/Dzy6p18g tZgA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=/Fup+VDAYBco9fVZ163AiwHqyzSBNFBZQllA3x1jvOc=; fh=8iy+GLBXZdpcs/hIddJ7mbUapYjefwP9Gb111pAzFms=; b=JW0D1UFzt+1keZ74XSv2uvUKSp1UFFuE3hJ9UOAaYTjT0Or4jNWfzuK9R53t19Ty2A 4q/VsmwlxOyrS4nARDYVfLeWeqSnRXRGgx1gUzXKCtTJ/9f3qdQ7Sk9tp9/YpuP90cPQ IGGHVWJDgQhK+xYOsGBHXtqp4Z6RW8aRmn0EVfRW4H3PZIkc6jL24WS2rA0K2pQdOkiR HLkcmi3EWnlC+c7SR2yO9oDwd8EYdXn5HDXfjq6ZyhxGjNXrQLBI4smHzZIhZC77JbhE ExsOCM31OoKf7kFGuNJKL2h2wD4c3gWw4v9f0ctD+A2MEDfdbMKo0E+qGomM8Jnhik6w 9OyQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="Y1/Hubca"; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=aS9i++kS; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id n2-20020a170902e54200b001c3411c9b83si1055085plf.454.2023.10.17.14.23.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 14:23:48 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="Y1/Hubca"; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=aS9i++kS; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 2522180FC736; Tue, 17 Oct 2023 14:23:48 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344121AbjJQVXj (ORCPT + 21 others); Tue, 17 Oct 2023 17:23:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32928 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1343950AbjJQVXb (ORCPT ); Tue, 17 Oct 2023 17:23:31 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F152BC4 for ; Tue, 17 Oct 2023 14:23:29 -0700 (PDT) Message-ID: <20231017211722.175910753@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1697577808; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=/Fup+VDAYBco9fVZ163AiwHqyzSBNFBZQllA3x1jvOc=; b=Y1/Hubca5qv1by3FanlczuXuft9wkvbELw+hPuI/XupeD8OjEvlq22ectfJ8+4Su0NyBrQ ONAeYHZ3DX3vnIk74h59foe9eA9p4CUNXNs7UHvCzKrgXIDf6HB7+PEW0zo3YW2vL4yRnD sVnvPFU92d5KYQs/UctkSlR8/OduYtbrms1BHRhdVHBS3E9JFlyN/FgCeFtLtVywFjiP5Z HsNoyqpHugWLI9dR5fKepTd78h0+fV2w+mkO6hWpJPR8Jo0eFejy1i/BWyHZh8Dmt1EI8W YvVvInj/GEv4RVUn0pW8+Elvbrw/eGW2+FHsg0BCGPtSAFxS7LAc/OWz0y7f4w== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1697577808; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=/Fup+VDAYBco9fVZ163AiwHqyzSBNFBZQllA3x1jvOc=; b=aS9i++kSJbA+FSxu8KZU33DP4E1pbRN8wLmpsNSokyiXAYUnyNAeqMkr6KI54KUonI9I9I jkVDeP6Wt6NWt7Dw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov Subject: [patch V5 04/39] x86/boot/32: Restructure mk_early_pgtbl_32() References: <20231017200758.877560658@linutronix.de> MIME-Version: 1.0 Date: Tue, 17 Oct 2023 23:23:28 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 17 Oct 2023 14:23:48 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780039369824225409 X-GMAIL-MSGID: 1780039369824225409 From: Thomas Gleixner Prepare it for adding a temporary initrd mapping by splitting out the actual map loop. No functional change. Signed-off-by: Thomas Gleixner --- V5: New patch --- arch/x86/kernel/head32.c | 42 +++++++++++++++++++++++------------------- 1 file changed, 23 insertions(+), 19 deletions(-) --- --- a/arch/x86/kernel/head32.c +++ b/arch/x86/kernel/head32.c @@ -81,35 +81,40 @@ typedef pgd_t pl2_t; #define SET_PL2(val) { .pgd = (val), } #endif -void __init __no_stack_protector mk_early_pgtbl_32(void) +static __init __no_stack_protector pte_t init_map(pte_t pte, pte_t **ptep, pl2_t **pl2p, + const unsigned long limit) { - /* Enough space to fit pagetables for the low memory linear map */ - const unsigned long limit = __pa_nodebug(_end) + - (PAGE_TABLE_SIZE(LOWMEM_PAGES) << PAGE_SHIFT); - pte_t pte, *ptep = (pte_t *)__pa_nodebug(__brk_base); - pl2_t *pl2p = (pl2_t *)__pa_nodebug(pl2_base); - unsigned long *ptr; - int i; - - pte.pte = PTE_IDENT_ATTR; - while ((pte.pte & PTE_PFN_MASK) < limit) { - pl2_t pl2 = SET_PL2((unsigned long)ptep | PDE_IDENT_ATTR); - - *pl2p = pl2; + pl2_t pl2 = SET_PL2((unsigned long)*ptep | PDE_IDENT_ATTR); + int i; + **pl2p = pl2; if (!IS_ENABLED(CONFIG_X86_PAE)) { /* Kernel PDE entry */ - *(pl2p + ((PAGE_OFFSET >> PGDIR_SHIFT))) = pl2; + *(*pl2p + ((PAGE_OFFSET >> PGDIR_SHIFT))) = pl2; } for (i = 0; i < PTRS_PER_PTE; i++) { - *ptep = pte; + **ptep = pte; pte.pte += PAGE_SIZE; - ptep++; + (*ptep)++; } - pl2p++; + (*pl2p)++; } + return pte; +} + +void __init __no_stack_protector mk_early_pgtbl_32(void) +{ + /* Enough space to fit pagetables for the low memory linear map */ + const unsigned long limit = __pa_nodebug(_end) + + (PAGE_TABLE_SIZE(LOWMEM_PAGES) << PAGE_SHIFT); + pte_t pte, *ptep = (pte_t *)__pa_nodebug(__brk_base); + pl2_t *pl2p = (pl2_t *)__pa_nodebug(pl2_base); + unsigned long *ptr; + + pte.pte = PTE_IDENT_ATTR; + pte = init_map(pte, &ptep, &pl2p, limit); ptr = (unsigned long *)__pa_nodebug(&max_pfn_mapped); /* Can't use pte_pfn() since it's a call with CONFIG_PARAVIRT */ @@ -118,4 +123,3 @@ void __init __no_stack_protector mk_earl ptr = (unsigned long *)__pa_nodebug(&_brk_end); *ptr = (unsigned long)ptep + PAGE_OFFSET; } - From patchwork Tue Oct 17 21:23:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 154541 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp4406114vqb; Tue, 17 Oct 2023 14:23:57 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHYJ7dM36SPHH8eP/4gm25nICttX7rqoulIz4wd8Mxoio5s4+bccDlgSIjMC+x3cgmRfPd/ X-Received: by 2002:a05:6359:8001:b0:166:db65:af9a with SMTP id rc1-20020a056359800100b00166db65af9amr2944966rwb.2.1697577837267; Tue, 17 Oct 2023 14:23:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697577837; cv=none; d=google.com; s=arc-20160816; b=IQpjR13Y5U+ONPJCOHlQN+qI11EzRWRWWb9PY/8AiRpbiNbDNzinfvotX0MGzQQfwr FCLUnqGLvdp4MiujXbED7aZNS/6fFtZ9VuDcso/5qOk1VDuTA/6MwezDMm80qgvsjvJK gdg4DF5/L/cAoHzMPecw1xFyRFRnLuwWldZfXqc0vuLknt6gzcNbWuqsGNe+0h3AVBPf zEO0K9x8ULwdv/GDLRvB9yqzYnBWOltlXO+TMQT77fAkENgKPmHSJ+17sYQh7XDiLyLh vwdgrgpHVyVdMDJfKR82KwWLLh02+KZzq5G+gbmi9LQ13IIE5B3jYWNqvihAoVzquMRQ gnrw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=TpbhN6EH+jiNlFeBACxkVLlnyXpjPlsl7WjVUOBjb5E=; fh=8iy+GLBXZdpcs/hIddJ7mbUapYjefwP9Gb111pAzFms=; b=BPbHuAApvTeZ0o6tSnMzt40UVRYDxzbarhIsAJliXO6QPBSUvz9aZ6HvhmnPz1TPrF wHIfZck6Oi3mL1iXh+pgINI88PvGy9/u8xRR7fdtwD1eo6W1sqcVngyXxU2A008Pe82M xqhZGgK+nTcB6z1uSV/GS/YrFOqL7UOVAAcYlMFQ/Dv+3ZCIvZAaXaJBwatwxfU0rGzS lrlGdG5JcRcIRY9OfCkIpOwPCpGjzFlOpVZtDbsIcFsYvNuekelNWWfWTny1sYRjhOFQ 19RDr4thJMhe4y8ZU6wCqKOas1unaosJeWsxkEB/qYUV0m4lDe6yDhlROczq53trpY6+ 9l1Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=gC+x+EvV; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id bv186-20020a632ec3000000b005b7c7f06e9esi617119pgb.34.2023.10.17.14.23.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 14:23:57 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=gC+x+EvV; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 2202980FC731; Tue, 17 Oct 2023 14:23:56 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344124AbjJQVXm (ORCPT + 21 others); Tue, 17 Oct 2023 17:23:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32942 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344006AbjJQVXc (ORCPT ); Tue, 17 Oct 2023 17:23:32 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5A44EC6 for ; Tue, 17 Oct 2023 14:23:31 -0700 (PDT) Message-ID: <20231017211722.236208250@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1697577810; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=TpbhN6EH+jiNlFeBACxkVLlnyXpjPlsl7WjVUOBjb5E=; b=gC+x+EvVfxKAiZ+DOfyq1S+E4UaAqAWTAhR2/44EsOyBdYqnC0XdpOjonqRbQZwkw0QvWM orzrrros9FpES4ZxI0VXcDwdkPLZdGFWFdkJYXUrC/bpvs3TXeH/MjBrSv3zHq8/ZMZP7H 9CXQa5cmD++WmrUqWMyqHrwTfv2LbH8kw3BhOhEr2gfCteT72eDyU4xHdNHbVVcmEKGaAP /vP76MYFHPa7R3KzGpbIBJOYTTnrnPGpmuk8dhVXHuJcyn8qHm0FV5kI6SDC9wijiAis5O V1thLANRD7Op8EHub7NxEaxAwgfwnec6Lwf7nsL7vYSv3WjYVRbaeqP703hk9A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1697577810; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=TpbhN6EH+jiNlFeBACxkVLlnyXpjPlsl7WjVUOBjb5E=; b=j32YI3DV5qMsZhqQBC7g0Ug5QDUZSpAr2/+R/2s5yWoU4vHzcj7nSGY8Wn/a2RZMtNBCgk pxrZPwFMarHTYnBA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov Subject: [patch V5 05/39] x86/microcode: Provide CONFIG_MICROCODE_INITRD32 References: <20231017200758.877560658@linutronix.de> MIME-Version: 1.0 Date: Tue, 17 Oct 2023 23:23:29 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 17 Oct 2023 14:23:56 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780039378542022175 X-GMAIL-MSGID: 1780039378542022175 From: Thomas Gleixner Create an aggregate config switch which covers X86_32, MICROCODE and BLK_DEV_INITRD to avoid lengthy #ifdeffery in upcoming code. Signed-off-by: Thomas Gleixner --- V5: New patch --- arch/x86/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) --- diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index d8ff206e503f..cadea3f3161e 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1313,6 +1313,10 @@ config MICROCODE def_bool y depends on CPU_SUP_AMD || CPU_SUP_INTEL +config MICROCODE_INITRD32 + def_bool y + depends on MICROCODE && X86_32 && BLK_DEV_INITRD + config MICROCODE_LATE_LOADING bool "Late microcode loading (DANGEROUS)" default n From patchwork Tue Oct 17 21:23:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 154545 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp4406312vqb; Tue, 17 Oct 2023 14:24:30 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGpvOk/zfJJD16J+IVOlPtNbOPOX8641DgIRA3uF6zPq74CBkUDISoysV7H4aonSgepdF/f X-Received: by 2002:a17:902:cf4e:b0:1c9:e48c:7260 with SMTP id e14-20020a170902cf4e00b001c9e48c7260mr3344237plg.6.1697577869734; Tue, 17 Oct 2023 14:24:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697577869; cv=none; d=google.com; s=arc-20160816; b=VOsvHOk5a0X77pd2WirhUGGlzfmJM9sBBR8N0SVOx/NFjWXQWdvfu6wX8Csa10SEOV 7h56V9NVRddKgnE9jsg4ecHLB1C7YYgKxUwpyHv+TSiwVExg/wAIpaKOTkKAA70fN+AO VKOJWezoK7vrsQw+1bxMyLle0SgEMIlGMmBGlPM3iNDTQOine5EuLdAqgEd8fcLn7+aM eAvwq0VP0oXqNXDXFEt2/QMYKiDAixw4sED1sSt/h6LGea+kbAjr70kdULs1Tx4mCRd3 a77HvQVr+xfP3hocSxGytV8E95RmYDAIgFW4OGCOsXgDt1owEQm8KpVM/vEZj0cNlnRk tgbA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=3mXXYCmv0bVfMYDZcEO6X7VusLAPyknFMuG5E+/gL3Y=; fh=8iy+GLBXZdpcs/hIddJ7mbUapYjefwP9Gb111pAzFms=; b=nU8b/GMnqQ48xKEZRvDTqtoSJoEHN+nhZG78gLASsiX4iSt/jlxCzEICGGZiy6Wyry 7xdSj1zOazYNMxYAu5xvBgpnfPtYvwQKcdRWELUS0xOPEJckksLjnsG5759MUZehfGg1 b3JqsO5YJO32f29kANTH90TFC8gyKcn6/EKiMt+muda11PpOKvILT889ciQ2uyasx1GU KGGys8iKq/L2oq5jp5atyvPLAhFntMNI19e6vgerLd9tgSxjKu6FOmNVB6Gq1jacEmwv 64emPYxAYgUu6o5bOHQtrHBcq5cwv+IpHSHsPqpYchhXkhcWBZHXoIXdxI2dzP1+3635 eU1A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="UMzh/2po"; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from morse.vger.email (morse.vger.email. [23.128.96.31]) by mx.google.com with ESMTPS id i9-20020a170902eb4900b001ca176b7974si2369395pli.103.2023.10.17.14.24.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 14:24:29 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) client-ip=23.128.96.31; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="UMzh/2po"; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by morse.vger.email (Postfix) with ESMTP id 3ADB6801B7BD; Tue, 17 Oct 2023 14:24:24 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at morse.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344144AbjJQVXq (ORCPT + 21 others); Tue, 17 Oct 2023 17:23:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33378 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344159AbjJQVXl (ORCPT ); Tue, 17 Oct 2023 17:23:41 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D1B15F9 for ; Tue, 17 Oct 2023 14:23:32 -0700 (PDT) Message-ID: <20231017211722.292291436@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1697577811; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=3mXXYCmv0bVfMYDZcEO6X7VusLAPyknFMuG5E+/gL3Y=; b=UMzh/2po3KoQQqnSV6luxMPgcv444x4N2N/4ZTRckWYVxEFL2VCfk5jhwgeoQmi1toPAnK taYhXCK0D1NI7A2UBdB5Kr+Ocgdged/jskGRUUo2mMJNiAgGO2QGWKsQWlA7EzAaNsoffe o/77rAUYNMlU3cjhtU4sDLYuwvL/raPveabrkTUVgdUjLZJbxGwLTT3AGX1C168GGE2oc/ /XbfMir2sYhRpgLZgj7LFPVlgiMA2cglYN8wKsLdiEBrkdfhaKydzabgHCzLSs8ohdQbwR fTF5cU1EYQYnfOB8QELImP2w7Dt2BUG1OWl8OIjGmCYmvYVNeBSiif2FSElPqQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1697577811; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=3mXXYCmv0bVfMYDZcEO6X7VusLAPyknFMuG5E+/gL3Y=; b=P0F1MWymNHMHaSxSJWrKIHU/uV/2nB6ASFkvWkJEcGt+JlEB+2bcEmTFf16fce202//iIx b7o0g/iHUj0VHWAg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov Subject: [patch V5 06/39] x86/boot/32: Temporarily map initrd for microcode loading References: <20231017200758.877560658@linutronix.de> MIME-Version: 1.0 Date: Tue, 17 Oct 2023 23:23:31 +0200 (CEST) X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Tue, 17 Oct 2023 14:24:24 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780039412005286727 X-GMAIL-MSGID: 1780039412005286727 From: Thomas Gleixner Early microcode loading on 32-bit runs in physical address mode because the initrd is not covered by the initial page tables. That results in a horrible mess all over the microcode loader code. Provide a temporary mapping for the initrd in the initial page tables by appending it to the actual initial mapping starting with a new PGD or PMD depending on the configured page table levels ([non-]PAE). The page table entries are located after _brk_end so they are not permanently using memory space. The mapping is invalidated right away in i386_start_kernel() after the early microcode loader has run. This prepares for removing the physical address mode oddities from all over the microcode loader code, which in turn allows further cleanups. Provide the map and unmap code and document the place where the microcode loader needs to be invoked with a comment. Signed-off-by: Thomas Gleixner --- V5: New patch --- arch/x86/include/asm/microcode.h | 2 + arch/x86/kernel/head32.c | 54 +++++++++++++++++++++++++++++++++++++-- 2 files changed, 54 insertions(+), 2 deletions(-) --- --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -23,6 +23,8 @@ static inline void load_ucode_ap(void) { static inline void microcode_bsp_resume(void) { } #endif +extern unsigned long initrd_start_early; + #ifdef CONFIG_CPU_SUP_INTEL /* Intel specific microcode defines. Public for IFS */ struct microcode_header_intel { --- a/arch/x86/kernel/head32.c +++ b/arch/x86/kernel/head32.c @@ -29,11 +29,33 @@ static void __init i386_default_early_se x86_init.mpparse.setup_ioapic_ids = setup_ioapic_ids_from_mpc; } +#ifdef CONFIG_MICROCODE_INITRD32 +unsigned long __initdata initrd_start_early; +static pte_t __initdata *initrd_pl2p_start, *initrd_pl2p_end; + +static void zap_early_initrd_mapping(void) +{ + pte_t *pl2p = initrd_pl2p_start; + + for (; pl2p < initrd_pl2p_end; pl2p++) { + *pl2p = (pte_t){ .pte = 0 }; + + if (!IS_ENABLED(CONFIG_X86_PAE)) + *(pl2p + ((PAGE_OFFSET >> PGDIR_SHIFT))) = (pte_t) {.pte = 0}; + } +} +#else +static inline void zap_early_initrd_mapping(void) { } +#endif + asmlinkage __visible void __init __noreturn i386_start_kernel(void) { /* Make sure IDT is set up before any exception happens */ idt_setup_early_handler(); + /* load_ucode_bsp() */ + zap_early_initrd_mapping(); + cr4_init_shadow(); sanitize_boot_params(&boot_params); @@ -107,9 +129,9 @@ static __init __no_stack_protector pte_t void __init __no_stack_protector mk_early_pgtbl_32(void) { /* Enough space to fit pagetables for the low memory linear map */ - const unsigned long limit = __pa_nodebug(_end) + - (PAGE_TABLE_SIZE(LOWMEM_PAGES) << PAGE_SHIFT); + unsigned long limit = __pa_nodebug(_end) + (PAGE_TABLE_SIZE(LOWMEM_PAGES) << PAGE_SHIFT); pte_t pte, *ptep = (pte_t *)__pa_nodebug(__brk_base); + struct boot_params __maybe_unused *params; pl2_t *pl2p = (pl2_t *)__pa_nodebug(pl2_base); unsigned long *ptr; @@ -122,4 +144,32 @@ void __init __no_stack_protector mk_earl ptr = (unsigned long *)__pa_nodebug(&_brk_end); *ptr = (unsigned long)ptep + PAGE_OFFSET; + +#ifdef CONFIG_MICROCODE_INITRD32 + /* Running on a hypervisor? */ + if (native_cpuid_ecx(1) & BIT(31)) + return; + + params = (struct boot_params *)__pa_nodebug(&boot_params); + if (!params->hdr.ramdisk_size || !params->hdr.ramdisk_image) + return; + + /* Save the virtual start address */ + ptr = (unsigned long *)__pa_nodebug(&initrd_start_early); + *ptr = (pte.pte & PTE_PFN_MASK) + PAGE_OFFSET; + *ptr += ((unsigned long)params->hdr.ramdisk_image) & ~PAGE_MASK; + + /* Save PLP2 for cleanup */ + ptr = (unsigned long *)__pa_nodebug(&initrd_pl2p_start); + *ptr = (unsigned long)pl2p + PAGE_OFFSET; + + limit = (unsigned long)params->hdr.ramdisk_image; + pte.pte = PTE_IDENT_ATTR | PFN_ALIGN(limit); + limit = (unsigned long)params->hdr.ramdisk_image + params->hdr.ramdisk_size; + + init_map(pte, &ptep, &pl2p, limit); + + ptr = (unsigned long *)__pa_nodebug(&initrd_pl2p_end); + *ptr = (unsigned long)pl2p + PAGE_OFFSET; +#endif } From patchwork Tue Oct 17 21:23:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 154553 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp4406570vqb; Tue, 17 Oct 2023 14:25:08 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFOrJYrggEyOwhWFUMH6lOd86F4C8azJMGBQ61EZ+x5WE7aUX/GdvBQBNJAiWvGVwaK4zGa X-Received: by 2002:a05:6a00:6008:b0:68f:c309:9736 with SMTP id fo8-20020a056a00600800b0068fc3099736mr3411772pfb.3.1697577908587; Tue, 17 Oct 2023 14:25:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697577908; cv=none; d=google.com; s=arc-20160816; b=GB3X7m6uwy4MjbX7S3PVPi1crMxZ95jppDaBPAIhBA6VyKZenyF3QhBuPZdNdkRlCK HDoej31o/5o42RUKahuH/XY1cCPpQA6VLHziI+4yO+UvlcWKGvqgwRh8dO2kHY5spl9j JVKebDnlEFAsjpHfqt2atMIS5/gSCHMIHElSH48pJAwIUx8v7tRpumoe8qEqr4SFrKa9 7+nTAru/H7q1SH/Q/HacVfC8yBLrv6SXC/wz08ZAgCJk2Zb/WVQPO73xo5PYOui0vFrB njS5ugUYD9r7xTrsA0uVKPiJs9/qBSfsxlT9+/r8dXodHa17lPQXxayRb47zlZqv7j8j jeXw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=xf8AcyqsHNHPMi3HiZYjmre7MRCXmeHHxs5Y2JvF46I=; fh=8iy+GLBXZdpcs/hIddJ7mbUapYjefwP9Gb111pAzFms=; b=PJu3+8hVGIqugyGB9ayhPIfk9SAFn51NY+vKNUfIjCKpF/IStImtgBca5W2Mu0+4mc dZhqdyv9GkPykZc6nG4lH4Hbo70iLQI2nQN9chxWcffkF/AXBRrHjqF7TMV2QygyQUtJ bTtCfrQTiUhDbqmxifwhbkv7aBlV7LZ9iwh6vempmwPzOBVSM128evZvJcmKqOgM6v2v 1bkREh4NKc2KMpmVjvnHvcNQLSyw9NWtwPv7CKRFMN4kB1yVDju5EtteM+N8B+n2ayfG uRnPNvL9VNTlNqjFlAJo9tQNw3a+tMuIGQEQisET7hfoXnjRtVVwzxXegEV4EUDcltxn kADg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=KIXU3+37; dkim=neutral (no key) header.i=@linutronix.de header.b=7KOOkLvH; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from howler.vger.email (howler.vger.email. [2620:137:e000::3:4]) by mx.google.com with ESMTPS id q8-20020aa78428000000b006b43657e872si2418014pfn.184.2023.10.17.14.25.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 14:25:08 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) client-ip=2620:137:e000::3:4; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=KIXU3+37; dkim=neutral (no key) header.i=@linutronix.de header.b=7KOOkLvH; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by howler.vger.email (Postfix) with ESMTP id E3CCD802D0C3; Tue, 17 Oct 2023 14:24:57 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at howler.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344302AbjJQVXw (ORCPT + 21 others); Tue, 17 Oct 2023 17:23:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33458 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344258AbjJQVXo (ORCPT ); Tue, 17 Oct 2023 17:23:44 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 434A6103 for ; Tue, 17 Oct 2023 14:23:34 -0700 (PDT) Message-ID: <20231017211722.348298216@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1697577812; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=xf8AcyqsHNHPMi3HiZYjmre7MRCXmeHHxs5Y2JvF46I=; b=KIXU3+37AH6Yqg129cemRL+s5kxIPMxs+U4Uo8asNKzVcqOIOyfav2seRnVqmQ+WQsgugi wR8iOJoNCt+wq8zW6avodVBmKJAD6COQcOmCfQnM9uBPFTOCvPiTAZOVDhBNXayImJ/GMG Xx/4WU88t4EJ/AZ3mP1pvW2vsxYP2SPITXwR82NKEPqh0EQz11XPfZg3CCAQC/u5FtjQsJ g/WON/dt3baj+imECVO4EyskTtp3vpI0jOKW4FyDh6CxQA0Khx7SycJCpjq/RPZeqBwRkE nCyxwvdSUheysfrw/CKsxyW4oKc9k3pnyCiOPONC36F3qheuA6Kp32EopAdUeA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1697577812; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=xf8AcyqsHNHPMi3HiZYjmre7MRCXmeHHxs5Y2JvF46I=; b=7KOOkLvHJNnV34HoqRXPx0XFdywHz/h/2PpIJc4o5W0PayFYYsIGB4lMny3AGTmeuGajmy Wa/UpVqN0RqeGcCw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov Subject: [patch V5 07/39] x86/microcode/32: Move early loading after paging enable References: <20231017200758.877560658@linutronix.de> MIME-Version: 1.0 Date: Tue, 17 Oct 2023 23:23:32 +0200 (CEST) X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on howler.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Tue, 17 Oct 2023 14:24:58 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780039453047121164 X-GMAIL-MSGID: 1780039453047121164 From: Thomas Gleixner 32-bit loads microcode before paging is enabled. The commit which introduced that has zero justification in the changelog. The cover letter has slightly more content, but it does not give any technical justification either: "The problem in current microcode loading method is that we load a microcode way, way too late; ideally we should load it before turning paging on. This may only be practical on 32 bits since we can't get to 64-bit mode without paging on, but we should still do it as early as at all possible." Handwaving word salad with zero technical content. Someone claimed in an offlist conversation that this is required for curing the ATOM erratum AAE44/AAF40/AAG38/AAH41. That erratum requires an microcode update in order to make the usage of PSE safe. But during early boot PSE is completely irrelevant and it is evaluated way later. Neither is it relevant for the AP on single core HT enabled CPUs as the microcode loading on the AP is not doing anything. On dual core CPUs there is a theoretical problem if a split of an executable large page between enabling paging including PSE and loading the microcode happens. But that's only theoretical, it's practically irrelevant because the affected dual core CPUs are 64bit enabled and therefore have paging and PSE enabled before loading the microcode on the second core. So why would it work on 64-bit but not on 32-bit? The erratum: "AAG38 Code Fetch May Occur to Incorrect Address After a Large Page is Split Into 4-Kbyte Pages Problem: If software clears the PS (page size) bit in a present PDE (page directory entry), that will cause linear addresses mapped through this PDE to use 4-KByte pages instead of using a large page after old TLB entries are invalidated. Due to this erratum, if a code fetch uses this PDE before the TLB entry for the large page is invalidated then it may fetch from a different physical address than specified by either the old large page translation or the new 4-KByte page translation. This erratum may also cause speculative code fetches from incorrect addresses." The practical relevance for this is exactly zero because there is no splitting of large text pages during early boot-time, i.e. between paging enable and microcode loading, and neither during CPU hotplug. IOW, this load microcode before paging enable is yet another voodoo programming solution in search of a problem. What's worse is that it causes at least two serious problems: 1) When stackprotector is enabled then the microcode loader code has the stackprotector mechanics enabled. The read from the per CPU variable __stack_chk_guard is always accessing the virtual address either directly on UP or via FS on SMP. In physical address mode this results in an access to memory above 3GB. So this works by chance as the hardware returns the same value when there is no RAM at this physical address. When there is RAM populated above 3G then the read is by chance the same as nothing changes that memory during the very early boot stage. That's not necessarily true during runtime CPU hotplug. 2) When function tracing is enabled, then the relevant microcode loader functions and the functions invoked from there will call into the tracing code and evaluate global and per CPU variables in physical address mode. What could potentially go wrong? Cure this and move the microcode loading after the early paging enable, use the new temporary initrd mapping and remove the gunk in the microcode loader which is required to handle physical address mode. Signed-off-by: Thomas Gleixner --- V5: Adopt to temporary mapping --- arch/x86/include/asm/microcode.h | 5 - arch/x86/kernel/cpu/common.c | 12 --- arch/x86/kernel/cpu/microcode/amd.c | 103 ++++++++------------------- arch/x86/kernel/cpu/microcode/core.c | 78 ++++---------------- arch/x86/kernel/cpu/microcode/intel.c | 116 ++++--------------------------- arch/x86/kernel/cpu/microcode/internal.h | 2 arch/x86/kernel/head32.c | 3 arch/x86/kernel/head_32.S | 10 -- arch/x86/kernel/smpboot.c | 12 +-- 9 files changed, 71 insertions(+), 270 deletions(-) --- --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -70,11 +70,6 @@ static inline u32 intel_get_microcode_re return rev; } - -void show_ucode_info_early(void); - -#else /* CONFIG_CPU_SUP_INTEL */ -static inline void show_ucode_info_early(void) { } #endif /* !CONFIG_CPU_SUP_INTEL */ #endif /* _ASM_X86_MICROCODE_H */ --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -2166,8 +2166,6 @@ static inline void setup_getcpu(int cpu) } #ifdef CONFIG_X86_64 -static inline void ucode_cpu_init(int cpu) { } - static inline void tss_setup_ist(struct tss_struct *tss) { /* Set up the per-CPU TSS IST stacks */ @@ -2178,16 +2176,8 @@ static inline void tss_setup_ist(struct /* Only mapped when SEV-ES is active */ tss->x86_tss.ist[IST_INDEX_VC] = __this_cpu_ist_top_va(VC); } - #else /* CONFIG_X86_64 */ - -static inline void ucode_cpu_init(int cpu) -{ - show_ucode_info_early(); -} - static inline void tss_setup_ist(struct tss_struct *tss) { } - #endif /* !CONFIG_X86_64 */ static inline void tss_setup_io_bitmap(struct tss_struct *tss) @@ -2243,8 +2233,6 @@ void cpu_init(void) struct task_struct *cur = current; int cpu = raw_smp_processor_id(); - ucode_cpu_init(cpu); - #ifdef CONFIG_NUMA if (this_cpu_read(numa_node) == 0 && early_cpu_to_node(cpu) != NUMA_NO_NODE) --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -121,24 +121,20 @@ static u16 find_equiv_id(struct equiv_cp /* * Check whether there is a valid microcode container file at the beginning - * of @buf of size @buf_size. Set @early to use this function in the early path. + * of @buf of size @buf_size. */ -static bool verify_container(const u8 *buf, size_t buf_size, bool early) +static bool verify_container(const u8 *buf, size_t buf_size) { u32 cont_magic; if (buf_size <= CONTAINER_HDR_SZ) { - if (!early) - pr_debug("Truncated microcode container header.\n"); - + pr_debug("Truncated microcode container header.\n"); return false; } cont_magic = *(const u32 *)buf; if (cont_magic != UCODE_MAGIC) { - if (!early) - pr_debug("Invalid magic value (0x%08x).\n", cont_magic); - + pr_debug("Invalid magic value (0x%08x).\n", cont_magic); return false; } @@ -147,23 +143,20 @@ static bool verify_container(const u8 *b /* * Check whether there is a valid, non-truncated CPU equivalence table at the - * beginning of @buf of size @buf_size. Set @early to use this function in the - * early path. + * beginning of @buf of size @buf_size. */ -static bool verify_equivalence_table(const u8 *buf, size_t buf_size, bool early) +static bool verify_equivalence_table(const u8 *buf, size_t buf_size) { const u32 *hdr = (const u32 *)buf; u32 cont_type, equiv_tbl_len; - if (!verify_container(buf, buf_size, early)) + if (!verify_container(buf, buf_size)) return false; cont_type = hdr[1]; if (cont_type != UCODE_EQUIV_CPU_TABLE_TYPE) { - if (!early) - pr_debug("Wrong microcode container equivalence table type: %u.\n", - cont_type); - + pr_debug("Wrong microcode container equivalence table type: %u.\n", + cont_type); return false; } @@ -172,9 +165,7 @@ static bool verify_equivalence_table(con equiv_tbl_len = hdr[2]; if (equiv_tbl_len < sizeof(struct equiv_cpu_entry) || buf_size < equiv_tbl_len) { - if (!early) - pr_debug("Truncated equivalence table.\n"); - + pr_debug("Truncated equivalence table.\n"); return false; } @@ -183,22 +174,19 @@ static bool verify_equivalence_table(con /* * Check whether there is a valid, non-truncated microcode patch section at the - * beginning of @buf of size @buf_size. Set @early to use this function in the - * early path. + * beginning of @buf of size @buf_size. * * On success, @sh_psize returns the patch size according to the section header, * to the caller. */ static bool -__verify_patch_section(const u8 *buf, size_t buf_size, u32 *sh_psize, bool early) +__verify_patch_section(const u8 *buf, size_t buf_size, u32 *sh_psize) { u32 p_type, p_size; const u32 *hdr; if (buf_size < SECTION_HDR_SIZE) { - if (!early) - pr_debug("Truncated patch section.\n"); - + pr_debug("Truncated patch section.\n"); return false; } @@ -207,17 +195,13 @@ static bool p_size = hdr[1]; if (p_type != UCODE_UCODE_TYPE) { - if (!early) - pr_debug("Invalid type field (0x%x) in container file section header.\n", - p_type); - + pr_debug("Invalid type field (0x%x) in container file section header.\n", + p_type); return false; } if (p_size < sizeof(struct microcode_header_amd)) { - if (!early) - pr_debug("Patch of size %u too short.\n", p_size); - + pr_debug("Patch of size %u too short.\n", p_size); return false; } @@ -269,7 +253,7 @@ static unsigned int __verify_patch_size( * 0: success */ static int -verify_patch(u8 family, const u8 *buf, size_t buf_size, u32 *patch_size, bool early) +verify_patch(u8 family, const u8 *buf, size_t buf_size, u32 *patch_size) { struct microcode_header_amd *mc_hdr; unsigned int ret; @@ -277,7 +261,7 @@ verify_patch(u8 family, const u8 *buf, s u16 proc_id; u8 patch_fam; - if (!__verify_patch_section(buf, buf_size, &sh_psize, early)) + if (!__verify_patch_section(buf, buf_size, &sh_psize)) return -1; /* @@ -292,16 +276,13 @@ verify_patch(u8 family, const u8 *buf, s * size sh_psize, as the section claims. */ if (buf_size < sh_psize) { - if (!early) - pr_debug("Patch of size %u truncated.\n", sh_psize); - + pr_debug("Patch of size %u truncated.\n", sh_psize); return -1; } ret = __verify_patch_size(family, sh_psize, buf_size); if (!ret) { - if (!early) - pr_debug("Per-family patch size mismatch.\n"); + pr_debug("Per-family patch size mismatch.\n"); return -1; } @@ -309,8 +290,7 @@ verify_patch(u8 family, const u8 *buf, s mc_hdr = (struct microcode_header_amd *)(buf + SECTION_HDR_SIZE); if (mc_hdr->nb_dev_id || mc_hdr->sb_dev_id) { - if (!early) - pr_err("Patch-ID 0x%08x: chipset-specific code unsupported.\n", mc_hdr->patch_id); + pr_err("Patch-ID 0x%08x: chipset-specific code unsupported.\n", mc_hdr->patch_id); return -1; } @@ -337,7 +317,7 @@ static size_t parse_container(u8 *ucode, u16 eq_id; u8 *buf; - if (!verify_equivalence_table(ucode, size, true)) + if (!verify_equivalence_table(ucode, size)) return 0; buf = ucode; @@ -364,7 +344,7 @@ static size_t parse_container(u8 *ucode, u32 patch_size; int ret; - ret = verify_patch(x86_family(desc->cpuid_1_eax), buf, size, &patch_size, true); + ret = verify_patch(x86_family(desc->cpuid_1_eax), buf, size, &patch_size); if (ret < 0) { /* * Patch verification failed, skip to the next container, if @@ -456,14 +436,8 @@ static bool early_apply_microcode(u32 cp { struct cont_desc desc = { 0 }; struct microcode_amd *mc; - u32 rev, dummy, *new_rev; bool ret = false; - -#ifdef CONFIG_X86_32 - new_rev = (u32 *)__pa_nodebug(&ucode_new_rev); -#else - new_rev = &ucode_new_rev; -#endif + u32 rev, dummy; desc.cpuid_1_eax = cpuid_1_eax; @@ -484,8 +458,8 @@ static bool early_apply_microcode(u32 cp return ret; if (!__apply_microcode_amd(mc)) { - *new_rev = mc->hdr.patch_id; - ret = true; + ucode_new_rev = mc->hdr.patch_id; + ret = true; } return ret; @@ -514,26 +488,13 @@ static bool get_builtin_microcode(struct static void find_blobs_in_containers(unsigned int cpuid_1_eax, struct cpio_data *ret) { - struct ucode_cpu_info *uci; struct cpio_data cp; - const char *path; - bool use_pa; - - if (IS_ENABLED(CONFIG_X86_32)) { - uci = (struct ucode_cpu_info *)__pa_nodebug(ucode_cpu_info); - path = (const char *)__pa_nodebug(ucode_path); - use_pa = true; - } else { - uci = ucode_cpu_info; - path = ucode_path; - use_pa = false; - } if (!get_builtin_microcode(&cp, x86_family(cpuid_1_eax))) - cp = find_microcode_in_initrd(path, use_pa); + cp = find_microcode_in_initrd(ucode_path); /* Needed in load_microcode_amd() */ - uci->cpu_sig.sig = cpuid_1_eax; + ucode_cpu_info->cpu_sig.sig = cpuid_1_eax; *ret = cp; } @@ -562,7 +523,7 @@ int __init save_microcode_in_initrd_amd( enum ucode_state ret; struct cpio_data cp; - cp = find_microcode_in_initrd(ucode_path, false); + cp = find_microcode_in_initrd(ucode_path); if (!(cp.data && cp.size)) return -EINVAL; @@ -738,7 +699,7 @@ static size_t install_equiv_cpu_table(co u32 equiv_tbl_len; const u32 *hdr; - if (!verify_equivalence_table(buf, buf_size, false)) + if (!verify_equivalence_table(buf, buf_size)) return 0; hdr = (const u32 *)buf; @@ -784,7 +745,7 @@ static int verify_and_add_patch(u8 famil u16 proc_id; int ret; - ret = verify_patch(family, fw, leftover, patch_size, false); + ret = verify_patch(family, fw, leftover, patch_size); if (ret) return ret; @@ -918,7 +879,7 @@ static enum ucode_state request_microcod } ret = UCODE_ERROR; - if (!verify_container(fw->data, fw->size, false)) + if (!verify_container(fw->data, fw->size)) goto fw_release; ret = load_microcode_amd(c->x86, fw->data, fw->size); --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -90,10 +90,7 @@ static bool amd_check_current_patch_leve native_rdmsr(MSR_AMD64_PATCH_LEVEL, lvl, dummy); - if (IS_ENABLED(CONFIG_X86_32)) - levels = (u32 *)__pa_nodebug(&final_levels); - else - levels = final_levels; + levels = final_levels; for (i = 0; levels[i]; i++) { if (lvl == levels[i]) @@ -105,17 +102,8 @@ static bool amd_check_current_patch_leve static bool __init check_loader_disabled_bsp(void) { static const char *__dis_opt_str = "dis_ucode_ldr"; - -#ifdef CONFIG_X86_32 - const char *cmdline = (const char *)__pa_nodebug(boot_command_line); - const char *option = (const char *)__pa_nodebug(__dis_opt_str); - bool *res = (bool *)__pa_nodebug(&dis_ucode_ldr); - -#else /* CONFIG_X86_64 */ const char *cmdline = boot_command_line; const char *option = __dis_opt_str; - bool *res = &dis_ucode_ldr; -#endif /* * CPUID(1).ECX[31]: reserved for hypervisor use. This is still not @@ -123,17 +111,17 @@ static bool __init check_loader_disabled * that's good enough as they don't land on the BSP path anyway. */ if (native_cpuid_ecx(1) & BIT(31)) - return *res; + return true; if (x86_cpuid_vendor() == X86_VENDOR_AMD) { if (amd_check_current_patch_level()) - return *res; + return true; } if (cmdline_find_option_bool(cmdline, option) <= 0) - *res = false; + dis_ucode_ldr = false; - return *res; + return dis_ucode_ldr; } void __init load_ucode_bsp(void) @@ -171,20 +159,11 @@ void __init load_ucode_bsp(void) load_ucode_amd_early(cpuid_1_eax); } -static bool check_loader_disabled_ap(void) -{ -#ifdef CONFIG_X86_32 - return *((bool *)__pa_nodebug(&dis_ucode_ldr)); -#else - return dis_ucode_ldr; -#endif -} - void load_ucode_ap(void) { unsigned int cpuid_1_eax; - if (check_loader_disabled_ap()) + if (dis_ucode_ldr) return; cpuid_1_eax = native_cpuid_eax(1); @@ -226,40 +205,28 @@ static int __init save_microcode_in_init return ret; } -struct cpio_data find_microcode_in_initrd(const char *path, bool use_pa) +struct cpio_data find_microcode_in_initrd(const char *path) { #ifdef CONFIG_BLK_DEV_INITRD unsigned long start = 0; size_t size; #ifdef CONFIG_X86_32 - struct boot_params *params; - - if (use_pa) - params = (struct boot_params *)__pa_nodebug(&boot_params); - else - params = &boot_params; - - size = params->hdr.ramdisk_size; - - /* - * Set start only if we have an initrd image. We cannot use initrd_start - * because it is not set that early yet. - */ + size = boot_params.hdr.ramdisk_size; + /* Early load on BSP has a temporary mapping. */ if (size) - start = params->hdr.ramdisk_image; + start = initrd_start_early; -# else /* CONFIG_X86_64 */ +#else /* CONFIG_X86_64 */ size = (unsigned long)boot_params.ext_ramdisk_size << 32; size |= boot_params.hdr.ramdisk_size; if (size) { start = (unsigned long)boot_params.ext_ramdisk_image << 32; start |= boot_params.hdr.ramdisk_image; - start += PAGE_OFFSET; } -# endif +#endif /* * Fixup the start address: after reserve_initrd() runs, initrd_start @@ -270,23 +237,10 @@ struct cpio_data find_microcode_in_initr * initrd_gone is for the hotplug case where we've thrown out initrd * already. */ - if (!use_pa) { - if (initrd_gone) - return (struct cpio_data){ NULL, 0, "" }; - if (initrd_start) - start = initrd_start; - } else { - /* - * The picture with physical addresses is a bit different: we - * need to get the *physical* address to which the ramdisk was - * relocated, i.e., relocated_ramdisk (not initrd_start) and - * since we're running from physical addresses, we need to access - * relocated_ramdisk through its *physical* address too. - */ - u64 *rr = (u64 *)__pa_nodebug(&relocated_ramdisk); - if (*rr) - start = *rr; - } + if (initrd_gone) + return (struct cpio_data){ NULL, 0, "" }; + if (initrd_start) + start = initrd_start; return find_cpio_data(path, (void *)start, size, NULL); #else /* !CONFIG_BLK_DEV_INITRD */ --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -319,15 +319,8 @@ static void save_microcode_patch(struct if (!intel_find_matching_signature(p->data, uci->cpu_sig.sig, uci->cpu_sig.pf)) return; - /* - * Save for early loading. On 32-bit, that needs to be a physical - * address as the APs are running from physical addresses, before - * paging has been enabled. - */ - if (IS_ENABLED(CONFIG_X86_32)) - intel_ucode_patch = (struct microcode_intel *)__pa_nodebug(p->data); - else - intel_ucode_patch = p->data; + /* Save for early loading */ + intel_ucode_patch = p->data; } /* @@ -420,66 +413,10 @@ static bool load_builtin_intel_microcode return false; } -static void print_ucode_info(int old_rev, int new_rev, unsigned int date) -{ - pr_info_once("updated early: 0x%x -> 0x%x, date = %04x-%02x-%02x\n", - old_rev, - new_rev, - date & 0xffff, - date >> 24, - (date >> 16) & 0xff); -} - -#ifdef CONFIG_X86_32 - -static int delay_ucode_info; -static int current_mc_date; -static int early_old_rev; - -/* - * Print early updated ucode info after printk works. This is delayed info dump. - */ -void show_ucode_info_early(void) -{ - struct ucode_cpu_info uci; - - if (delay_ucode_info) { - intel_cpu_collect_info(&uci); - print_ucode_info(early_old_rev, uci.cpu_sig.rev, current_mc_date); - delay_ucode_info = 0; - } -} - -/* - * At this point, we can not call printk() yet. Delay printing microcode info in - * show_ucode_info_early() until printk() works. - */ -static void print_ucode(int old_rev, int new_rev, int date) -{ - int *delay_ucode_info_p; - int *current_mc_date_p; - int *early_old_rev_p; - - delay_ucode_info_p = (int *)__pa_nodebug(&delay_ucode_info); - current_mc_date_p = (int *)__pa_nodebug(¤t_mc_date); - early_old_rev_p = (int *)__pa_nodebug(&early_old_rev); - - *delay_ucode_info_p = 1; - *current_mc_date_p = date; - *early_old_rev_p = old_rev; -} -#else - -static inline void print_ucode(int old_rev, int new_rev, int date) -{ - print_ucode_info(old_rev, new_rev, date); -} -#endif - -static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) +static int apply_microcode_early(struct ucode_cpu_info *uci) { struct microcode_intel *mc; - u32 rev, old_rev; + u32 rev, old_rev, date; mc = uci->mc; if (!mc) @@ -513,11 +450,9 @@ static int apply_microcode_early(struct uci->cpu_sig.rev = rev; - if (early) - print_ucode(old_rev, uci->cpu_sig.rev, mc->hdr.date); - else - print_ucode_info(old_rev, uci->cpu_sig.rev, mc->hdr.date); - + date = mc->hdr.date; + pr_info_once("updated early: 0x%x -> 0x%x, date = %04x-%02x-%02x\n", + old_rev, rev, date & 0xffff, date >> 24, (date >> 16) & 0xff); return 0; } @@ -535,7 +470,7 @@ int __init save_microcode_in_initrd_inte intel_ucode_patch = NULL; if (!load_builtin_intel_microcode(&cp)) - cp = find_microcode_in_initrd(ucode_path, false); + cp = find_microcode_in_initrd(ucode_path); if (!(cp.data && cp.size)) return 0; @@ -551,21 +486,11 @@ int __init save_microcode_in_initrd_inte */ static struct microcode_intel *__load_ucode_intel(struct ucode_cpu_info *uci) { - static const char *path; struct cpio_data cp; - bool use_pa; - - if (IS_ENABLED(CONFIG_X86_32)) { - path = (const char *)__pa_nodebug(ucode_path); - use_pa = true; - } else { - path = ucode_path; - use_pa = false; - } /* try built-in microcode first */ if (!load_builtin_intel_microcode(&cp)) - cp = find_microcode_in_initrd(path, use_pa); + cp = find_microcode_in_initrd(ucode_path); if (!(cp.data && cp.size)) return NULL; @@ -586,30 +511,21 @@ void __init load_ucode_intel_bsp(void) uci.mc = patch; - apply_microcode_early(&uci, true); + apply_microcode_early(&uci); } void load_ucode_intel_ap(void) { - struct microcode_intel *patch, **iup; struct ucode_cpu_info uci; - if (IS_ENABLED(CONFIG_X86_32)) - iup = (struct microcode_intel **) __pa_nodebug(&intel_ucode_patch); - else - iup = &intel_ucode_patch; - - if (!*iup) { - patch = __load_ucode_intel(&uci); - if (!patch) + if (!intel_ucode_patch) { + intel_ucode_patch = __load_ucode_intel(&uci); + if (!intel_ucode_patch) return; - - *iup = patch; } - uci.mc = *iup; - - apply_microcode_early(&uci, true); + uci.mc = intel_ucode_patch; + apply_microcode_early(&uci); } static struct microcode_intel *find_patch(struct ucode_cpu_info *uci) @@ -647,7 +563,7 @@ void reload_ucode_intel(void) uci.mc = p; - apply_microcode_early(&uci, false); + apply_microcode_early(&uci); } static int collect_cpu_info(int cpu_num, struct cpu_signature *csig) --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -44,7 +44,7 @@ struct microcode_ops { }; extern struct ucode_cpu_info ucode_cpu_info[]; -struct cpio_data find_microcode_in_initrd(const char *path, bool use_pa); +struct cpio_data find_microcode_in_initrd(const char *path); #define MAX_UCODE_COUNT 128 --- a/arch/x86/kernel/head32.c +++ b/arch/x86/kernel/head32.c @@ -19,6 +19,7 @@ #include #include #include +#include #include #include @@ -53,7 +54,7 @@ asmlinkage __visible void __init __noret /* Make sure IDT is set up before any exception happens */ idt_setup_early_handler(); - /* load_ucode_bsp() */ + load_ucode_bsp(); zap_early_initrd_mapping(); cr4_init_shadow(); --- a/arch/x86/kernel/head_32.S +++ b/arch/x86/kernel/head_32.S @@ -118,11 +118,6 @@ SYM_CODE_START(startup_32) movl %eax, pa(olpc_ofw_pgd) #endif -#ifdef CONFIG_MICROCODE - /* Early load ucode on BSP. */ - call load_ucode_bsp -#endif - /* Create early pagetables. */ call mk_early_pgtbl_32 @@ -157,11 +152,6 @@ SYM_FUNC_START(startup_32_smp) movl %eax,%ss leal -__PAGE_OFFSET(%ecx),%esp -#ifdef CONFIG_MICROCODE - /* Early load ucode on AP. */ - call load_ucode_ap -#endif - .Ldefault_entry: movl $(CR0_STATE & ~X86_CR0_PG),%eax movl %eax,%cr0 --- a/arch/x86/kernel/smpboot.c +++ b/arch/x86/kernel/smpboot.c @@ -258,12 +258,9 @@ static void notrace start_secondary(void cpu_init_exception_handling(); /* - * 32-bit systems load the microcode from the ASM startup code for - * historical reasons. - * - * On 64-bit systems load it before reaching the AP alive - * synchronization point below so it is not part of the full per - * CPU serialized bringup part when "parallel" bringup is enabled. + * Load the microcode before reaching the AP alive synchronization + * point below so it is not part of the full per CPU serialized + * bringup part when "parallel" bringup is enabled. * * That's even safe when hyperthreading is enabled in the CPU as * the core code starts the primary threads first and leaves the @@ -276,8 +273,7 @@ static void notrace start_secondary(void * CPUID, MSRs etc. must be strictly serialized to maintain * software state correctness. */ - if (IS_ENABLED(CONFIG_X86_64)) - load_ucode_ap(); + load_ucode_ap(); /* * Synchronization point with the hotplug core. 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[23.128.96.38]) by mx.google.com with ESMTPS id d8-20020a170902cec800b001c1f1394bf9si2803748plg.357.2023.10.17.14.25.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 14:25:07 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) client-ip=23.128.96.38; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=YMZgiIJq; dkim=neutral (no key) header.i=@linutronix.de header.b=aA5P6cAd; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by fry.vger.email (Postfix) with ESMTP id 614FE80FC15F; Tue, 17 Oct 2023 14:24:59 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at fry.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343997AbjJQVX4 (ORCPT + 21 others); Tue, 17 Oct 2023 17:23:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33354 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344261AbjJQVXo (ORCPT ); Tue, 17 Oct 2023 17:23:44 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A3CB2113 for ; Tue, 17 Oct 2023 14:23:35 -0700 (PDT) Message-ID: <20231017211722.404362809@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1697577814; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=qLdDIl2mZ+CWLaLjL64BzzcibNcGCr9vh3NZAsceVbo=; b=YMZgiIJq4zd4JlcOiWeY5F5RhU84IewfR18KGHFrk+oyOErhsdG5XzBZqLgWh1RzQMAwoG 2yYdFEVtQ7pn3Z5lkvjVeu0b/2GLv7p7U1NTI3HrI+NJWWlSpB30rHErpxS+UPMaLNcQjB dRFuFHlqG6MKHfRE+caFUi7VUHMW8e+wjBnkBXUh62xy9I6L4jOU1y0ouZf8eWXeaGLAIZ KpASRug0GVuE8PeZI+6xuCrGmah/DZGZ98AiWeE0GxoHADkTRf0C+efdBiwLhcnW9KNnwm rxMd4zULFehaJHrZd7YiQDVjCcozSOIrXYprCQv1mB2bk2rF9eT5wZ/3stwO5Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1697577814; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=qLdDIl2mZ+CWLaLjL64BzzcibNcGCr9vh3NZAsceVbo=; b=aA5P6cAdd9WmK1K9g/F3k0gEftfyXHShoU+ozmrY476Gjk3tHYqrkUmV8DFhC8tMOQ2EG0 xQD7+hdUsEIdD/Cw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj Subject: [patch V5 08/39] x86/microcode/intel: Rip out mixed stepping support for Intel CPUs References: <20231017200758.877560658@linutronix.de> MIME-Version: 1.0 Date: Tue, 17 Oct 2023 23:23:33 +0200 (CEST) X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Tue, 17 Oct 2023 14:24:59 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780039451873582211 X-GMAIL-MSGID: 1780039451873582211 From: Ashok Raj Mixed steppings aren't supported on Intel CPUs. Only one microcode patch is required for the entire system. The caching of microcode blobs which match the family and model is therefore pointless and in fact is dysfunctional as CPU hotplug updates use only a single microcode blob, i.e. the one where *intel_ucode_patch points to. Remove the microcode cache and make it an AMD local feature. [ tglx: Save only at the end. Otherwise random microcode ends up in the pointer for early loading ] Originally-by: Thomas Gleixner Signed-off-by: Ashok Raj Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/amd.c | 10 ++- arch/x86/kernel/cpu/microcode/core.c | 2 +- arch/x86/kernel/cpu/microcode/intel.c | 133 ++++++-------------------------- arch/x86/kernel/cpu/microcode/internal.h | 10 +-- 4 files changed, 35 insertions(+), 120 deletions(-) --- diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/microcode/amd.c index ccca39f063bb..0f15e82a536c 100644 --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -37,6 +37,16 @@ #include "internal.h" +struct ucode_patch { + struct list_head plist; + void *data; + unsigned int size; + u32 patch_id; + u16 equiv_cpu; +}; + +static LIST_HEAD(microcode_cache); + #define UCODE_MAGIC 0x00414d44 #define UCODE_EQUIV_CPU_TABLE_TYPE 0x00000000 #define UCODE_UCODE_TYPE 0x00000001 diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c index f76c2c102810..4366a33030a9 100644 --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -46,8 +46,6 @@ static bool dis_ucode_ldr = true; bool initrd_gone; -LIST_HEAD(microcode_cache); - /* * Synchronization. * diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index 24a5c8b594c6..1f45f5c44246 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -33,10 +33,10 @@ static const char ucode_path[] = "kernel/x86/microcode/GenuineIntel.bin"; /* Current microcode patch used in early patching on the APs. */ -static struct microcode_intel *intel_ucode_patch; +static struct microcode_intel *intel_ucode_patch __read_mostly; /* last level cache size per core */ -static int llc_size_per_core; +static int llc_size_per_core __ro_after_init; /* microcode format is extended from prescott processors */ struct extended_signature { @@ -253,74 +253,19 @@ static int has_newer_microcode(void *mc, unsigned int csig, int cpf, int new_rev return intel_find_matching_signature(mc, csig, cpf); } -static struct ucode_patch *memdup_patch(void *data, unsigned int size) +static void save_microcode_patch(void *data, unsigned int size) { - struct ucode_patch *p; + struct microcode_header_intel *p; - p = kzalloc(sizeof(struct ucode_patch), GFP_KERNEL); - if (!p) - return NULL; - - p->data = kmemdup(data, size, GFP_KERNEL); - if (!p->data) { - kfree(p); - return NULL; - } - - return p; -} - -static void save_microcode_patch(struct ucode_cpu_info *uci, void *data, unsigned int size) -{ - struct microcode_header_intel *mc_hdr, *mc_saved_hdr; - struct ucode_patch *iter, *tmp, *p = NULL; - bool prev_found = false; - unsigned int sig, pf; - - mc_hdr = (struct microcode_header_intel *)data; - - list_for_each_entry_safe(iter, tmp, µcode_cache, plist) { - mc_saved_hdr = (struct microcode_header_intel *)iter->data; - sig = mc_saved_hdr->sig; - pf = mc_saved_hdr->pf; - - if (intel_find_matching_signature(data, sig, pf)) { - prev_found = true; - - if (mc_hdr->rev <= mc_saved_hdr->rev) - continue; - - p = memdup_patch(data, size); - if (!p) - pr_err("Error allocating buffer %p\n", data); - else { - list_replace(&iter->plist, &p->plist); - kfree(iter->data); - kfree(iter); - } - } - } - - /* - * There weren't any previous patches found in the list cache; save the - * newly found. - */ - if (!prev_found) { - p = memdup_patch(data, size); - if (!p) - pr_err("Error allocating buffer for %p\n", data); - else - list_add_tail(&p->plist, µcode_cache); - } + kfree(intel_ucode_patch); + intel_ucode_patch = NULL; + p = kmemdup(data, size, GFP_KERNEL); if (!p) return; - if (!intel_find_matching_signature(p->data, uci->cpu_sig.sig, uci->cpu_sig.pf)) - return; - /* Save for early loading */ - intel_ucode_patch = p->data; + intel_ucode_patch = (struct microcode_intel *)p; } /* @@ -332,6 +277,7 @@ scan_microcode(void *data, size_t size, struct ucode_cpu_info *uci, bool save) { struct microcode_header_intel *mc_header; struct microcode_intel *patch = NULL; + u32 cur_rev = uci->cpu_sig.rev; unsigned int mc_size; while (size) { @@ -341,8 +287,7 @@ scan_microcode(void *data, size_t size, struct ucode_cpu_info *uci, bool save) mc_header = (struct microcode_header_intel *)data; mc_size = get_totalsize(mc_header); - if (!mc_size || - mc_size > size || + if (!mc_size || mc_size > size || intel_microcode_sanity_check(data, false, MC_HEADER_TYPE_MICROCODE) < 0) break; @@ -354,31 +299,16 @@ scan_microcode(void *data, size_t size, struct ucode_cpu_info *uci, bool save) continue; } - if (save) { - save_microcode_patch(uci, data, mc_size); + /* BSP scan: Check whether there is newer microcode */ + if (!save && cur_rev >= mc_header->rev) goto next; - } - - - if (!patch) { - if (!has_newer_microcode(data, - uci->cpu_sig.sig, - uci->cpu_sig.pf, - uci->cpu_sig.rev)) - goto next; - } else { - struct microcode_header_intel *phdr = &patch->hdr; - - if (!has_newer_microcode(data, - phdr->sig, - phdr->pf, - phdr->rev)) - goto next; - } + /* Save scan: Check whether there is newer or matching microcode */ + if (save && cur_rev != mc_header->rev) + goto next; - /* We have a newer patch, save it. */ patch = data; + cur_rev = mc_header->rev; next: data += mc_size; @@ -387,6 +317,9 @@ scan_microcode(void *data, size_t size, struct ucode_cpu_info *uci, bool save) if (size) return NULL; + if (save && patch) + save_microcode_patch(patch, mc_size); + return patch; } @@ -528,26 +461,10 @@ void load_ucode_intel_ap(void) apply_microcode_early(&uci); } -static struct microcode_intel *find_patch(struct ucode_cpu_info *uci) +/* Accessor for microcode pointer */ +static struct microcode_intel *ucode_get_patch(void) { - struct microcode_header_intel *phdr; - struct ucode_patch *iter, *tmp; - - list_for_each_entry_safe(iter, tmp, µcode_cache, plist) { - - phdr = (struct microcode_header_intel *)iter->data; - - if (phdr->rev <= uci->cpu_sig.rev) - continue; - - if (!intel_find_matching_signature(phdr, - uci->cpu_sig.sig, - uci->cpu_sig.pf)) - continue; - - return iter->data; - } - return NULL; + return intel_ucode_patch; } void reload_ucode_intel(void) @@ -557,7 +474,7 @@ void reload_ucode_intel(void) intel_cpu_collect_info(&uci); - p = find_patch(&uci); + p = ucode_get_patch(); if (!p) return; @@ -601,7 +518,7 @@ static enum ucode_state apply_microcode_intel(int cpu) return UCODE_ERROR; /* Look for a newer patch in our cache: */ - mc = find_patch(uci); + mc = ucode_get_patch(); if (!mc) { mc = uci->mc; if (!mc) @@ -730,7 +647,7 @@ static enum ucode_state generic_load_microcode(int cpu, struct iov_iter *iter) uci->mc = (struct microcode_intel *)new_mc; /* Save for CPU hotplug */ - save_microcode_patch(uci, new_mc, new_mc_size); + save_microcode_patch(new_mc, new_mc_size); pr_debug("CPU%d found a matching microcode update with version 0x%x (current=0x%x)\n", cpu, new_rev, uci->cpu_sig.rev); diff --git a/arch/x86/kernel/cpu/microcode/internal.h b/arch/x86/kernel/cpu/microcode/internal.h index 8843c32480ef..6001da4c946a 100644 --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -8,16 +8,6 @@ #include #include -struct ucode_patch { - struct list_head plist; - void *data; /* Intel uses only this one */ - unsigned int size; - u32 patch_id; - u16 equiv_cpu; -}; - -extern struct list_head microcode_cache; - struct device; enum ucode_state { From patchwork Tue Oct 17 21:23:35 2023 Content-Type: text/plain; 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Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/intel.c | 28 +++++++--------------------- 1 file changed, 7 insertions(+), 21 deletions(-) --- diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index 1f45f5c44246..24dd4835d544 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -268,22 +268,16 @@ static void save_microcode_patch(void *data, unsigned int size) intel_ucode_patch = (struct microcode_intel *)p; } -/* - * Get microcode matching with BSP's model. Only CPUs with the same model as - * BSP can stay in the platform. - */ -static struct microcode_intel * -scan_microcode(void *data, size_t size, struct ucode_cpu_info *uci, bool save) +/* Scan CPIO for microcode matching the boot CPU's family, model, stepping */ +static struct microcode_intel *scan_microcode(void *data, size_t size, + struct ucode_cpu_info *uci, bool save) { struct microcode_header_intel *mc_header; struct microcode_intel *patch = NULL; u32 cur_rev = uci->cpu_sig.rev; unsigned int mc_size; - while (size) { - if (size < sizeof(struct microcode_header_intel)) - break; - + for (; size >= sizeof(struct microcode_header_intel); size -= mc_size, data += mc_size) { mc_header = (struct microcode_header_intel *)data; mc_size = get_totalsize(mc_header); @@ -291,27 +285,19 @@ scan_microcode(void *data, size_t size, struct ucode_cpu_info *uci, bool save) intel_microcode_sanity_check(data, false, MC_HEADER_TYPE_MICROCODE) < 0) break; - size -= mc_size; - - if (!intel_find_matching_signature(data, uci->cpu_sig.sig, - uci->cpu_sig.pf)) { - data += mc_size; + if (!intel_find_matching_signature(data, uci->cpu_sig.sig, uci->cpu_sig.pf)) continue; - } /* BSP scan: Check whether there is newer microcode */ if (!save && cur_rev >= mc_header->rev) - goto next; + continue; /* Save scan: Check whether there is newer or matching microcode */ if (save && cur_rev != mc_header->rev) - goto next; + continue; patch = data; cur_rev = mc_header->rev; - -next: - data += mc_size; } if (size) From patchwork Tue Oct 17 21:23:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 154547 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp4406341vqb; Tue, 17 Oct 2023 14:24:35 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGpZaGJsysxk0PwIUrHWTOGJ8jLLNmsX/GpebLKyM/fJlcvnYBh/Wq3kEAZmPrcGPBlCVkg X-Received: by 2002:a05:6870:cb89:b0:192:6fce:d3be with SMTP id ov9-20020a056870cb8900b001926fced3bemr3450470oab.1.1697577875424; Tue, 17 Oct 2023 14:24:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697577875; cv=none; d=google.com; s=arc-20160816; b=JwYPnuaYByq+bz6NQoFDNs/o4FDKS/r9Y7jADl8zFZv9C/uBIZRuwxuYI0C725VSBh Sq6ZHZD9S8CXc1ePh3YXFW1cU56k4c0GG+s0qQp/Oh8NXfLUi+/axzd8xZwOi3KuHDRz c/z7lIe4JwBszQuXTvOT7H/S6WhebPAa65HUmmccJa3CUyHlDWMW12vsZ/7eO1YpBfGd Vx6WakHasCATPUM/OYzIEjblPMYMydp+uOHPG0uHEn35y+q/LC6+iW/RgjBbfN0+6YhQ 1ud1wVc35bvBWS1mJRqDY598SkyLvw9dQ8P7gdI4Z2whHZKo3FcBJEqi3n21aOqnwoHN dsTw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=boldlZsu3iXRBUur5KXLfTWW2rgpdymImyUkM2N8NEs=; fh=8iy+GLBXZdpcs/hIddJ7mbUapYjefwP9Gb111pAzFms=; b=LLd7jRnNmdEzglnk6T/QhCxkWwhUkty33QQs1pcmZweuoFFh1cK8tMwaPn9fmUF5Dq MN7T0a9aqu2RndqmcAIZawQT7DTMbYTycB7hper95AqoXcFVNxyxDYXbcg2bjwa/DAzE j/v57Nd9TkziWUFm/baaJ6fDizXmfAIv2li4Ekjvu+x+SfAaIuaDntIIbkxBRuiIhkFn CKMe2NpZ7l/WjUeHUrguNNvPGt3ZZDHRNkaIO5+oNmHY3xnW4bTmODrzAeXZtbiUBGbD fmT9r380yTk+iczClQ/w2XgCrR1odR9pvw5RXeO1BA2LEj6A4YE9R/tuYwwNA8WFx3+M kh2Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=ZN0wB1Sa; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=+n2LCZfC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from lipwig.vger.email (lipwig.vger.email. [2620:137:e000::3:3]) by mx.google.com with ESMTPS id s85-20020a632c58000000b005b22561c968si647346pgs.499.2023.10.17.14.24.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 14:24:35 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) client-ip=2620:137:e000::3:3; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=ZN0wB1Sa; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=+n2LCZfC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id 426AF80F5F2E; Tue, 17 Oct 2023 14:24:31 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235096AbjJQVYJ (ORCPT + 21 others); Tue, 17 Oct 2023 17:24:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33378 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344066AbjJQVXt (ORCPT ); Tue, 17 Oct 2023 17:23:49 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D0044129 for ; Tue, 17 Oct 2023 14:23:38 -0700 (PDT) Message-ID: <20231017211722.517552303@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1697577817; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=boldlZsu3iXRBUur5KXLfTWW2rgpdymImyUkM2N8NEs=; b=ZN0wB1Sa3PhA3W/8di2L5k23vnAsdRL/uAdcWAyMg5lpX5uasXVvBXxjW939++yM9IKIiV YJadtQvxxot3QsHrmTkZpd5cLzeqR4bw5Qh8Y5qywBjisNcAQ+9YxU3xsJywo1PrSwnZfV 0aPn2D3556zMp5DKC9OuDprK46vMq/Qju4mBaD3BCP4SzwlBBLFYS5juL8F4BO0Uj8ZR4O 41A8fBQhtMMUsIRRva6OBnT1t1Cnqu1eaMv62RIFxxTiygmVI4+Kw1ft2VC0yFwvF0WypX qSKZ0oWvxHWrbjnqMtpWCjJamPOrZAHdrm7bOIG31Tw3rFyJSV0XEaLaOvJ26w== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1697577817; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=boldlZsu3iXRBUur5KXLfTWW2rgpdymImyUkM2N8NEs=; b=+n2LCZfCJidgtFyJOpagqxmlTf7NeiRt2sSo7JIoCqBxGZkWF/Jr44VE7JIidvGpqb7oDH l4T/AF7BsLStLEBg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov Subject: [patch V5 10/39] x86/microcode/intel: Simplify and rename generic_load_microcode() References: <20231017200758.877560658@linutronix.de> MIME-Version: 1.0 Date: Tue, 17 Oct 2023 23:23:36 +0200 (CEST) X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Tue, 17 Oct 2023 14:24:31 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780039418014569303 X-GMAIL-MSGID: 1780039418014569303 From: Thomas Gleixner so it becomes less obfuscated and rename it because there is nothing generic about it. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/intel.c | 47 +++++++++++++----------------------- 1 file changed, 17 insertions(+), 30 deletions(-) --- diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index 24dd4835d544..60862f6c0ded 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -240,19 +240,6 @@ int intel_microcode_sanity_check(void *mc, bool print_err, int hdr_type) } EXPORT_SYMBOL_GPL(intel_microcode_sanity_check); -/* - * Returns 1 if update has been found, 0 otherwise. - */ -static int has_newer_microcode(void *mc, unsigned int csig, int cpf, int new_rev) -{ - struct microcode_header_intel *mc_hdr = mc; - - if (mc_hdr->rev <= new_rev) - return 0; - - return intel_find_matching_signature(mc, csig, cpf); -} - static void save_microcode_patch(void *data, unsigned int size) { struct microcode_header_intel *p; @@ -561,14 +548,12 @@ static enum ucode_state apply_microcode_intel(int cpu) return ret; } -static enum ucode_state generic_load_microcode(int cpu, struct iov_iter *iter) +static enum ucode_state parse_microcode_blobs(int cpu, struct iov_iter *iter) { struct ucode_cpu_info *uci = ucode_cpu_info + cpu; unsigned int curr_mc_size = 0, new_mc_size = 0; - enum ucode_state ret = UCODE_OK; - int new_rev = uci->cpu_sig.rev; + int cur_rev = uci->cpu_sig.rev; u8 *new_mc = NULL, *mc = NULL; - unsigned int csig, cpf; while (iov_iter_count(iter)) { struct microcode_header_intel mc_header; @@ -585,6 +570,7 @@ static enum ucode_state generic_load_microcode(int cpu, struct iov_iter *iter) pr_err("error! Bad data in microcode data file (totalsize too small)\n"); break; } + data_size = mc_size - sizeof(mc_header); if (data_size > iov_iter_count(iter)) { pr_err("error! Bad data in microcode data file (truncated file?)\n"); @@ -607,16 +593,17 @@ static enum ucode_state generic_load_microcode(int cpu, struct iov_iter *iter) break; } - csig = uci->cpu_sig.sig; - cpf = uci->cpu_sig.pf; - if (has_newer_microcode(mc, csig, cpf, new_rev)) { - vfree(new_mc); - new_rev = mc_header.rev; - new_mc = mc; - new_mc_size = mc_size; - mc = NULL; /* trigger new vmalloc */ - ret = UCODE_NEW; - } + if (cur_rev >= mc_header.rev) + continue; + + if (!intel_find_matching_signature(mc, uci->cpu_sig.sig, uci->cpu_sig.pf)) + continue; + + vfree(new_mc); + cur_rev = mc_header.rev; + new_mc = mc; + new_mc_size = mc_size; + mc = NULL; } vfree(mc); @@ -636,9 +623,9 @@ static enum ucode_state generic_load_microcode(int cpu, struct iov_iter *iter) save_microcode_patch(new_mc, new_mc_size); pr_debug("CPU%d found a matching microcode update with version 0x%x (current=0x%x)\n", - cpu, new_rev, uci->cpu_sig.rev); + cpu, cur_rev, uci->cpu_sig.rev); - return ret; + return UCODE_NEW; } static bool is_blacklisted(unsigned int cpu) @@ -687,7 +674,7 @@ static enum ucode_state request_microcode_fw(int cpu, struct device *device) kvec.iov_base = (void *)firmware->data; kvec.iov_len = firmware->size; iov_iter_kvec(&iter, ITER_SOURCE, &kvec, 1, firmware->size); - ret = generic_load_microcode(cpu, &iter); + ret = parse_microcode_blobs(cpu, &iter); release_firmware(firmware); From patchwork Tue Oct 17 21:23:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 154544 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp4406303vqb; Tue, 17 Oct 2023 14:24:28 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEFyEdbzFSP8Nr4d8eIWF4+Eb5fl/IWQFZCFyWy6CvTkecYAVVRZGJGkxzAk5LyK1QrnH70 X-Received: by 2002:a17:902:bd07:b0:1ca:28f3:569a with SMTP id p7-20020a170902bd0700b001ca28f3569amr3424620pls.5.1697577868427; Tue, 17 Oct 2023 14:24:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697577868; cv=none; d=google.com; s=arc-20160816; b=kdgtPg44FRfQmdAfeWyfFaUY04//f0NI0GlCjIt79Mjortiyva2NgLxOYCYYUXY+cP SFB1AU+4bVRqQbGDI2FNRa4nBqzMj7na3ZNKwOqixUECrAh4tumzEj57ZLI6yiC939Vy cQNSpmVJkZ4dr1V7n9jlUqEQdvIwgEW08J9ixvH+UetpUCYmZZOzjqF985Sg2V1boYL1 CEzrOO/2blbg00Jr+8uzKj5e86VmydkUGt0QKnCmXme0xoQURcSpHYs+Hj/3IWCry1KJ 9CRwDM6KI/7vjD0JoziahKJ9g2Tcs5jPvlgwSCXTHofIcSVLWOji1KoAzrnmKEbkVsX9 EuTw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=05Gqko9jJI9HsYd+9soRg3VHFk81iJGJf/+onp0NjzU=; fh=8iy+GLBXZdpcs/hIddJ7mbUapYjefwP9Gb111pAzFms=; b=EhQFlBbEwvFiGGuHTSmSgOkcLRSJOXA7zsCGkLIVPIoCM8hk5f0qzWRNpqXOosOier N2s3RPLRQ2VDtOJ0IvKEyrNi9Y1vev77axhwTq13u7Iq01KG2lZrMsay2dtWMa344FvE sNidVIgLbfrg5fH5BZ/bt0Dliyt63LPjdya8IIf7vU0LbhsHDqg2erXNxQjDlV+rs338 eJ9Oo5Rku7DkRC3BP+qdjdGPFFOXlK6JQkJ/qdEH5lOuwEud4j3LF5T6GP6+D2dsJMvs ok41YfiD0RSb7UTA6HrxhYZn99oejxMGI421yUZObOmi3CJyvFqQWEDX6Pgl8FFYbLz7 Ba0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=rKfuiann; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=lbPebnvW; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id u14-20020a170902e5ce00b001c752577582si2923688plf.359.2023.10.17.14.24.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 14:24:28 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=rKfuiann; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=lbPebnvW; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 9AC3F81043A6; Tue, 17 Oct 2023 14:24:27 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234679AbjJQVYQ (ORCPT + 21 others); Tue, 17 Oct 2023 17:24:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234836AbjJQVXy (ORCPT ); Tue, 17 Oct 2023 17:23:54 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8B0C0C4 for ; Tue, 17 Oct 2023 14:23:40 -0700 (PDT) Message-ID: <20231017211722.573068907@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1697577818; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=05Gqko9jJI9HsYd+9soRg3VHFk81iJGJf/+onp0NjzU=; b=rKfuiannQ8zq7ko98nW0jLx1mC9qvDzj+6Zsp3Q6DbnCHsKD/Hh6ZiLGqNuvti1ox+ybNz /mBRRmtvZgMsoprkC3v6qZ3AcjqKIGOB4xiF/s9zrIYge4DGkNjc8HiCpgoPbTlGR1zFsb 9e7b6RV3gp5nzSEQ+moHcKRMkJeQUALP7zMF6MQSj4IPJIhFQbiM8v6j/PBKNPRdo2vizu APJWB1V9yB6l8CByorAZmVmkCLZrMJE0vC661kvtjwv+M9QMbie86u2HzBVy+N4frbRO2p g102cSKMvxqjRScE/LSGzE3GRLBCzR1O0BWpCWyUbsgsgqnNghwUCd39LgVl4Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1697577818; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=05Gqko9jJI9HsYd+9soRg3VHFk81iJGJf/+onp0NjzU=; b=lbPebnvWgpfIFbZ6EPADg4NAHDvuCJsVFqEWpcYQH3Wx6O7IK4RBeQyJj7RcX2L7hvYTLv ccZRIvuyvWAnWiBQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov Subject: [patch V5 11/39] x86/microcode/intel: Cleanup code further References: <20231017200758.877560658@linutronix.de> MIME-Version: 1.0 Date: Tue, 17 Oct 2023 23:23:38 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 17 Oct 2023 14:24:27 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780039411159729411 X-GMAIL-MSGID: 1780039411159729411 From: Thomas Gleixner Sanitize the microcode scan loop, fixup printks and move the loading function for builtin microcode next to the place where it is used and mark it __init. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/intel.c | 76 +++++++++++++++--------------------- 1 file changed, 32 insertions(+), 44 deletions(-) --- diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c index 60862f6c0ded..bf6e083cc2a3 100644 --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -36,7 +36,7 @@ static const char ucode_path[] = "kernel/x86/microcode/GenuineIntel.bin"; static struct microcode_intel *intel_ucode_patch __read_mostly; /* last level cache size per core */ -static int llc_size_per_core __ro_after_init; +static unsigned int llc_size_per_core __ro_after_init; /* microcode format is extended from prescott processors */ struct extended_signature { @@ -296,29 +296,6 @@ static struct microcode_intel *scan_microcode(void *data, size_t size, return patch; } -static bool load_builtin_intel_microcode(struct cpio_data *cp) -{ - unsigned int eax = 1, ebx, ecx = 0, edx; - struct firmware fw; - char name[30]; - - if (IS_ENABLED(CONFIG_X86_32)) - return false; - - native_cpuid(&eax, &ebx, &ecx, &edx); - - sprintf(name, "intel-ucode/%02x-%02x-%02x", - x86_family(eax), x86_model(eax), x86_stepping(eax)); - - if (firmware_request_builtin(&fw, name)) { - cp->size = fw.size; - cp->data = (void *)fw.data; - return true; - } - - return false; -} - static int apply_microcode_early(struct ucode_cpu_info *uci) { struct microcode_intel *mc; @@ -362,6 +339,28 @@ static int apply_microcode_early(struct ucode_cpu_info *uci) return 0; } +static bool load_builtin_intel_microcode(struct cpio_data *cp) +{ + unsigned int eax = 1, ebx, ecx = 0, edx; + struct firmware fw; + char name[30]; + + if (IS_ENABLED(CONFIG_X86_32)) + return false; + + native_cpuid(&eax, &ebx, &ecx, &edx); + + sprintf(name, "intel-ucode/%02x-%02x-%02x", + x86_family(eax), x86_model(eax), x86_stepping(eax)); + + if (firmware_request_builtin(&fw, name)) { + cp->size = fw.size; + cp->data = (void *)fw.data; + return true; + } + return false; +} + int __init save_microcode_in_initrd_intel(void) { struct ucode_cpu_info uci; @@ -434,25 +433,16 @@ void load_ucode_intel_ap(void) apply_microcode_early(&uci); } -/* Accessor for microcode pointer */ -static struct microcode_intel *ucode_get_patch(void) -{ - return intel_ucode_patch; -} - void reload_ucode_intel(void) { - struct microcode_intel *p; struct ucode_cpu_info uci; intel_cpu_collect_info(&uci); - p = ucode_get_patch(); - if (!p) + uci.mc = intel_ucode_patch; + if (!uci.mc) return; - uci.mc = p; - apply_microcode_early(&uci); } @@ -490,8 +480,7 @@ static enum ucode_state apply_microcode_intel(int cpu) if (WARN_ON(raw_smp_processor_id() != cpu)) return UCODE_ERROR; - /* Look for a newer patch in our cache: */ - mc = ucode_get_patch(); + mc = intel_ucode_patch; if (!mc) { mc = uci->mc; if (!mc) @@ -682,18 +671,17 @@ static enum ucode_state request_microcode_fw(int cpu, struct device *device) } static struct microcode_ops microcode_intel_ops = { - .request_microcode_fw = request_microcode_fw, - .collect_cpu_info = collect_cpu_info, - .apply_microcode = apply_microcode_intel, + .request_microcode_fw = request_microcode_fw, + .collect_cpu_info = collect_cpu_info, + .apply_microcode = apply_microcode_intel, }; -static int __init calc_llc_size_per_core(struct cpuinfo_x86 *c) +static __init void calc_llc_size_per_core(struct cpuinfo_x86 *c) { u64 llc_size = c->x86_cache_size * 1024ULL; do_div(llc_size, c->x86_max_cores); - - return (int)llc_size; + llc_size_per_core = (unsigned int)llc_size; } struct microcode_ops * __init init_intel_microcode(void) @@ -706,7 +694,7 @@ struct microcode_ops * __init init_intel_microcode(void) return NULL; } - llc_size_per_core = calc_llc_size_per_core(c); + calc_llc_size_per_core(c); return µcode_intel_ops; } From patchwork Tue Oct 17 21:23:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 154546 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp4406321vqb; Tue, 17 Oct 2023 14:24:31 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFjyg05ESrk1Ys0keKRdz30yTSFLqYy03Bg5c431vIsZcJ8b20BF2t/rGVXXuuPYP/7dX9q X-Received: by 2002:a05:6a20:d80d:b0:163:ab09:193e with SMTP id iv13-20020a056a20d80d00b00163ab09193emr3368951pzb.1.1697577871583; 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[2620:137:e000::3:7]) by mx.google.com with ESMTPS id m8-20020a17090a4d8800b002774c17dd73si2485609pjh.11.2023.10.17.14.24.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 14:24:31 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=I5fGmp9z; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id BD80B8104512; Tue, 17 Oct 2023 14:24:30 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344357AbjJQVYU (ORCPT + 21 others); Tue, 17 Oct 2023 17:24:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55552 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235019AbjJQVYF (ORCPT ); Tue, 17 Oct 2023 17:24:05 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 70629182 for ; Tue, 17 Oct 2023 14:23:41 -0700 (PDT) Message-ID: <20231017211722.629085215@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1697577819; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=o4wPtZ0zuuS0mqtblAnsQ5W8blhZ2Q+8lWeI4fE1kYo=; b=I5fGmp9z3/TtZpdfpanwYaRUTXdSbc7u5IlUrUCPQ4R33joG6eNGSGEaObZEYYcfl0L9Qk eGffknl+DunzLcf0+6HHyqcB4Y3oEmwNMzGTXQUsDn1LvXesjZRFlTIqgM0aCZBP17BM/I oLaqj9E0xouX2rBhNVhsuK7e07Q3byU9TR3uz0QiPSq4X3G7ckmIKYDFbqG1FIEWRBB0oH a7HYtEWi3nzpQpuoFQNSoHuf0ywEu06Wh0Xy8LmBis+3AVaf4vKzxXtRFjirNToRfyq5t6 6yf+o6rhEwXLl/joZpRW9TopM7LEdUBX0Z+y32YVxbqY2dgpPtHZGRrfXBycIw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1697577819; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=o4wPtZ0zuuS0mqtblAnsQ5W8blhZ2Q+8lWeI4fE1kYo=; b=/0LbkxfUvKx9e2t9sP/rqclPBdHX3ZvABakJwB7ZzBwhgDEKDGjQU6hc/h2ej4Fx1d8aXM /GXZb7dXwHJoyjAA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov Subject: [patch V5 12/39] x86/microcode/intel: Simplify early loading References: <20231017200758.877560658@linutronix.de> MIME-Version: 1.0 Date: Tue, 17 Oct 2023 23:23:39 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 17 Oct 2023 14:24:30 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780039414191187296 X-GMAIL-MSGID: 1780039414191187296 From: Thomas Gleixner The early loading code is overly complicated: - It scans the builtin/initrd for microcode not only on the BSP, but also on all APs during early boot and then later in the boot process it scans again to duplicate and saves the microcode before initrd goes away. That's a pointless exercise because this can be simply done before bringing up the APs when the memory allocator is up and running. - Saving the microcode from within the scan loop is completely non-obvious and a left over of the microcode cache. This can be done at the call site now which makes it obvious. Rework the code so that only the BSP scans the builtin/initrd microcode during early boot and then rescans to save it away in an early initcall for later use. Signed-off-by: Thomas Gleixner --- V5: Rescan in save_microcode() to handle relocated initrds correctly --- arch/x86/kernel/cpu/microcode/core.c | 6 - arch/x86/kernel/cpu/microcode/intel.c | 149 ++++++++++++------------------- arch/x86/kernel/cpu/microcode/internal.h | 3 3 files changed, 63 insertions(+), 95 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -42,7 +42,7 @@ #define DRIVER_VERSION "2.2" static struct microcode_ops *microcode_ops; -static bool dis_ucode_ldr = true; +bool dis_ucode_ldr = true; bool initrd_gone; @@ -186,10 +186,6 @@ static int __init save_microcode_in_init int ret = -EINVAL; switch (c->x86_vendor) { - case X86_VENDOR_INTEL: - if (c->x86 >= 6) - ret = save_microcode_in_initrd_intel(); - break; case X86_VENDOR_AMD: if (c->x86 >= 0x10) ret = save_microcode_in_initrd_amd(cpuid_eax(1)); --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -33,7 +33,7 @@ static const char ucode_path[] = "kernel/x86/microcode/GenuineIntel.bin"; /* Current microcode patch used in early patching on the APs. */ -static struct microcode_intel *intel_ucode_patch __read_mostly; +static struct microcode_intel *ucode_patch_va __read_mostly; /* last level cache size per core */ static unsigned int llc_size_per_core __ro_after_init; @@ -240,24 +240,29 @@ int intel_microcode_sanity_check(void *m } EXPORT_SYMBOL_GPL(intel_microcode_sanity_check); -static void save_microcode_patch(void *data, unsigned int size) +static void update_ucode_pointer(struct microcode_intel *mc) { - struct microcode_header_intel *p; + kfree(ucode_patch_va); - kfree(intel_ucode_patch); - intel_ucode_patch = NULL; + /* + * Save the virtual address for early loading and for eventual free + * on late loading. + */ + ucode_patch_va = mc; +} - p = kmemdup(data, size, GFP_KERNEL); - if (!p) - return; +static void save_microcode_patch(struct microcode_intel *patch) +{ + struct microcode_intel *mc; - /* Save for early loading */ - intel_ucode_patch = (struct microcode_intel *)p; + mc = kmemdup(patch, get_totalsize(&patch->hdr), GFP_KERNEL); + if (mc) + update_ucode_pointer(mc); } -/* Scan CPIO for microcode matching the boot CPU's family, model, stepping */ -static struct microcode_intel *scan_microcode(void *data, size_t size, - struct ucode_cpu_info *uci, bool save) +/* Scan blob for microcode matching the boot CPUs family, model, stepping */ +static __init struct microcode_intel *scan_microcode(void *data, size_t size, + struct ucode_cpu_info *uci) { struct microcode_header_intel *mc_header; struct microcode_intel *patch = NULL; @@ -275,35 +280,25 @@ static struct microcode_intel *scan_micr if (!intel_find_matching_signature(data, uci->cpu_sig.sig, uci->cpu_sig.pf)) continue; - /* BSP scan: Check whether there is newer microcode */ - if (!save && cur_rev >= mc_header->rev) - continue; - - /* Save scan: Check whether there is newer or matching microcode */ - if (save && cur_rev != mc_header->rev) + /* Check whether there is newer microcode */ + if (cur_rev >= mc_header->rev) continue; patch = data; cur_rev = mc_header->rev; } - if (size) - return NULL; - - if (save && patch) - save_microcode_patch(patch, mc_size); - - return patch; + return size ? NULL : patch; } -static int apply_microcode_early(struct ucode_cpu_info *uci) +static enum ucode_state apply_microcode_early(struct ucode_cpu_info *uci) { struct microcode_intel *mc; u32 rev, old_rev, date; mc = uci->mc; if (!mc) - return 0; + return UCODE_NFOUND; /* * Save us the MSR write below - which is a particular expensive @@ -329,17 +324,17 @@ static int apply_microcode_early(struct rev = intel_get_microcode_revision(); if (rev != mc->hdr.rev) - return -1; + return UCODE_ERROR; uci->cpu_sig.rev = rev; date = mc->hdr.date; pr_info_once("updated early: 0x%x -> 0x%x, date = %04x-%02x-%02x\n", old_rev, rev, date & 0xffff, date >> 24, (date >> 16) & 0xff); - return 0; + return UCODE_UPDATED; } -static bool load_builtin_intel_microcode(struct cpio_data *cp) +static __init bool load_builtin_intel_microcode(struct cpio_data *cp) { unsigned int eax = 1, ebx, ecx = 0, edx; struct firmware fw; @@ -361,89 +356,68 @@ static bool load_builtin_intel_microcode return false; } -int __init save_microcode_in_initrd_intel(void) +static __init struct microcode_intel *get_microcode_blob(struct ucode_cpu_info *uci) { - struct ucode_cpu_info uci; struct cpio_data cp; - /* - * initrd is going away, clear patch ptr. We will scan the microcode one - * last time before jettisoning and save a patch, if found. Then we will - * update that pointer too, with a stable patch address to use when - * resuming the cores. - */ - intel_ucode_patch = NULL; - if (!load_builtin_intel_microcode(&cp)) cp = find_microcode_in_initrd(ucode_path); if (!(cp.data && cp.size)) - return 0; + return NULL; - intel_cpu_collect_info(&uci); + intel_cpu_collect_info(uci); - scan_microcode(cp.data, cp.size, &uci, true); - return 0; + return scan_microcode(cp.data, cp.size, uci); } /* - * @res_patch, output: a pointer to the patch we found. + * Invoked from an early init call to save the microcode blob which was + * selected during early boot when mm was not usable. The microcode must be + * saved because initrd is going away. It's an early init call so the APs + * just can use the pointer and do not have to scan initrd/builtin firmware + * again. */ -static struct microcode_intel *__load_ucode_intel(struct ucode_cpu_info *uci) +static int __init save_builtin_microcode(void) { - struct cpio_data cp; - - /* try built-in microcode first */ - if (!load_builtin_intel_microcode(&cp)) - cp = find_microcode_in_initrd(ucode_path); - - if (!(cp.data && cp.size)) - return NULL; + struct ucode_cpu_info uci; - intel_cpu_collect_info(uci); + if (dis_ucode_ldr || boot_cpu_data.x86_vendor != X86_VENDOR_INTEL) + return 0; - return scan_microcode(cp.data, cp.size, uci, false); + uci.mc = get_microcode_blob(&uci); + if (uci.mc) + save_microcode_patch(uci.mc); + return 0; } +early_initcall(save_builtin_microcode); +/* Load microcode on BSP from initrd or builtin blobs */ void __init load_ucode_intel_bsp(void) { - struct microcode_intel *patch; struct ucode_cpu_info uci; - patch = __load_ucode_intel(&uci); - if (!patch) - return; - - uci.mc = patch; - - apply_microcode_early(&uci); + uci.mc = get_microcode_blob(&uci); + if (uci.mc) + apply_microcode_early(&uci); } void load_ucode_intel_ap(void) { struct ucode_cpu_info uci; - if (!intel_ucode_patch) { - intel_ucode_patch = __load_ucode_intel(&uci); - if (!intel_ucode_patch) - return; - } - - uci.mc = intel_ucode_patch; - apply_microcode_early(&uci); + uci.mc = ucode_patch_va; + if (uci.mc) + apply_microcode_early(&uci); } +/* Reload microcode on resume */ void reload_ucode_intel(void) { - struct ucode_cpu_info uci; - - intel_cpu_collect_info(&uci); - - uci.mc = intel_ucode_patch; - if (!uci.mc) - return; + struct ucode_cpu_info uci = { .mc = ucode_patch_va, }; - apply_microcode_early(&uci); + if (uci.mc) + apply_microcode_early(&uci); } static int collect_cpu_info(int cpu_num, struct cpu_signature *csig) @@ -480,7 +454,7 @@ static enum ucode_state apply_microcode_ if (WARN_ON(raw_smp_processor_id() != cpu)) return UCODE_ERROR; - mc = intel_ucode_patch; + mc = ucode_patch_va; if (!mc) { mc = uci->mc; if (!mc) @@ -540,8 +514,8 @@ static enum ucode_state apply_microcode_ static enum ucode_state parse_microcode_blobs(int cpu, struct iov_iter *iter) { struct ucode_cpu_info *uci = ucode_cpu_info + cpu; - unsigned int curr_mc_size = 0, new_mc_size = 0; int cur_rev = uci->cpu_sig.rev; + unsigned int curr_mc_size = 0; u8 *new_mc = NULL, *mc = NULL; while (iov_iter_count(iter)) { @@ -591,7 +565,6 @@ static enum ucode_state parse_microcode_ vfree(new_mc); cur_rev = mc_header.rev; new_mc = mc; - new_mc_size = mc_size; mc = NULL; } @@ -605,11 +578,11 @@ static enum ucode_state parse_microcode_ if (!new_mc) return UCODE_NFOUND; - vfree(uci->mc); - uci->mc = (struct microcode_intel *)new_mc; - /* Save for CPU hotplug */ - save_microcode_patch(new_mc, new_mc_size); + save_microcode_patch((struct microcode_intel *)new_mc); + uci->mc = ucode_patch_va; + + vfree(new_mc); pr_debug("CPU%d found a matching microcode update with version 0x%x (current=0x%x)\n", cpu, cur_rev, uci->cpu_sig.rev); --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -84,6 +84,7 @@ static inline unsigned int x86_cpuid_fam return x86_family(eax); } +extern bool dis_ucode_ldr; extern bool initrd_gone; #ifdef CONFIG_CPU_SUP_AMD @@ -107,13 +108,11 @@ static inline void exit_amd_microcode(vo #ifdef CONFIG_CPU_SUP_INTEL void load_ucode_intel_bsp(void); void load_ucode_intel_ap(void); -int save_microcode_in_initrd_intel(void); void reload_ucode_intel(void); struct microcode_ops *init_intel_microcode(void); #else /* CONFIG_CPU_SUP_INTEL */ static inline void load_ucode_intel_bsp(void) { } static inline void load_ucode_intel_ap(void) { } -static inline int save_microcode_in_initrd_intel(void) { return -EINVAL; } static inline void reload_ucode_intel(void) { } static inline struct microcode_ops *init_intel_microcode(void) { return NULL; } #endif /* !CONFIG_CPU_SUP_INTEL */ From patchwork Tue Oct 17 21:23:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 154554 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp4406664vqb; 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[23.128.96.33]) by mx.google.com with ESMTPS id bd33-20020a056a0027a100b006bdb7c5f75dsi2471043pfb.357.2023.10.17.14.25.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 14:25:20 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) client-ip=23.128.96.33; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=GJgy2+dR; dkim=neutral (no key) header.i=@linutronix.de header.b=lz8GikNW; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id 27787810EC04; Tue, 17 Oct 2023 14:25:15 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344369AbjJQVYW (ORCPT + 21 others); Tue, 17 Oct 2023 17:24:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33434 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235051AbjJQVYH (ORCPT ); Tue, 17 Oct 2023 17:24:07 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1189F19D for ; Tue, 17 Oct 2023 14:23:44 -0700 (PDT) Message-ID: <20231017211722.684478751@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1697577821; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=IngjRZMYBg+VzV6jYzAlKokUKzc8AuAEYq+N8B/D1cs=; b=GJgy2+dRIwEnNDuSq07extpWPmQgYDylQ5koP9G88almTeNbawYL86g1gIvjPKA2ohzeqH Odet0jCHUCS35zRtdgpNEb1ifRQX2qFS/DihTzjd07lZxeTiEZwDt0wx0aPRfS8NnHEebT qW5s63VCN84TdRFneGVtOnY1AJx5ACcwstxiv/T9xb9BcnzzZwerAxcY66dBSV4iXb1r6K MK/37DxuiD5QV4L/dEwrZrT6nWbJvvm6hDyjooQ/ccLWN3EiQr/W1DmS8gEGqtYqLZqabv 8zyoR+tSCQu0ly/2G2NrPpeIakbvdW5SzBDkBnyLgQa/UpOcC1Z/Czf+k9lYrw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1697577821; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=IngjRZMYBg+VzV6jYzAlKokUKzc8AuAEYq+N8B/D1cs=; b=lz8GikNW2MDaI+OdI2bTncK6u/xvUN3QLoosaN39CILvqzyikcjml4AHGyonlOnWFpg0ki VSEeZnKI1dQsG/BA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov Subject: [patch V5 13/39] x86/microcode/intel: Save the microcode only after a successful late-load References: <20231017200758.877560658@linutronix.de> MIME-Version: 1.0 Date: Tue, 17 Oct 2023 23:23:41 +0200 (CEST) X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Tue, 17 Oct 2023 14:25:15 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780039465375165879 X-GMAIL-MSGID: 1780039465375165879 From: Thomas Gleixner There are situations where the late microcode is loaded into memory but is not applied: 1) The rendezvous fails 2) The microcode is rejected by the CPUs If any of this happens then the pointer which was updated at firmware load time is stale and subsequent CPU hotplug operations either fail to update or create inconsistent microcode state. Save the loaded microcode in a separate pointer before the late load is attempted and when successful, update the hotplug pointer accordingly via a new microcode_ops callback. Remove the pointless fallback in the loader to a microcode pointer which is never populated. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/core.c | 4 ++++ arch/x86/kernel/cpu/microcode/intel.c | 30 +++++++++++++++--------------- arch/x86/kernel/cpu/microcode/internal.h | 1 + 3 files changed, 20 insertions(+), 15 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -397,6 +397,10 @@ static int microcode_reload_late(void) store_cpu_caps(&prev_info); ret = stop_machine_cpuslocked(__reload_late, NULL, cpu_online_mask); + + if (microcode_ops->finalize_late_load) + microcode_ops->finalize_late_load(ret); + if (!ret) { pr_info("Reload succeeded, microcode revision: 0x%x -> 0x%x\n", old, boot_cpu_data.microcode); --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -34,6 +34,7 @@ static const char ucode_path[] = "kernel /* Current microcode patch used in early patching on the APs. */ static struct microcode_intel *ucode_patch_va __read_mostly; +static struct microcode_intel *ucode_patch_late __read_mostly; /* last level cache size per core */ static unsigned int llc_size_per_core __ro_after_init; @@ -454,12 +455,9 @@ static enum ucode_state apply_microcode_ if (WARN_ON(raw_smp_processor_id() != cpu)) return UCODE_ERROR; - mc = ucode_patch_va; - if (!mc) { - mc = uci->mc; - if (!mc) - return UCODE_NFOUND; - } + mc = ucode_patch_late; + if (!mc) + return UCODE_NFOUND; /* * Save us the MSR write below - which is a particular expensive @@ -578,15 +576,7 @@ static enum ucode_state parse_microcode_ if (!new_mc) return UCODE_NFOUND; - /* Save for CPU hotplug */ - save_microcode_patch((struct microcode_intel *)new_mc); - uci->mc = ucode_patch_va; - - vfree(new_mc); - - pr_debug("CPU%d found a matching microcode update with version 0x%x (current=0x%x)\n", - cpu, cur_rev, uci->cpu_sig.rev); - + ucode_patch_late = (struct microcode_intel *)new_mc; return UCODE_NEW; } @@ -643,10 +633,20 @@ static enum ucode_state request_microcod return ret; } +static void finalize_late_load(int result) +{ + if (!result) + save_microcode_patch(ucode_patch_late); + + vfree(ucode_patch_late); + ucode_patch_late = NULL; +} + static struct microcode_ops microcode_intel_ops = { .request_microcode_fw = request_microcode_fw, .collect_cpu_info = collect_cpu_info, .apply_microcode = apply_microcode_intel, + .finalize_late_load = finalize_late_load, }; static __init void calc_llc_size_per_core(struct cpuinfo_x86 *c) --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -31,6 +31,7 @@ struct microcode_ops { */ enum ucode_state (*apply_microcode)(int cpu); int (*collect_cpu_info)(int cpu, struct cpu_signature *csig); + void (*finalize_late_load)(int result); }; extern struct ucode_cpu_info ucode_cpu_info[]; From patchwork Tue Oct 17 21:23:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 154548 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp4406378vqb; Tue, 17 Oct 2023 14:24:40 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHfVWCidwM1uKZmZooINMSCXKvkcQhOZk3pEvjUSr8NPURkE2CHN7OTrjwSOGbns/n0+3Qh X-Received: by 2002:a05:6a20:d80d:b0:15d:f804:6907 with SMTP id iv13-20020a056a20d80d00b0015df8046907mr3414584pzb.0.1697577879740; Tue, 17 Oct 2023 14:24:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697577879; cv=none; d=google.com; s=arc-20160816; b=Nzwyxb51oMqtcaEAylio9Q6fV6VZf4KyESkcyTqlOPITAJ6CpMFpakD5iiD8R7eQAB fo0n8EPlO9l0BoLLBxY4JLkxQyXEwhHQpsxzmq38n1Rs8ftfBqYlejuKZcMfAJhGB7K4 Sm5Z34gGVqmd+AtCjfqME29E+4l0NJCN9U2JgWBUp3S9QuUJ86Br509UBZJRVBSPPMiF H9mMDdl5D7vzqOubjhqAGIjmmzZdJHA0GwFFPsQP/wpqrAMrUwhpiazPWNrt8SvWWNaZ eqEffoYGK8Fas64CaoFEsTLDtQAgFL45bGkMD20MLx752bvWaEmo1jFLBFP9RQPT6Cv3 s21Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=VA3GjOwSQakWu1mfAzsmut9V6c1bKPim6FgZiDMaO9A=; fh=8iy+GLBXZdpcs/hIddJ7mbUapYjefwP9Gb111pAzFms=; b=k9ArDGrG6+a+RvQcX5LqWNiVeiYBo73zO8u6DKA0XHCx/tStOK/7bF09+f2E6LQ252 Fr2UjhHx4ZUYyCr8lNZyRLDJloW06srChcGgzDXOg9OiFbCXlq42J/gZeQRcUXAZjQyE A6E6+cjn1r9zQXJty4CWgFGR6UzJsSAxk2me7Yd1OnIHrVUdbxJTFkFboRtTjty/GXPA Feq6/ZEbu2dxsbIunqGuMt1H0+54oUT2b7sSE54ud1OcJL/h4rUsTKfQY3qN3f98UVYX Jt07FFYFY1w498fv9T17gmdDD24x1ewTLkITgb95slOR3BAMZACsKBKZB5iaiwmkkeH+ 13Nw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=wL6Uez1d; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id a7-20020a170902b58700b001bdc664cd69si2493096pls.153.2023.10.17.14.24.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 14:24:39 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=wL6Uez1d; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 783DF8104524; Tue, 17 Oct 2023 14:24:38 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344000AbjJQVYb (ORCPT + 21 others); Tue, 17 Oct 2023 17:24:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33472 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344105AbjJQVYL (ORCPT ); Tue, 17 Oct 2023 17:24:11 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A82361B8 for ; Tue, 17 Oct 2023 14:23:45 -0700 (PDT) Message-ID: <20231017211722.739983189@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1697577823; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=VA3GjOwSQakWu1mfAzsmut9V6c1bKPim6FgZiDMaO9A=; b=wL6Uez1dTKOYzx6VLXpSfhhaXgs1ie2maErFqXjfHjrh391LQuEhtrlQlVZTaLh9WwHRCM 93cV0+UWr0GZkBRg0Fu4lOg1r7861vH6ffW8OHutpCrNNSQoZ4v62qF+On367/6XQuwEi6 Rxoc1eHMMuGSKCTPKGbbKPYdwGdMOTDO3S+aEQ/9Aw6swylYcpdjTR6m5kJOmQCIisi8wj ehK4z1YKfRMQiZChLNFi2OKOZIOALa6SaMs9BTjYHTEPaFFPIztv+6ZWtAlZHIYo7unZFd Qj6ihRJjSxeJ8YF5bmZv2U/EkRFxo+Gbh6d6cizug3NsiDdW7V6OpicHTqRo/w== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1697577823; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=VA3GjOwSQakWu1mfAzsmut9V6c1bKPim6FgZiDMaO9A=; b=Zggs9U2uUhKbekNtn746/6GRIfgG6oAB26+VB9l644K9W+2HVIQ63SXIziK/1ehKeb9RWV lCG+IerfpT2R0xDw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov Subject: [patch V5 14/39] x86/microcode/intel: Switch to kvmalloc() References: <20231017200758.877560658@linutronix.de> MIME-Version: 1.0 Date: Tue, 17 Oct 2023 23:23:42 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 17 Oct 2023 14:24:38 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780039422641504145 X-GMAIL-MSGID: 1780039422641504145 From: Thomas Gleixner Microcode blobs are getting larger and might soon reach the kmalloc() limit. Switch over kvmalloc(). Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/intel.c | 48 +++++++++++++++++----------------- 1 file changed, 25 insertions(+), 23 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -14,7 +14,6 @@ #include #include #include -#include #include #include #include @@ -243,7 +242,7 @@ EXPORT_SYMBOL_GPL(intel_microcode_sanity static void update_ucode_pointer(struct microcode_intel *mc) { - kfree(ucode_patch_va); + kvfree(ucode_patch_va); /* * Save the virtual address for early loading and for eventual free @@ -254,11 +253,14 @@ static void update_ucode_pointer(struct static void save_microcode_patch(struct microcode_intel *patch) { + unsigned int size = get_totalsize(&patch->hdr); struct microcode_intel *mc; - mc = kmemdup(patch, get_totalsize(&patch->hdr), GFP_KERNEL); + mc = kvmemdup(patch, size, GFP_KERNEL); if (mc) update_ucode_pointer(mc); + else + pr_err("Unable to allocate microcode memory size: %u\n", size); } /* Scan blob for microcode matching the boot CPUs family, model, stepping */ @@ -523,36 +525,34 @@ static enum ucode_state parse_microcode_ if (!copy_from_iter_full(&mc_header, sizeof(mc_header), iter)) { pr_err("error! Truncated or inaccessible header in microcode data file\n"); - break; + goto fail; } mc_size = get_totalsize(&mc_header); if (mc_size < sizeof(mc_header)) { pr_err("error! Bad data in microcode data file (totalsize too small)\n"); - break; + goto fail; } - data_size = mc_size - sizeof(mc_header); if (data_size > iov_iter_count(iter)) { pr_err("error! Bad data in microcode data file (truncated file?)\n"); - break; + goto fail; } /* For performance reasons, reuse mc area when possible */ if (!mc || mc_size > curr_mc_size) { - vfree(mc); - mc = vmalloc(mc_size); + kvfree(mc); + mc = kvmalloc(mc_size, GFP_KERNEL); if (!mc) - break; + goto fail; curr_mc_size = mc_size; } memcpy(mc, &mc_header, sizeof(mc_header)); data = mc + sizeof(mc_header); if (!copy_from_iter_full(data, data_size, iter) || - intel_microcode_sanity_check(mc, true, MC_HEADER_TYPE_MICROCODE) < 0) { - break; - } + intel_microcode_sanity_check(mc, true, MC_HEADER_TYPE_MICROCODE) < 0) + goto fail; if (cur_rev >= mc_header.rev) continue; @@ -560,24 +560,26 @@ static enum ucode_state parse_microcode_ if (!intel_find_matching_signature(mc, uci->cpu_sig.sig, uci->cpu_sig.pf)) continue; - vfree(new_mc); + kvfree(new_mc); cur_rev = mc_header.rev; new_mc = mc; mc = NULL; } - vfree(mc); - - if (iov_iter_count(iter)) { - vfree(new_mc); - return UCODE_ERROR; - } + if (iov_iter_count(iter)) + goto fail; + kvfree(mc); if (!new_mc) return UCODE_NFOUND; ucode_patch_late = (struct microcode_intel *)new_mc; return UCODE_NEW; + +fail: + kvfree(mc); + kvfree(new_mc); + return UCODE_ERROR; } static bool is_blacklisted(unsigned int cpu) @@ -636,9 +638,9 @@ static enum ucode_state request_microcod static void finalize_late_load(int result) { if (!result) - save_microcode_patch(ucode_patch_late); - - vfree(ucode_patch_late); + update_ucode_pointer(ucode_patch_late); + else + kvfree(ucode_patch_late); ucode_patch_late = NULL; } From patchwork Tue Oct 17 21:23:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 154549 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp4406408vqb; Tue, 17 Oct 2023 14:24:47 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHH+J46CTXDmx3Ogc7wpDOSOiAgwfAWBBdL4dFo/IU22cpJ395EZzR81KQVmzR2gVG1bY8d X-Received: by 2002:a05:6a20:8f28:b0:172:55c1:f1d4 with SMTP id b40-20020a056a208f2800b0017255c1f1d4mr3866737pzk.4.1697577887267; Tue, 17 Oct 2023 14:24:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697577887; cv=none; d=google.com; s=arc-20160816; b=w4V7wTt8kycyBZCo60kja3vSyhkszoMi03DoaQ9CmOiJijS7cSQVrX8pGDmOOmWlVy iWst/frGnjiavdVHpauhyrN+Yps8W6+kdjlgFWdkrr6w7YGqKh04aeWu+bOvnIyTW/2G ioORmE5LcXuaaz4Ugnwba5lg08zoVdRWgKKxP4yRQ1XckgeDrkYAT4BvOUpzr7kchPn7 XjbmpOzMEG9m7FIVeDKMXZfzIF0AWAt4fZDsgnRDWSl3JOb4B3VvXV1s48hlR7CI9Dpq p2+HJVTAha++gp3B3rP6dykZKVI4jEqLMgAITtle00TZB8Vcpt08TnPKBof7aNbxFFhX ObOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=FE0DpDNtp2Ico6oBJ9Mij9/yYPkvhH9gw/gnV/1rNSg=; fh=8iy+GLBXZdpcs/hIddJ7mbUapYjefwP9Gb111pAzFms=; b=ArkhMLh7cyKiG8W0a92SDddSQy/0YXXc4BxDjo/jFLIsBdHLUyTzmHjSfvubMbol38 NzXu1C6ICgvmzFUAlVAfaZoMYwql0Mj9Qiz1rqi0rZulg1r07YHr4NC7FQS+PzrNq8+f JHP2WhgbM1rx42kx0yP/fxJ7ossqBO5EyBh/wkzwW8vcZCe3PL2VgTzVJXLrL9raFlHf dnRabRrLx5BjBeZPAxIqQBpXtwMmhos+eQMuXCEDb3w/xryWyFzG5EDpQ3ZFTuq4sG7D C3X1wcoZSgIQieLgEkTUZA+6yKjRsGH9jMVcvAfh59FENSAIG0a1x+rfjY8Kz0NjIQCG ijPA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="UuNXvB/O"; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=DoaEDhVS; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id m68-20020a633f47000000b005ac4854b202si611809pga.321.2023.10.17.14.24.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 14:24:47 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="UuNXvB/O"; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=DoaEDhVS; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 84C328106595; Tue, 17 Oct 2023 14:24:46 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344332AbjJQVYf (ORCPT + 21 others); Tue, 17 Oct 2023 17:24:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44906 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344286AbjJQVYP (ORCPT ); Tue, 17 Oct 2023 17:24:15 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C2FC2D4F for ; Tue, 17 Oct 2023 14:23:46 -0700 (PDT) Message-ID: <20231017211722.795508212@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1697577824; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=FE0DpDNtp2Ico6oBJ9Mij9/yYPkvhH9gw/gnV/1rNSg=; b=UuNXvB/OaGXH1Srp8kcVCcxiwIzEPMkxKx6knVJ3WURLCoZrLuhU5BRAbX8m5tDl8GPj4c B33a5hfF4r1n5QhWvqbOXtDF8RLvDv24T2IEqQIgaMEZv1svsJ2Wd9rTyXht5/vORun9eK 5y12TBLBZx66Ks65H8Z6YeWNv+r5AyHWdILIQ1U7Ph8IarsYPdPtkSjo4TLKdQeXhoELpH 1sMRCcfatNK+ngNp+lqI8rIVZabxOhLzCZdpAeavbSQ7GUV/e4gEDB14ZPLespMax7DFCw Nvrq4ssFM3VIPR6mdwMP2s4bJdjTz+3v6ZVMNJ87S6lTBYqEABC8nkKUoePZ2g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1697577824; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=FE0DpDNtp2Ico6oBJ9Mij9/yYPkvhH9gw/gnV/1rNSg=; b=DoaEDhVSp6lJyl9VlqMUt+dRNgi/qOdbv7Vvm14bgJE+J35SxuttVnRUzTcaW3WSFiMCp3 fnVfhffxdC0TwPDw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov Subject: [patch V5 15/39] x86/microcode/intel: Unify microcode apply() functions References: <20231017200758.877560658@linutronix.de> MIME-Version: 1.0 Date: Tue, 17 Oct 2023 23:23:44 +0200 (CEST) X-Spam-Status: No, score=-0.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,PDS_OTHER_BAD_TLD, RCVD_IN_DNSWL_BLOCKED,SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 17 Oct 2023 14:24:46 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780039430774148202 X-GMAIL-MSGID: 1780039430774148202 From: Thomas Gleixner Deduplicate the early and late apply() functions. [ bp: Rename the function which does the actual application to __apply_microcode() to differentiate it from microcode_ops.apply_microcode(). ] Signed-off-by: Thomas Gleixner Signed-off-by: Borislav Petkov (AMD) Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/intel.c | 106 +++++++++++----------------------- 1 file changed, 37 insertions(+), 69 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -294,12 +294,12 @@ static __init struct microcode_intel *sc return size ? NULL : patch; } -static enum ucode_state apply_microcode_early(struct ucode_cpu_info *uci) +static enum ucode_state __apply_microcode(struct ucode_cpu_info *uci, + struct microcode_intel *mc, + u32 *cur_rev) { - struct microcode_intel *mc; - u32 rev, old_rev, date; + u32 rev; - mc = uci->mc; if (!mc) return UCODE_NFOUND; @@ -308,14 +308,12 @@ static enum ucode_state apply_microcode_ * operation - when the other hyperthread has updated the microcode * already. */ - rev = intel_get_microcode_revision(); - if (rev >= mc->hdr.rev) { - uci->cpu_sig.rev = rev; + *cur_rev = intel_get_microcode_revision(); + if (*cur_rev >= mc->hdr.rev) { + uci->cpu_sig.rev = *cur_rev; return UCODE_OK; } - old_rev = rev; - /* * Writeback and invalidate caches before updating microcode to avoid * internal issues depending on what the microcode is updating. @@ -330,13 +328,24 @@ static enum ucode_state apply_microcode_ return UCODE_ERROR; uci->cpu_sig.rev = rev; - - date = mc->hdr.date; - pr_info_once("updated early: 0x%x -> 0x%x, date = %04x-%02x-%02x\n", - old_rev, rev, date & 0xffff, date >> 24, (date >> 16) & 0xff); return UCODE_UPDATED; } +static enum ucode_state apply_microcode_early(struct ucode_cpu_info *uci) +{ + struct microcode_intel *mc = uci->mc; + enum ucode_state ret; + u32 cur_rev, date; + + ret = __apply_microcode(uci, mc, &cur_rev); + if (ret == UCODE_UPDATED) { + date = mc->hdr.date; + pr_info_once("updated early: 0x%x -> 0x%x, date = %04x-%02x-%02x\n", + cur_rev, mc->hdr.rev, date & 0xffff, date >> 24, (date >> 16) & 0xff); + } + return ret; +} + static __init bool load_builtin_intel_microcode(struct cpio_data *cp) { unsigned int eax = 1, ebx, ecx = 0, edx; @@ -443,70 +452,29 @@ static int collect_cpu_info(int cpu_num, return 0; } -static enum ucode_state apply_microcode_intel(int cpu) +static enum ucode_state apply_microcode_late(int cpu) { struct ucode_cpu_info *uci = ucode_cpu_info + cpu; - struct cpuinfo_x86 *c = &cpu_data(cpu); - bool bsp = c->cpu_index == boot_cpu_data.cpu_index; - struct microcode_intel *mc; + struct microcode_intel *mc = ucode_patch_late; enum ucode_state ret; - static int prev_rev; - u32 rev; - - /* We should bind the task to the CPU */ - if (WARN_ON(raw_smp_processor_id() != cpu)) - return UCODE_ERROR; - - mc = ucode_patch_late; - if (!mc) - return UCODE_NFOUND; - - /* - * Save us the MSR write below - which is a particular expensive - * operation - when the other hyperthread has updated the microcode - * already. - */ - rev = intel_get_microcode_revision(); - if (rev >= mc->hdr.rev) { - ret = UCODE_OK; - goto out; - } + u32 cur_rev; - /* - * Writeback and invalidate caches before updating microcode to avoid - * internal issues depending on what the microcode is updating. - */ - native_wbinvd(); - - /* write microcode via MSR 0x79 */ - wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); - - rev = intel_get_microcode_revision(); - - if (rev != mc->hdr.rev) { - pr_err("CPU%d update to revision 0x%x failed\n", - cpu, mc->hdr.rev); + if (WARN_ON_ONCE(smp_processor_id() != cpu)) return UCODE_ERROR; - } - if (bsp && rev != prev_rev) { - pr_info("updated to revision 0x%x, date = %04x-%02x-%02x\n", - rev, - mc->hdr.date & 0xffff, - mc->hdr.date >> 24, + ret = __apply_microcode(uci, mc, &cur_rev); + if (ret != UCODE_UPDATED && ret != UCODE_OK) + return ret; + + if (!cpu && uci->cpu_sig.rev != cur_rev) { + pr_info("Updated to revision 0x%x, date = %04x-%02x-%02x\n", + uci->cpu_sig.rev, mc->hdr.date & 0xffff, mc->hdr.date >> 24, (mc->hdr.date >> 16) & 0xff); - prev_rev = rev; } - ret = UCODE_UPDATED; - -out: - uci->cpu_sig.rev = rev; - c->microcode = rev; - - /* Update boot_cpu_data's revision too, if we're on the BSP: */ - if (bsp) - boot_cpu_data.microcode = rev; + cpu_data(cpu).microcode = uci->cpu_sig.rev; + if (!cpu) + boot_cpu_data.microcode = uci->cpu_sig.rev; return ret; } @@ -647,7 +615,7 @@ static void finalize_late_load(int resul static struct microcode_ops microcode_intel_ops = { .request_microcode_fw = request_microcode_fw, .collect_cpu_info = collect_cpu_info, - .apply_microcode = apply_microcode_intel, + .apply_microcode = apply_microcode_late, .finalize_late_load = finalize_late_load, }; From patchwork Tue Oct 17 21:23:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 154550 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp4406435vqb; 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[23.128.96.37]) by mx.google.com with ESMTPS id n14-20020a170903110e00b001bf01fee6bcsi2809521plh.610.2023.10.17.14.24.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 14:24:50 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=gWD0lue8; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=NSMFh03M; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id C86A48106596; Tue, 17 Oct 2023 14:24:49 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344346AbjJQVYj (ORCPT + 21 others); Tue, 17 Oct 2023 17:24:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33608 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344339AbjJQVYP (ORCPT ); Tue, 17 Oct 2023 17:24:15 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AED70D61 for ; Tue, 17 Oct 2023 14:23:47 -0700 (PDT) Message-ID: <20231017211722.851573238@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1697577825; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=in5lcKaTOq2HRl8ZSeTrcUYrMkDHoeYPGl+VTJIKes4=; b=gWD0lue8AJsGoo3Y/f9fKOe0tceQEpea/1nTuArLacGMnesihAdO3oOm6hbY2k7UCXSo5O tV86JDLIc9/qUDMMPbyI+3Qr73vazqBoQr6tnD08uX4GUStQkhdNsBIXYwUiCCu10ANNqr w+H658VpJGBvIvCHC4aL2UdPmTkcCAOtFQO++A09MZVXhWvDWM2enfP+7HsNEIhZPwzDOF 5F11jKkItXBrnBKxbb6tmL1uoidWITzgFzFnpMI7y1LxqHrGvpPkW6EQL5xKzJm1nvd1Rh egDmjXI4ZtuSFk5cupFw3+nC7C2aE6eU30xnILmvchyFqsOsx+tRqrTJP8uoJw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1697577825; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=in5lcKaTOq2HRl8ZSeTrcUYrMkDHoeYPGl+VTJIKes4=; b=NSMFh03MLvfkQPxlPk3XwByCUecGsitnqZV1otjx6vAWvGjq2wtB12X9b+Tr75RY2IeAYU gJUP07pTGbBiY6Bw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov Subject: [patch V5 16/39] x86/microcode/intel: Rework intel_cpu_collect_info() References: <20231017200758.877560658@linutronix.de> MIME-Version: 1.0 Date: Tue, 17 Oct 2023 23:23:45 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 17 Oct 2023 14:24:49 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780039434154943859 X-GMAIL-MSGID: 1780039434154943859 From: Thomas Gleixner Nothing needs struct ucode_cpu_info. Make it take struct cpu_signature, let it return a boolean and simplify the implementation. Rename it now that the silly name clash with collect_cpu_info() is gone. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/cpu.h | 4 ++-- arch/x86/kernel/cpu/microcode/intel.c | 33 +++++++++------------------------ drivers/platform/x86/intel/ifs/load.c | 8 +++----- 3 files changed, 14 insertions(+), 31 deletions(-) --- --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -73,9 +73,9 @@ static inline void init_ia32_feat_ctl(st extern __noendbr void cet_disable(void); -struct ucode_cpu_info; +struct cpu_signature; -int intel_cpu_collect_info(struct ucode_cpu_info *uci); +void intel_collect_cpu_info(struct cpu_signature *sig); static inline bool intel_cpu_signatures_match(unsigned int s1, unsigned int p1, unsigned int s2, unsigned int p2) --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -66,36 +66,21 @@ static inline unsigned int exttable_size return et->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE; } -int intel_cpu_collect_info(struct ucode_cpu_info *uci) +void intel_collect_cpu_info(struct cpu_signature *sig) { - unsigned int val[2]; - unsigned int family, model; - struct cpu_signature csig = { 0 }; - unsigned int eax, ebx, ecx, edx; + sig->sig = cpuid_eax(1); + sig->pf = 0; + sig->rev = intel_get_microcode_revision(); - memset(uci, 0, sizeof(*uci)); + if (x86_model(sig->sig) >= 5 || x86_family(sig->sig) > 6) { + unsigned int val[2]; - eax = 0x00000001; - ecx = 0; - native_cpuid(&eax, &ebx, &ecx, &edx); - csig.sig = eax; - - family = x86_family(eax); - model = x86_model(eax); - - if (model >= 5 || family > 6) { /* get processor flags from MSR 0x17 */ native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]); - csig.pf = 1 << ((val[1] >> 18) & 7); + sig->pf = 1 << ((val[1] >> 18) & 7); } - - csig.rev = intel_get_microcode_revision(); - - uci->cpu_sig = csig; - - return 0; } -EXPORT_SYMBOL_GPL(intel_cpu_collect_info); +EXPORT_SYMBOL_GPL(intel_collect_cpu_info); /* * Returns 1 if update has been found, 0 otherwise. @@ -378,7 +363,7 @@ static __init struct microcode_intel *ge if (!(cp.data && cp.size)) return NULL; - intel_cpu_collect_info(uci); + intel_collect_cpu_info(&uci->cpu_sig); return scan_microcode(cp.data, cp.size, uci); } --- a/drivers/platform/x86/intel/ifs/load.c +++ b/drivers/platform/x86/intel/ifs/load.c @@ -227,7 +227,7 @@ static int scan_chunks_sanity_check(stru static int image_sanity_check(struct device *dev, const struct microcode_header_intel *data) { - struct ucode_cpu_info uci; + struct cpu_signature sig; /* Provide a specific error message when loading an older/unsupported image */ if (data->hdrver != MC_HEADER_TYPE_IFS) { @@ -240,11 +240,9 @@ static int image_sanity_check(struct dev return -EINVAL; } - intel_cpu_collect_info(&uci); + intel_collect_cpu_info(&sig); - if (!intel_find_matching_signature((void *)data, - uci.cpu_sig.sig, - uci.cpu_sig.pf)) { + if (!intel_find_matching_signature((void *)data, sig.sig, sig.pf)) { dev_err(dev, "cpu signature, processor flags not matching\n"); return -EINVAL; } From patchwork Tue Oct 17 21:23:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 154551 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp4406504vqb; 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[2620:137:e000::3:1]) by mx.google.com with ESMTPS id a9-20020a1709027d8900b001c9fb3b55f0si2440693plm.652.2023.10.17.14.25.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 14:25:00 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) client-ip=2620:137:e000::3:1; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=VpueM5HD; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by morse.vger.email (Postfix) with ESMTP id 76B02801B6E4; Tue, 17 Oct 2023 14:24:58 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at morse.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344439AbjJQVYt (ORCPT + 21 others); Tue, 17 Oct 2023 17:24:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33684 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235099AbjJQVYR (ORCPT ); Tue, 17 Oct 2023 17:24:17 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 16600109 for ; Tue, 17 Oct 2023 14:23:49 -0700 (PDT) Message-ID: <20231017211722.906846627@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1697577827; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=ADl+tJKDMR2begbrrA6j9nZiECrMHsdLH4cmpVlI80c=; b=VpueM5HDqoiK3sCXhwPD6b0fiPdVfrHugBHN7qhHb+lqxjjg5iZs3MZdP3nfVpTS5CBGJ2 Qoz2G5mg3fPS+1gHSp4DPUB9IvawsSK3MZy+/qdk4Gv9CoUQQEkY0DpU1a+qcntGJWn5Qm CovYxLc1w1z1MY36YxkcTYYzmKugmE4UKH27sstOUzPv+NuaGhY49A3pM/bl0qUgFY/kVR VBtdd3RMvJRJCSfXCDFLpHc/yw9aFnif8orGuPmwXNvQhQRMPOljT1VPgZJINTA1n60jDJ WXX1cNio81VqipAwJNxbJl8RYgu5YzMD9DMq/kDonk3KpBmEaMTdMrHDSEhKzg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1697577827; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=ADl+tJKDMR2begbrrA6j9nZiECrMHsdLH4cmpVlI80c=; b=JfbmqsMHChDAPl3sxuOtQzJeb4BqdGbG7mBqTOHEFsSw4Bs9IsIvs0ifCVFpfMtotA6Jim IPTzli7NFvmsRDAg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov Subject: [patch V5 17/39] x86/microcode/intel: Reuse intel_cpu_collect_info() References: <20231017200758.877560658@linutronix.de> MIME-Version: 1.0 Date: Tue, 17 Oct 2023 23:23:46 +0200 (CEST) X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Tue, 17 Oct 2023 14:24:58 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780039444576149232 X-GMAIL-MSGID: 1780039444576149232 From: Thomas Gleixner No point for an almost duplicate function. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/intel.c | 16 +--------------- 1 file changed, 1 insertion(+), 15 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -419,21 +419,7 @@ void reload_ucode_intel(void) static int collect_cpu_info(int cpu_num, struct cpu_signature *csig) { - struct cpuinfo_x86 *c = &cpu_data(cpu_num); - unsigned int val[2]; - - memset(csig, 0, sizeof(*csig)); - - csig->sig = cpuid_eax(0x00000001); - - if ((c->x86_model >= 5) || (c->x86 > 6)) { - /* get processor flags from MSR 0x17 */ - rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]); - csig->pf = 1 << ((val[1] >> 18) & 7); - } - - csig->rev = c->microcode; - + intel_collect_cpu_info(csig); return 0; } From patchwork Tue Oct 17 21:23:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 154556 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp4406723vqb; Tue, 17 Oct 2023 14:25:27 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGSvV7Y9PrlJIVHQIQ0M6X+fYnXeUpdSI1rqSaZNCPsNzPGNs3TAUaJSU3oJZtF8m10g0kl X-Received: by 2002:a05:6830:6e9a:b0:6c7:aab5:6e50 with SMTP id ed26-20020a0568306e9a00b006c7aab56e50mr4510972otb.2.1697577926986; Tue, 17 Oct 2023 14:25:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697577926; cv=none; d=google.com; s=arc-20160816; b=HdmRX3jauf8jtLJO3Dt1xWFY9MNy/0gjW+/CYrJDCd1a1/oDBu9BsixEBbRw8CzjEp qX/FDkg+NTU4Ey0ZcYQCqFY4btiKOHENAnC3LLtWn28CfkzNmZklWl7PRigvSYGIh2JN UlYTlgfL8Au8ROPzXJtLX99YExKJ3hHvVXLg3C6+gD12Q96gnZERidRSIMX+bp9wjIZg Hx+oC9lryaG13TuMFtQ/8DE3wN2LETi+Byjsf1XGTlQ0WSeVx3qi2HnXgJbA8Au3loA1 0lzugyl5TumeQvcdH1M4Tn2Ex2gv0G4q3sgFw9qyKIV/7B/1kshvNOPQICBO28r8Y1Lo 0bqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=qm9Kw9R9Buar+uEGcw+Q04P//kyP8Ip+yyin4VVf6fc=; fh=8iy+GLBXZdpcs/hIddJ7mbUapYjefwP9Gb111pAzFms=; b=weKjP8W4RNWAr7kjDCh/Y01/vo12LaaNKmUakMkNKgcNq9PJaC2dtSswMnnAG20Rqr +0yxKMuPjwWvSHzyyslxZhXGGfAl6jRqXklcupT/mhyo26OgBVZ7Ua3/N9ign8yN/Or3 xHsd47XQ5wxJxtxreGMqvLitzohBLcIqxz18Kbb/HVYxSLwpRPFsV8wxlUKwYAZuXMsS id1F6IalHGndtzOhs87s54BAxP+rbAZZZP87kzg6QG5sDNgi+XBDFloPr7nFRw0vCpJg eA/+KqC6s/RhVB44YPS5LxJ5tetZpY1fLMzH+rpo3fImX7iZiz8hMgc3j8Z4OaU3Le/E QVxw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=XmHMtSnp; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from fry.vger.email (fry.vger.email. [23.128.96.38]) by mx.google.com with ESMTPS id y35-20020a056a00182300b00690d42e3347si2546455pfa.157.2023.10.17.14.25.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 14:25:26 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) client-ip=23.128.96.38; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=XmHMtSnp; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by fry.vger.email (Postfix) with ESMTP id F41FC80FC14E; Tue, 17 Oct 2023 14:25:18 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at fry.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344470AbjJQVYy (ORCPT + 21 others); Tue, 17 Oct 2023 17:24:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33442 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235057AbjJQVYT (ORCPT ); Tue, 17 Oct 2023 17:24:19 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4E472D72 for ; Tue, 17 Oct 2023 14:23:50 -0700 (PDT) Message-ID: <20231017211722.962868378@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1697577828; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=qm9Kw9R9Buar+uEGcw+Q04P//kyP8Ip+yyin4VVf6fc=; b=XmHMtSnpUX+/XnUEeYwIHyeTSZ9XYlfLTtpQgfKubNGRb6zp8Gx6aQhapzfBHxjXKoXFgI SK7CZWlXN/cqANnwBNXgLJZ5i5cvZVhTY7pCXkVEuKw+6QNrN0O913KxgWNSVRDF0ysvJE Qo3mOPCzrKyjmOLIM5Rj+7qKHgYcALOhusz7rHMsdZYzFSxMtq2agEPIP92nl4Rjp8DMFZ aobLcIxXT1jIzQTkiqHb+z0pBZhOjPE2ya7G6/G7SU1gioskmKbPGWdJqOuBPdB8hqdjOT qTSLpMpYEqbJIEQ6T8Fi3h1a5OfGGjJUYG9YEB94Uj8nd74oHzQbZJrncV6Fow== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1697577828; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=qm9Kw9R9Buar+uEGcw+Q04P//kyP8Ip+yyin4VVf6fc=; b=wHfhx4u9CZY37OArg4sSHzFlY019s+ETXT8sr+nMiIX6tT2W8fxFtb3yurRM4Kx2F5zFyo T2gjTNzWnkUREKCA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov Subject: [patch V5 18/39] x86/microcode/intel: Rework intel_find_matching_signature() References: <20231017200758.877560658@linutronix.de> MIME-Version: 1.0 Date: Tue, 17 Oct 2023 23:23:48 +0200 (CEST) X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Tue, 17 Oct 2023 14:25:19 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780039472095263048 X-GMAIL-MSGID: 1780039472095263048 From: Thomas Gleixner Take a cpu_signature argument and work from there. Move the match() helper next to the callsite as there is no point for having it in a header. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/cpu.h | 16 +--------------- arch/x86/kernel/cpu/microcode/intel.c | 31 +++++++++++++++++++------------ drivers/platform/x86/intel/ifs/load.c | 2 +- 3 files changed, 21 insertions(+), 28 deletions(-) --- --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -77,22 +77,8 @@ struct cpu_signature; void intel_collect_cpu_info(struct cpu_signature *sig); -static inline bool intel_cpu_signatures_match(unsigned int s1, unsigned int p1, - unsigned int s2, unsigned int p2) -{ - if (s1 != s2) - return false; - - /* Processor flags are either both 0 ... */ - if (!p1 && !p2) - return true; - - /* ... or they intersect. */ - return p1 & p2; -} - extern u64 x86_read_arch_cap_msr(void); -int intel_find_matching_signature(void *mc, unsigned int csig, int cpf); +bool intel_find_matching_signature(void *mc, struct cpu_signature *sig); int intel_microcode_sanity_check(void *mc, bool print_err, int hdr_type); extern struct cpumask cpus_stop_mask; --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -82,29 +82,36 @@ void intel_collect_cpu_info(struct cpu_s } EXPORT_SYMBOL_GPL(intel_collect_cpu_info); -/* - * Returns 1 if update has been found, 0 otherwise. - */ -int intel_find_matching_signature(void *mc, unsigned int csig, int cpf) +static inline bool cpu_signatures_match(struct cpu_signature *s1, unsigned int sig2, + unsigned int pf2) +{ + if (s1->sig != sig2) + return false; + + /* Processor flags are either both 0 or they intersect. */ + return ((!s1->pf && !pf2) || (s1->pf & pf2)); +} + +bool intel_find_matching_signature(void *mc, struct cpu_signature *sig) { struct microcode_header_intel *mc_hdr = mc; - struct extended_sigtable *ext_hdr; struct extended_signature *ext_sig; + struct extended_sigtable *ext_hdr; int i; - if (intel_cpu_signatures_match(csig, cpf, mc_hdr->sig, mc_hdr->pf)) - return 1; + if (cpu_signatures_match(sig, mc_hdr->sig, mc_hdr->pf)) + return true; /* Look for ext. headers: */ if (get_totalsize(mc_hdr) <= intel_microcode_get_datasize(mc_hdr) + MC_HEADER_SIZE) - return 0; + return false; ext_hdr = mc + intel_microcode_get_datasize(mc_hdr) + MC_HEADER_SIZE; ext_sig = (void *)ext_hdr + EXT_HEADER_SIZE; for (i = 0; i < ext_hdr->count; i++) { - if (intel_cpu_signatures_match(csig, cpf, ext_sig->sig, ext_sig->pf)) - return 1; + if (cpu_signatures_match(sig, ext_sig->sig, ext_sig->pf)) + return true; ext_sig++; } return 0; @@ -265,7 +272,7 @@ static __init struct microcode_intel *sc intel_microcode_sanity_check(data, false, MC_HEADER_TYPE_MICROCODE) < 0) break; - if (!intel_find_matching_signature(data, uci->cpu_sig.sig, uci->cpu_sig.pf)) + if (!intel_find_matching_signature(data, &uci->cpu_sig)) continue; /* Check whether there is newer microcode */ @@ -496,7 +503,7 @@ static enum ucode_state parse_microcode_ if (cur_rev >= mc_header.rev) continue; - if (!intel_find_matching_signature(mc, uci->cpu_sig.sig, uci->cpu_sig.pf)) + if (!intel_find_matching_signature(mc, &uci->cpu_sig)) continue; kvfree(new_mc); --- a/drivers/platform/x86/intel/ifs/load.c +++ b/drivers/platform/x86/intel/ifs/load.c @@ -242,7 +242,7 @@ static int image_sanity_check(struct dev intel_collect_cpu_info(&sig); - if (!intel_find_matching_signature((void *)data, sig.sig, sig.pf)) { + if (!intel_find_matching_signature((void *)data, &sig)) { dev_err(dev, "cpu signature, processor flags not matching\n"); return -EINVAL; } From patchwork Tue Oct 17 21:23:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 154558 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp4406788vqb; Tue, 17 Oct 2023 14:25:37 -0700 (PDT) X-Google-Smtp-Source: AGHT+IErvJwsEvj4+gWQ98fBX5NnshzIwJWPNks/czjP14kg5Jl/URJifPqxP3/rS73CoANDdg+1 X-Received: by 2002:a17:90b:3802:b0:27c:f653:37b2 with SMTP id mq2-20020a17090b380200b0027cf65337b2mr3697311pjb.1.1697577937270; Tue, 17 Oct 2023 14:25:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697577937; cv=none; d=google.com; s=arc-20160816; b=LvFiMp9OoCeFoFYwofYI6FYDt5pU9u3DNcXH0pdQVP/6k7acrzJrpJ5ltfRmV2zCFL 8r6AXOy1lIMETIuNkBZdHwxLzThemyMfiVIfwEYVpvTZrCBB3LlcjxYXubfFaIA69oO1 obMScgT7p2L8K8bxS7uaTeTH5oKcrR6Q1ivEGfeS+iJzeYl72q2+p+h2kV6SNkJ4sqL2 Mr3gd2QliNwQGq3KOVtBQO04bim0r/plc4ldIVUn7+uwUv7HlBDzdKYmf2fC2say5OHw AHO0Z1TYDTBjKzndrWouAcWRvszpNWdHKcPtUiMeYW+Up3nZ5VOJuMTctBwaPNN4O550 pCbg== ARC-Message-Signature: i=1; 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[23.128.96.36]) by mx.google.com with ESMTPS id a12-20020a17090a854c00b002683f507990si9444735pjw.109.2023.10.17.14.25.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 14:25:37 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) client-ip=23.128.96.36; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=l2kPJv8n; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by pete.vger.email (Postfix) with ESMTP id B686680284ED; Tue, 17 Oct 2023 14:25:27 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at pete.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344277AbjJQVY7 (ORCPT + 21 others); Tue, 17 Oct 2023 17:24:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33536 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344250AbjJQVYb (ORCPT ); Tue, 17 Oct 2023 17:24:31 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4BB8910CE for ; Tue, 17 Oct 2023 14:23:51 -0700 (PDT) Message-ID: <20231017211723.018821624@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1697577830; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=k082nSPppDUkOLh9xMaYiiJZSBP4qeS6H+UxEpdLYkw=; b=l2kPJv8n4GOVejsCnVP6iRSA/vsKQw93X1p+Wb15YN96cr94WkEAWzUW5UA8qIwy0bpIa/ JItFlgQikDeguLVBCCjXYmaLqbijQoL4lIjf4h91bH0iMa2h5frCsXEloAAnZIEgBMzrBF Es5COMMDY8vHLUExrY8qWP1W+nDCCdWQQV4apAtHato/T1sFfwCXcjvLcYc4REzxQiaXeV gkB44OozvZOngaPVVTHayv3BQmlY5KaWZ0+VUph9kRFLB+O2gdROpLAw5KVgEGxMh2v7Op boesDTjxiSWGjPuR3WgutufxEJiJdiyRT2YRcnezBtqt6ZU0qd7HKmrKT4p3/Q== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1697577830; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=k082nSPppDUkOLh9xMaYiiJZSBP4qeS6H+UxEpdLYkw=; b=oV8f795DOcI4kzPmF1+3APolA3gE4P91Peuk7h1rbjJuGPD8VUrfISmUVS9fNdN2hWNvEi MbAHAd77DfWRHhCA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov Subject: [patch V5 19/39] x86/microcode: Remove pointless apply() invocation References: <20231017200758.877560658@linutronix.de> MIME-Version: 1.0 Date: Tue, 17 Oct 2023 23:23:49 +0200 (CEST) X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Tue, 17 Oct 2023 14:25:27 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780039482963706401 X-GMAIL-MSGID: 1780039482963706401 From: Thomas Gleixner Microcode is applied on the APs during early bringup. There is no point in trying to apply the microcode again during the hotplug operations and neither at the point where the microcode device is initialized. Collect CPU info and microcode revision in setup_online_cpu() for now. This will move to the CPU hotplug callback later. [ bp: Leave the starting notifier for the following scenario: - boot, late load, suspend to disk, resume without the starting notifier, only the last core manages to update the microcode upon resume: # rdmsr -a 0x8b 10000bf 10000bf 10000bf 10000bf 10000bf 10000dc <---- This is on an AMD F10h machine. For the future, one should check whether potential unification of the CPU init path could cover the resume path too so that this can be simplified even more. tglx: This is caused by the odd handling of APs which try to find the microcode blob in builtin or initrd instead of caching the microcode blob during early init before the APs are brought up. Will be cleaned up in a later step. ] Signed-off-by: Thomas Gleixner Signed-off-by: Borislav Petkov (AMD) Signed-off-by: Thomas Gleixner --- V5: Drop the starting notifier change as that requires rework of the AMD code. --- arch/x86/kernel/cpu/microcode/core.c | 23 ++++++----------------- 1 file changed, 6 insertions(+), 17 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -487,17 +487,6 @@ static void microcode_fini_cpu(int cpu) microcode_ops->microcode_fini_cpu(cpu); } -static enum ucode_state microcode_init_cpu(int cpu) -{ - struct ucode_cpu_info *uci = ucode_cpu_info + cpu; - - memset(uci, 0, sizeof(*uci)); - - microcode_ops->collect_cpu_info(cpu, &uci->cpu_sig); - - return microcode_ops->apply_microcode(cpu); -} - /** * microcode_bsp_resume - Update boot CPU microcode during resume. */ @@ -552,14 +541,14 @@ static int mc_cpu_down_prep(unsigned int static void setup_online_cpu(struct work_struct *work) { int cpu = smp_processor_id(); - enum ucode_state err; + struct ucode_cpu_info *uci = ucode_cpu_info + cpu; - err = microcode_init_cpu(cpu); - if (err == UCODE_ERROR) { - pr_err("Error applying microcode on CPU%d\n", cpu); - return; - } + memset(uci, 0, sizeof(*uci)); + microcode_ops->collect_cpu_info(cpu, &uci->cpu_sig); + cpu_data(cpu).microcode = uci->cpu_sig.rev; + if (!cpu) + boot_cpu_data.microcode = uci->cpu_sig.rev; mc_cpu_online(cpu); } From patchwork Tue Oct 17 21:23:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 154555 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp4406677vqb; Tue, 17 Oct 2023 14:25:22 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEg8BBlv7Lwrw85XIhFX0vwz3uGIP8sBs0kKhjk42pUwpn2kvSXdNTGgUFMFldYG5KpnXIx X-Received: by 2002:a17:90b:4a0b:b0:27d:4d4d:3b19 with SMTP id kk11-20020a17090b4a0b00b0027d4d4d3b19mr3720346pjb.0.1697577921859; Tue, 17 Oct 2023 14:25:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697577921; cv=none; d=google.com; s=arc-20160816; b=sIK93lNXrD1s+CpOV7cKFQwyJoC1VZzkFGYBJcQNamMqpWN/+cjgWE9kcnqwbDjuDN SFEoM2O5rc6tjR5frXQ0dTHqhiowfeXoUeHa2zzEGXLZQDSMrrnX9X3iAcK5HnrFE8nJ 18B4wXxZ2Su8Owb2LPR0bZbw70ytBVChqE/oNN2deh4WuFgXRxw02VbE8g03bDcvbcHJ z24mOS88pv2/oNFtt/1xr5QnQWI9OXDPpccaIvBuVDDtRD4F6YhHOKUczIpEaEpbV86u YGwEEDc/O3SxlH+j2Eo9MLIfPEwaRVoT5ONmxj27XZxNf3O1bP0L9gLc9EvdfDcLR5Cs VahA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=MlY9vNxYaPkZBTjl1vPw4VNof43qV6pbee+MSxw01wA=; fh=8iy+GLBXZdpcs/hIddJ7mbUapYjefwP9Gb111pAzFms=; b=tBO5z12R5xwaQ+/sm4UTrGsTHxdf2SLvRADFjXrYtch0KKuKV6wz5CB3It/x7dZWYK 41hf+rJB2lq9b8igi1QkgqeWSad1J6ZV80dwvvg0NYwf9/43BNGhQwPJ2SzhVNlhr4JB rGfsQI+6BxQVTJ1AeFG8c6VoixGsPzOexvx6BZ2wN4C6DRqHPzalclpkBBAIunh3RNMD OdIKzIBfBD74Kesgiifn7EXIZYx2JryAAAGdWPL/H4SzXworFlREsAEnN9KlRuzGCk/7 rauHJQnNjNEo0ERcWKLX2InBanoUjkOcuX7YASIjbPgSvSlRgZbIH2Osk5mpKi31Lexq rhmg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="yjc/FqRp"; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from morse.vger.email (morse.vger.email. [23.128.96.31]) by mx.google.com with ESMTPS id o7-20020a17090a744700b00268293118efsi2424747pjk.47.2023.10.17.14.25.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 14:25:21 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) client-ip=23.128.96.31; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="yjc/FqRp"; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by morse.vger.email (Postfix) with ESMTP id B4C00801B6FB; Tue, 17 Oct 2023 14:25:19 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at morse.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344302AbjJQVZD (ORCPT + 21 others); Tue, 17 Oct 2023 17:25:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44894 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344272AbjJQVYc (ORCPT ); Tue, 17 Oct 2023 17:24:32 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C93ED10E5 for ; Tue, 17 Oct 2023 14:23:53 -0700 (PDT) Message-ID: <20231017211723.074939820@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1697577831; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=MlY9vNxYaPkZBTjl1vPw4VNof43qV6pbee+MSxw01wA=; b=yjc/FqRpzap5/+q5puPwOhuS46yEgu+mzgRJSU+NmSkeZjlO31PGoF0uwuU8dexWF/4OtC RtzB4UCBCl8wAlkf5y8M5NKStatXyWT9g102i7XIqetlEg+zGs2TeFqeRdWYThphYpSu1J JPV6ErX80cE2PjjYIsMhkjtu4pJLC3nGAMyyKa//ABhh4HgiUGmThyDLKaLEKW2vd0CUEG IWUEez+bpA8gwbRR40r+ebD+HYONJQnG388H8a2Ffpky95cLqnC7PRQpX3wy5eF/8btpRA YAuwP2YWQMkViqmnfFuXC4NjBXWXRaYMZLF2s1NmHBXwBgKNOtEphvajO9wfew== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1697577831; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=MlY9vNxYaPkZBTjl1vPw4VNof43qV6pbee+MSxw01wA=; b=zBVqXmxAMua3u1QFXNfwJeOvtL3Z0dFP1k/JuzncmsWB5uuzw9WGzLhNgsnY/FIioachtG ERxAZZfw1N5jSPDw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov Subject: [patch V5 20/39] x86/microcode/amd: Use correct per CPU ucode_cpu_info References: <20231017200758.877560658@linutronix.de> MIME-Version: 1.0 Date: Tue, 17 Oct 2023 23:23:51 +0200 (CEST) X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Tue, 17 Oct 2023 14:25:19 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780039466708385731 X-GMAIL-MSGID: 1780039466708385731 From: Thomas Gleixner find_blobs_in_containers() is invoked on every CPU but overwrites unconditionally ucode_cpu_info of CPU0. Fix this by using the proper CPU data and move the assignment into the call site apply_ucode_from_containers() so that the function can be reused. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/amd.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) --- diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/microcode/amd.c index a2776f2af93b..f6ed2c5be932 100644 --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -503,9 +503,6 @@ static void find_blobs_in_containers(unsigned int cpuid_1_eax, struct cpio_data if (!get_builtin_microcode(&cp, x86_family(cpuid_1_eax))) cp = find_microcode_in_initrd(ucode_path); - /* Needed in load_microcode_amd() */ - ucode_cpu_info->cpu_sig.sig = cpuid_1_eax; - *ret = cp; } @@ -513,6 +510,9 @@ static void apply_ucode_from_containers(unsigned int cpuid_1_eax) { struct cpio_data cp = { }; + /* Needed in load_microcode_amd() */ + ucode_cpu_info[smp_processor_id()].cpu_sig.sig = cpuid_1_eax; + find_blobs_in_containers(cpuid_1_eax, &cp); if (!(cp.data && cp.size)) return; From patchwork Tue Oct 17 21:23:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 154564 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp4407188vqb; Tue, 17 Oct 2023 14:26:35 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEkGp+09tbxxLBZ61g89kmBapdyGNfbP8i4UYt9k9m0+NKLNLEEp5Ud6tbEC2pxTi2QGFvE X-Received: by 2002:a05:6a00:330c:b0:68e:2fd4:288a with SMTP id cq12-20020a056a00330c00b0068e2fd4288amr3352405pfb.3.1697577995676; Tue, 17 Oct 2023 14:26:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697577995; cv=none; d=google.com; s=arc-20160816; b=IlnLbhrI0QJtfiCvlSwuclUa3Rae0tkTjmzfuuwfcPfNA4BfOYH6YMm6vfMdhK6gcB lLV7B9ihph7hALlFAHzuVmxmln2IEEQkmcy94OL/2w78CZe7ZFj4yW7ZTiyecCuJn/aY PKhIthk1BqFK4E73RxJJaGIq9FrDUGteAsyLByjaAwTP2EEf9aXggIuTSS+dKy7vEH6G ZF05qBhEh0PJ4YcQvxdgv5pZ5KFBWQdoBwMvMjZUCBjZuFl5EtlEadlN776y54Zv/yhJ nAs47AXxWg6p7J2KYlEX1u2aw+3QrRnjFTTt1ygBBiApizxhLr5ay2XAipJS0UhcMJ6Y hsyA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=QfJgwvaKg9KDiVtt/bFmM4IrpyyKSnPnwhur+L5KJQY=; fh=8iy+GLBXZdpcs/hIddJ7mbUapYjefwP9Gb111pAzFms=; b=p+T7qfxsT7SXnJxSVzhWY7OU7UeZH5gOo5afRKQJECmrTjXcKnLkUnqSnAwFojT6Dm 4gmzNkbKw0GsmP1Tfy+sRD+mfr4DB7rbHgYuhUgB6o96EQfdGU/RSPk9OtqmYqrgGN8E qVwktTJQbnKLaoxWnVU8S7i+5spfRr2q6zY+v1AruNWTdOMrdHx342UNLVLA2lRYaZFe lG3IlzPrQ6e3MeE9SUAF+32iDIqmeKoddoqZ2CzeR9uVR4E/bLwldzahFSwL/1kt/+ES HH08yJJshIJCQjDvQFz1ObESiBIfElHFsiq7qLRvs6Er2kzd77mndsd9X5+3S/kuNX+8 ATfA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=e00lgK0D; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=UYjLIWBg; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from lipwig.vger.email (lipwig.vger.email. [23.128.96.33]) by mx.google.com with ESMTPS id o22-20020a656a56000000b00565dd3fbfdfsi760321pgu.214.2023.10.17.14.26.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 14:26:35 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) client-ip=23.128.96.33; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=e00lgK0D; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=UYjLIWBg; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id 96E548057E7B; Tue, 17 Oct 2023 14:25:57 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235108AbjJQVZN (ORCPT + 21 others); Tue, 17 Oct 2023 17:25:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33630 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344345AbjJQVYi (ORCPT ); Tue, 17 Oct 2023 17:24:38 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F021C126 for ; Tue, 17 Oct 2023 14:23:54 -0700 (PDT) Message-ID: <20231017211723.131454229@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1697577832; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=QfJgwvaKg9KDiVtt/bFmM4IrpyyKSnPnwhur+L5KJQY=; b=e00lgK0DRqOEfU52Ne3s53o+MgjBCGgovEyu0/2ynCn5FA6HM5NPf1folkm3p9kxW8zO2R 9I+OQ6j/RocuZEoiDDWNGESQuNabCqBJe0m8c0Qi6SUyWqyq/kkkrd2D18CTeHZCOQ0dam aePXbAWa8ulRgjFmW+grfgM+j+5Sc8aj3LCP2HAimjN09KJIvADLu5rzwHDK3b6PZ+dNUC daveamMXE+FYKz890J548mS9CMslw4Rr/ch5KcMJM5JAomHkJxBuKpTg/W6g7cm7xGnukC IRPZ1QdK5HRXb2bF+NkP+RhcIt8W7841+988Ls5n5rHtkUcu9VBVz1w7s3nrWQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1697577832; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=QfJgwvaKg9KDiVtt/bFmM4IrpyyKSnPnwhur+L5KJQY=; b=UYjLIWBgfoxZ/nskVAHhlvCmiHI7TQxwmKsvRfNm2+hzLWTkJzZtgNKBpOLBN2P8ojCEDd ib+bXEUdDjkuCwBw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov Subject: [patch V5 21/39] x86/microcode/amd: Cache builtin microcode too References: <20231017200758.877560658@linutronix.de> MIME-Version: 1.0 Date: Tue, 17 Oct 2023 23:23:52 +0200 (CEST) X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Tue, 17 Oct 2023 14:25:57 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780039544003146812 X-GMAIL-MSGID: 1780039544003146812 From: Thomas Gleixner save_microcode_in_initrd_amd() fails to cache builtin microcode and only scans initrd. Use find_blobs_in_containers() instead which covers both. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/amd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) --- diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/microcode/amd.c index f6ed2c5be932..046b3a6c8594 100644 --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -533,7 +533,7 @@ int __init save_microcode_in_initrd_amd(unsigned int cpuid_1_eax) enum ucode_state ret; struct cpio_data cp; - cp = find_microcode_in_initrd(ucode_path); + find_blobs_in_containers(cpuid_1_eax, &cp); if (!(cp.data && cp.size)) return -EINVAL; From patchwork Tue Oct 17 21:23:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 154557 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp4406779vqb; Tue, 17 Oct 2023 14:25:36 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGJhTH+XveWa8efjCRoIi6len1vXUyLb8Hx79oQeDs6ecUCfqUcOaif1K5mzyiv5448q+7h X-Received: by 2002:a92:c568:0:b0:357:5188:1f83 with SMTP id b8-20020a92c568000000b0035751881f83mr4397362ilj.1.1697577935841; Tue, 17 Oct 2023 14:25:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697577935; cv=none; d=google.com; s=arc-20160816; b=QkD2p4HH3uXy2d2q1S8Kvr5DSaynWV9gbjE5sXcU/ViG0v+j0ga+7eMe3kdtnNNFXJ 46abd6Z+Y72pu5CWY2bY0NS1K4vTrr+bLT9Cg8rVApUhxukFZKeSdLJN/LYWTAb8ThoM Qven5K1LH8Ocd4M39jNY4JQ39XrUi759BRL7WsVL2f0ojsLhKws3P7pJu5QfIR4RQprq QvW60AH78pzE/bfEC2/jxUNCRXJbR8UpbUvP5la/v1Mo0PqDARs4IiPdBhtUWW+cRq0H 0cnrmu+DaNeP9IgfwPFoHccfL4eI2w5hNiU1+xr6VGn5y2bpsqTq9qx3bbzVRebIZvW/ rUyg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=WQKKrIM+Or60lNHBMCvYO0+xUQpVl/8KUTxnGXot8hw=; fh=8iy+GLBXZdpcs/hIddJ7mbUapYjefwP9Gb111pAzFms=; b=alpcVfiiGWUkpDOMFaLHFZXbLwQit2jQia8iVHVDB8YI7K93MdMU7UwrunBnZipssp PBsMlISzZr54sxAzrYfy5+EBve2NuoI1vMRpxw5/PoO/rBLnX5VEmk4tqsFFSkQV7fJR ruwngsSI7vqM40pW3DkHDhOKp0Ngl8uLDZK3AJiZ+YXhhspRrKANQ5kw5SV6TQdQMk9D adGOAytuzAfwo0c6h3NvHBeljS/vTNyCKS6WtYrUZUB4wXVeu9fEVBWUnDOBMDZvIAR7 B4h+2q0vTjfnMwTSNXlkgQ4/lZLW0oFypq/26roZW4jRFi/O+13lTbsZrbVs4ITIGmeH 9o5A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=Lanv0vBp; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from morse.vger.email (morse.vger.email. [2620:137:e000::3:1]) by mx.google.com with ESMTPS id f10-20020a63554a000000b00578b9d1d118si628791pgm.219.2023.10.17.14.25.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 14:25:35 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) client-ip=2620:137:e000::3:1; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=Lanv0vBp; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by morse.vger.email (Postfix) with ESMTP id 1482D801B6EF; Tue, 17 Oct 2023 14:25:33 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at morse.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344395AbjJQVZP (ORCPT + 21 others); Tue, 17 Oct 2023 17:25:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33698 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234927AbjJQVYr (ORCPT ); Tue, 17 Oct 2023 17:24:47 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1A66C1700 for ; Tue, 17 Oct 2023 14:23:55 -0700 (PDT) Message-ID: <20231017211723.187566507@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1697577834; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=WQKKrIM+Or60lNHBMCvYO0+xUQpVl/8KUTxnGXot8hw=; b=Lanv0vBpQoMbZM/KWgBw4Od9bGin2InD8vXKL3eE+KARCkojPUAAPyPaSauMFO0ENx4sBZ JiU2PzALQVXFrDzjPHoWXWdUorFmnJupEHN86gcibcBK1j2SkcmubfoDa0dVkFDWrUrziU MUyUrc7wak0CboC4nUleonq5PiTIMbTg0SiQd+18PGLxh9gkBRkucN6grb0qncdEsE9B8y 18l3F2OhXgsSgHPZqfBPOW9xLj1xw1hZWemL95aZb/ExLwcxPitvu5qahvMC30GOZVUG3M aAma1o6HwmHi3NRtNOZhQWoVIvAo+jOz+D26tzH0VBPRJNFgUt4fy3dqs3TVeQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1697577834; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=WQKKrIM+Or60lNHBMCvYO0+xUQpVl/8KUTxnGXot8hw=; b=GUHPZio0Nhd7IiYCGlmlUc2IudFKDbmJFU9iHYKnN8VcXQ+REnAmE4ciT692iHLRELQp5G riF0JUi6mzq2DYCw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov Subject: [patch V5 22/39] x86/microcode/amd: Cache builtin/initrd microcode early References: <20231017200758.877560658@linutronix.de> MIME-Version: 1.0 Date: Tue, 17 Oct 2023 23:23:53 +0200 (CEST) X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Tue, 17 Oct 2023 14:25:33 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780039481586393055 X-GMAIL-MSGID: 1780039481586393055 From: Thomas Gleixner There is no reason to scan builtin/initrd microcode on each AP. Cache the builtin/initrd microcode in an early initcall so that the early AP loader can utilize the cache. The existing fs initcall which invoked save_microcode_in_initrd_amd() is still required to maintain the initrd_gone flag. Rename it accordingly. This will be removed once the AP loader code is converted to use the cache. Signed-off-by: Thomas Gleixner --- V5: Prevent saving the microcode blob when the loader is disabled --- arch/x86/kernel/cpu/microcode/amd.c | 8 +++++++- arch/x86/kernel/cpu/microcode/core.c | 20 ++++---------------- 2 files changed, 11 insertions(+), 17 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -527,12 +527,17 @@ void load_ucode_amd_early(unsigned int c static enum ucode_state load_microcode_amd(u8 family, const u8 *data, size_t size); -int __init save_microcode_in_initrd_amd(unsigned int cpuid_1_eax) +static int __init save_microcode_in_initrd(void) { + unsigned int cpuid_1_eax = native_cpuid_eax(1); + struct cpuinfo_x86 *c = &boot_cpu_data; struct cont_desc desc = { 0 }; enum ucode_state ret; struct cpio_data cp; + if (dis_ucode_ldr || c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) + return 0; + find_blobs_in_containers(cpuid_1_eax, &cp); if (!(cp.data && cp.size)) return -EINVAL; @@ -549,6 +554,7 @@ int __init save_microcode_in_initrd_amd( return 0; } +early_initcall(save_microcode_in_initrd); /* * a small, trivial cache of per-family ucode patches --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -180,24 +180,13 @@ void load_ucode_ap(void) } } -static int __init save_microcode_in_initrd(void) +/* Temporary workaround until find_microcode_in_initrd() is __init */ +static int __init mark_initrd_gone(void) { - struct cpuinfo_x86 *c = &boot_cpu_data; - int ret = -EINVAL; - - switch (c->x86_vendor) { - case X86_VENDOR_AMD: - if (c->x86 >= 0x10) - ret = save_microcode_in_initrd_amd(cpuid_eax(1)); - break; - default: - break; - } - initrd_gone = true; - - return ret; + return 0; } +fs_initcall(mark_initrd_gone); struct cpio_data find_microcode_in_initrd(const char *path) { @@ -615,5 +604,4 @@ static int __init microcode_init(void) return error; } -fs_initcall(save_microcode_in_initrd); late_initcall(microcode_init); From patchwork Tue Oct 17 21:23:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 154561 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp4407082vqb; Tue, 17 Oct 2023 14:26:22 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEi3fRIwUxCkaWFhfks5KMCgkk8YoJ9JNmr1wbE8VCzlrYDntDfqEfD++oSZZgoS+heW8N5 X-Received: by 2002:a05:6359:8001:b0:166:db65:af9a with SMTP id rc1-20020a056359800100b00166db65af9amr2949194rwb.2.1697577981883; Tue, 17 Oct 2023 14:26:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697577981; cv=none; d=google.com; s=arc-20160816; b=I0+v2xogsjG5nMw5TxZc7q4QBLfRPnEj/XaifGK4aBfPEfqJj/8iIfYCSjqkZhc+r3 bWB6QtJ0w4/CzPsrU+ipnWRf3IWrf9wtjs/3vQ2M/DfB9JEQSmabKVoSLnG3h3hQj9Rn svYbxZzjr/Yd6beaXBWmHp5L4eh2VDo7XPFDoRxEviIVRm7o+RsPOm8QtCTIEMnqZfg0 /90ViFVcnNapmAzHU+wB3flBEqfttAFAh4yU6Koo4gsxytd3HEECye34X66E1BJEViom PZCzuB/A6dgCYAEdeD8/Cmur54/P93mcbmfYI46JdBrI7DR6sHBatT+Eud38S1wAH3JE BDiw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=5J8QSw18DvBo/9uLrOmSNX2r4sT8ND8hl0n59mIpNI0=; fh=8iy+GLBXZdpcs/hIddJ7mbUapYjefwP9Gb111pAzFms=; b=J4dINEZLfvva1ob9Ug7uFmIINath4vxBk7Yrc/j+KcNdCNYrvhbSF5+BWfcDgpFpm0 wyI5CaJjNVF/WT1CBfWBjmAa98MTLKjiXfBZsJxyXY/asFFt/gQ2Cuk/069xqsRs6C67 mZubOTIVVODlIAoLdDHh3hMrdKw91LgTaMZPMxB2RLT5bAcjUPp34Bv2Icw5IRrjM8qj 12ZQecafeRI68VRf259XLvvzXB7b17/4JIOLxYGC81J9+HpmHdIs4uiXOz9kq9BndQK6 Yy8kFIaS/BzIIc5mxs/wR78Le8+AISa6ld1OxmznC+3I41W2X2Mtz/r6TY9g+2mNtWuV OJEg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=HeJJ8lQo; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=gZ2ZNIpB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from morse.vger.email (morse.vger.email. [2620:137:e000::3:1]) by mx.google.com with ESMTPS id q23-20020a656257000000b0059cc8d682dfsi617768pgv.814.2023.10.17.14.26.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 14:26:21 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) client-ip=2620:137:e000::3:1; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=HeJJ8lQo; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=gZ2ZNIpB; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by morse.vger.email (Postfix) with ESMTP id BFF2D8068894; Tue, 17 Oct 2023 14:25:44 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at morse.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344464AbjJQVZV (ORCPT + 21 others); Tue, 17 Oct 2023 17:25:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33450 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344141AbjJQVYv (ORCPT ); Tue, 17 Oct 2023 17:24:51 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7719F1721 for ; Tue, 17 Oct 2023 14:23:57 -0700 (PDT) Message-ID: <20231017211723.243426023@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1697577835; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=5J8QSw18DvBo/9uLrOmSNX2r4sT8ND8hl0n59mIpNI0=; b=HeJJ8lQo5ICDsUUqQo+UkADGtOYnYR0sTietgp3I4Osr/+Qd+mtoKOuzXNP8u1h/nI5/P8 uR16q+BR1sjybXfCI7rd+/bScUu8Ir4BlkY4l84LK3c/18zyeEAhlv5ZzhUdRatgNFIVaa aCqB0NGiNW5cxZNHPtPhzbPGmSotlnKUm2DOfV6IABlI3FkRBVyPRGdJblQEZHBgXGuEXZ G5VOtPumOBIoNmksNEum6YDFPVNyVz6dYSNU/hrz0IpuIBVb2zmYmQBsGyIPqOxjy+bg5S 3EhZzDG5+qzh3IveL2vwgmSa5aRk/S0nyGI7H7rXHYbm+l06ZYt+EbE0wLc0QQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1697577835; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=5J8QSw18DvBo/9uLrOmSNX2r4sT8ND8hl0n59mIpNI0=; b=gZ2ZNIpBVfvSTfhlC70B7M2twcH3Jz9aiZS4Ld3p8RYUSPU+kW535e8Y9nWqCcZAArMKPv 7LRVx1KDUzISzrDw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov Subject: [patch V5 23/39] x86/microcode/amd: Use cached microcode for AP load References: <20231017200758.877560658@linutronix.de> MIME-Version: 1.0 Date: Tue, 17 Oct 2023 23:23:55 +0200 (CEST) X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Tue, 17 Oct 2023 14:25:44 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780039529943565664 X-GMAIL-MSGID: 1780039529943565664 From: Thomas Gleixner Now that the microcode cache is initialized before the APs are brought up, there is no point in scanning builtin/initrd microcode during AP loading. Convert the AP loader to utilize the cache, which in turn makes the CPU hotplug callback which applies the microcode after initrd/builtin is gone obsolete as the early loading during late hotplug operations including the resume path depends now only on the cache. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/amd.c | 20 +++++++++++--------- arch/x86/kernel/cpu/microcode/core.c | 15 ++------------- arch/x86/kernel/cpu/microcode/internal.h | 2 -- 3 files changed, 13 insertions(+), 24 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -496,7 +496,7 @@ static bool get_builtin_microcode(struct return false; } -static void find_blobs_in_containers(unsigned int cpuid_1_eax, struct cpio_data *ret) +static void __init find_blobs_in_containers(unsigned int cpuid_1_eax, struct cpio_data *ret) { struct cpio_data cp; @@ -506,12 +506,12 @@ static void find_blobs_in_containers(uns *ret = cp; } -static void apply_ucode_from_containers(unsigned int cpuid_1_eax) +void __init load_ucode_amd_bsp(unsigned int cpuid_1_eax) { struct cpio_data cp = { }; /* Needed in load_microcode_amd() */ - ucode_cpu_info[smp_processor_id()].cpu_sig.sig = cpuid_1_eax; + ucode_cpu_info[0].cpu_sig.sig = cpuid_1_eax; find_blobs_in_containers(cpuid_1_eax, &cp); if (!(cp.data && cp.size)) @@ -520,11 +520,6 @@ static void apply_ucode_from_containers( early_apply_microcode(cpuid_1_eax, cp.data, cp.size); } -void load_ucode_amd_early(unsigned int cpuid_1_eax) -{ - return apply_ucode_from_containers(cpuid_1_eax); -} - static enum ucode_state load_microcode_amd(u8 family, const u8 *data, size_t size); static int __init save_microcode_in_initrd(void) @@ -608,7 +603,6 @@ static struct ucode_patch *find_patch(un struct ucode_cpu_info *uci = ucode_cpu_info + cpu; u16 equiv_id; - equiv_id = find_equiv_id(&equiv_table, uci->cpu_sig.sig); if (!equiv_id) return NULL; @@ -710,6 +704,14 @@ static enum ucode_state apply_microcode_ return ret; } +void load_ucode_amd_ap(unsigned int cpuid_1_eax) +{ + unsigned int cpu = smp_processor_id(); + + ucode_cpu_info[cpu].cpu_sig.sig = cpuid_1_eax; + apply_microcode_amd(cpu); +} + static size_t install_equiv_cpu_table(const u8 *buf, size_t buf_size) { u32 equiv_tbl_len; --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -154,7 +154,7 @@ void __init load_ucode_bsp(void) if (intel) load_ucode_intel_bsp(); else - load_ucode_amd_early(cpuid_1_eax); + load_ucode_amd_bsp(cpuid_1_eax); } void load_ucode_ap(void) @@ -173,7 +173,7 @@ void load_ucode_ap(void) break; case X86_VENDOR_AMD: if (x86_family(cpuid_1_eax) >= 0x10) - load_ucode_amd_early(cpuid_1_eax); + load_ucode_amd_ap(cpuid_1_eax); break; default: break; @@ -494,15 +494,6 @@ static struct syscore_ops mc_syscore_ops .resume = microcode_bsp_resume, }; -static int mc_cpu_starting(unsigned int cpu) -{ - enum ucode_state err = microcode_ops->apply_microcode(cpu); - - pr_debug("%s: CPU%d, err: %d\n", __func__, cpu, err); - - return err == UCODE_ERROR; -} - static int mc_cpu_online(unsigned int cpu) { struct device *dev = get_cpu_device(cpu); @@ -590,8 +581,6 @@ static int __init microcode_init(void) schedule_on_each_cpu(setup_online_cpu); register_syscore_ops(&mc_syscore_ops); - cpuhp_setup_state_nocalls(CPUHP_AP_MICROCODE_LOADER, "x86/microcode:starting", - mc_cpu_starting, NULL); cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "x86/microcode:online", mc_cpu_online, mc_cpu_down_prep); --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -91,7 +91,6 @@ extern bool initrd_gone; #ifdef CONFIG_CPU_SUP_AMD void load_ucode_amd_bsp(unsigned int family); void load_ucode_amd_ap(unsigned int family); -void load_ucode_amd_early(unsigned int cpuid_1_eax); int save_microcode_in_initrd_amd(unsigned int family); void reload_ucode_amd(unsigned int cpu); struct microcode_ops *init_amd_microcode(void); @@ -99,7 +98,6 @@ void exit_amd_microcode(void); #else /* CONFIG_CPU_SUP_AMD */ static inline void load_ucode_amd_bsp(unsigned int family) { } static inline void load_ucode_amd_ap(unsigned int family) { } -static inline void load_ucode_amd_early(unsigned int family) { } static inline int save_microcode_in_initrd_amd(unsigned int family) { return -EINVAL; } static inline void reload_ucode_amd(unsigned int cpu) { } static inline struct microcode_ops *init_amd_microcode(void) { return NULL; } From patchwork Tue Oct 17 21:23:56 2023 Content-Type: text/plain; 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[23.128.96.33]) by mx.google.com with ESMTPS id cw10-20020a056a00450a00b006be0b0f000csi456624pfb.156.2023.10.17.14.26.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 14:26:36 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) client-ip=23.128.96.33; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=cBEr8e03; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id C91CB80A58FA; Tue, 17 Oct 2023 14:26:09 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344452AbjJQVZT (ORCPT + 21 others); Tue, 17 Oct 2023 17:25:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33792 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344454AbjJQVYv (ORCPT ); Tue, 17 Oct 2023 17:24:51 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4EBD91725 for ; Tue, 17 Oct 2023 14:23:58 -0700 (PDT) Message-ID: <20231017211723.298854846@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1697577837; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=zoWn/zXSQdOkoPj//a7eVm5ZP4GBukZaN+6DN0KBVgk=; b=cBEr8e03WG+GmnA4WsTF6/8Jg2B8kH9VnkRTposOKhsNVYavR+/Ic0vkc4jLJgx7xioKm9 Fee6wWk3ecipeDlxiwIRBx7r3otZclDL0mnHnU4LCXFC+AjYMHMn981Oqxteq2rIwCOsCl 3tZvXym/PUrenB2z3hmEv3FKRyN5htq3HagnaHlGC9BRKeRl3AUYaMnV00jMK9f4T5HP8q Hz34E4iDqEIxgauP4ULDIK/58hdDlZm4q/mf9E4BQQmtvksJZJnVdjZDyeNvIaIpZqbIgI XNw3lLsqPHRPBwWxA+DP/Wfe4HAcgcO1oYyCBMNyfSqXDGRL9S+lpzmD920JRg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1697577837; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=zoWn/zXSQdOkoPj//a7eVm5ZP4GBukZaN+6DN0KBVgk=; b=xsTGKtKrEhmas/Bc8L/ESg/iBvi3XieGd1hwId9WzgeJGRGRaL/Jn8SNZnc+9G0m2CULa5 2QlSmmIEe6HJQPAw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov Subject: [patch V5 24/39] x86/microcode: Mop up early loading leftovers References: <20231017200758.877560658@linutronix.de> MIME-Version: 1.0 Date: Tue, 17 Oct 2023 23:23:56 +0200 (CEST) X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Tue, 17 Oct 2023 14:26:09 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780039545185840809 X-GMAIL-MSGID: 1780039545185840809 From: Thomas Gleixner Get rid of the initrd_gone hack which was required to keep find_microcode_in_initrd() functional after init. As find_microcode_in_initrd() is now only used during init, mark it accordingly. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/core.c | 17 +---------------- arch/x86/kernel/cpu/microcode/internal.h | 1 - 2 files changed, 1 insertion(+), 17 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -44,8 +44,6 @@ static struct microcode_ops *microcode_ops; bool dis_ucode_ldr = true; -bool initrd_gone; - /* * Synchronization. * @@ -180,15 +178,7 @@ void load_ucode_ap(void) } } -/* Temporary workaround until find_microcode_in_initrd() is __init */ -static int __init mark_initrd_gone(void) -{ - initrd_gone = true; - return 0; -} -fs_initcall(mark_initrd_gone); - -struct cpio_data find_microcode_in_initrd(const char *path) +struct cpio_data __init find_microcode_in_initrd(const char *path) { #ifdef CONFIG_BLK_DEV_INITRD unsigned long start = 0; @@ -216,12 +206,7 @@ struct cpio_data find_microcode_in_initr * has the virtual address of the beginning of the initrd. It also * possibly relocates the ramdisk. In either case, initrd_start contains * the updated address so use that instead. - * - * initrd_gone is for the hotplug case where we've thrown out initrd - * already. */ - if (initrd_gone) - return (struct cpio_data){ NULL, 0, "" }; if (initrd_start) start = initrd_start; --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -86,7 +86,6 @@ static inline unsigned int x86_cpuid_fam } extern bool dis_ucode_ldr; -extern bool initrd_gone; #ifdef CONFIG_CPU_SUP_AMD void load_ucode_amd_bsp(unsigned int family); From patchwork Tue Oct 17 21:23:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 154560 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp4407026vqb; Tue, 17 Oct 2023 14:26:16 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEtZqh1McEIlGVcJQycky0j7nWU2DQDLSxvY9VGr5Z5r93SI+iQmN7IaY+l4mGLEmxFTL4P X-Received: by 2002:a05:6358:72a6:b0:166:d9c9:dbe with SMTP id w38-20020a05635872a600b00166d9c90dbemr3894673rwf.3.1697577975541; Tue, 17 Oct 2023 14:26:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697577975; cv=none; d=google.com; s=arc-20160816; b=KpBxrAxSQzCQRbyrJHikX27xhVUMuyNldlKxgKjDTJQDCRcmF2N31d+jz0t82lxBNe 0WmyAuM8fJObC45V69t6NzWQJcItDAEQpgBJSSJoToozkGcCnaKxmVWUKdykdHnwj6CH kQhmOKrznnu30tb6NKW1Vif70ra5Dqa6pxvO8iMzJyVltM+LeYGxaVLWC4qfSVTgZDUz tEz7yItMoNl9D8h4PsOL1BrNDu1NuMG679PRsZcuWW6gYp7sLce7SroHvrSS4FoiQMwz 9ZeNNlFBYzvlL0/K1l+HvGzjT7wnMb6hJIXEwzaoTtDn6THlGqRlHiOpSwYaYRdre7c/ KQGQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=AEefiq52pPUgmPeVighqihDNKb7+a/WAgWU3npzdjNY=; fh=8iy+GLBXZdpcs/hIddJ7mbUapYjefwP9Gb111pAzFms=; b=T9wRyypu6X/UweJ/DjJelbA6C6xTOQEEd0xk/H0lJm7NNYsK5SKs3hEiDyFKqVUxHW g7RvOn7+lKqRaBhTJxueDzrxZdFMN4LsEJTet+4B8Sb2FWlqkvqBCdLEtc0NyFaKsAsP ld6RYKN+2PMsag61vJCT4WhGbA/rqJT8v/a0Zjp+6nwnWqM4/QdKBcwVvFh2q1Qa3Unq T78YNHkzMcLUenKgitOffCSVensmJXRJxlKwLuYjG2UAGVjXPm+oArQ5TNrPyV3x3hZN omNndm47FW8idTXvl9y2oXYkh0V1iHGYBThIICrC3Ray2wUsPLVn2suaQgJL3F5cmZGv TMaA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=EYKNMpDt; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=8KNku87K; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from fry.vger.email (fry.vger.email. [23.128.96.38]) by mx.google.com with ESMTPS id g5-20020a63b145000000b0058986c0753bsi579774pgp.670.2023.10.17.14.26.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 14:26:15 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) client-ip=23.128.96.38; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=EYKNMpDt; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=8KNku87K; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.38 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by fry.vger.email (Postfix) with ESMTP id 4B46A80FC173; Tue, 17 Oct 2023 14:25:57 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at fry.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1343885AbjJQVZZ (ORCPT + 21 others); Tue, 17 Oct 2023 17:25:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33508 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344463AbjJQVYw (ORCPT ); Tue, 17 Oct 2023 17:24:52 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 195E71735 for ; Tue, 17 Oct 2023 14:23:59 -0700 (PDT) Message-ID: <20231017211723.354748138@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1697577838; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=AEefiq52pPUgmPeVighqihDNKb7+a/WAgWU3npzdjNY=; b=EYKNMpDtKuM4jWc3arlyk87+6yYwVe0W2wPgYRcM+kc0WqdqOByLuNLZ5ObTGEvTWs6mUw mZLWkwDtlHXIm+oPep3keIvFUhcOhGTGWKNN3XvzhONtBJigano+7QDqNZM9J2aNbZxd0G FAOR+lYnFzq78k9LB05bjoceGGYqL5sxMZUV4DrpcolcvKyJCN2K09FmUezv3AIEUunfCs ldQGLl99SpBcgdy9E3mVVzR4cGgT+0kAwDPVIctpq7JcP2bs/86eudAfgf/Rn8rDLsTIrd u+hFvf9tBSYlvchvSGxFWmEFfA+IFdCEX82lYZ0T/K3ntX0NDaLFuck6EaSDLg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1697577838; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=AEefiq52pPUgmPeVighqihDNKb7+a/WAgWU3npzdjNY=; b=8KNku87KQxzmfqtLyEXrm1BV1EO48fiCad1o/VwPa2cOQdFjhyD5jYPE1EM9sGXIGebpam aDapPFkZDhUIAOBw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov Subject: [patch V5 25/39] x86/microcode: Get rid of the schedule work indirection References: <20231017200758.877560658@linutronix.de> MIME-Version: 1.0 Date: Tue, 17 Oct 2023 23:23:58 +0200 (CEST) X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Tue, 17 Oct 2023 14:25:57 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780039523467661165 X-GMAIL-MSGID: 1780039523467661165 From: Thomas Gleixner Scheduling work on all CPUs to collect the microcode information is just another extra step for no value. Let the CPU hotplug callback registration do it. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/core.c | 29 ++++++++++------------------- 1 file changed, 10 insertions(+), 19 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -481,8 +481,16 @@ static struct syscore_ops mc_syscore_ops static int mc_cpu_online(unsigned int cpu) { + struct ucode_cpu_info *uci = ucode_cpu_info + cpu; struct device *dev = get_cpu_device(cpu); + memset(uci, 0, sizeof(*uci)); + + microcode_ops->collect_cpu_info(cpu, &uci->cpu_sig); + cpu_data(cpu).microcode = uci->cpu_sig.rev; + if (!cpu) + boot_cpu_data.microcode = uci->cpu_sig.rev; + if (sysfs_create_group(&dev->kobj, &mc_attr_group)) pr_err("Failed to create group for CPU%d\n", cpu); return 0; @@ -503,20 +511,6 @@ static int mc_cpu_down_prep(unsigned int return 0; } -static void setup_online_cpu(struct work_struct *work) -{ - int cpu = smp_processor_id(); - struct ucode_cpu_info *uci = ucode_cpu_info + cpu; - - memset(uci, 0, sizeof(*uci)); - - microcode_ops->collect_cpu_info(cpu, &uci->cpu_sig); - cpu_data(cpu).microcode = uci->cpu_sig.rev; - if (!cpu) - boot_cpu_data.microcode = uci->cpu_sig.rev; - mc_cpu_online(cpu); -} - static struct attribute *cpu_root_microcode_attrs[] = { #ifdef CONFIG_MICROCODE_LATE_LOADING &dev_attr_reload.attr, @@ -562,12 +556,9 @@ static int __init microcode_init(void) } } - /* Do per-CPU setup */ - schedule_on_each_cpu(setup_online_cpu); - register_syscore_ops(&mc_syscore_ops); - cpuhp_setup_state_nocalls(CPUHP_AP_ONLINE_DYN, "x86/microcode:online", - mc_cpu_online, mc_cpu_down_prep); + cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "x86/microcode:online", + mc_cpu_online, mc_cpu_down_prep); pr_info("Microcode Update Driver: v%s.", DRIVER_VERSION); From patchwork Tue Oct 17 21:23:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 154559 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp4407024vqb; Tue, 17 Oct 2023 14:26:16 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHiFf9OJVs1KwJOvrM7WITBdi6hang/IMGAOUAZ1dQxnAiDiuUt0QKXTp6OCodEwXL5OLR/ X-Received: by 2002:a05:6a21:8182:b0:17a:d292:25d1 with SMTP id pd2-20020a056a21818200b0017ad29225d1mr2823157pzb.6.1697577975736; Tue, 17 Oct 2023 14:26:15 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697577975; cv=none; d=google.com; s=arc-20160816; b=PPu99LRFeq3kKVGlR01euqemLS+3rySmyZOIDQhZHBZe7+p0sUWBnXBa1UHOkwMoSh 7X9thKlJTvVnuFlkT7ZJvS4iZ2O1AErzuCvM9Eckfw+omNRCnzoJObPrTxHC7KnQKyhs Mgy0AKfWTTY+YIsnUF6mqIfqLM8W0ldaP15jvoNT7UP/ndOJm1imWT3DbcNnxevbWFhf +yehBJwQH674HrKMbkYEvCMsSwbFP0UZCAfOQ5T6+CfXAGLcfgQdNY+DSxFfTlwtpa77 7JwlP+/h/cJ2qEmRTytSKYJ/dtV6vy+mhaMNDG9qILMzM2Ca9f7p3fDLrTWyxriFYXCJ SAqg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=dYbY4CrL+bZF98vnVnxg6x/cq61iSItj/EIDVLdFSto=; fh=8iy+GLBXZdpcs/hIddJ7mbUapYjefwP9Gb111pAzFms=; b=e6El6pzV55YhlsUsYg/5l8Zjp5z1aIwP7d4zuQRWiZWiWpNWCAbL0R1jOQo9do2U6z 1OY4O6BW7Diry53HGPSHJL1OYuGkasb7Tt6cJuN1b1JFgrmraFGUbz83bscNKNV2XTNU o8AcDpkHlhjSRafRrBDow9L9WQtUWJkmhkSZYIK1Aa43m67vAZB+Wa/I7+TncYVhn1Oe E9mW4HAC/IDKDFU+jcpk2mNV0tzD3CnIVh2M5jy3cyktcNZmXl0Vm6Se/a4xcBTuFTqV 5HTH8D9cSt3b9d9P3UbemzAuJ/tZsUwvmCmratgUFBqzVaT+jxostKPhgD+u2oV+e9Hr /9yA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=XrXuI0TH; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=IphzYFtD; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from pete.vger.email (pete.vger.email. [23.128.96.36]) by mx.google.com with ESMTPS id r3-20020a1709028bc300b001beeb49d890si351845plo.185.2023.10.17.14.26.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 14:26:15 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) client-ip=23.128.96.36; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=XrXuI0TH; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=IphzYFtD; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by pete.vger.email (Postfix) with ESMTP id 0640680C9A4A; Tue, 17 Oct 2023 14:26:06 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at pete.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235050AbjJQVZe (ORCPT + 21 others); Tue, 17 Oct 2023 17:25:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33596 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344006AbjJQVZJ (ORCPT ); Tue, 17 Oct 2023 17:25:09 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 321C7199B for ; Tue, 17 Oct 2023 14:24:03 -0700 (PDT) Message-ID: <20231017211723.409940426@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1697577839; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=dYbY4CrL+bZF98vnVnxg6x/cq61iSItj/EIDVLdFSto=; b=XrXuI0THL3knM5bRR+KpTqKC0/OCz9xTYl/iG9jLlqJBhItBLCr82Jy7abK7AaHgxQJ3u1 oOOXX8JNu70PXYDH53+mA6uMHKP4jftYtbzZreqGfnjp/ATImmbnDDX+Zv3p96L+a5dxPN RiLOVpqHBoxfo9GFjMmoNZK7PBUySb+a8aZJzj4Whf30YYjtE/fsI1mbrcTh0wkMpaxltX Oi/VBekZz/VfyB14V7yLiRJoy3T/2No398p8B0CAxNLpjs8E5Ohfe244zSnmePtgv/4v9Y i73C8xVmKH6rYSSJJjXtfuWFTxtdpKVVZs/0WmKhd7rkCsIYO7o67NzckvNF7w== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1697577839; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=dYbY4CrL+bZF98vnVnxg6x/cq61iSItj/EIDVLdFSto=; b=IphzYFtD3IH8bseqEHACdUlZrsIk6HKGsPxUdz3QUv0Vih4VX86KkLYH8g6qCZ2sQaWOc8 s5ZUpapzXoXZOoAg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov Subject: [patch V5 26/39] x86/microcode: Clean up mc_cpu_down_prep() References: <20231017200758.877560658@linutronix.de> MIME-Version: 1.0 Date: Tue, 17 Oct 2023 23:23:59 +0200 (CEST) X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Tue, 17 Oct 2023 14:26:06 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780039523177547636 X-GMAIL-MSGID: 1780039523177547636 From: Thomas Gleixner This function has nothing to do with suspend. It's a hotplug callback. Remove the bogus comment. Drop the pointless debug printk. The hotplug core provides tracepoints which track the invocation of those callbacks. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/core.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -498,16 +498,10 @@ static int mc_cpu_online(unsigned int cp static int mc_cpu_down_prep(unsigned int cpu) { - struct device *dev; - - dev = get_cpu_device(cpu); + struct device *dev = get_cpu_device(cpu); microcode_fini_cpu(cpu); - - /* Suspend is in progress, only remove the interface */ sysfs_remove_group(&dev->kobj, &mc_attr_group); - pr_debug("%s: CPU%d\n", __func__, cpu); - return 0; } From patchwork Tue Oct 17 21:24:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 154562 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp4407112vqb; Tue, 17 Oct 2023 14:26:26 -0700 (PDT) X-Google-Smtp-Source: AGHT+IErCllgrJB+DKfA8x/v188mDcxAPxU5PXM5vqVks61u9awQ/mh7Bnf3kcyJQDugId10ONO4 X-Received: by 2002:a17:902:e80c:b0:1c4:1e65:1e5e with SMTP id u12-20020a170902e80c00b001c41e651e5emr3637739plg.0.1697577985489; Tue, 17 Oct 2023 14:26:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697577985; cv=none; d=google.com; s=arc-20160816; b=eSmfzb8BF//Lm07WgkctaREZ7Kao0en5x2PwREABUNV04i+Hbit4OyJa2Hn19/ZY68 NtC6rgSCdyppCuHw5RdSXYFp0Bi377xGXLeNy976AhHN/aMpNPoG/x30HzWQJFEfUy8Q kVx5kW8eyR9gE5Ud/BrZ61jOlMHSkwiqKHs+tm6MNST7uKrFH6zCGJ+skPRPWcMfETBx gVk/Y5QK3kJDg8hbb1ZIkAAgIJF6q24EXDxlVTDmd2fo3y5hZ2C5SYD68Rb258VxvOhQ E+eE24z1kwENmF0Eh2yNTx+flfDd1+vsz2iWneHEkSC6jQPi8h/zezCMZf9aUf39qnlH VPpw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=FxegNWCnpFWvIlhkHULtqrm7vjN3o62RaGltaGWsUSA=; fh=8iy+GLBXZdpcs/hIddJ7mbUapYjefwP9Gb111pAzFms=; b=Fvoz5lXqCYI+t7xk+oU5437v+qC60fE9sqQonfURwFvtBC1eYWaBPnhjldDGsRoox2 qX2fDCcHX2F0FHkfToac5BAGW8UysHypyir+pBzIlwPpQdkDOujlc3MXoVrCwkz4ZR3h IU0ZdlKXMjogPrCPYsHaaBTKDLEoM3twAFByU+UiPxDhpaZwRjGyRPRSmyOQiv0LZ0vT anqS8au2ChfLWeLgHA5NOieqYiAu19Y56VrriRiRj3LlbwE2glGPzeELl99NeHPCLcis QZglRYwHvisEUx6uQJnuXzrNhEC4AokCAfgUwl6dHzl3DaSTTWAzNsoeHMeUTlyAHC8f 99rA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=cCU0zRWM; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from morse.vger.email (morse.vger.email. [23.128.96.31]) by mx.google.com with ESMTPS id li11-20020a170903294b00b001c9fe071f2esi2383082plb.128.2023.10.17.14.26.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 14:26:25 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) client-ip=23.128.96.31; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=cCU0zRWM; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by morse.vger.email (Postfix) with ESMTP id EA9DF80A1372; Tue, 17 Oct 2023 14:26:06 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at morse.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235099AbjJQVZi (ORCPT + 21 others); Tue, 17 Oct 2023 17:25:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33618 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234891AbjJQVZK (ORCPT ); Tue, 17 Oct 2023 17:25:10 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9ADF419A0 for ; Tue, 17 Oct 2023 14:24:03 -0700 (PDT) Message-ID: <20231017211723.465514319@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1697577841; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=FxegNWCnpFWvIlhkHULtqrm7vjN3o62RaGltaGWsUSA=; b=cCU0zRWMDmLxyfgulio75QjVQgD2isJt3zbWv9/TXTo/IrcvJBoE+QG5ZsJF/Lo6vpUmGf Bhx4BqsMD49XqgYM3e8NZ1+WU06WHIzG6/u//QHbtBvoNFKcFUCfCYA2fyXW7iCsoF72JQ Y43veQ7eXD72VExHJwauMRzdWkcox5FCN02ZtdNFfF4I7xTsN29WL6vvNUyFgEvTnwoLr6 Z0gI8tUWsJP99md1hXyEF6nktGJI3UbmGZwqQahGodmsggZ0cqwEuyN0lm8DERt/O0/ZT8 yHZE0TcyvKMyyoF4dis/MlPgoRwhpmFskvhlRsjG4t3hYWr9fpUMRGxS9Fsxng== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1697577841; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=FxegNWCnpFWvIlhkHULtqrm7vjN3o62RaGltaGWsUSA=; b=sXK0ukSPvkGQZchsR2qnYUzZuO7d1N9TyrZU2Cxpv8FDRwszGBAJ8xgTfsnidN/HS8FiuQ BBB3RUF6+lmbuhDg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov Subject: [patch V5 27/39] x86/microcode: Handle "nosmt" correctly References: <20231017200758.877560658@linutronix.de> MIME-Version: 1.0 Date: Tue, 17 Oct 2023 23:24:00 +0200 (CEST) X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Tue, 17 Oct 2023 14:26:07 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780039533261901436 X-GMAIL-MSGID: 1780039533261901436 From: Thomas Gleixner On CPUs where microcode loading is not NMI-safe the SMT siblings which are parked in one of the play_dead() variants still react to NMIs. So if an NMI hits while the primary thread updates the microcode the resulting behaviour is undefined. The default play_dead() implementation on modern CPUs is using MWAIT which is not guaranteed to be safe against a microcode update which affects MWAIT. Take the cpus_booted_once_mask into account to detect this case and refuse to load late if the vendor specific driver does not advertise that late loading is NMI safe. AMD stated that this is safe, so mark the AMD driver accordingly. This requirement will be partially lifted in later changes. Signed-off-by: Thomas Gleixner --- arch/x86/Kconfig | 2 - arch/x86/kernel/cpu/microcode/amd.c | 9 +++-- arch/x86/kernel/cpu/microcode/core.c | 51 +++++++++++++++++++------------ arch/x86/kernel/cpu/microcode/internal.h | 13 +++---- 4 files changed, 44 insertions(+), 31 deletions(-) --- --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1320,7 +1320,7 @@ config MICROCODE_INITRD32 config MICROCODE_LATE_LOADING bool "Late microcode loading (DANGEROUS)" default n - depends on MICROCODE + depends on MICROCODE && SMP help Loading microcode late, when the system is up and executing instructions is a tricky business and should be avoided if possible. Just the sequence --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -917,10 +917,11 @@ static void microcode_fini_cpu_amd(int c } static struct microcode_ops microcode_amd_ops = { - .request_microcode_fw = request_microcode_amd, - .collect_cpu_info = collect_cpu_info_amd, - .apply_microcode = apply_microcode_amd, - .microcode_fini_cpu = microcode_fini_cpu_amd, + .request_microcode_fw = request_microcode_amd, + .collect_cpu_info = collect_cpu_info_amd, + .apply_microcode = apply_microcode_amd, + .microcode_fini_cpu = microcode_fini_cpu_amd, + .nmi_safe = true, }; struct microcode_ops * __init init_amd_microcode(void) --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -254,23 +254,6 @@ static struct platform_device *microcode */ #define SPINUNIT 100 /* 100 nsec */ -static int check_online_cpus(void) -{ - unsigned int cpu; - - /* - * Make sure all CPUs are online. It's fine for SMT to be disabled if - * all the primary threads are still online. - */ - for_each_present_cpu(cpu) { - if (topology_is_primary_thread(cpu) && !cpu_online(cpu)) { - pr_err("Not all CPUs online, aborting microcode update.\n"); - return -EINVAL; - } - } - - return 0; -} static atomic_t late_cpus_in; static atomic_t late_cpus_out; @@ -387,6 +370,35 @@ static int microcode_reload_late(void) return ret; } +/* + * Ensure that all required CPUs which are present and have been booted + * once are online. + * + * To pass this check, all primary threads must be online. + * + * If the microcode load is not safe against NMI then all SMT threads + * must be online as well because they still react to NMIs when they are + * soft-offlined and parked in one of the play_dead() variants. So if a + * NMI hits while the primary thread updates the microcode the resulting + * behaviour is undefined. The default play_dead() implementation on + * modern CPUs uses MWAIT, which is also not guaranteed to be safe + * against a microcode update which affects MWAIT. + */ +static bool ensure_cpus_are_online(void) +{ + unsigned int cpu; + + for_each_cpu_and(cpu, cpu_present_mask, &cpus_booted_once_mask) { + if (!cpu_online(cpu)) { + if (topology_is_primary_thread(cpu) || !microcode_ops->nmi_safe) { + pr_err("CPU %u not online\n", cpu); + return false; + } + } + } + return true; +} + static ssize_t reload_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t size) @@ -402,9 +414,10 @@ static ssize_t reload_store(struct devic cpus_read_lock(); - ret = check_online_cpus(); - if (ret) + if (!ensure_cpus_are_online()) { + ret = -EBUSY; goto put; + } tmp_ret = microcode_ops->request_microcode_fw(bsp, µcode_pdev->dev); if (tmp_ret != UCODE_NEW) --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -20,18 +20,17 @@ enum ucode_state { struct microcode_ops { enum ucode_state (*request_microcode_fw)(int cpu, struct device *dev); - void (*microcode_fini_cpu)(int cpu); /* - * The generic 'microcode_core' part guarantees that - * the callbacks below run on a target cpu when they - * are being called. + * The generic 'microcode_core' part guarantees that the callbacks + * below run on a target CPU when they are being called. * See also the "Synchronization" section in microcode_core.c. */ - enum ucode_state (*apply_microcode)(int cpu); - int (*collect_cpu_info)(int cpu, struct cpu_signature *csig); - void (*finalize_late_load)(int result); + enum ucode_state (*apply_microcode)(int cpu); + int (*collect_cpu_info)(int cpu, struct cpu_signature *csig); + void (*finalize_late_load)(int result); + unsigned int nmi_safe : 1; }; extern struct ucode_cpu_info ucode_cpu_info[]; From patchwork Tue Oct 17 21:24:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 154572 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp4407326vqb; Tue, 17 Oct 2023 14:27:03 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHwIG1Fw3Q7NymnK2J00Jwc6HLCpp+mDHGM+YqHWQGqchZqWTvyi6T7L0KYzTLPUQ+mugf+ X-Received: by 2002:a05:6a20:c182:b0:15a:2c0b:6c81 with SMTP id bg2-20020a056a20c18200b0015a2c0b6c81mr3767098pzb.3.1697578022978; Tue, 17 Oct 2023 14:27:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697578022; cv=none; d=google.com; s=arc-20160816; b=nQqrWKQDBVBQ2JlQ1ZkjFjn970UuDnBJlFI3rDNZOmP/DXre0dJlo82+6mRXsb892f oDX9rw0JhqiR63gmoW1P7Rv1Qvwtoka8Vc9BB/Ijh7VdKdrbCHaCrY5KNRYnoSayCcqT 38VA2HIxXPv5lrZ/3moKIBGE2Pl9sOFRjkHTlF1acDxqn2e1SkKBd+Hph64MdRlT+WJ+ cODJkgB67Cer5RDfDMj3EkkEBY9DqkI2/hgR8+BLJBSYCeaaaWaGUUJxUxMPSJquKa1l WRBiht+tVbfsw2dKh/GOXqxVkBD26CUFpkbl8kmUNxrw/+hJitBGLP1TNt1jerHtwLvb OG3A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=OcSOc/XQeQCSpMT+2YS3SG7DHGO6SXxO16x4Tum9Ox4=; fh=yP3AKHrl8EneyfHpNpX6YrVM96aNveB7lDxykgAWBds=; b=D1XR45M6KSvZdi83k11tVyu/MYzmeucT+ncWx2hk/Ma79ZHd2jVtaXHamsVcWk/RgV rexZjxv89cFQGgTHVjP9TjHYQQjPHp38TNVdCQo8P1joEY+RLPdIn5LRBzZDjq5ZWthd aoF3sOpvApCwvf6lL5be7a3k9JQuv1Q3+JSTw1E8AhWlE0dH9TUeR0q8MCXilj8Mogih 3bFxSILU1Z8TDDxslAL6Jfeve6RuB7C2UTXM2ni6oAODOvFHaKLU0zfIMqDpf+u/rhww SfStAeIZ1LL/huJkPMnISdQGRj6t1HDVDSHsiB0bajWCpzkgeSncZrRRhySvmpD08LUr 0a/Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="ZVO/K+jO"; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from fry.vger.email (fry.vger.email. [2620:137:e000::3:8]) by mx.google.com with ESMTPS id be3-20020a656e43000000b0056b024a4dd0si582512pgb.614.2023.10.17.14.27.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 14:27:02 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) client-ip=2620:137:e000::3:8; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b="ZVO/K+jO"; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:8 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by fry.vger.email (Postfix) with ESMTP id 9D57080FC14F; Tue, 17 Oct 2023 14:26:57 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at fry.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344282AbjJQVZu (ORCPT + 21 others); Tue, 17 Oct 2023 17:25:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33438 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344394AbjJQVZP (ORCPT ); Tue, 17 Oct 2023 17:25:15 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3179119A9 for ; Tue, 17 Oct 2023 14:24:04 -0700 (PDT) Message-ID: <20231017211723.521532582@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1697577842; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=OcSOc/XQeQCSpMT+2YS3SG7DHGO6SXxO16x4Tum9Ox4=; b=ZVO/K+jO6vRqem1k1hMH9SpDBFqQjuQrCMF2QpUZi4WM43scmzoClcnA3dSMgh8+7M83sa DZKOJQaunLrl8GDvzipwl5lEADch8TrjOhzM1KAOI8K04nVrtKBjuhIAz0OFbtooF/EpE6 txw9YrZwJJ0tuWo5Gbxn1zU4Vr7UVA75Dm/DNaQ0HanWMZ0TNs1AVIfyKzlhdTg+3QeoU3 TwSyKzAeCACzBCVwUKnvOFIAD3G9yp1E82zZj21TvVVGbljxSdM4y6/vktgnnyg2ReOIvx 2Q8JOzdFcakO/dvyBR2ID1fyQXupr/ba1ber3zsABiULANNRFvow6eDrnqvSbA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1697577842; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=OcSOc/XQeQCSpMT+2YS3SG7DHGO6SXxO16x4Tum9Ox4=; b=bv3tw+1v7efKmyC72N5dUlDQ8Sy0lfikRX6ofHUeQBFJC1KpQN+niGRw3vt3fohxlDllGb pM1qW+gEE3Ceo+Cw== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Nikolay Borisov Subject: [patch V5 28/39] x86/microcode: Clarify the late load logic References: <20231017200758.877560658@linutronix.de> MIME-Version: 1.0 Date: Tue, 17 Oct 2023 23:24:02 +0200 (CEST) X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on fry.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (fry.vger.email [0.0.0.0]); Tue, 17 Oct 2023 14:26:57 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780039573408635008 X-GMAIL-MSGID: 1780039573408635008 From: Thomas Gleixner reload_store() is way too complicated. Split the inner workings out and make the following enhancements: - Taint the kernel only when the microcode was actually updated. If. e.g. the rendezvous fails, then nothing happened and there is no reason for tainting. - Return useful error codes Signed-off-by: Thomas Gleixner Reviewed-by: Nikolay Borisov --- arch/x86/kernel/cpu/microcode/core.c | 41 ++++++++++++++++------------------- 1 file changed, 19 insertions(+), 22 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -362,11 +362,11 @@ static int microcode_reload_late(void) pr_info("Reload succeeded, microcode revision: 0x%x -> 0x%x\n", old, boot_cpu_data.microcode); microcode_check(&prev_info); + add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); } else { pr_info("Reload failed, current microcode revision: 0x%x\n", boot_cpu_data.microcode); } - return ret; } @@ -399,40 +399,37 @@ static bool ensure_cpus_are_online(void) return true; } +static int ucode_load_late_locked(void) +{ + if (!ensure_cpus_are_online()) + return -EBUSY; + + switch (microcode_ops->request_microcode_fw(0, µcode_pdev->dev)) { + case UCODE_NEW: + return microcode_reload_late(); + case UCODE_NFOUND: + return -ENOENT; + default: + return -EBADFD; + } +} + static ssize_t reload_store(struct device *dev, struct device_attribute *attr, const char *buf, size_t size) { - enum ucode_state tmp_ret = UCODE_OK; - int bsp = boot_cpu_data.cpu_index; unsigned long val; - ssize_t ret = 0; + ssize_t ret; ret = kstrtoul(buf, 0, &val); if (ret || val != 1) return -EINVAL; cpus_read_lock(); - - if (!ensure_cpus_are_online()) { - ret = -EBUSY; - goto put; - } - - tmp_ret = microcode_ops->request_microcode_fw(bsp, µcode_pdev->dev); - if (tmp_ret != UCODE_NEW) - goto put; - - ret = microcode_reload_late(); -put: + ret = ucode_load_late_locked(); cpus_read_unlock(); - if (ret == 0) - ret = size; - - add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); - - return ret; + return ret ? : size; } static DEVICE_ATTR_WO(reload); From patchwork Tue Oct 17 21:24:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 154571 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp4407263vqb; Tue, 17 Oct 2023 14:26:48 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGd081KP/Il3bcd8rSUu29Gs3w97gcQh25MuSE67lhD5pqU313Wv4kn9MJZDAd925QRoI6B X-Received: by 2002:a05:6a20:c182:b0:13d:fff1:c672 with SMTP id bg2-20020a056a20c18200b0013dfff1c672mr3710033pzb.4.1697578008501; Tue, 17 Oct 2023 14:26:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697578008; cv=none; d=google.com; s=arc-20160816; b=fb926N8MeYPdPxoU8TD3sldPm+uVHvJ0ramOm7oypbkVbA4sVi/g4VgqyxLmrMKJrN sVwnnr/8NJ9JVeOYCmkikHKVmluvvhFq3SRtqO6DW8Xa6paDqpe+auQ6au0eT9rjEmrl H6rhoi3U8EGOeNblUXFhUv9x2HQQcdezsaJEs/emgYcgfGRUjRNVdjUyl8ULVMqjxrec Ri6bJil4JnA5/XbMDBqCSRN6vNXKr0jWT3nvKitnFmWvkU0lLFmtq6EHdP7qr5/UK5Ps iYurxePOBN6RG5R6AErGP0AdMekKrVaJoFdy0hrp9/FFdcvDj1z/xllAtG3q0mgSoIjt nZHQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=yQPGGk4tDFoJNz7sLEo7/Vp9lMjMiS6Izxa7zaPjZi4=; fh=8iy+GLBXZdpcs/hIddJ7mbUapYjefwP9Gb111pAzFms=; b=iFcJiLMvsvdESvcTxxlXX22iugxO3q4NpI0izfQWBINHkmlzdRJZzYjSIPcmiMhBL5 ZVaNYsfeOZn0wuvMsa5cbWX4IeByfd7q4eJJ+69BKkf+KMBMtCGdS12/DWB8DERQNs7U nPTny0EVGNyWIH7NcrxpdVNc7t9uRdcGogjzhFLUWd0tRAwYdrM2bN8mBv7CNZvzogV3 8lvPL/mIgrGBC0xV6VhB8yDe2MoM7P9cjgs6jNktXOnFrXm/EboPVRE9kdu7Wvt+dknZ UepUy3Iao8ow3PPLAp2grsw7FQ5zhUwV/36Kl4fACFWgBUwkJf0B5ng8BlOk0cqmlucW VPEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=UasE8dKL; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from snail.vger.email (snail.vger.email. [23.128.96.37]) by mx.google.com with ESMTPS id w3-20020a17090a4f4300b0027cdee52324si9043747pjl.74.2023.10.17.14.26.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 14:26:48 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) client-ip=23.128.96.37; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=UasE8dKL; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.37 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id 2F2CA8092D82; Tue, 17 Oct 2023 14:25:57 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344190AbjJQVZo (ORCPT + 21 others); Tue, 17 Oct 2023 17:25:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33692 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344295AbjJQVZN (ORCPT ); Tue, 17 Oct 2023 17:25:13 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 61C8319B1 for ; Tue, 17 Oct 2023 14:24:05 -0700 (PDT) Message-ID: <20231017211723.577159633@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1697577844; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=yQPGGk4tDFoJNz7sLEo7/Vp9lMjMiS6Izxa7zaPjZi4=; b=UasE8dKLBf1mElOAA808GuU/+ud5e1n+/zVqNK7DW7JOPvxmKmXAZJ0gAnLWXfGhsz4rDa DhnoMtsAnegZOQevVsTo6MFL7Mf3AVzxR/TQIVeWLkz1INNxw1AU8i1lRgezQ7n0Z8mkhV rTNwVaPYfsTqZffX1VaJ3IG06UbYdKg1huivXZHYeW5RK0+PJnhSNnfBxdc/7wxWDN4q5M jDBW4ZHN28q1eZZQ9QLVh5d6EcdTo0l9ufvx5IdeJU1eYSxTlz70LRy13b8o32eZowP+yE fYM476F+AlVYQhDCdaoydQfFzVD2MjvbUqHY22rCD1A9+6673vOzR7QpbXnueg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1697577844; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=yQPGGk4tDFoJNz7sLEo7/Vp9lMjMiS6Izxa7zaPjZi4=; b=37yFBhEfzbUm/LF21lWv5/AomeqNAIF3trwQTaPVde3nfpIbVeV+l3wjBRS6CBD5i0oRBB O/0onR7n7hP/h1AQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov Subject: [patch V5 29/39] x86/microcode: Sanitize __wait_for_cpus() References: <20231017200758.877560658@linutronix.de> MIME-Version: 1.0 Date: Tue, 17 Oct 2023 23:24:03 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 17 Oct 2023 14:25:57 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780039557536404291 X-GMAIL-MSGID: 1780039557536404291 From: Thomas Gleixner The code is too complicated for no reason: - The return value is pointless as this is a strict boolean. - It's way simpler to count down from num_online_cpus() and check for zero. - The timeout argument is pointless as this is always one second. - Touching the NMI watchdog every 100ns does not make any sense, neither does checking every 100ns. This is really not a hotpath operation. Preload the atomic counter with the number of online CPUs and simplify the whole timeout logic. Delay for one microsecond and touch the NMI watchdog once per millisecond. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/core.c | 39 +++++++++++++++-------------------- 1 file changed, 17 insertions(+), 22 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -252,31 +252,26 @@ static struct platform_device *microcode * requirement can be relaxed in the future. Right now, this is conservative * and good. */ -#define SPINUNIT 100 /* 100 nsec */ +static atomic_t late_cpus_in, late_cpus_out; - -static atomic_t late_cpus_in; -static atomic_t late_cpus_out; - -static int __wait_for_cpus(atomic_t *t, long long timeout) +static bool wait_for_cpus(atomic_t *cnt) { - int all_cpus = num_online_cpus(); + unsigned int timeout; - atomic_inc(t); + WARN_ON_ONCE(atomic_dec_return(cnt) < 0); - while (atomic_read(t) < all_cpus) { - if (timeout < SPINUNIT) { - pr_err("Timeout while waiting for CPUs rendezvous, remaining: %d\n", - all_cpus - atomic_read(t)); - return 1; - } + for (timeout = 0; timeout < USEC_PER_SEC; timeout++) { + if (!atomic_read(cnt)) + return true; - ndelay(SPINUNIT); - timeout -= SPINUNIT; + udelay(1); - touch_nmi_watchdog(); + if (!(timeout % USEC_PER_MSEC)) + touch_nmi_watchdog(); } - return 0; + /* Prevent the late comers from making progress and let them time out */ + atomic_inc(cnt); + return false; } /* @@ -294,7 +289,7 @@ static int __reload_late(void *info) * Wait for all CPUs to arrive. A load will not be attempted unless all * CPUs show up. * */ - if (__wait_for_cpus(&late_cpus_in, NSEC_PER_SEC)) + if (!wait_for_cpus(&late_cpus_in)) return -1; /* @@ -317,7 +312,7 @@ static int __reload_late(void *info) } wait_for_siblings: - if (__wait_for_cpus(&late_cpus_out, NSEC_PER_SEC)) + if (!wait_for_cpus(&late_cpus_out)) panic("Timeout during microcode update!\n"); /* @@ -344,8 +339,8 @@ static int microcode_reload_late(void) pr_err("Attempting late microcode loading - it is dangerous and taints the kernel.\n"); pr_err("You should switch to early loading, if possible.\n"); - atomic_set(&late_cpus_in, 0); - atomic_set(&late_cpus_out, 0); + atomic_set(&late_cpus_in, num_online_cpus()); + atomic_set(&late_cpus_out, num_online_cpus()); /* * Take a snapshot before the microcode update in order to compare and From patchwork Tue Oct 17 21:24:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 154566 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp4407192vqb; Tue, 17 Oct 2023 14:26:36 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFQH2w7lCobNNT4IBGKDUmYQV+BuQywfvaOkIxLSBlzqO2mEB45fwlbmpeGgibla9BEXKGO X-Received: by 2002:a17:90b:4c8b:b0:27d:2762:2728 with SMTP id my11-20020a17090b4c8b00b0027d27622728mr3733683pjb.0.1697577996315; Tue, 17 Oct 2023 14:26:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697577996; cv=none; d=google.com; s=arc-20160816; b=vldLJBQqzt1I3me9eftd8tpPHlov5DRJzapkf3WfJxuftrOGmvQGrhvwd/9tFFARGb RStB8juTaxdU+TaOK7ZWsnqFB+1TAJALgwkGLMxrZ0rofM8cTWUSYF3AJ/3vTci8nNM9 GOAOwicwjSBFaOAs0HAQYYXZUeXYH5i1fPHZx5BmXAFvc70UeLSqtRKqTKiQLPIXJklg x+VPqThX/PzONrgrqD8ewAbw7Buj2Zh1vmcndTWPZsY48BQ+JyBbOrlPXmhZB9TXSt9Z s3V5kWL8TFDgxyNlS+Rl7v+uKc/BKIcMIaMqHx8v/c01LO2QdLp5AWvbJ40HNrDfuHM6 uf3A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=QjcerSYtQUE8Lx8f8JosHi9f4nt1WbYnOT38iwWvnnc=; fh=8iy+GLBXZdpcs/hIddJ7mbUapYjefwP9Gb111pAzFms=; b=oVgYge9zeeROVNkgx2jlv1Kh0ODcgKUSiAMdNgRw0lKG8+JgDmbqy2lqsihc/XOqev x1620Nawei0uXVUEnf618XpntdTHJqUecJjWZonyuTWw3Mzw9TKTmVXe36qwvf21S0Oo tLjOgCmk4Bw04RfCooL1LaA94nmY/l8nnN/Vm9P6/WpIs/doVVkcqif7VXstIz+6Zb/q 5LRm0xLdnlMaRe8cTTD5QzbKdLb6TXMPNKl6l8zjcD1H1c833DE36jM2EyxD9MjFuoGc TUVbecwNWnThjVBxjs8e0nSY+5n0EkROXk3rdHgpl77rVC3h5HxB/LE7+iBYov8mmSkp Fz1A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=p1msP50A; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from agentk.vger.email (agentk.vger.email. [2620:137:e000::3:2]) by mx.google.com with ESMTPS id bo13-20020a17090b090d00b0026c198d8182si9514428pjb.105.2023.10.17.14.26.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 14:26:36 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) client-ip=2620:137:e000::3:2; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=p1msP50A; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:2 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by agentk.vger.email (Postfix) with ESMTP id 6CFF480947FD; Tue, 17 Oct 2023 14:26:09 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at agentk.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344384AbjJQVZy (ORCPT + 21 others); Tue, 17 Oct 2023 17:25:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33736 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344398AbjJQVZQ (ORCPT ); Tue, 17 Oct 2023 17:25:16 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 55FD019BA for ; Tue, 17 Oct 2023 14:24:06 -0700 (PDT) Message-ID: <20231017211723.632681010@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1697577845; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=QjcerSYtQUE8Lx8f8JosHi9f4nt1WbYnOT38iwWvnnc=; b=p1msP50Atm24FvpHP62M2qSOfw2vX1H24wsJIUbg2sA00W/wxWBoXZ4yyATt6XAp/Xb0V5 kmrRcWDBLxbeijgu0X1QwLHt2Tfe3KNR5ag4q0BlwSJ1wIEuaJHJ9w8aeRiyUDP7PmdCDJ l250IeosqCJJH4mPVh5Bg6n+gftrcxbQHLG5cU1f4A5Do9pCitrkH4LRJMjXIULlPJ8KA9 SZQa+CzC9eBXmk30m3lZQmI21PfUnsn3SCkMnT188kImbThkjmQMJogVWpM0ujKNFiZn2g +fSJRBinKgujSGLTLN8h8r/8vpVSlpJ8a7NOK+ZFlWpxmr2Dvy77XNx7kxS7pQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1697577845; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=QjcerSYtQUE8Lx8f8JosHi9f4nt1WbYnOT38iwWvnnc=; b=p/EWCrJO7nlfRm2zqjZe6c91DGTSlJ4H1+3eg0YdYho5ReBb99TPeyLd/i09Q9bxGEVqEx fcHC/VNHefZyGpCQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov Subject: [patch V5 30/39] x86/microcode: Add per CPU result state References: <20231017200758.877560658@linutronix.de> MIME-Version: 1.0 Date: Tue, 17 Oct 2023 23:24:05 +0200 (CEST) X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on agentk.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (agentk.vger.email [0.0.0.0]); Tue, 17 Oct 2023 14:26:09 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780039545528956553 X-GMAIL-MSGID: 1780039545528956553 From: Thomas Gleixner The microcode rendezvous is purely acting on global state, which does not allow to analyze fails in a coherent way. Introduce per CPU state where the results are written into, which allows to analyze the return codes of the individual CPUs. Initialize the state when walking the cpu_present_mask in the online check to avoid another for_each_cpu() loop. Enhance the result print out with that. The structure is intentionally named ucode_ctrl as it will gain control fields in subsequent changes. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/core.c | 112 ++++++++++++++++++------------- arch/x86/kernel/cpu/microcode/internal.h | 1 2 files changed, 67 insertions(+), 46 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -252,6 +252,11 @@ static struct platform_device *microcode * requirement can be relaxed in the future. Right now, this is conservative * and good. */ +struct microcode_ctrl { + enum ucode_state result; +}; + +static DEFINE_PER_CPU(struct microcode_ctrl, ucode_ctrl); static atomic_t late_cpus_in, late_cpus_out; static bool wait_for_cpus(atomic_t *cnt) @@ -274,23 +279,19 @@ static bool wait_for_cpus(atomic_t *cnt) return false; } -/* - * Returns: - * < 0 - on error - * 0 - success (no update done or microcode was updated) - */ -static int __reload_late(void *info) +static int load_cpus_stopped(void *unused) { int cpu = smp_processor_id(); - enum ucode_state err; - int ret = 0; + enum ucode_state ret; /* * Wait for all CPUs to arrive. A load will not be attempted unless all * CPUs show up. * */ - if (!wait_for_cpus(&late_cpus_in)) - return -1; + if (!wait_for_cpus(&late_cpus_in)) { + this_cpu_write(ucode_ctrl.result, UCODE_TIMEOUT); + return 0; + } /* * On an SMT system, it suffices to load the microcode on one sibling of @@ -299,17 +300,11 @@ static int __reload_late(void *info) * loading attempts happen on multiple threads of an SMT core. See * below. */ - if (cpumask_first(topology_sibling_cpumask(cpu)) == cpu) - err = microcode_ops->apply_microcode(cpu); - else + if (cpumask_first(topology_sibling_cpumask(cpu)) != cpu) goto wait_for_siblings; - if (err >= UCODE_NFOUND) { - if (err == UCODE_ERROR) { - pr_warn("Error reloading microcode on CPU %d\n", cpu); - ret = -1; - } - } + ret = microcode_ops->apply_microcode(cpu); + this_cpu_write(ucode_ctrl.result, ret); wait_for_siblings: if (!wait_for_cpus(&late_cpus_out)) @@ -321,19 +316,18 @@ static int __reload_late(void *info) * per-cpu cpuinfo can be updated with right microcode * revision. */ - if (cpumask_first(topology_sibling_cpumask(cpu)) != cpu) - err = microcode_ops->apply_microcode(cpu); + if (cpumask_first(topology_sibling_cpumask(cpu)) == cpu) + return 0; - return ret; + ret = microcode_ops->apply_microcode(cpu); + this_cpu_write(ucode_ctrl.result, ret); + return 0; } -/* - * Reload microcode late on all CPUs. Wait for a sec until they - * all gather together. - */ -static int microcode_reload_late(void) +static int load_late_stop_cpus(void) { - int old = boot_cpu_data.microcode, ret; + unsigned int cpu, updated = 0, failed = 0, timedout = 0, siblings = 0; + int old_rev = boot_cpu_data.microcode; struct cpuinfo_x86 prev_info; pr_err("Attempting late microcode loading - it is dangerous and taints the kernel.\n"); @@ -348,26 +342,47 @@ static int microcode_reload_late(void) */ store_cpu_caps(&prev_info); - ret = stop_machine_cpuslocked(__reload_late, NULL, cpu_online_mask); + stop_machine_cpuslocked(load_cpus_stopped, NULL, cpu_online_mask); + + /* Analyze the results */ + for_each_cpu_and(cpu, cpu_present_mask, &cpus_booted_once_mask) { + switch (per_cpu(ucode_ctrl.result, cpu)) { + case UCODE_UPDATED: updated++; break; + case UCODE_TIMEOUT: timedout++; break; + case UCODE_OK: siblings++; break; + default: failed++; break; + } + } if (microcode_ops->finalize_late_load) - microcode_ops->finalize_late_load(ret); + microcode_ops->finalize_late_load(!updated); - if (!ret) { - pr_info("Reload succeeded, microcode revision: 0x%x -> 0x%x\n", - old, boot_cpu_data.microcode); - microcode_check(&prev_info); - add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); - } else { - pr_info("Reload failed, current microcode revision: 0x%x\n", - boot_cpu_data.microcode); + if (!updated) { + /* Nothing changed. */ + if (!failed && !timedout) + return 0; + pr_err("update failed: %u CPUs failed %u CPUs timed out\n", + failed, timedout); + return -EIO; } - return ret; + + add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); + pr_info("load: updated on %u primary CPUs with %u siblings\n", updated, siblings); + if (failed || timedout) { + pr_err("load incomplete. %u CPUs timed out or failed\n", + num_online_cpus() - (updated + siblings)); + } + pr_info("revision: 0x%x -> 0x%x\n", old_rev, boot_cpu_data.microcode); + microcode_check(&prev_info); + + return updated + siblings == num_online_cpus() ? 0 : -EIO; } /* - * Ensure that all required CPUs which are present and have been booted - * once are online. + * This function does two things: + * + * 1) Ensure that all required CPUs which are present and have been booted + * once are online. * * To pass this check, all primary threads must be online. * @@ -378,9 +393,12 @@ static int microcode_reload_late(void) * behaviour is undefined. The default play_dead() implementation on * modern CPUs uses MWAIT, which is also not guaranteed to be safe * against a microcode update which affects MWAIT. + * + * 2) Initialize the per CPU control structure */ -static bool ensure_cpus_are_online(void) +static bool setup_cpus(void) { + struct microcode_ctrl ctrl = { .result = -1, }; unsigned int cpu; for_each_cpu_and(cpu, cpu_present_mask, &cpus_booted_once_mask) { @@ -390,18 +408,20 @@ static bool ensure_cpus_are_online(void) return false; } } + /* Initialize the per CPU state */ + per_cpu(ucode_ctrl, cpu) = ctrl; } return true; } -static int ucode_load_late_locked(void) +static int load_late_locked(void) { - if (!ensure_cpus_are_online()) + if (!setup_cpus()) return -EBUSY; switch (microcode_ops->request_microcode_fw(0, µcode_pdev->dev)) { case UCODE_NEW: - return microcode_reload_late(); + return load_late_stop_cpus(); case UCODE_NFOUND: return -ENOENT; default: @@ -421,7 +441,7 @@ static ssize_t reload_store(struct devic return -EINVAL; cpus_read_lock(); - ret = ucode_load_late_locked(); + ret = load_late_locked(); cpus_read_unlock(); return ret ? : size; --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -16,6 +16,7 @@ enum ucode_state { UCODE_UPDATED, UCODE_NFOUND, UCODE_ERROR, + UCODE_TIMEOUT, }; struct microcode_ops { From patchwork Tue Oct 17 21:24:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 154570 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp4407259vqb; Tue, 17 Oct 2023 14:26:48 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHsxd18ODw3JaDKkR+KO5FUsncUaog0VE/o6tPlo7q1HxBgoixYrxkMbcypnRKj7LlSLdZs X-Received: by 2002:a05:6a00:428e:b0:692:b3d4:e6c3 with SMTP id bx14-20020a056a00428e00b00692b3d4e6c3mr3590351pfb.0.1697578007851; Tue, 17 Oct 2023 14:26:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697578007; cv=none; d=google.com; s=arc-20160816; b=LjdWZuFVvQOA82CofO+0T8DZwTL6Hcae9atZ1OSPsK+3J8SWYIOK3Du5R+N1+tXRxw tj56AHInckV4g/tC9pfREfAP27HZW62MF7+4LD/fWhRF3RdoKX3Vdbmhk5FS7fFtD2X6 3YPd0XyOWERUvZOoaHxSzZBp1UPO2Gb7WjxJ9phlZV/Fzl1TeOEtdYj6qhgn60Jewpfo 0tiIXRxKRvvVq1le7+yQ+D80aLpSh0HPw3WQOElkRqSU5J7w7X2xYKPBJ/txPszJZ5K1 AwJltoDmb6RTFWJ61L0dbDXNdvqNqUlopjiJKcoSuLiDZxXE2XBPv5cOvxyucSnSAsCK ik7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=L9m8W4bdzDuhhTI4cJap7V+acmOzj+yrZ+giYWgienc=; fh=8iy+GLBXZdpcs/hIddJ7mbUapYjefwP9Gb111pAzFms=; b=KQFf68jv7NqjIokNvaFELKv3i0GDpKH1fGK5rNSkIjhVX+xEruPmq48RztwFOKcQCd yLGaJBbO0sZujE/5zUNvejhgtJjbPKtWQXUzQ20zw1B7YvXOKFYR9QBibkIie2N37Zii Ss7+0DxGvBgzDm0pSwuIM+T6MfUojUK/l7RTHXgzyn/lDET1XzH8Wyxxr2uBy5LjPa5n lcIMaZxLosi9njyy0UaVmBaClcsnpBKdvB8XH1AM1P8yM9UWZVvcjj3UpmpM0mQRg2/1 X5ZU0Xkrptj+nabHB1D0TrHm/cgAXV3CSMm0zmUs0JwNxlh2+iicRgLeM8WRxaXbTbO9 14aw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=eMFbUfbn; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=Hir2o4x4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from lipwig.vger.email (lipwig.vger.email. [2620:137:e000::3:3]) by mx.google.com with ESMTPS id fd42-20020a056a002eaa00b006b62dbc1a62si2559487pfb.117.2023.10.17.14.26.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 14:26:47 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) client-ip=2620:137:e000::3:3; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=eMFbUfbn; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=Hir2o4x4; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:3 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id 9A1DB810EC1F; Tue, 17 Oct 2023 14:26:45 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344402AbjJQV0e (ORCPT + 21 others); Tue, 17 Oct 2023 17:26:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33780 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344321AbjJQVZw (ORCPT ); Tue, 17 Oct 2023 17:25:52 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 595E4131 for ; Tue, 17 Oct 2023 14:24:08 -0700 (PDT) Message-ID: <20231017211723.688807375@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1697577846; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=L9m8W4bdzDuhhTI4cJap7V+acmOzj+yrZ+giYWgienc=; b=eMFbUfbn//zHbW26T91mEuzFJyURdXE/G8WGZCvGYbFkFo+qqd593s20T6Snrj6q3AycWZ B7nZvUFiWljt6c3NFH4eQ1O00dGHhGGiGYouDw1AQJOO5oFvnvRNHmq4QFo1nN1uRLsxFM 8P9BohzMx7nqp2DhXCVBobMnJdYUy7Zw+vuns9KY1GN1WsvfId31285yuFQHwfcyQWbApb NYpWKdsbJl3qELKhQvtMpR4LlVqdp4ZlbS8jiuwjUuMr77uaNAj7uO61iwWbwTBZGGi2p/ DTI9Quu/hd32N0oqqCEo6rLZzft/t84zWaFdxhBkAfCAQY4xHmK+6Luinjqe9g== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1697577846; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=L9m8W4bdzDuhhTI4cJap7V+acmOzj+yrZ+giYWgienc=; b=Hir2o4x4E6IN7gYByVkLrAKiDLDgzKdmWcbf61iXoqbeDyulOsd/AmdNOQlSK0fyDd2Ryn s04lVl9+idPIAmBA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov Subject: [patch V5 31/39] x86/microcode: Add per CPU control field References: <20231017200758.877560658@linutronix.de> MIME-Version: 1.0 Date: Tue, 17 Oct 2023 23:24:06 +0200 (CEST) X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Tue, 17 Oct 2023 14:26:45 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780039557008279710 X-GMAIL-MSGID: 1780039557008279710 From: Thomas Gleixner Add a per CPU control field to ucode_ctrl and define constants for it which are going to be used to control the loading state machine. In theory this could be a global control field, but a global control does not cover the following case: 15 primary CPUs load microcode successfully 1 primary CPU fails and returns with an error code With global control the sibling of the failed CPU would either try again or the whole operation would be aborted with the consequence that the 15 siblings do not invoke the apply path and end up with inconsistent software state. The result in dmesg would be inconsistent too. There are two additional fields added and initialized: ctrl_cpu and secondaries. ctrl_cpu is the CPU number of the primary thread for now, but with the upcoming uniform loading at package or system scope this will be one CPU per package or just one CPU. Secondaries hands the control CPU a CPU mask which will be required to release the secondary CPUs out of the wait loop. Preparatory change for implementing a properly split control flow for primary and secondary CPUs. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/core.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -252,8 +252,19 @@ static struct platform_device *microcode * requirement can be relaxed in the future. Right now, this is conservative * and good. */ +enum sibling_ctrl { + /* Spinwait with timeout */ + SCTRL_WAIT, + /* Invoke the microcode_apply() callback */ + SCTRL_APPLY, + /* Proceed without invoking the microcode_apply() callback */ + SCTRL_DONE, +}; + struct microcode_ctrl { + enum sibling_ctrl ctrl; enum ucode_state result; + unsigned int ctrl_cpu; }; static DEFINE_PER_CPU(struct microcode_ctrl, ucode_ctrl); @@ -398,7 +409,7 @@ static int load_late_stop_cpus(void) */ static bool setup_cpus(void) { - struct microcode_ctrl ctrl = { .result = -1, }; + struct microcode_ctrl ctrl = { .ctrl = SCTRL_WAIT, .result = -1, }; unsigned int cpu; for_each_cpu_and(cpu, cpu_present_mask, &cpus_booted_once_mask) { @@ -408,7 +419,12 @@ static bool setup_cpus(void) return false; } } - /* Initialize the per CPU state */ + + /* + * Initialize the per CPU state. This is core scope for now, + * but prepared to take package or system scope into account. + */ + ctrl.ctrl_cpu = cpumask_first(topology_sibling_cpumask(cpu)); per_cpu(ucode_ctrl, cpu) = ctrl; } return true; From patchwork Tue Oct 17 21:24:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 154563 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp4407157vqb; Tue, 17 Oct 2023 14:26:31 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEDzJ+NhodsHOxFsKNt+49mlLAmpf3l7KQ9UfAXzPK2CxHDgIxLeDSY3zz4PFIhR36RZqgI X-Received: by 2002:a05:6870:96a3:b0:1e9:8a7e:5893 with SMTP id o35-20020a05687096a300b001e98a7e5893mr4385644oaq.5.1697577991351; Tue, 17 Oct 2023 14:26:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697577991; cv=none; d=google.com; s=arc-20160816; b=UTYwZMYkwssHrCgPFHblCzg0JmKqFOHS6qEm82hGHTZqMZcJUJoBLPTGxlw32hutMk VOezrvUWUhmHHlFaO4w16qcxL+zDUrInCThF37mkOt7WHBSdAczbC89lOo9T1Oy6C+lC QV2oFSgdD4nvM1hVHOR719AVmFkYH7th0JNPjqdpSKlkFEPfpiNUaFEsFECH5bed+sGQ KPjcEhDIBQjhpwdlgG9S12oB+cPm+XAK+LhYtkxlYkK0/NvEnX4MmC8jnCSZ2Ewu9C6R wIIdYkv79nnWAMVQcRFWFU0gAV1HoHl2bRRGC3O8+IFZxsFBNrJ1maWnmrxcgEK+nYmm y0OQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=DYpFBBpPPIpr7s0xN04Gww/sMhU6DEDh0WPjEvKx6sw=; fh=8iy+GLBXZdpcs/hIddJ7mbUapYjefwP9Gb111pAzFms=; b=ZVjX4rs6B9pMNlRj1UwG1eKmhR5u/mIcsB0k8seL4AUbjmoBT0MlQ0waI6xO4ybfQz DrTHgRO0UPBonGqKgMR1cOdhUBxqIoMSybj/n38goobjDY+4mzc1DLuCSHAQvAWuTTyL sxxyoJkmXo3D3V2q5A37hwTXuET+Bb0HItXZKSIUO5VBSJHxDQnNdjUGzdEk3AXJzB+Y EBhYVbin94HzXh/te6pLbiFxJ+qRTfyqmHUHARc7+O8lvps6V0aY0JBH7dvZhqCp60z5 2aTNK0olhKHys7fW5t+dlUgiPkNWGR3wQBYt9BtrChTwvoYXqjnDh/4YXHyWfxD5PNAa QT0w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=srBlugJB; dkim=neutral (no key) header.i=@linutronix.de header.b=Nno5QhnD; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from morse.vger.email (morse.vger.email. [2620:137:e000::3:1]) by mx.google.com with ESMTPS id q9-20020a655249000000b0055be9543340si605408pgp.872.2023.10.17.14.26.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 14:26:31 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) client-ip=2620:137:e000::3:1; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=srBlugJB; dkim=neutral (no key) header.i=@linutronix.de header.b=Nno5QhnD; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by morse.vger.email (Postfix) with ESMTP id F0F36801B398; Tue, 17 Oct 2023 14:26:28 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at morse.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344427AbjJQVZ6 (ORCPT + 21 others); Tue, 17 Oct 2023 17:25:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33780 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344301AbjJQVZQ (ORCPT ); Tue, 17 Oct 2023 17:25:16 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B148C1BC3 for ; Tue, 17 Oct 2023 14:24:09 -0700 (PDT) Message-ID: <20231017211723.745013003@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1697577848; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=DYpFBBpPPIpr7s0xN04Gww/sMhU6DEDh0WPjEvKx6sw=; b=srBlugJBUc1azwPbSq0/W6kuIr9PmndhxDRKDved5N7e33L8Mkfo56yfaJsLaYAFNmGzRw Z4MSzXz1p8J4OLE7Lds19+dd4Zy53ilyRZDPbCATPbGReC1nzPkmU+VbSl11pSNcUHClFL 8bFiPnCbPhpC+GK19bu+zC4I8BHXxGsupc/PwZnX5DICAWzjAwpsM7ULAB1wqh+ErNld9Z z1+Obib6eeDs0voDMXgMm+G42fOuvHZfGjzKztQ5FGYe/oP5Xc9imDu9l19ix6LFJt7N+E j+FUqeXaWILB5Vio5QmkM1ZsDZBKFuLP/jaMtLeRM+7G/BS0+1ZzdP57ajn1iQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1697577848; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=DYpFBBpPPIpr7s0xN04Gww/sMhU6DEDh0WPjEvKx6sw=; b=Nno5QhnDLK1ZJvtSrcNZvcc45uCBvhR1yQThYT9pSyNyGR9fgHURI+Y5otZ3/RNPPFJtdt oJKtjNK8TArNHZBA== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov Subject: [patch V5 32/39] x86/microcode: Provide new control functions References: <20231017200758.877560658@linutronix.de> MIME-Version: 1.0 Date: Tue, 17 Oct 2023 23:24:07 +0200 (CEST) X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Tue, 17 Oct 2023 14:26:29 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780039540192926765 X-GMAIL-MSGID: 1780039540192926765 From: Thomas Gleixner The current all in one code is unreadable and really not suited for adding future features like uniform loading with package or system scope. Provide a set of new control functions which split the handling of the primary and secondary CPUs. These will replace the current rendezvous all in one function in the next step. This is intentionally a separate change because diff makes an complete unreadable mess otherwise. So the flow separates the primary and the secondary CPUs into their own functions which use the control field in the per CPU ucode_ctrl struct. primary() secondary() wait_for_all() wait_for_all() apply_ucode() wait_for_release() release() apply_ucode() Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/core.c | 84 +++++++++++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) --- --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -290,6 +290,90 @@ static bool wait_for_cpus(atomic_t *cnt) return false; } +static bool wait_for_ctrl(void) +{ + unsigned int timeout; + + for (timeout = 0; timeout < USEC_PER_SEC; timeout++) { + if (this_cpu_read(ucode_ctrl.ctrl) != SCTRL_WAIT) + return true; + udelay(1); + if (!(timeout % 1000)) + touch_nmi_watchdog(); + } + return false; +} + +static __maybe_unused void load_secondary(unsigned int cpu) +{ + unsigned int ctrl_cpu = this_cpu_read(ucode_ctrl.ctrl_cpu); + enum ucode_state ret; + + /* Initial rendezvous to ensure that all CPUs have arrived */ + if (!wait_for_cpus(&late_cpus_in)) { + pr_err_once("load: %d CPUs timed out\n", atomic_read(&late_cpus_in) - 1); + this_cpu_write(ucode_ctrl.result, UCODE_TIMEOUT); + return; + } + + /* + * Wait for primary threads to complete. If one of them hangs due + * to the update, there is no way out. This is non-recoverable + * because the CPU might hold locks or resources and confuse the + * scheduler, watchdogs etc. There is no way to safely evacuate the + * machine. + */ + if (!wait_for_ctrl()) + panic("Microcode load: Primary CPU %d timed out\n", ctrl_cpu); + + /* + * If the primary succeeded then invoke the apply() callback, + * otherwise copy the state from the primary thread. + */ + if (this_cpu_read(ucode_ctrl.ctrl) == SCTRL_APPLY) + ret = microcode_ops->apply_microcode(cpu); + else + ret = per_cpu(ucode_ctrl.result, ctrl_cpu); + + this_cpu_write(ucode_ctrl.result, ret); + this_cpu_write(ucode_ctrl.ctrl, SCTRL_DONE); +} + +static __maybe_unused void load_primary(unsigned int cpu) +{ + struct cpumask *secondaries = topology_sibling_cpumask(cpu); + enum sibling_ctrl ctrl; + enum ucode_state ret; + unsigned int sibling; + + /* Initial rendezvous to ensure that all CPUs have arrived */ + if (!wait_for_cpus(&late_cpus_in)) { + this_cpu_write(ucode_ctrl.result, UCODE_TIMEOUT); + pr_err_once("load: %d CPUs timed out\n", atomic_read(&late_cpus_in) - 1); + return; + } + + ret = microcode_ops->apply_microcode(cpu); + this_cpu_write(ucode_ctrl.result, ret); + this_cpu_write(ucode_ctrl.ctrl, SCTRL_DONE); + + /* + * If the update was successful, let the siblings run the apply() + * callback. If not, tell them it's done. This also covers the + * case where the CPU has uniform loading at package or system + * scope implemented but does not advertise it. + */ + if (ret == UCODE_UPDATED || ret == UCODE_OK) + ctrl = SCTRL_APPLY; + else + ctrl = SCTRL_DONE; + + for_each_cpu(sibling, secondaries) { + if (sibling != cpu) + per_cpu(ucode_ctrl.ctrl, sibling) = ctrl; + } +} + static int load_cpus_stopped(void *unused) { int cpu = smp_processor_id(); From patchwork Tue Oct 17 21:24:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 154567 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp4407227vqb; Tue, 17 Oct 2023 14:26:42 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFIqexuNVCWcjAk/P12Vdsl8786uLwJagd6LakyIMc9S+IlqA+YswzM19HzbB17BKap1e6z X-Received: by 2002:a05:6358:514e:b0:166:d909:74e with SMTP id 14-20020a056358514e00b00166d909074emr3333594rwj.0.1697578002056; Tue, 17 Oct 2023 14:26:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697578002; cv=none; d=google.com; s=arc-20160816; b=PnMx3UxaRoNSId7TWEblC5bZ+pY0jt9+ceg6LyIH686R2p/UlPpa0fKApuqc9mRmFD 3YF+Etf1ENqxmIucwZw3ZVNwi3EGm7GIGZkNWQ/41/AZ2sC33E/ewfiKEhspWmX7PcmO tbG0fY0ivsRCLvVOx13qC+nsEke7ALk/w/UT+mLqsUfC623dl80XAip4fBAoXsxkuzt4 cmNqHbV1dSwWywMbUize4dzBLdc0+vS9/s0/STWSSP5onCEoEARWPlM1vl7uu4ZMzgfG jUaNFxiDjWLnqDyQnNpGTpfwBVj/HZZREHgOvjegOwIjJgXs+0XcyoSWhNHQ+ZcKpkuE Ffag== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=1dgZfFCQy1fCsT2A7+aTGFWxyq9HxCOqu34JaoQN2i8=; fh=8iy+GLBXZdpcs/hIddJ7mbUapYjefwP9Gb111pAzFms=; b=oVKkHBM9U+I1Uw5uYE+NVTUXBPe1AIx4aI8T8FarNg4XA3tc+i5copKDXHF3MQAxhT 0N8nEA/QVbUgCj/gJW2hsv8rS6dQ3SEctqOWdQbVafjyiUk5+h2CB9nblJVlbaihWIpX YNyH7+tJisWTKCrThnVd9x/F6hZPycCAqPqUcMXEjiHgmPQil9Pn89jgYmgimvKeS5AM zHkU8c9wD1v1e9ILgv0pZoD/J8JnINctWiN2F+Pa5+O1SyA6XEcbX5f5nWIAUmHm+MMP nr75xbMIqj+D3xg0HqhZKIcG6tmciNKtFW8gMUS9wT8553opvG7ZSnE9lKJ9QJ6ewUAw RbOg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=F0fcouqt; dkim=neutral (no key) header.i=@linutronix.de header.b=+fAUrz66; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from lipwig.vger.email (lipwig.vger.email. [23.128.96.33]) by mx.google.com with ESMTPS id x31-20020a056a00189f00b006b728259b67si2522314pfh.177.2023.10.17.14.26.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 14:26:42 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) client-ip=23.128.96.33; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=F0fcouqt; dkim=neutral (no key) header.i=@linutronix.de header.b=+fAUrz66; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.33 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by lipwig.vger.email (Postfix) with ESMTP id 0ECD9807BEC4; Tue, 17 Oct 2023 14:26:39 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at lipwig.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344021AbjJQV0F (ORCPT + 21 others); Tue, 17 Oct 2023 17:26:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33488 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344341AbjJQVZT (ORCPT ); Tue, 17 Oct 2023 17:25:19 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 22375125 for ; Tue, 17 Oct 2023 14:24:11 -0700 (PDT) Message-ID: <20231017211723.801060436@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1697577849; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=1dgZfFCQy1fCsT2A7+aTGFWxyq9HxCOqu34JaoQN2i8=; b=F0fcouqtvhw5TK5MccA+4303A21LGeZiPkIw3v/6NzCKhetM+MygQaku+nsX5FOLijB1xO nSzqXI6d7F3sAsSOhYzpqA2uCJvRucTG/udlG03+r6QnBWtW9cGu+An9f4Eey+Uhs2fC1x NvSw+b9DL2fKADWJ0fUSG8IQaZrSET76hTx07HrWJxE8LO5vC1jzqPwx+AF82/IIoWWQGG jO1eIidfTP/R92zoVh6dhDrdNj1RoC9qxyyYURXzv+7xOJn2QEEp+/frQJVZQmqdH7ws0Y D4Xu2EyZCRksXY/Z3+36NgucrBYSS5yOvikcGZ3AONeV7+rVQn5u+JtR4Ak8cw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1697577849; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=1dgZfFCQy1fCsT2A7+aTGFWxyq9HxCOqu34JaoQN2i8=; b=+fAUrz66BW4vQLt7ylctRn6mSAkuVtze16T6+r+Ju1+GpTLsv3CO26ykrUwXgan/88S6AM XDQ/wGDAxsZncpAg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov Subject: [patch V5 33/39] x86/microcode: Replace the all-in-one rendevous handler References: <20231017200758.877560658@linutronix.de> MIME-Version: 1.0 Date: Tue, 17 Oct 2023 23:24:09 +0200 (CEST) X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lipwig.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (lipwig.vger.email [0.0.0.0]); Tue, 17 Oct 2023 14:26:40 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780039551274130600 X-GMAIL-MSGID: 1780039551274130600 From: Thomas Gleixner with a new handler which just separates the control flow of primary and secondary CPUs. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/core.c | 51 ++++++----------------------------- 1 file changed, 9 insertions(+), 42 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -268,7 +268,7 @@ struct microcode_ctrl { }; static DEFINE_PER_CPU(struct microcode_ctrl, ucode_ctrl); -static atomic_t late_cpus_in, late_cpus_out; +static atomic_t late_cpus_in; static bool wait_for_cpus(atomic_t *cnt) { @@ -304,7 +304,7 @@ static bool wait_for_ctrl(void) return false; } -static __maybe_unused void load_secondary(unsigned int cpu) +static void load_secondary(unsigned int cpu) { unsigned int ctrl_cpu = this_cpu_read(ucode_ctrl.ctrl_cpu); enum ucode_state ret; @@ -339,7 +339,7 @@ static __maybe_unused void load_secondar this_cpu_write(ucode_ctrl.ctrl, SCTRL_DONE); } -static __maybe_unused void load_primary(unsigned int cpu) +static void load_primary(unsigned int cpu) { struct cpumask *secondaries = topology_sibling_cpumask(cpu); enum sibling_ctrl ctrl; @@ -376,46 +376,14 @@ static __maybe_unused void load_primary( static int load_cpus_stopped(void *unused) { - int cpu = smp_processor_id(); - enum ucode_state ret; - - /* - * Wait for all CPUs to arrive. A load will not be attempted unless all - * CPUs show up. - * */ - if (!wait_for_cpus(&late_cpus_in)) { - this_cpu_write(ucode_ctrl.result, UCODE_TIMEOUT); - return 0; - } - - /* - * On an SMT system, it suffices to load the microcode on one sibling of - * the core because the microcode engine is shared between the threads. - * Synchronization still needs to take place so that no concurrent - * loading attempts happen on multiple threads of an SMT core. See - * below. - */ - if (cpumask_first(topology_sibling_cpumask(cpu)) != cpu) - goto wait_for_siblings; + unsigned int cpu = smp_processor_id(); - ret = microcode_ops->apply_microcode(cpu); - this_cpu_write(ucode_ctrl.result, ret); - -wait_for_siblings: - if (!wait_for_cpus(&late_cpus_out)) - panic("Timeout during microcode update!\n"); - - /* - * At least one thread has completed update on each core. - * For others, simply call the update to make sure the - * per-cpu cpuinfo can be updated with right microcode - * revision. - */ - if (cpumask_first(topology_sibling_cpumask(cpu)) == cpu) - return 0; + if (this_cpu_read(ucode_ctrl.ctrl_cpu) == cpu) + load_primary(cpu); + else + load_secondary(cpu); - ret = microcode_ops->apply_microcode(cpu); - this_cpu_write(ucode_ctrl.result, ret); + /* No point to wait here. The CPUs will all wait in stop_machine(). */ return 0; } @@ -429,7 +397,6 @@ static int load_late_stop_cpus(void) pr_err("You should switch to early loading, if possible.\n"); atomic_set(&late_cpus_in, num_online_cpus()); - atomic_set(&late_cpus_out, num_online_cpus()); /* * Take a snapshot before the microcode update in order to compare and From patchwork Tue Oct 17 21:24:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 154569 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp4407243vqb; Tue, 17 Oct 2023 14:26:45 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH0XybJ1qv1TUIm+v2CaCj/YoWhbRnBXaON3LGwweQN0BQT4KRsygdFWGkc312hLvDszoek X-Received: by 2002:a05:6a21:3987:b0:133:6e3d:68cd with SMTP id ad7-20020a056a21398700b001336e3d68cdmr3417911pzc.3.1697578004957; Tue, 17 Oct 2023 14:26:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697578004; cv=none; d=google.com; s=arc-20160816; b=bWwgsRftIAy4QBQCiMgGkMFSleZPzsCwv6m41v8w4o2rVMGraAJyk8yK37lzHpo0S4 Wo2JKjsd7ZztYs4mULZtw1tnVqNtSaT7dm5IBYbo5keNP4T8m+0jgDKO5Ufq6SRGwNRY Q8XDu//mHJWbKcIY10VbagNkuC28Yu775/k56/xdAbEBNEUdiPsU9lvPeHOzUVUrFe5k mJIYqA9xK4JzRbq87UIq4cyU/W3XI0/AsG8dzQQM1/s2X0vIVvH4a1dg+L3VCWt4E3l/ hL+/wtvhBmhnSPjuT8dpHUcUg2sl65hEngd601EsiyvRSQn2bikBXUCUHkJdM0/SYSN1 vAGA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=1B5sHXZsVnKtrOfKNlTlVMA9O9//zwk+GRrR9QnN4Ps=; fh=8iy+GLBXZdpcs/hIddJ7mbUapYjefwP9Gb111pAzFms=; b=CX8JqvbCsHDYhiFw3GX6tudcjonXT3MCHbsQq7IqJ2djvSwVvnjAiHLq9mKAb3YVim S4Ls4iNTr6YA7ntLJ45pqiP4KuBlDCRXlGvIpo132aNcaQFpBLVLETRFHXul1/rvBsyp 6gCJs/TTxgY9vMgh8W1Lan4rcO0obTtYbBnu+7r4tbW/ou3eJJdCYIj1f3TtvsbXrI+i qbgf7A0Pm96bQZNhkOvAXht6NBsIDj12bP/jNcHPFNo0ZFC1tmSKXUxqyCcJEOctf+Q7 fT8JAv00RpeIRUTP78h6X9oywjYu9+L9lbGDt7NFaGuPSJol7NNY1lNAWdlwzxzuN6Pe jM+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=GUhDRkt8; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from morse.vger.email (morse.vger.email. [23.128.96.31]) by mx.google.com with ESMTPS id i191-20020a6387c8000000b00578cbee11easi640631pge.9.2023.10.17.14.26.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 14:26:44 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) client-ip=23.128.96.31; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=GUhDRkt8; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.31 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by morse.vger.email (Postfix) with ESMTP id EBD24801B180; Tue, 17 Oct 2023 14:26:41 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at morse.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232593AbjJQV0K (ORCPT + 21 others); Tue, 17 Oct 2023 17:26:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33512 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1344463AbjJQVZ2 (ORCPT ); Tue, 17 Oct 2023 17:25:28 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8FDD81BD5 for ; Tue, 17 Oct 2023 14:24:12 -0700 (PDT) Message-ID: <20231017211723.856859665@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1697577851; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=1B5sHXZsVnKtrOfKNlTlVMA9O9//zwk+GRrR9QnN4Ps=; b=GUhDRkt8FEtrhPCJURYt8xdkPK0gwhVg5J96yxSgnXhlnJB5CdEKSG3KrElemk5ZG5ZDUB 64o6LbllLBUlOO6yyD5jrc4c+WOsCsr/VKNcE2aDc33iWX6/ukNaW8fexN+s0UrS5hz/1i bb+GNGQkyq+3WjkZltWz/xJA4wMxGS3GO8DgLK5rbbvvuK9MiBXlYRBS6TkGHU6P8fVUz8 kPQ44w7bVOkSimaJ0XZCniGaKd8NtdCAYzZ3CR+0zyRAKcnz27MQmZsyF5YmmyEbNXsdqQ lOXgPTFuD9kaPhcWO1xD+xeJb+tIQA461ipq1wgurPlq4Fj0hebhrZTOa/aSiw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1697577851; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=1B5sHXZsVnKtrOfKNlTlVMA9O9//zwk+GRrR9QnN4Ps=; b=P5KgVL7ZhSXKs0T5pZMmOqR0Bnt4ph9J15UctnJ3DpgQ+c/4udLd2TEFZdM1GccJ/bdDee wHVUSMUt5sxhydCQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov Subject: [patch V5 34/39] x86/microcode: Rendezvous and load in NMI References: <20231017200758.877560658@linutronix.de> MIME-Version: 1.0 Date: Tue, 17 Oct 2023 23:24:10 +0200 (CEST) X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Tue, 17 Oct 2023 14:26:42 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780039553712684187 X-GMAIL-MSGID: 1780039553712684187 From: Thomas Gleixner stop_machine() does not prevent the spin-waiting sibling from handling an NMI, which is obviously violating the whole concept of rendezvous. Implement a static branch right in the beginning of the NMI handler which is nopped out except when enabled by the late loading mechanism. The late loader enables the static branch before stop_machine() is invoked. Each CPU has an nmi_enable in its control structure which indicates whether the CPU should go into the update routine. This is required to bridge the gap between enabling the branch and actually being at the point where it is required to enter the loader wait loop. Each CPU which arrives in the stopper thread function sets that flag and issues a self NMI right after that. If the NMI function sees the flag clear, it returns. If it's set it clears the flag and enters the rendezvous. This is safe against a real NMI which hits in between setting the flag and sending the NMI to itself. The real NMI will be swallowed by the microcode update and the self NMI will then let stuff continue. Otherwise this would end up with a spurious NMI. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/microcode.h | 12 ++++++++ arch/x86/kernel/cpu/microcode/core.c | 42 ++++++++++++++++++++++++++++--- arch/x86/kernel/cpu/microcode/intel.c | 1 arch/x86/kernel/cpu/microcode/internal.h | 3 +- arch/x86/kernel/nmi.c | 4 ++ 5 files changed, 57 insertions(+), 5 deletions(-) --- --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -72,4 +72,16 @@ static inline u32 intel_get_microcode_re } #endif /* !CONFIG_CPU_SUP_INTEL */ +bool microcode_nmi_handler(void); + +#ifdef CONFIG_MICROCODE_LATE_LOADING +DECLARE_STATIC_KEY_FALSE(microcode_nmi_handler_enable); +static __always_inline bool microcode_nmi_handler_enabled(void) +{ + return static_branch_unlikely(µcode_nmi_handler_enable); +} +#else +static __always_inline bool microcode_nmi_handler_enabled(void) { return false; } +#endif + #endif /* _ASM_X86_MICROCODE_H */ --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -23,6 +23,7 @@ #include #include #include +#include #include #include #include @@ -31,6 +32,7 @@ #include #include +#include #include #include #include @@ -265,8 +267,10 @@ struct microcode_ctrl { enum sibling_ctrl ctrl; enum ucode_state result; unsigned int ctrl_cpu; + bool nmi_enabled; }; +DEFINE_STATIC_KEY_FALSE(microcode_nmi_handler_enable); static DEFINE_PER_CPU(struct microcode_ctrl, ucode_ctrl); static atomic_t late_cpus_in; @@ -282,7 +286,8 @@ static bool wait_for_cpus(atomic_t *cnt) udelay(1); - if (!(timeout % USEC_PER_MSEC)) + /* If invoked directly, tickle the NMI watchdog */ + if (!microcode_ops->use_nmi && !(timeout % USEC_PER_MSEC)) touch_nmi_watchdog(); } /* Prevent the late comers from making progress and let them time out */ @@ -298,7 +303,8 @@ static bool wait_for_ctrl(void) if (this_cpu_read(ucode_ctrl.ctrl) != SCTRL_WAIT) return true; udelay(1); - if (!(timeout % 1000)) + /* If invoked directly, tickle the NMI watchdog */ + if (!microcode_ops->use_nmi && !(timeout % 1000)) touch_nmi_watchdog(); } return false; @@ -374,7 +380,7 @@ static void load_primary(unsigned int cp } } -static int load_cpus_stopped(void *unused) +static bool microcode_update_handler(void) { unsigned int cpu = smp_processor_id(); @@ -383,7 +389,29 @@ static int load_cpus_stopped(void *unuse else load_secondary(cpu); - /* No point to wait here. The CPUs will all wait in stop_machine(). */ + touch_nmi_watchdog(); + return true; +} + +bool microcode_nmi_handler(void) +{ + if (!this_cpu_read(ucode_ctrl.nmi_enabled)) + return false; + + this_cpu_write(ucode_ctrl.nmi_enabled, false); + return microcode_update_handler(); +} + +static int load_cpus_stopped(void *unused) +{ + if (microcode_ops->use_nmi) { + /* Enable the NMI handler and raise NMI */ + this_cpu_write(ucode_ctrl.nmi_enabled, true); + apic->send_IPI(smp_processor_id(), NMI_VECTOR); + } else { + /* Just invoke the handler directly */ + microcode_update_handler(); + } return 0; } @@ -404,8 +432,14 @@ static int load_late_stop_cpus(void) */ store_cpu_caps(&prev_info); + if (microcode_ops->use_nmi) + static_branch_enable_cpuslocked(µcode_nmi_handler_enable); + stop_machine_cpuslocked(load_cpus_stopped, NULL, cpu_online_mask); + if (microcode_ops->use_nmi) + static_branch_disable_cpuslocked(µcode_nmi_handler_enable); + /* Analyze the results */ for_each_cpu_and(cpu, cpu_present_mask, &cpus_booted_once_mask) { switch (per_cpu(ucode_ctrl.result, cpu)) { --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -595,6 +595,7 @@ static struct microcode_ops microcode_in .collect_cpu_info = collect_cpu_info, .apply_microcode = apply_microcode_late, .finalize_late_load = finalize_late_load, + .use_nmi = IS_ENABLED(CONFIG_X86_64), }; static __init void calc_llc_size_per_core(struct cpuinfo_x86 *c) --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -31,7 +31,8 @@ struct microcode_ops { enum ucode_state (*apply_microcode)(int cpu); int (*collect_cpu_info)(int cpu, struct cpu_signature *csig); void (*finalize_late_load)(int result); - unsigned int nmi_safe : 1; + unsigned int nmi_safe : 1, + use_nmi : 1; }; extern struct ucode_cpu_info ucode_cpu_info[]; --- a/arch/x86/kernel/nmi.c +++ b/arch/x86/kernel/nmi.c @@ -33,6 +33,7 @@ #include #include #include +#include #include #define CREATE_TRACE_POINTS @@ -343,6 +344,9 @@ static noinstr void default_do_nmi(struc instrumentation_begin(); + if (microcode_nmi_handler_enabled() && microcode_nmi_handler()) + goto out; + handled = nmi_handle(NMI_LOCAL, regs); __this_cpu_add(nmi_stats.normal, handled); if (handled) { From patchwork Tue Oct 17 21:24:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 154574 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp4407519vqb; Tue, 17 Oct 2023 14:27:36 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGKwnVuUr1MNPg8uH3KI2gs72GKgj1si9v25yBLIK8J24Rb1F+/2PQyhdhhnN2pHl0xX5kI X-Received: by 2002:a05:6a20:54a6:b0:163:d382:ba99 with SMTP id i38-20020a056a2054a600b00163d382ba99mr3685296pzk.5.1697578056082; Tue, 17 Oct 2023 14:27:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697578056; cv=none; d=google.com; s=arc-20160816; b=rWuziiZ8+y3BsBjXeG5JEiO4B30CrvICuw1PGEOn0iXYpIR5qLdwGMC7gOUEwUTYn9 sqFC2GTM4rGay/K2IayR0SDHLjJ+bp7byKDQRs/Idwaie2OpjuLDiNmy3bXRzGuxl3nE p3YzW91nOFQxCt7sto0Fb5ZkHjt5pBl7CVjWmxikqb5z4nm8H0o4KgQKmp86UkVLEtiR XiPeUOb+UN+1sNItWt1unyS94K5xbO0vciKFc3CbzK+ay2THR6DCbBJ7YISgNlP6Q4KF dZK2N6t3tmtl0jbd/6FjJ23sPKhUJVVgJtd0eZdpclje4zU6rbTDjZ1htwmL+BzWomtE bXUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=pcUNzlGOZjGTyhpL0LalziQeFNTF1DVz8FsuLXtLvIU=; fh=8iy+GLBXZdpcs/hIddJ7mbUapYjefwP9Gb111pAzFms=; b=R9fZcDFmDrr+sCzT9WONiTctOMmjC3jtKGA+/+rCVNFsqF2hYwpp3NC8g61Dm8ocGF MABPBLkqz1mJRiIyJ/fFktZnfr1ihUT7CjrZFpgunY8Kq1GRTdb+Snfzko+49CDnjgcF ntTXWRyHKhU+35yE1GSQ0Fon7oGThdhvgMWdPhavBnuMTEyF+v8gQRNYrE1gYiMZ76uy HvqkdM7Wilrs5GmklPF5dUn3rMzVfAxHvfZuf7Eu4wuDgWajVQO8UvyOfj0Vovty8awe aPbpDq+leRlrGmVv/I4EZOBR0sWoDDQqWfPqmyO9meFz1rTNckDaBqLDrGXpLXMRu7Kk HQhg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=YE5eGKKR; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from pete.vger.email (pete.vger.email. [23.128.96.36]) by mx.google.com with ESMTPS id d8-20020a63f248000000b005ad14d37968si585599pgk.773.2023.10.17.14.27.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 14:27:36 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) client-ip=23.128.96.36; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=YE5eGKKR; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.36 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by pete.vger.email (Postfix) with ESMTP id 56E5B80C9A59; Tue, 17 Oct 2023 14:27:24 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at pete.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344341AbjJQV0P (ORCPT + 21 others); Tue, 17 Oct 2023 17:26:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44782 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234836AbjJQVZb (ORCPT ); Tue, 17 Oct 2023 17:25:31 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DF612F0 for ; Tue, 17 Oct 2023 14:24:13 -0700 (PDT) Message-ID: <20231017211723.912645011@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1697577852; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=pcUNzlGOZjGTyhpL0LalziQeFNTF1DVz8FsuLXtLvIU=; b=YE5eGKKReBJ9rydVVCuMK3J5Js1dxYh4e58jp6NqqUbTk+NeetoMZu47IgssueMNFe06yY XfwAtADCfmQxR4iZJ9yHEWAdJHR9u1hHWwW5i9400O2oE8b1wPFyIqKLISeFtEHVp7ZKpJ OdtAuSa0f6xYEHF9531d1+CRU0stBSaL2g1JLC0ZOuOwWWKIt7A9+JLR//NijQY5r2alq5 HOK1cB3qaAld60eVVonRo6b89WkjcQywLgkJow0K8aqCzeEVdmEoGelry+Db3WygIFjqZ2 /6UwL2mVdRkovQbidAM8APt7k+CkCerL0vgB119ELLWE3jCgkJVI/28BpjH9gQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1697577852; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=pcUNzlGOZjGTyhpL0LalziQeFNTF1DVz8FsuLXtLvIU=; b=uVV5etO5KswKTSb/CmrNIiXEubKr8RWJF3xJ8ubO75DIkI9IwTBcnRDkRrU0Zk0Utp1FBN aEPTbVIPZwZboNDQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov Subject: [patch V5 35/39] x86/microcode: Protect against instrumentation References: <20231017200758.877560658@linutronix.de> MIME-Version: 1.0 Date: Tue, 17 Oct 2023 23:24:12 +0200 (CEST) X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Tue, 17 Oct 2023 14:27:24 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780039607400283883 X-GMAIL-MSGID: 1780039607400283883 From: Thomas Gleixner The wait for control loop in which the siblings are waiting for the microcode update on the primary thread must be protected against instrumentation as instrumentation can end up in #INT3, #DB or #PF, which then returns with IRET. That IRET reenables NMI which is the opposite of what the NMI rendezvous is trying to achieve. Signed-off-by: Thomas Gleixner --- arch/x86/kernel/cpu/microcode/core.c | 111 ++++++++++++++++++++++++++--------- 1 file changed, 83 insertions(+), 28 deletions(-) --- --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -272,54 +272,65 @@ struct microcode_ctrl { DEFINE_STATIC_KEY_FALSE(microcode_nmi_handler_enable); static DEFINE_PER_CPU(struct microcode_ctrl, ucode_ctrl); +static unsigned int loops_per_usec; static atomic_t late_cpus_in; -static bool wait_for_cpus(atomic_t *cnt) +static noinstr bool wait_for_cpus(atomic_t *cnt) { - unsigned int timeout; + unsigned int timeout, loops; - WARN_ON_ONCE(atomic_dec_return(cnt) < 0); + WARN_ON_ONCE(raw_atomic_dec_return(cnt) < 0); for (timeout = 0; timeout < USEC_PER_SEC; timeout++) { - if (!atomic_read(cnt)) + if (!raw_atomic_read(cnt)) return true; - udelay(1); + for (loops = 0; loops < loops_per_usec; loops++) + cpu_relax(); /* If invoked directly, tickle the NMI watchdog */ - if (!microcode_ops->use_nmi && !(timeout % USEC_PER_MSEC)) + if (!microcode_ops->use_nmi && !(timeout % USEC_PER_MSEC)) { + instrumentation_begin(); touch_nmi_watchdog(); + instrumentation_end(); + } } /* Prevent the late comers from making progress and let them time out */ - atomic_inc(cnt); + raw_atomic_inc(cnt); return false; } -static bool wait_for_ctrl(void) +static noinstr bool wait_for_ctrl(void) { - unsigned int timeout; + unsigned int timeout, loops; for (timeout = 0; timeout < USEC_PER_SEC; timeout++) { - if (this_cpu_read(ucode_ctrl.ctrl) != SCTRL_WAIT) + if (raw_cpu_read(ucode_ctrl.ctrl) != SCTRL_WAIT) return true; - udelay(1); + + for (loops = 0; loops < loops_per_usec; loops++) + cpu_relax(); + /* If invoked directly, tickle the NMI watchdog */ - if (!microcode_ops->use_nmi && !(timeout % 1000)) + if (!microcode_ops->use_nmi && !(timeout % USEC_PER_MSEC)) { + instrumentation_begin(); touch_nmi_watchdog(); + instrumentation_end(); + } } return false; } -static void load_secondary(unsigned int cpu) +/* + * Protected against instrumentation up to the point where the primary + * thread completed the update. See microcode_nmi_handler() for details. + */ +static noinstr bool load_secondary_wait(unsigned int ctrl_cpu) { - unsigned int ctrl_cpu = this_cpu_read(ucode_ctrl.ctrl_cpu); - enum ucode_state ret; - /* Initial rendezvous to ensure that all CPUs have arrived */ if (!wait_for_cpus(&late_cpus_in)) { - pr_err_once("load: %d CPUs timed out\n", atomic_read(&late_cpus_in) - 1); - this_cpu_write(ucode_ctrl.result, UCODE_TIMEOUT); - return; + raw_cpu_write(ucode_ctrl.result, UCODE_TIMEOUT); + return false; } /* @@ -329,9 +340,33 @@ static void load_secondary(unsigned int * scheduler, watchdogs etc. There is no way to safely evacuate the * machine. */ - if (!wait_for_ctrl()) - panic("Microcode load: Primary CPU %d timed out\n", ctrl_cpu); + if (wait_for_ctrl()) + return true; + + instrumentation_begin(); + panic("Microcode load: Primary CPU %d timed out\n", ctrl_cpu); + instrumentation_end(); +} +/* + * Protected against instrumentation up to the point where the primary + * thread completed the update. See microcode_nmi_handler() for details. + */ +static noinstr void load_secondary(unsigned int cpu) +{ + unsigned int ctrl_cpu = raw_cpu_read(ucode_ctrl.ctrl_cpu); + enum ucode_state ret; + + if (!load_secondary_wait(ctrl_cpu)) { + instrumentation_begin(); + pr_err_once("load: %d CPUs timed out\n", + atomic_read(&late_cpus_in) - 1); + instrumentation_end(); + return; + } + + /* Primary thread completed. Allow to invoke instrumentable code */ + instrumentation_begin(); /* * If the primary succeeded then invoke the apply() callback, * otherwise copy the state from the primary thread. @@ -343,6 +378,7 @@ static void load_secondary(unsigned int this_cpu_write(ucode_ctrl.result, ret); this_cpu_write(ucode_ctrl.ctrl, SCTRL_DONE); + instrumentation_end(); } static void load_primary(unsigned int cpu) @@ -380,25 +416,43 @@ static void load_primary(unsigned int cp } } -static bool microcode_update_handler(void) +static noinstr bool microcode_update_handler(void) { - unsigned int cpu = smp_processor_id(); + unsigned int cpu = raw_smp_processor_id(); - if (this_cpu_read(ucode_ctrl.ctrl_cpu) == cpu) + if (raw_cpu_read(ucode_ctrl.ctrl_cpu) == cpu) { + instrumentation_begin(); load_primary(cpu); - else + instrumentation_end(); + } else { load_secondary(cpu); + } + instrumentation_begin(); touch_nmi_watchdog(); + instrumentation_end(); + return true; } -bool microcode_nmi_handler(void) +/* + * Protection against instrumentation is required for CPUs which are not + * safe against an NMI which is delivered to the secondary SMT sibling + * while the primary thread updates the microcode. Instrumentation can end + * up in #INT3, #DB and #PF. The IRET from those exceptions reenables NMI + * which is the opposite of what the NMI rendezvous is trying to achieve. + * + * The primary thread is safe versus instrumentation as the actual + * microcode update handles this correctly. It's only the sibling code + * path which must be NMI safe until the primary thread completed the + * update. + */ +bool noinstr microcode_nmi_handler(void) { - if (!this_cpu_read(ucode_ctrl.nmi_enabled)) + if (!raw_cpu_read(ucode_ctrl.nmi_enabled)) return false; - this_cpu_write(ucode_ctrl.nmi_enabled, false); + raw_cpu_write(ucode_ctrl.nmi_enabled, false); return microcode_update_handler(); } @@ -425,6 +479,7 @@ static int load_late_stop_cpus(void) pr_err("You should switch to early loading, if possible.\n"); atomic_set(&late_cpus_in, num_online_cpus()); + loops_per_usec = loops_per_jiffy / (TICK_NSEC / 1000); /* * Take a snapshot before the microcode update in order to compare and From patchwork Tue Oct 17 21:24:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 154580 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp4415952vqb; Tue, 17 Oct 2023 14:49:51 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHmdNJ6AqhIVNSlqe0gEkUSff21Yj9bz7Yhkug5AcYRX7+eRuCcd0I1LDKWrZk8JmXtsynJ X-Received: by 2002:a17:903:26c2:b0:1b8:9fc4:2733 with SMTP id jg2-20020a17090326c200b001b89fc42733mr3489019plb.3.1697579390742; Tue, 17 Oct 2023 14:49:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697579390; cv=none; d=google.com; s=arc-20160816; b=ab2VzCSo6fUJEwhgNPjJ1xIncnxtDfc/xooooVC5DTV09CZSinhGM3WvBCVGHc/+5m 9+iLj+YAI8zfisnDdm1q9eeIJWlk/I4WB7U7CZTuGmI0N/AgQSp8LEw7sGkbj/9bhmR8 Q7nwDgqqkiLvxoduw2InPEbnZuH1jy0nLgFLB20nXjZYq904VVZQpu466th4a0A85H+1 3Be1TafCfTWz9Il4+bRg3UwGEKcoo7kIHAIrmp8dSbvYnt1S1MTkR1DdOIYRi0YoyIGV z9Y4Fpzp6DYDDbInklUxXwsWH+lPo8wR80IPMbfE5IBFOpRuLozXZJ4P0oGqA1UP4N7f +jlA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=upCMQ/5CIR2zAhmP8hpPxpV8M1jyj+Jpzo+XS/jhO+0=; fh=8iy+GLBXZdpcs/hIddJ7mbUapYjefwP9Gb111pAzFms=; b=yC2JBuJeIDyJuRiHgs6f2SjFM9BUeXZY9mN04BRtu+cB5mh1b27kw1GUbrrFSLspwL e3lnuE4hVNiyGZN+OpoJ7nyQfo77Gler+cg4HEZHxe6j0Fbv293TZvoxFpz2xwaC9sc5 GLXP3a/L8JX9Bh4+QC53niNbX7hlO0h039+4hHxA0Mx7Ueyg8L4jENQ7QIX+ChhTTWdx F0VS435iYmGbHxlHb5yz+zAziqdYhZ/jeTZUX6EmtglpdCOyC3/9hEjA4pDwyApyIVnM DGbwSeQ5K2Q8c6L5dKlqCEICSzowR3/AJVdacdF7DMzqFLF619sR4FB88coNRHzOUuoK B3lA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=1PnSod6v; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from groat.vger.email (groat.vger.email. [23.128.96.35]) by mx.google.com with ESMTPS id n16-20020a170902d2d000b001c1e4f9c63esi2722914plc.491.2023.10.17.14.49.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 14:49:50 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) client-ip=23.128.96.35; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=1PnSod6v; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by groat.vger.email (Postfix) with ESMTP id 6D52180BB57E; Tue, 17 Oct 2023 14:49:48 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at groat.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234627AbjJQVtg (ORCPT + 21 others); Tue, 17 Oct 2023 17:49:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54076 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230056AbjJQVtf (ORCPT ); Tue, 17 Oct 2023 17:49:35 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [IPv6:2a0a:51c0:0:12e:550::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D995EB0 for ; Tue, 17 Oct 2023 14:49:33 -0700 (PDT) Message-ID: <20231017211723.968077065@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1697579372; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=upCMQ/5CIR2zAhmP8hpPxpV8M1jyj+Jpzo+XS/jhO+0=; b=1PnSod6vZzDr9jJkGLsmQyMOGlxpyZVl325FufYwCF48Xw+wAgYWx9erUjmqms9yvST0sN KXyzLp4Ero8ZBtP9Gd33QYnedGX20/+CfN/HkPszzJ1mVsMCGd8a44Jfu+D7Tg3pdRqmk2 XxHeqONERElAlL31lC5cgBUcnKBWswAhk/ThxGBr+sugzm7uzI/Gkj8DE0y9JZUXMBQxZJ V5Jpx2QjnUSn7gF0fmdGsP0hIfelaX3MPsFNadzJ7T7Zo5QQYDU+Xp3nyl8J3oG+fT0JYT lcihwE8oqgaBhvRZYE+nMWD8VjwSN00MJZ47waqRDb9btSCWXdRZAdkERKO2uA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1697579372; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=upCMQ/5CIR2zAhmP8hpPxpV8M1jyj+Jpzo+XS/jhO+0=; b=SxAZKWhlYrQ2qxhOmlrf/Q5QqX8qsd/s9oTnpL6P42nkGhcv4nm1Q7girkdq3YhV4aNzcW ptj/64LlUFzwrGAQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov Subject: [patch V5 36/39] x86/apic: Provide apic_force_nmi_on_cpu() References: <20231017200758.877560658@linutronix.de> MIME-Version: 1.0 Date: Tue, 17 Oct 2023 23:24:13 +0200 (CEST) X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Tue, 17 Oct 2023 14:49:48 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780041007316431846 X-GMAIL-MSGID: 1780041007316431846 From: Thomas Gleixner When SMT siblings are soft-offlined and parked in one of the play_dead() variants they still react on NMI, which is problematic on affected Intel CPUs. The default play_dead() variant uses MWAIT on modern CPUs, which is not guaranteed to be safe when updated concurrently. Right now late loading is prevented when not all SMT siblings are online, but as they still react on NMI, it is possible to bring them out of their park position into a trivial rendezvous handler. Provide a function which allows to do that. I does sanity checks whether the target is in the cpus_booted_once_mask and whether the APIC driver supports it. Mark X2APIC and XAPIC as capable, but exclude 32bit and the UV and NUMACHIP variants as that needs feedback from the relevant experts. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/apic.h | 5 ++++- arch/x86/kernel/apic/apic_flat_64.c | 2 ++ arch/x86/kernel/apic/ipi.c | 8 ++++++++ arch/x86/kernel/apic/x2apic_cluster.c | 1 + arch/x86/kernel/apic/x2apic_phys.c | 1 + 5 files changed, 16 insertions(+), 1 deletion(-) --- --- a/arch/x86/include/asm/apic.h +++ b/arch/x86/include/asm/apic.h @@ -276,7 +276,8 @@ struct apic { u32 disable_esr : 1, dest_mode_logical : 1, - x2apic_set_max_apicid : 1; + x2apic_set_max_apicid : 1, + nmi_to_offline_cpu : 1; u32 (*calc_dest_apicid)(unsigned int cpu); @@ -542,6 +543,8 @@ extern bool default_check_apicid_used(ph extern void default_ioapic_phys_id_map(physid_mask_t *phys_map, physid_mask_t *retmap); extern int default_cpu_present_to_apicid(int mps_cpu); +void apic_send_nmi_to_offline_cpu(unsigned int cpu); + #else /* CONFIG_X86_LOCAL_APIC */ static inline unsigned int read_apic_id(void) { return 0; } --- a/arch/x86/kernel/apic/apic_flat_64.c +++ b/arch/x86/kernel/apic/apic_flat_64.c @@ -103,6 +103,7 @@ static struct apic apic_flat __ro_after_ .send_IPI_allbutself = default_send_IPI_allbutself, .send_IPI_all = default_send_IPI_all, .send_IPI_self = default_send_IPI_self, + .nmi_to_offline_cpu = true, .read = native_apic_mem_read, .write = native_apic_mem_write, @@ -175,6 +176,7 @@ static struct apic apic_physflat __ro_af .send_IPI_allbutself = default_send_IPI_allbutself, .send_IPI_all = default_send_IPI_all, .send_IPI_self = default_send_IPI_self, + .nmi_to_offline_cpu = true, .read = native_apic_mem_read, .write = native_apic_mem_write, --- a/arch/x86/kernel/apic/ipi.c +++ b/arch/x86/kernel/apic/ipi.c @@ -97,6 +97,14 @@ void native_send_call_func_ipi(const str __apic_send_IPI_mask(mask, CALL_FUNCTION_VECTOR); } +void apic_send_nmi_to_offline_cpu(unsigned int cpu) +{ + if (WARN_ON_ONCE(!apic->nmi_to_offline_cpu)) + return; + if (WARN_ON_ONCE(!cpumask_test_cpu(cpu, &cpus_booted_once_mask))) + return; + apic->send_IPI(cpu, NMI_VECTOR); +} #endif /* CONFIG_SMP */ static inline int __prepare_ICR2(unsigned int mask) --- a/arch/x86/kernel/apic/x2apic_cluster.c +++ b/arch/x86/kernel/apic/x2apic_cluster.c @@ -251,6 +251,7 @@ static struct apic apic_x2apic_cluster _ .send_IPI_allbutself = x2apic_send_IPI_allbutself, .send_IPI_all = x2apic_send_IPI_all, .send_IPI_self = x2apic_send_IPI_self, + .nmi_to_offline_cpu = true, .read = native_apic_msr_read, .write = native_apic_msr_write, --- a/arch/x86/kernel/apic/x2apic_phys.c +++ b/arch/x86/kernel/apic/x2apic_phys.c @@ -166,6 +166,7 @@ static struct apic apic_x2apic_phys __ro .send_IPI_allbutself = x2apic_send_IPI_allbutself, .send_IPI_all = x2apic_send_IPI_all, .send_IPI_self = x2apic_send_IPI_self, + .nmi_to_offline_cpu = true, .read = native_apic_msr_read, .write = native_apic_msr_write, From patchwork Tue Oct 17 21:24:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 154575 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp4407945vqb; Tue, 17 Oct 2023 14:28:51 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHaqa0AHbs2D5YLgMi/4mrrdgs1MzQ2T/vg/v88UApAW1HSK6NWksvIn8dacwpOQrzkHNlC X-Received: by 2002:a05:6359:3118:b0:166:d9b6:1db3 with SMTP id rh24-20020a056359311800b00166d9b61db3mr2926070rwb.2.1697578131554; Tue, 17 Oct 2023 14:28:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697578131; cv=none; d=google.com; s=arc-20160816; b=k3bo6OveKbvQaSnO7Nqf2pxqCKvYAark4U7anWoK821+1cX6lJNLmZhP6+84DqLz0q H7e7omNQu+p+Wpyb4abR0p4hGf1mU/P3wO+mW3z3QX8Kx5cega4n5J83ZT3pp4wXzzRV U40ifICeFRCsfXy3iXSHWm+wflDAtI8XTdxt9u2BC007nC2UVHqgR1opZeG+QunXM8SZ a95FM7oqEsvax1MuU5OriPdI31Vb2VOEsfYAWIJz41hxafnopLKOzYuKTBc7TrxekFbG QB7ZSCkAnRq3msl7DN8Vj9tSnR0H6cmd0Snwz9YG/95/noXzrnDOUGupDYBs0TQYRTjA tz4A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=MMisw33zmF+VluqK8COR66jdwehytciBcDcDKBkX0pQ=; fh=8iy+GLBXZdpcs/hIddJ7mbUapYjefwP9Gb111pAzFms=; b=q+tSjUpxHQmzIjVdDukeDwy/Dk5SH5xLJZGvD1WBny6yxGWjQZPQJSkya6jryIjg2X vTe7BzCprzkhyvizn5BQlfRjtXM8e69UcaoDMXNmOqKCV9tB5hTSSCz2upxwjpjYhx2B kh1oIG87fw0cclIpuJNVJQO6BmrW5Ys5HV6bj0gIh9pRWx42G0D0cajlBPfIxCBXYjOt so/QPPQk/L47sgXamaTZ9uzFI0rQnWNix4ZnQy90Z0+oREKqKibglIoFl3hxtduzyGE5 ww+qkU4LAOLvZqP0AoTNzkuSlIR3+vTJd4moFdPdZNMoPyLu1cgQ8X2U/ET7d9sH4uQx 3Y9w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=dQlvfZ3l; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=DEgzrGcV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from howler.vger.email (howler.vger.email. [2620:137:e000::3:4]) by mx.google.com with ESMTPS id y12-20020aa7942c000000b006b7582b294dsi2485538pfo.129.2023.10.17.14.28.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 14:28:51 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) client-ip=2620:137:e000::3:4; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=dQlvfZ3l; dkim=neutral (no key) header.i=@linutronix.de header.s=2020e header.b=DEgzrGcV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:4 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by howler.vger.email (Postfix) with ESMTP id D899C80C4D43; Tue, 17 Oct 2023 14:28:48 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at howler.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234819AbjJQV2f (ORCPT + 21 others); Tue, 17 Oct 2023 17:28:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33728 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235107AbjJQV2Y (ORCPT ); Tue, 17 Oct 2023 17:28:24 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9F92518B for ; Tue, 17 Oct 2023 14:24:16 -0700 (PDT) Message-ID: <20231017211724.023973386@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1697577855; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=MMisw33zmF+VluqK8COR66jdwehytciBcDcDKBkX0pQ=; b=dQlvfZ3ly2Uukq4DAJK4g9ZTXp9HdRaNE83B6M9DNgjJaIdLS3CBcZLEd0lfMcSLVmUaXI Jm4FxE/eW418S3fTAgz7M+SoIBT9Djkk6AspyBbC/oDgzdRggjZUs/bip5Eyl4ufatyaYq qo82zP63d6ZP4lX5fLDKrXc14kuqTYR7qSKOvZDrsP5B6rvl0/ojcZZzSvEafrMSyae1yQ oQuK0LNA3oR5tdKu6RrDI3p4uwvBwzhIkgTHbeJ8no58gxAuTQnwZV1rDzGXdmVNQT8J3i iCvN2Uhj9KRC6ytnFRckHNMZZJFnUQwDFRuY8tcR8S6lnHgHVLr3VoFjuE08Ow== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1697577855; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=MMisw33zmF+VluqK8COR66jdwehytciBcDcDKBkX0pQ=; b=DEgzrGcVBjqAM5hPcuavbwBpVhSXOgCLioetZsh2kNaQveaQlWq2C5KsI/639jlC3sKoYj Idur3RI6/usNDfDg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov Subject: [patch V5 37/39] x86/microcode: Handle "offline" CPUs correctly References: <20231017200758.877560658@linutronix.de> MIME-Version: 1.0 Date: Tue, 17 Oct 2023 23:24:14 +0200 (CEST) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (howler.vger.email [0.0.0.0]); Tue, 17 Oct 2023 14:28:48 -0700 (PDT) X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on howler.vger.email X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780039686824666542 X-GMAIL-MSGID: 1780039686824666542 From: Thomas Gleixner Offline CPUs need to be parked in a safe loop when microcode update is in progress on the primary CPU. Currently, offline CPUs are parked in mwait_play_dead(), and for Intel CPUs, its not a safe instruction, because the MWAIT instruction can be patched in the new microcode update that can cause instability. - Add a new microcode state 'UCODE_OFFLINE' to report status on per-CPU basis. - Force NMI on the offline CPUs. Wake up offline CPUs while the update is in progress and then return them back to mwait_play_dead() after microcode update is complete. Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/microcode.h | 1 arch/x86/kernel/cpu/microcode/core.c | 112 +++++++++++++++++++++++++++++-- arch/x86/kernel/cpu/microcode/internal.h | 1 arch/x86/kernel/nmi.c | 5 + 4 files changed, 113 insertions(+), 6 deletions(-) --- --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -73,6 +73,7 @@ static inline u32 intel_get_microcode_re #endif /* !CONFIG_CPU_SUP_INTEL */ bool microcode_nmi_handler(void); +void microcode_offline_nmi_handler(void); #ifdef CONFIG_MICROCODE_LATE_LOADING DECLARE_STATIC_KEY_FALSE(microcode_nmi_handler_enable); --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -272,8 +272,9 @@ struct microcode_ctrl { DEFINE_STATIC_KEY_FALSE(microcode_nmi_handler_enable); static DEFINE_PER_CPU(struct microcode_ctrl, ucode_ctrl); +static atomic_t late_cpus_in, offline_in_nmi; static unsigned int loops_per_usec; -static atomic_t late_cpus_in; +static cpumask_t cpu_offline_mask; static noinstr bool wait_for_cpus(atomic_t *cnt) { @@ -381,7 +382,7 @@ static noinstr void load_secondary(unsig instrumentation_end(); } -static void load_primary(unsigned int cpu) +static void __load_primary(unsigned int cpu) { struct cpumask *secondaries = topology_sibling_cpumask(cpu); enum sibling_ctrl ctrl; @@ -416,6 +417,67 @@ static void load_primary(unsigned int cp } } +static bool kick_offline_cpus(unsigned int nr_offl) +{ + unsigned int cpu, timeout; + + for_each_cpu(cpu, &cpu_offline_mask) { + /* Enable the rendezvous handler and send NMI */ + per_cpu(ucode_ctrl.nmi_enabled, cpu) = true; + apic_send_nmi_to_offline_cpu(cpu); + } + + /* Wait for them to arrive */ + for (timeout = 0; timeout < (USEC_PER_SEC / 2); timeout++) { + if (atomic_read(&offline_in_nmi) == nr_offl) + return true; + udelay(1); + } + /* Let the others time out */ + return false; +} + +static void release_offline_cpus(void) +{ + unsigned int cpu; + + for_each_cpu(cpu, &cpu_offline_mask) + per_cpu(ucode_ctrl.ctrl, cpu) = SCTRL_DONE; +} + +static void load_primary(unsigned int cpu) +{ + unsigned int nr_offl = cpumask_weight(&cpu_offline_mask); + bool proceed = true; + + /* Kick soft-offlined SMT siblings if required */ + if (!cpu && nr_offl) + proceed = kick_offline_cpus(nr_offl); + + /* If the soft-offlined CPUs did not respond, abort */ + if (proceed) + __load_primary(cpu); + + /* Unconditionally release soft-offlined SMT siblings if required */ + if (!cpu && nr_offl) + release_offline_cpus(); +} + +/* + * Minimal stub rendezvous handler for soft-offlined CPUs which participate + * in the NMI rendezvous to protect against a concurrent NMI on affected + * CPUs. + */ +void noinstr microcode_offline_nmi_handler(void) +{ + if (!raw_cpu_read(ucode_ctrl.nmi_enabled)) + return; + raw_cpu_write(ucode_ctrl.nmi_enabled, false); + raw_cpu_write(ucode_ctrl.result, UCODE_OFFLINE); + raw_atomic_inc(&offline_in_nmi); + wait_for_ctrl(); +} + static noinstr bool microcode_update_handler(void) { unsigned int cpu = raw_smp_processor_id(); @@ -472,6 +534,7 @@ static int load_cpus_stopped(void *unuse static int load_late_stop_cpus(void) { unsigned int cpu, updated = 0, failed = 0, timedout = 0, siblings = 0; + unsigned int nr_offl, offline = 0; int old_rev = boot_cpu_data.microcode; struct cpuinfo_x86 prev_info; @@ -479,6 +542,7 @@ static int load_late_stop_cpus(void) pr_err("You should switch to early loading, if possible.\n"); atomic_set(&late_cpus_in, num_online_cpus()); + atomic_set(&offline_in_nmi, 0); loops_per_usec = loops_per_jiffy / (TICK_NSEC / 1000); /* @@ -501,6 +565,7 @@ static int load_late_stop_cpus(void) case UCODE_UPDATED: updated++; break; case UCODE_TIMEOUT: timedout++; break; case UCODE_OK: siblings++; break; + case UCODE_OFFLINE: offline++; break; default: failed++; break; } } @@ -512,6 +577,13 @@ static int load_late_stop_cpus(void) /* Nothing changed. */ if (!failed && !timedout) return 0; + + nr_offl = cpumask_weight(&cpu_offline_mask); + if (offline < nr_offl) { + pr_warn("%u offline siblings did not respond.\n", + nr_offl - atomic_read(&offline_in_nmi)); + return -EIO; + } pr_err("update failed: %u CPUs failed %u CPUs timed out\n", failed, timedout); return -EIO; @@ -545,19 +617,49 @@ static int load_late_stop_cpus(void) * modern CPUs uses MWAIT, which is also not guaranteed to be safe * against a microcode update which affects MWAIT. * - * 2) Initialize the per CPU control structure + * As soft-offlined CPUs still react on NMIs, the SMT sibling + * restriction can be lifted when the vendor driver signals to use NMI + * for rendezvous and the APIC provides a mechanism to send an NMI to a + * soft-offlined CPU. The soft-offlined CPUs are then able to + * participate in the rendezvous in a trivial stub handler. + * + * 2) Initialize the per CPU control structure and create a cpumask + * which contains "offline"; secondary threads, so they can be handled + * correctly by a control CPU. */ static bool setup_cpus(void) { struct microcode_ctrl ctrl = { .ctrl = SCTRL_WAIT, .result = -1, }; + bool allow_smt_offline; unsigned int cpu; + allow_smt_offline = microcode_ops->nmi_safe || + (microcode_ops->use_nmi && apic->nmi_to_offline_cpu); + + cpumask_clear(&cpu_offline_mask); + for_each_cpu_and(cpu, cpu_present_mask, &cpus_booted_once_mask) { + /* + * Offline CPUs sit in one of the play_dead() functions + * with interrupts disabled, but they still react on NMIs + * and execute arbitrary code. Also MWAIT being updated + * while the offline CPU sits there is not necessarily safe + * on all CPU variants. + * + * Mark them in the offline_cpus mask which will be handled + * by CPU0 later in the update process. + * + * Ensure that the primary thread is online so that it is + * guaranteed that all cores are updated. + */ if (!cpu_online(cpu)) { - if (topology_is_primary_thread(cpu) || !microcode_ops->nmi_safe) { - pr_err("CPU %u not online\n", cpu); + if (topology_is_primary_thread(cpu) || !allow_smt_offline) { + pr_err("CPU %u not online, loading aborted\n", cpu); return false; } + cpumask_set_cpu(cpu, &cpu_offline_mask); + per_cpu(ucode_ctrl, cpu) = ctrl; + continue; } /* --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -17,6 +17,7 @@ enum ucode_state { UCODE_NFOUND, UCODE_ERROR, UCODE_TIMEOUT, + UCODE_OFFLINE, }; struct microcode_ops { --- a/arch/x86/kernel/nmi.c +++ b/arch/x86/kernel/nmi.c @@ -502,8 +502,11 @@ DEFINE_IDTENTRY_RAW(exc_nmi) if (IS_ENABLED(CONFIG_NMI_CHECK_CPU)) raw_atomic_long_inc(&nsp->idt_calls); - if (IS_ENABLED(CONFIG_SMP) && arch_cpu_is_offline(smp_processor_id())) + if (IS_ENABLED(CONFIG_SMP) && arch_cpu_is_offline(smp_processor_id())) { + if (microcode_nmi_handler_enabled()) + microcode_offline_nmi_handler(); return; + } if (this_cpu_read(nmi_state) != NMI_NOT_RUNNING) { this_cpu_write(nmi_state, NMI_LATCHED); From patchwork Tue Oct 17 21:24:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 154573 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp4407471vqb; Tue, 17 Oct 2023 14:27:24 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGlbqSO6TqH5qzsn/wZywbVgIRb65xktH4Dz0d8c145GCIh3mLOkgt9TqhFNRpknknjjLh1 X-Received: by 2002:a05:6a20:54a6:b0:163:d382:ba99 with SMTP id i38-20020a056a2054a600b00163d382ba99mr3684805pzk.5.1697578044508; Tue, 17 Oct 2023 14:27:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697578044; cv=none; d=google.com; s=arc-20160816; b=pF8tOXoDzXAHerBZAL94SAYqnMLy4a/p6ycEor+y3O11/V7i3hX8UpqvbX2qAMymr/ i37uj6SlfRoIu9PIhZ3/AyAVRW67x336SjB4DZCox+t3bFB1Kp4EjaikCG5zrofkiVvH IEiyTCZqyJ/SkYCLd00XdwAf8d0z9tv+I7MqV5jiJkDmz/qtc1SAHjvs8CJ4s4//Y2hL qjXXLlfE/GCWQyMSuDP5vJYvWMl/G26yh9Yx4wAz2IWSvpsbxATN+qvZoMfcrlEkS7Ky 5yz0OnDCsNq9cbwP7eDjjxoz6kFuXDZK8nPjzA24hFrncwmtuHX2z4j/3AI0BHH4qvnt 1+qQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:date:mime-version:references:subject:cc:to:from :dkim-signature:dkim-signature:message-id; bh=F/5U7P0sx26flD9fqxOXKFZwzuuin+uNCrwyAbmgerk=; fh=8iy+GLBXZdpcs/hIddJ7mbUapYjefwP9Gb111pAzFms=; b=rRkQwaBsYccUqssOc904RCrMFQqjYvQ1S5Rzb2JPoGwMLpEBy5FZDHyDG278Ofm0C7 ZKNr8g6eJe1vAldNH/psbdZclhp9Pm0cDU4+OnmWfhWu6sKQ15nwuoYh0MjHD7SCEF0Z s4apu2drkHE9Mly5eEEE7jzNop5rg7jkWDZTPjLc/NifxL6sDM7dYciGpminduRrsJGh a9hVvs65hsc3EiM8CXL2Koemplttm7uyeVFmGPry00zxJuiPQVyeFc80bMrEWkFgRxT3 Ynttl+sMVqq8KdCQ8j2WMbvr+wmQRyx7rH7bTW4CvMVtU8i/3DY/Bu6wLf6fNhr5G94s UidQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=wTbdrbW0; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from snail.vger.email (snail.vger.email. [2620:137:e000::3:7]) by mx.google.com with ESMTPS id bz33-20020a056a02062100b005a0018ec785si774236pgb.375.2023.10.17.14.27.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 14:27:24 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) client-ip=2620:137:e000::3:7; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=wTbdrbW0; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:7 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by snail.vger.email (Postfix) with ESMTP id D619180CF54B; Tue, 17 Oct 2023 14:27:23 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at snail.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344235AbjJQV1P (ORCPT + 21 others); Tue, 17 Oct 2023 17:27:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33450 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235178AbjJQV06 (ORCPT ); Tue, 17 Oct 2023 17:26:58 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E0AEC195 for ; Tue, 17 Oct 2023 14:24:18 -0700 (PDT) Message-ID: <20231017211724.079611170@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1697577856; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=F/5U7P0sx26flD9fqxOXKFZwzuuin+uNCrwyAbmgerk=; b=wTbdrbW03qJeh12giab6ID7C01ukGXnHD+l8MAC4HpDx1uuIF73FUh3ShL60pAiRGiLClo i+Ov8wq5ccrjEKh+0zgqNbyYsKSHa9AgQmNRdvB79Pnb8ablIwvj4giVuz/ZSmYm/Yi0e/ R2Yx6FbAyv3eR+8gKlJ1goi5/BD/n/u7RSZkoYGwb8TdBEf0+scwVDhukGviq/kEEM3D6X XuDOcCSmZqVQzCZFgQIzIGfKqtEyG7pVX+dJpVQTXlSRfWKlRNbURcOhQH75U0YLT4RXOm zP2XVZfNhuapIsbD0mFezKxsp42joS6NQ4VitG8huEtBBywwfYH3NJ8bYmzSKw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1697577856; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=F/5U7P0sx26flD9fqxOXKFZwzuuin+uNCrwyAbmgerk=; b=dKE9xxcDMHoCifFX4PGaPutYbALIq9xQfzs5XfW4Qh/4XiPDqRd/9NaQcGIKQZmL8PyGij +KVwAoabmUW7S2Dg== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov Subject: [patch V5 38/39] x86/microcode: Prepare for minimal revision check References: <20231017200758.877560658@linutronix.de> MIME-Version: 1.0 Date: Tue, 17 Oct 2023 23:24:16 +0200 (CEST) X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (snail.vger.email [0.0.0.0]); Tue, 17 Oct 2023 14:27:23 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780039595682541456 X-GMAIL-MSGID: 1780039595682541456 From: Thomas Gleixner Applying microcode late can be fatal for the running kernel when the update changes functionality which is in use already in a non-compatible way, e.g. by removing a CPUID bit. There is no way for admins which do not have access to the vendors deep technical support to decide whether late loading of such a microcode is safe or not. Intel has added a new field to the microcode header which tells the minimal microcode revision which is required to be active in the CPU in order to be safe. Provide infrastructure for handling this in the core code and a command line switch which allows to enforce it. If the update is considered safe the kernel is not tainted and the annoying warning message not emitted. If it's enforced and the currently loaded microcode revision is not safe for late loading then the load is aborted. Signed-off-by: Thomas Gleixner --- Documentation/admin-guide/kernel-parameters.txt | 5 +++++ arch/x86/Kconfig | 23 ++++++++++++++++++++++- arch/x86/kernel/cpu/microcode/amd.c | 3 +++ arch/x86/kernel/cpu/microcode/core.c | 19 ++++++++++++++----- arch/x86/kernel/cpu/microcode/intel.c | 3 +++ arch/x86/kernel/cpu/microcode/internal.h | 2 ++ 6 files changed, 49 insertions(+), 6 deletions(-) --- --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -3275,6 +3275,11 @@ mga= [HW,DRM] + microcode.force_minrev= [X86] + Format: + Enable or disable the microcode minimal revision + enforcement for the runtime microcode loader. + min_addr=nn[KMG] [KNL,BOOT,IA-64] All physical memory below this physical address is ignored. --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -1326,7 +1326,28 @@ config MICROCODE_LATE_LOADING is a tricky business and should be avoided if possible. Just the sequence of synchronizing all cores and SMT threads is one fragile dance which does not guarantee that cores might not softlock after the loading. Therefore, - use this at your own risk. Late loading taints the kernel too. + use this at your own risk. Late loading taints the kernel unless the + microcode header indicates that it is safe for late loading via the + minimal revision check. This minimal revision check can be enforced on + the kernel command line with "microcode.minrev=Y". + +config MICROCODE_LATE_FORCE_MINREV + bool "Enforce late microcode loading minimal revision check" + default n + depends on MICROCODE_LATE_LOADING + help + To prevent that users load microcode late which modifies already + in use features, newer microcode patches have a minimum revision field + in the microcode header, which tells the kernel which minimum + revision must be active in the CPU to safely load that new microcode + late into the running system. If disabled the check will not + be enforced but the kernel will be tainted when the minimal + revision check fails. + + This minimal revision check can also be controlled via the + "microcode.minrev" parameter on the kernel command line. + + If unsure say Y. config X86_MSR tristate "/dev/cpu/*/msr - Model-specific register support" --- a/arch/x86/kernel/cpu/microcode/amd.c +++ b/arch/x86/kernel/cpu/microcode/amd.c @@ -888,6 +888,9 @@ static enum ucode_state request_microcod enum ucode_state ret = UCODE_NFOUND; const struct firmware *fw; + if (force_minrev) + return UCODE_NFOUND; + if (c->x86 >= 0x15) snprintf(fw_name, sizeof(fw_name), "amd-ucode/microcode_amd_fam%.2xh.bin", c->x86); --- a/arch/x86/kernel/cpu/microcode/core.c +++ b/arch/x86/kernel/cpu/microcode/core.c @@ -46,6 +46,9 @@ static struct microcode_ops *microcode_ops; bool dis_ucode_ldr = true; +bool force_minrev = IS_ENABLED(CONFIG_MICROCODE_LATE_FORCE_MINREV); +module_param(force_minrev, bool, S_IRUSR | S_IWUSR); + /* * Synchronization. * @@ -531,15 +534,17 @@ static int load_cpus_stopped(void *unuse return 0; } -static int load_late_stop_cpus(void) +static int load_late_stop_cpus(bool is_safe) { unsigned int cpu, updated = 0, failed = 0, timedout = 0, siblings = 0; unsigned int nr_offl, offline = 0; int old_rev = boot_cpu_data.microcode; struct cpuinfo_x86 prev_info; - pr_err("Attempting late microcode loading - it is dangerous and taints the kernel.\n"); - pr_err("You should switch to early loading, if possible.\n"); + if (!is_safe) { + pr_err("Late microcode loading without minimal revision check.\n"); + pr_err("You should switch to early loading, if possible.\n"); + } atomic_set(&late_cpus_in, num_online_cpus()); atomic_set(&offline_in_nmi, 0); @@ -589,7 +594,9 @@ static int load_late_stop_cpus(void) return -EIO; } - add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); + if (!is_safe || failed || timedout) + add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK); + pr_info("load: updated on %u primary CPUs with %u siblings\n", updated, siblings); if (failed || timedout) { pr_err("load incomplete. %u CPUs timed out or failed\n", @@ -679,7 +686,9 @@ static int load_late_locked(void) switch (microcode_ops->request_microcode_fw(0, µcode_pdev->dev)) { case UCODE_NEW: - return load_late_stop_cpus(); + return load_late_stop_cpus(false); + case UCODE_NEW_SAFE: + return load_late_stop_cpus(true); case UCODE_NFOUND: return -ENOENT; default: --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -464,6 +464,9 @@ static enum ucode_state parse_microcode_ unsigned int curr_mc_size = 0; u8 *new_mc = NULL, *mc = NULL; + if (force_minrev) + return UCODE_NFOUND; + while (iov_iter_count(iter)) { struct microcode_header_intel mc_header; unsigned int mc_size, data_size; --- a/arch/x86/kernel/cpu/microcode/internal.h +++ b/arch/x86/kernel/cpu/microcode/internal.h @@ -13,6 +13,7 @@ struct device; enum ucode_state { UCODE_OK = 0, UCODE_NEW, + UCODE_NEW_SAFE, UCODE_UPDATED, UCODE_NFOUND, UCODE_ERROR, @@ -88,6 +89,7 @@ static inline unsigned int x86_cpuid_fam } extern bool dis_ucode_ldr; +extern bool force_minrev; #ifdef CONFIG_CPU_SUP_AMD void load_ucode_amd_bsp(unsigned int family); From patchwork Tue Oct 17 21:24:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Thomas Gleixner X-Patchwork-Id: 154568 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp4407234vqb; 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[2620:137:e000::3:1]) by mx.google.com with ESMTPS id z17-20020a170903019100b001c9af7debbasi143198plg.520.2023.10.17.14.26.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Oct 2023 14:26:43 -0700 (PDT) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) client-ip=2620:137:e000::3:1; Authentication-Results: mx.google.com; dkim=pass header.i=@linutronix.de header.s=2020 header.b=JefohOHT; dkim=neutral (no key) header.i=@linutronix.de; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::3:1 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=linutronix.de Received: from out1.vger.email (depot.vger.email [IPv6:2620:137:e000::3:0]) by morse.vger.email (Postfix) with ESMTP id 1EEAD801B323; Tue, 17 Oct 2023 14:26:41 -0700 (PDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.103.10 at morse.vger.email Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1344430AbjJQV03 (ORCPT + 21 others); Tue, 17 Oct 2023 17:26:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33434 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235107AbjJQVZh (ORCPT ); Tue, 17 Oct 2023 17:25:37 -0400 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BD7BB197 for ; Tue, 17 Oct 2023 14:24:19 -0700 (PDT) Message-ID: <20231017211724.135503217@linutronix.de> DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1697577858; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=VEdToj6uFLFPCubRLaSXMguz5WtO049V21/nw5QnioQ=; b=JefohOHTevmlDp2/uxgFm8oECSsOI3vi8HUaz9d5ArSiWDVufmUMM+VBtn4lmpVsS79J17 WnjJmOFqFFN8YJANwBrijER9mfwnOrWZEsDR9zy6rX65ksmIV5mp/f6MojQvGiw4AbMCN1 XKFpdZT6mjqtWLfQ8MNN/3/4T+/99JqCQ22J7CJz5gIzM545SKNTebvWMZInz1DIxk8zlk vE9O3rlzD9CHvaTzCamIQ2Izzr+IkYpqbXYgnI/pELwZmDgxvsULkbp6dtdk9iXeIaHfJQ QmXM+66N6IlAMXNZ6KsWkRu3wQico18mGYOKUw2QHhS+6OqZGRo9bYUBfOhiDw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1697577858; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: references:references; bh=VEdToj6uFLFPCubRLaSXMguz5WtO049V21/nw5QnioQ=; b=c8k0IaT0LYrO60QNA3c65L2MjogS8hWdiE5sFlgdAModYkSrH0Z1fpgwYo9TKChQJOIGrx VoGOHoHfiZkOY9BQ== From: Thomas Gleixner To: LKML Cc: x86@kernel.org, Borislav Petkov , Ashok Raj Subject: [patch V5 39/39] x86/microcode/intel: Add a minimum required revision for late loading References: <20231017200758.877560658@linutronix.de> MIME-Version: 1.0 Date: Tue, 17 Oct 2023 23:24:17 +0200 (CEST) X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on morse.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (morse.vger.email [0.0.0.0]); Tue, 17 Oct 2023 14:26:41 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1780039552787856800 X-GMAIL-MSGID: 1780039552787856800 From: Ashok Raj In general users, don't have the necessary information to determine whether late loading of a new microcode version is safe and does not modify anything which the currently running kernel uses already, e.g. removal of CPUID bits or behavioural changes of MSRs. To address this issue, Intel has added a "minimum required version" field to a previously reserved field in the microcode header. Microcode updates should only be applied if the current microcode version is equal to, or greater than this minimum required version. Thomas made some suggestions on how meta-data in the microcode file could provide Linux with information to decide if the new microcode is suitable candidate for late loading. But even the "simpler" option requires a lot of metadata and corresponding kernel code to parse it, so the final suggestion was to add the 'minimum required version' field in the header. When microcode changes visible features, microcode will set the minimum required version to its own revision which prevents late loading. Old microcode blobs have the minimum revision field always set to 0, which indicates that there is no information and the kernel considers it unsafe. This is a pure OS software mechanism. The hardware/firmware ignores this header field. For early loading there is no restriction because OS visible features are enumerated after the early load and therefore a change has no effect. The check is always enabled, but by default not enforced. It can be enforced via Kconfig or kernel command line. If enforced, the kernel refuses to late load microcode with a minimum required version field which is zero or when the currently loaded microcode revision is smaller than the minimum required revision. If not enforced the load happens independent of the revision check to stay compatible with the existing behaviour, but it influences the decision whether the kernel is tainted or not. If the check signals that the late load is safe, then the kernel is not tainted. Early loading is not affected by this. [ tglx: Massaged changelog and fixed up the implementation ] Suggested-by: Thomas Gleixner Signed-off-by: Ashok Raj Signed-off-by: Thomas Gleixner --- arch/x86/include/asm/microcode.h | 3 +- arch/x86/kernel/cpu/microcode/intel.c | 37 ++++++++++++++++++++++++++++++---- 2 files changed, 35 insertions(+), 5 deletions(-) --- --- a/arch/x86/include/asm/microcode.h +++ b/arch/x86/include/asm/microcode.h @@ -38,7 +38,8 @@ struct microcode_header_intel { unsigned int datasize; unsigned int totalsize; unsigned int metasize; - unsigned int reserved[2]; + unsigned int min_req_ver; + unsigned int reserved; }; struct microcode_intel { --- a/arch/x86/kernel/cpu/microcode/intel.c +++ b/arch/x86/kernel/cpu/microcode/intel.c @@ -457,16 +457,40 @@ static enum ucode_state apply_microcode_ return ret; } +static bool ucode_validate_minrev(struct microcode_header_intel *mc_header) +{ + int cur_rev = boot_cpu_data.microcode; + + /* + * When late-loading, ensure the header declares a minimum revision + * required to perform a late-load. The previously reserved field + * is 0 in older microcode blobs. + */ + if (!mc_header->min_req_ver) { + pr_info("Unsafe microcode update: Microcode header does not specify a required min version\n"); + return false; + } + + /* + * Check whether the current revision is either greater or equal to + * to the minimum revision specified in the header. + */ + if (cur_rev < mc_header->min_req_ver) { + pr_info("Unsafe microcode update: Current revision 0x%x too old\n", cur_rev); + pr_info("Current should be at 0x%x or higher. Use early loading instead\n", mc_header->min_req_ver); + return false; + } + return true; +} + static enum ucode_state parse_microcode_blobs(int cpu, struct iov_iter *iter) { struct ucode_cpu_info *uci = ucode_cpu_info + cpu; + bool is_safe, new_is_safe = false; int cur_rev = uci->cpu_sig.rev; unsigned int curr_mc_size = 0; u8 *new_mc = NULL, *mc = NULL; - if (force_minrev) - return UCODE_NFOUND; - while (iov_iter_count(iter)) { struct microcode_header_intel mc_header; unsigned int mc_size, data_size; @@ -509,9 +533,14 @@ static enum ucode_state parse_microcode_ if (!intel_find_matching_signature(mc, &uci->cpu_sig)) continue; + is_safe = ucode_validate_minrev(&mc_header); + if (force_minrev && !is_safe) + continue; + kvfree(new_mc); cur_rev = mc_header.rev; new_mc = mc; + new_is_safe = is_safe; mc = NULL; } @@ -523,7 +552,7 @@ static enum ucode_state parse_microcode_ return UCODE_NFOUND; ucode_patch_late = (struct microcode_intel *)new_mc; - return UCODE_NEW; + return new_is_safe ? UCODE_NEW_SAFE : UCODE_NEW; fail: kvfree(mc);