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Mon, 16 Oct 2023 23:18:22 -0700 (PDT) From: Manivannan Sadhasivam Date: Tue, 17 Oct 2023 11:47:54 +0530 Subject: [PATCH 1/2] PCI: dwc: Add new accessors to enable/disable DBI CS2 while setting the BAR size MIME-Version: 1.0 Message-Id: <20231017-pcie-qcom-bar-v1-1-3e26de07bec0@linaro.org> References: <20231017-pcie-qcom-bar-v1-0-3e26de07bec0@linaro.org> In-Reply-To: <20231017-pcie-qcom-bar-v1-0-3e26de07bec0@linaro.org> To: Jingoo Han , Gustavo Pimentel , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=2745; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=OP4W5AEhgUSDaHDy2B4OZk3Grr6XP1yl9oNf0R8rWUQ=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBlLicmILNyHAyc5XZnCRhkGM2ygXAYYTDPEUJfF otuvUxk3HuJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZS4nJgAKCRBVnxHm/pHO 9VDZCACPrTqVHF2758C661bi9dz+Xl3g3KKSa/tO6cUWWRo87iggp2VrgX4Ph9hdg7fGjHoY5O/ 7g0tAocoLXawOXjvADKmqAljh0tuTaQO9ks9Ers8xrSfa26mmgWxojG1c9jPHS0ac3uaG+YJdm+ /Bd0UVcVlrp60NpTBwDklAbuSU/KeAXPwYElDVe0JwwQ8tcYy6/3fgE7c0mbcSugF6V1fDIZ6Ei eJQRYvXUdY4czYybme0NxNol/uz5ZxMZf63BQ7cbv9i2PK5UqrRCI7k+cxMriTDLDP5zRP7fA8z WH/0kI7KuwagZa8T+f5beHAqmtoE8kWClmpJnrZwX6DdJ9NW X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on pete.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (pete.vger.email [0.0.0.0]); Mon, 16 Oct 2023 23:18:44 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779982429324109983 X-GMAIL-MSGID: 1779982429324109983 From: Manivannan Sadhasivam As per the DWC databook v4.21a, section M.4.1, in order to write some read only and shadow registers through application DBI, the device driver should assert DBI Chip Select 2 (CS2) in addition to DBI Chip Select (CS). This is a requirement at least on the Qcom platforms while programming the BAR size, as the BAR mask registers are marked RO. So let's add two new accessors dw_pcie_dbi_cs2_{en/dis} to enable/disable CS2 access in a vendor specific way while programming the BAR size. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-designware-ep.c | 6 ++++++ drivers/pci/controller/dwc/pcie-designware.h | 13 +++++++++++++ 2 files changed, 19 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index d34a5e87ad18..1874fb3d8df4 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -269,11 +269,17 @@ static int dw_pcie_ep_set_bar(struct pci_epc *epc, u8 func_no, u8 vfunc_no, dw_pcie_dbi_ro_wr_en(pci); + dw_pcie_dbi_cs2_en(pci); dw_pcie_writel_dbi2(pci, reg_dbi2, lower_32_bits(size - 1)); + dw_pcie_dbi_cs2_dis(pci); + dw_pcie_writel_dbi(pci, reg, flags); if (flags & PCI_BASE_ADDRESS_MEM_TYPE_64) { + dw_pcie_dbi_cs2_en(pci); dw_pcie_writel_dbi2(pci, reg_dbi2 + 4, upper_32_bits(size - 1)); + dw_pcie_dbi_cs2_dis(pci); + dw_pcie_writel_dbi(pci, reg + 4, 0); } diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 55ff76e3d384..3cba27b5bbe5 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -379,6 +379,7 @@ struct dw_pcie_ops { size_t size, u32 val); void (*write_dbi2)(struct dw_pcie *pcie, void __iomem *base, u32 reg, size_t size, u32 val); + void (*dbi_cs2_access)(struct dw_pcie *pcie, bool enable); int (*link_up)(struct dw_pcie *pcie); enum dw_pcie_ltssm (*get_ltssm)(struct dw_pcie *pcie); int (*start_link)(struct dw_pcie *pcie); @@ -508,6 +509,18 @@ static inline void dw_pcie_dbi_ro_wr_dis(struct dw_pcie *pci) dw_pcie_writel_dbi(pci, reg, val); } +static inline void dw_pcie_dbi_cs2_en(struct dw_pcie *pci) +{ + if (pci->ops && pci->ops->dbi_cs2_access) + pci->ops->dbi_cs2_access(pci, true); +} + +static inline void dw_pcie_dbi_cs2_dis(struct dw_pcie *pci) +{ + if (pci->ops && pci->ops->dbi_cs2_access) + pci->ops->dbi_cs2_access(pci, false); +} + static inline int dw_pcie_start_link(struct dw_pcie *pci) { if (pci->ops && pci->ops->start_link) From patchwork Tue Oct 17 06:17:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 153925 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:612c:2908:b0:403:3b70:6f57 with SMTP id ib8csp3930628vqb; Mon, 16 Oct 2023 23:18:50 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHLo2mk7JvxD4WGaI86zmu8Zq+bpKbcNEEHg8Y/Famwl1q4fXoL4FAydkG7EEmLBbHLNKbu X-Received: by 2002:a05:6359:3118:b0:166:d9b6:1db3 with SMTP id rh24-20020a056359311800b00166d9b61db3mr1140206rwb.2.1697523530333; Mon, 16 Oct 2023 23:18:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1697523530; cv=none; d=google.com; s=arc-20160816; b=RK+LaJuju9Z1eWT+o4fH9ZMbtcJamDy2AElbtVCrwsJp5P7LfW6QlLbsGUXFcMux4v wNclxKbJng8jZCOpW2/53UTZhzlFJWu7joZyytjxKmC/EQXM0KJupWl/Ua2QiLT4GhCh EnHi58imyJKxJVqOBknIC08HeCTcnG+7kI2sJsitycBMS42VwrE2o15vcr4dxT9cmt3m hbKF0Qyl/mUDQpZauObzIu2Hs5ISJTmrJY2WhuJ8QOrb7rPUGQfM1+LFlWDgue/rx4pw 4N9xLcW1gybpGk+f3RtnbLu1JbqQqWrFvZ3kXfIO4nyxc4Yg67dOwd0TY1GHlCko3kba z4Bw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:cc:to:in-reply-to:references:message-id :content-transfer-encoding:mime-version:subject:date:from :dkim-signature; bh=gkYO1bScO1Nh1mhDBKqPQqvg77TORt1VTesmsXej5Zo=; fh=AL7uOW7XpDa++9W8UyVEmNJlkLbwtkYB45DjIzYa5dA=; b=XfDp6k6fG/4iVYvLky3H+1VhN4mjdqjNpeyLJuagr5YtODRnnLBrCf3kzupZMx3I1F ySThDaJRs31YF5b+1Zb2o0bBEWbMrdjhHr23bh2qWtz68LMeOxnOti5GsI/PhS4mTnrM 6kRjVA+2r1WrD6CActx/OdGHJ6ipGpreaYjb+X5bX2Kh7NjCewaUw8UPh4wpJ0iSM9Xx I0tG+E8QpPjBDKYq4whTMArcoq4j2wP/ZfCVxnFfhjVcwTYqHeqtiZfy8dFDFHaf7zmi JpqVcNmkT1QAKKOI6qa2TX49L9BBDSOMtTSuLz0CdjQxlwRyaOt7nGZWoabZiz2z2Csd mKww== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dTuXzuC3; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 23.128.96.35 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from groat.vger.email (groat.vger.email. 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Mon, 16 Oct 2023 23:18:27 -0700 (PDT) From: Manivannan Sadhasivam Date: Tue, 17 Oct 2023 11:47:55 +0530 Subject: [PATCH 2/2] PCI: qcom-ep: Implement dbi_cs2_access() function callback for DBI CS2 access MIME-Version: 1.0 Message-Id: <20231017-pcie-qcom-bar-v1-2-3e26de07bec0@linaro.org> References: <20231017-pcie-qcom-bar-v1-0-3e26de07bec0@linaro.org> In-Reply-To: <20231017-pcie-qcom-bar-v1-0-3e26de07bec0@linaro.org> To: Jingoo Han , Gustavo Pimentel , Manivannan Sadhasivam , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=openpgp-sha256; l=1955; i=manivannan.sadhasivam@linaro.org; h=from:subject:message-id; bh=T4a7lgG8ADnBOXiiRIvPHtgQQvh1D/dQF3320fos0xc=; b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBlLicmGF31I/FDgbYgWQOFxOQucjTRctHyuLkNx yHPARkm4AuJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCZS4nJgAKCRBVnxHm/pHO 9ekTCACOVYldI/Jbzvfj0Br85YHE10/BeAbFb0Bw8D/TRVjTHodwXArult4wCKHRG9u38cBK+YW 6u4Rd85AmgXvmLuNxJIdBdb3IJ2xLC3xK9BUUrDp3BQxtgxJiXkO/iK74LeIoYJUeCp5yGSAD85 dTUsY81gs6PExIsrrcJO0Ya0tB4zMVOq6VLCN2zWk/VWDKGqf+5Os3qzFj3CLbGeAcwt8uvF4/G m08NZAqU5eaW6fQ4YvB1CzR/fxrJ3mz3zchFRoRxtnVlCOr6i80Gzd3mT77vtYN1lqCUSLoFXae bpvuSLn1LIxXDD4foOUAJ1j7Qiq9yoeTDA+2Ych8vojNsrw1 X-Developer-Key: i=manivannan.sadhasivam@linaro.org; a=openpgp; fpr=C668AEC3C3188E4C611465E7488550E901166008 X-Spam-Status: No, score=-0.8 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on groat.vger.email Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-Greylist: Sender passed SPF test, not delayed by milter-greylist-4.6.4 (groat.vger.email [0.0.0.0]); Mon, 16 Oct 2023 23:18:48 -0700 (PDT) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1779982433759862553 X-GMAIL-MSGID: 1779982433759862553 From: Manivannan Sadhasivam Qcom EP platforms require enabling/disabling the DBI CS2 access while programming some read only and shadow registers through DBI. So let's implement the dbi_cs2_access() callback that will be called by the DWC core while programming such registers like BAR mask register. Without DBI CS2 access, writes to those registers will not be reflected. Fixes: f55fee56a631 ("PCI: qcom-ep: Add Qualcomm PCIe Endpoint controller driver") Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 32c8d9e37876..4653cbf7f9ed 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -124,6 +124,7 @@ /* ELBI registers */ #define ELBI_SYS_STTS 0x08 +#define ELBI_CS2_ENABLE 0xa4 /* DBI registers */ #define DBI_CON_STATUS 0x44 @@ -262,6 +263,18 @@ static void qcom_pcie_dw_stop_link(struct dw_pcie *pci) disable_irq(pcie_ep->perst_irq); } +static void qcom_pcie_dbi_cs2_access(struct dw_pcie *pci, bool enable) +{ + struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci); + + writel_relaxed(enable, pcie_ep->elbi + ELBI_CS2_ENABLE); + /* + * Do a dummy read to make sure that the previous write has reached the + * memory before returning. + */ + readl_relaxed(pcie_ep->elbi + ELBI_CS2_ENABLE); +} + static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep) { struct dw_pcie *pci = &pcie_ep->pci; @@ -500,6 +513,7 @@ static const struct dw_pcie_ops pci_ops = { .link_up = qcom_pcie_dw_link_up, .start_link = qcom_pcie_dw_start_link, .stop_link = qcom_pcie_dw_stop_link, + .dbi_cs2_access = qcom_pcie_dbi_cs2_access, }; static int qcom_pcie_ep_get_io_resources(struct platform_device *pdev,